2-Digit BCD Counter 671493 Features / Benefits Drive numeric displays Expansion in 2-digit increments e 24-pin SKINNYDIP saves space Bus structured pinout Low current PNP inputs reduce loading Three-state output drive bus lines Description The 2-digit BCD (Binary Coded Decimal) Counter is a synchro- nous counter with complementary count enables (CE1, CE2), parallel load (LD), and carry out (6). Three control inputs (LD, CE1, CE2) provide one of three operations which occur syn- chronously on the rising edge of the clock (CK). The load operation loads the inputs (D1 and D2) into the output register (Q1 and Q2) when load is LOW. Note that the load line overrides the increment. When LO is not active, the counter will increment in a Binary- Coded-Decimal sequence if both count enables are asserted (CE1 = L and CE2 = H), otherwise it holds. Two or more BCD Counters can be cascaded to implement larger BCD counters by connecting carry out (CO) of the first stage to count enable (CE1) of the second stage. This signal is not affected by OE. Parallel loading allows programmability of the BCD Counter and numeric indicator. This BCD Counter is ideal in an industrial control application where an event counter is needed to drive numeric displays. The device can receive one count enable in the form of strobes from a motor or other device. The second count enable can receive the period signal. With connections in this manner, the counter counts events during a period. The device will provide two active high BCD outputs (Q1 and Q2) to drive two numeric indicators, which feature an on-board decoder/driver. Block Diagram D2 DI COUNT ENABLE 2 COUNT ENABLE 1 LOAD CARRY OUT CLOCK OUTPUT ENABLE 2-DIGIF BCD COUNTER Q2 Qi SKINNYDIP is a registered trademark of Monolithic Memories. 2175 Mission Coliege Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374 Ordering Information PART NUMBER PACKAGE TEMPERATURE 671493 NS, JS Com Function Table = a= jos D1A-D1D/ |Q1A-Q1D/ E|CK|LD |CE1 |CE2 D2A-D2D | Q2A-Q2D OPERATION Hlele]*]- * Z HI-z* L}r;}Lyx} xX D D Load Lit |H}|H |X X Q Hold (CE1=H) LJ) t]Hy XL x Q Hold (CE2=L) Lit }|H] tH Xx Q plus 1 Increment * When OE is HIGH, Q1 and Q2 are disabled to the high-impedance state; however, sequential operation of the counter is not affected. Pin Configuration OS om ck [7 24] voc ce 23) CE2 oa LB] 22] Q1A acy [ote [5] zi] 018 | eco DIGIT DIGIT in joie [5] aa] arc OUT ri3] a2a or [a] oa [7] aco |o28 [5] 7] a2B | aco bIGiT DIGIT IN [pac El rig} aac | OUT pap [i] ott GND [12 [15] a2p [ta] 66 (CARRY OUT) Monolithic Memories TWX: 910-338-2376 7-33671493 ee Absolute Maximum Ratings Supply voltage VOC oo. eee ee Ene een E EEE EEE EEE REE EEE EERE EEE EE e EERE EEE EE EES 7V 17a ) 91 an ce] C21 |= a 55V Off-state OUTPUT VOITAGE 66... cece cee eee eee ne ene EE EERE EEE EERE EE EEE EOE E EEE eee ES EEE HERE E EES 5.5V Storage temperature 2.0... cece cece eee een E EE EEE ete een ens eee nese teen eens ~65C to +150 Operating Conditions COMMERCIAL ; SYMBOL PARAMETER MIN TYP MAX UNIT Voc Supply voltage 4.75 5 5.25 Vv Ta Operating free air temperature 0 75) C Low 35 tw Clock width ns High 25 teu Setup time 50 ns 1 th Hald time 0 ~15 ns | Electrical Characteristics over Operating Conditions COMMERCIAL SYMBOL PARAMETER TEST CONDITIONS MIN TYPt max [UNIT Vy" Low-level input voltage os] Vv Vin High-level input voltage 2 Vv Vic Input clamp voltage Voc = MIN = ~-18 mA -15 | V Ye Low-level input current Voc = MAX Vj, =04V ~0.25 | mA WH High-level input current Voc = MAX Vj=2.4V 25) pA \ Maximum input current Voc = MAX V,=5.5V 1 |} mA Voo2Min J VoL Low-level output voltage Vit. = 0.8V lol = 24mA 05) V Vin =2V Voc = MIN VoH High-level output voltage | Vit =0.8V loH =-3.2 MA | 2.4 Vv iVIH =2V Voz Voc= MAX =] Vg #04V ~100 | Off-state output current Vit =0.8V | BA loz Vin, = 2M Vo? 24V 100. log** Output short-circuit current** Voc = 5.0V Vo =9V -30 ~130 | mA loc Supply current Voc = MAX 120 180 | mA * ViL and Vj} are, in effect, input conditions of output tests and are not, themselves, directly tested. As conditions of tests, Vj, <= 0.8 V and Vip 2 2.0V. ** Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. } Typicals at Voc = V, Ta = 26C. Switching Characteristics over Operating Conditions SYMBOL PARAMETER vegec teat load) MIN COMMERCIAL ax [UNIT fMAX Maximum clock frequency ; 12.5 MHz tpp1 Clock to Q Commercial 20 30 | ns tpp2 | Clock to CO Rt : or 55 80 | ns tpzx Output enable delay Ro = 3909 35 45 ns tpxz Output disable delay : 35 45 | ns 7-34 Monolithic fe Memories671493 a Standard Test Load OUTPUT ) TEST POINT ~ CL v az wv }p. Notes: 1. tpp is tested with switch S1 closed. C_ = 50 pF and measured! at 1.5 V output level. 2. tpzx is measured at the 1.5 V output level with Cy = 50 pF. Sy is open for high impedance to 1 test, and closed for high impedance to 0 test. 3. tpyz is tested with Cy = 5 pF. Sq is open for 1 to high impedance test, measured at Voy -0.5 V output level: Sy is closed for 0 to high impedance test measured at Vc)_ +0.5 V output level. Output Timing of \ SNS. 93.9 9 o ~ 'po, Q7.4 g oO pp. > co / input Timing Loading VN SVS &l Monolithic KD Memories 7-35671493 Application: LED Displays The Event Counter can be implemented using the 2-Digit BCD Counters. The 2-Digit BCD Counters control the display for three pairs of LED displays. The 2-Digit BCD Counters count the events. The displays are controlled by the output enable. These coun- ters display the count in 10s, 100s and 1000s respectively. These simply count the occurrence of an external event. 671493 2-Digit BCD Counter Application: Event Counter I +5V tS a2 D2 D1 CE2 CEI 671493 OE q ai D2 Di CE2 _02 D1 CE2 CET &o CEI 671493 GE 671493 OE LB iD dq Q2 a2. al a RESET Pe at 7) ty "1 EVENT COUNT [7] [-] LI i) Li mi 7-36 Monolithic RR Memories