Product Specification 28410/Z84C10 NMOS/CMOS Z80 DMA Direct Memory Access Controller FEATURES @ Transfers, searches, and search/transfers in Byte-at-a- a CMOS version for the designs requiring low power Time, Burst, or Continuous modes. Cycle length and consumption edge timing can be programmed to match the speed of any port. a NMOS Z0841004 - 4MHz Dual port addresses (source and destination) generated for memory-to-I/O, memory-to-memory, or 1/O-to-I/O operations. Addresses may be fixed or automatically incremented/decremented. a CMOS 284C1006 - DC to 6.17 MHz, Z84C1008 - DC to 8 MHz m 6 MHz version supports 6.144 MHz CPU clock opera- m Next-operation loading without disturbing current tion clock. operations via buffered starting-address registers. An entire previous sequence can be repeated automatically. @ Standard Z80 Family bus-request and prioritized interrupt-request daisy chains implemented without external logic. Sophisticated, internally modifiable interrupt vectoring. m Extensive programmability of functions. CPU can read complete channel status. = NMOS version for cost sensitive performance solutions @ Direct interfacing to system buses without external logic. GENERAL DESCRIPTION The Z80 DMA (Direct Memory Access), hereaiter referred function of managing CPU-independent transfers between to as Z80 DMA or DMA, is a powerful and versatile device for two ports is augmented by an array of features that optimize controlling and processing transfers of data. Its basic transfer speed and control with little or no external logic in systems using an 8- or 16-bit data bus and a 16-bit address } Op se - bus. r] D, a- -?] 2 & -. system | . 1 0, As > DATA : gus ) <>] &- ie 1 QL oO A te] Os ae aM 2 x ay +] 04 Ag -> a3 ae] SYSTEM wn ge | O, 47 | popress a {4 37 C] intiPucse Ma f | sus aC s 3 [] 160 < >| sUSREG A }> aot s 95 L] bp CONTROL oy ai A cx (7 up} o, . _] 50 au - wets 330] o2 Z80DMA = An F fC) 9 321] 0s ats FORG ( 10 nO om Ate }-_> +sv(} 11 260 DMA 21] ano | Mi As MREG Cj 12 29 [7] 0s system | +>] fa 540 C13 20] CONTROL ( | MREG avy J~-. | oma Gai] 14 27] oy pus | sd aa ciwart |} f CONTROL ausrea CL 1 26] mi <a] wa INTPULSE |}__ MTEARUPT cerwait ([] 16 25 [J Rov CTT (er } CONTROL as Ov 2aT] As | -m] RESET | to -e au(] 23] A Loy | ; An [19 22D] Ato C-MOS DMA av [2 a an PLCC PACKAGE ONLY +5 GND CLK . Figure 2a. 40-pin Dual-in-Line Package (DIP), Figure 1. Pin Functions Pin Assignments 4INT/PULSE a Sef2izecsles OOOO} 6 5 43 2 1 4443424140 Ao (7 39 oe cx [_]8 38f ]o, wae 37[_]o, Ro [10 36 [7] 0, toro [_]11 357], ac [12 Z8410 34][]ano ov [313 33[ Jo, wreo (714 32[ Jo, Bao L] 15 3tf 07 bai Cts 30 im eusrea: [117 20] Nc 18 19 20 21 22 23 24 2526 27 28 DODOUOUUUUU ee>o p fff ee tee: is Figure 2b. 28410 NMOS 280 DMA 44-Pin PLCC Pinout w ; 8 2 vv 7 ww wr & o zZeieaeceaee alk uw MOOOON MINI 6 5 43 2 1 444342 4140 Ao Li 391] % ceux Je 381} = 37) WO Lf10 36[}% ora fit 35} % feser (12 284C10 34 [7] GND +5v (13 33[]0, ~ WREG [14 32[[J9, pao L}15 31 Jo, paLfie 307) Wi Busreg [_}17 2o[]N.c 18 19 20 21 22 23 24 2526 27 28 QUOUWUUOOO Eb 2s ae 7 oe => oO <<4 lg fff eFzZ2 <B2z 1S Figure 2c. Z84C10 CMOS Z80 DMA PLCC Pinout 42Transfers can be done between any two ports (source and destination), including memory-to-I/O, memory-to-memory, and I/O-to-/O. Dual port addresses are automatically generated for each transaction and may be either fixed or incrementing/decrementing. In addition, bit-maskable byte searches can be performed either concurrently with transfers or as an operation in itself. The Z80 DMA contains direct interfacing to, and independent control of, system buses, as well as sophisticated bus and interrupt controls. Many programmable features, including variable cycle timirig and auto-restart, minimize CPU software overhead. They are especially useful in adapting this special-purpose transfer processor to a broad variety of memory, /O and CPU environments. The Z80 DMA is packaged in a 40-pin plastic or Cerdip DIP, or 44-pin PCC. It uses a single +5V power supply and the standard Z80 Family single-phase clock. FUNCTIONAL DESCRIPTION Classes of Operation. Th Z80 DMA has three basic classes of operation: @ Transfers of data between two ports (memory or 1/O peripheral) , : @ Searches for a particular 8-bit maskable byte at a single port in memory or an {/O peripheral a Combined transfers with simultaneous search between two ports Figure 4 illustrates the basic functions served by these Classes of operation. SYSTEM BUSES = cPu DMA INT INT +5V (Et : ZCrTO, crc ZCiO02 INT tEO te) _ ie) RxCA int - ' INT TxCaA 1EO 1l RxCB TxCB WIRDYA WIADYB RDY s10 DMA Figure 3. Typical 280 Environment During a transfer, the DMA assumes control of the system address and data buses. Byte by byte, data is read from one addressable port and written to the other addressable port. The ports may be programmed to be either system main memory or peripheral 1/O devices. Thus, a block of data may be written from one peripheral to another, from one area of main memory to another, or from a peripheral to main memory and vice versa. During a search-only operation, data is read from the source port and compared byte by byte with a DMA-internal register containing a programmable match byte. This match byte may optionally be masked so that only certain bits within the match byte are compared. Search rates up to 2M bytes per second can be obtained with the 4 MHz Z80 DMA. In combined searches and transfers, data is transferred between two ports while simultaneously searching for a bit-maskable byte match. Data transfers or searches can be programmed to step, or interrupt, under various conditions. In addition, CPU- readable status bits can be programmed to reflect the condition. Modes of Operation. The Z80 DMA can be programmed to operate in one of three transfer and/or search modes: @ Byie-at-a-Time: data operations are performed one byte at a time. Between each byte operation the system buses are released to the CPU. The buses are requested again for each succeeding byte operation. to PERIPHERAL MEMORY 1. Search memory 2. Transfer memory-to-memory (optional search) 3. Transter memory-to-VO (optional search) 4. Search WO 5. Transfer O-to-/O0 (optional search) Figure 4. Basic Functions of the Z80 DMA 43m BGurst: data operations continue until a port's Ready line to the DMA goes inactive. The DMA then stops and releases the system buses after completing its current byte operation. : . @ Continuous: data operations continue until the end of the programmed block of data is reached before the system buses are released. If a port's Ready line goes inactive before this occurs, the DMA simply pauses until the Ready line comes active again. In all modes, once a byte of data is read into the DMA, the operation on the byte will be completed in an orderly fashion, regardless of the state of other signals (including a port's Ready line). Due to the DMAs high-speed buffered method of reading data, operations on one byte are not completed until the next byte is read in. This means that total transfer or search block lengths must be two or more bytes, and that block lengths programmed into the DMA must be one byte less than the desired block tength (count is N-1 where N is the block length). Commands and Status. The Z80 DMA has several writable control registers and readable status registers available to the CPU. Control bytes can be written to the DMA whenever the DMA is not controlling the system buses, but the act of writing a control byte to the DMA disables the DMA until it is again enabled by a specific command. Status bytes can also be read at any such time, but writing the Read Status Byte command or the Initiate Read Sequence command disables the DMA. Control bytes to the DMA include those which affect immediate command actions such as enable, disable, reset, load starting-address buffers, continue, clear counters, and clear status bits. In addition, many mode-setting control bytes can be written, including mode and class of operation, port configuration, starting addresses, block length, address counting rule, match and match-mask byte, interrupt conditions, interrupt vector, status-affects-vector condition, pulse counting, auto restart, Ready-line and Wait-line rules, and read mask. Readable status registers include a general status byte reflecting Ready-line, end-of-block, byte-match, and interrupt conditions, as well as 2-byte registers for the current byte count, Port A address, and Port B address. Variable Cycle. The Z80 DMA has the unique feature of programmable operation-cycle length. This is valuable in tailoring the DMA to the particular requirements of other system components (fast or slow) and maximizes the data-transfer rate. It also eliminates external logic for signal conditioning. There are two aspects to the variable cycle feature. First, the entire read and write cycles (periods) associated with the source and destination ports can be independently programmed as 2, 3, or 4 Tcycles long (more if Wait cycles are used), thereby increasing or decreasing the speed with which all DMA signals change (Figure 5). Second, the four signals in each port specifically associated with transfers of data (I/O Request, Memory Request, Read and Write) can each have its active trailing edge terminated one-half T-cycie early. This adds a further dimerision of flexibility and speed, allowing such things as shorter-than-normal Read or Write signals that go Mractive before data starts to change. Address Generation. Two 16-bit addresses are generated by the Z80 DMA for every transfer operation, one address for the source port and another for the destinatign port. Each address can be either variable or fixed. Variable addresses can increment or decrement fram the programmed starting address. The fixed-address capability eliminates the need for separate enabling wires to I/O ports. Port addresses are multiplexed onto the system address bus, depending on whether the DMA is reading the source port or writing to the destination port. Two readable address counters (2 bytes each) keep the current address of each port. Auto Restart. The starting addresses of either port. can be reloaded automatically at the end of a block. This aption is selected by the Auto Restart control bit. The byte counter is cleared when the addresses are reloaded. The Auto Restart feature relieves the CPU of software overhead for repetitive operations such as CRT refrdsh and many others. Moreover, when the CPU has access to the buses during byte-at-a-time or burst transfers, different starting addresses can be written into buffer registers during transfers, causing the Auto Restart to begin at a new location. Interrupts. The Z80 DMA can be programmed to imterrupt the CPU on four conditions: Interrupt on Ready (before requesting bus) @ Interrupt on Match . @ Interrupt on End of Block @ Interrupt on Match and End of Block Any of these interrupts causes an interrupt-pending status bit to be set, and each of them can optionally alter the DMA's interrupt vector. Due to the buffered constraint mentioned under Modes of Operation, interrupts on Match atl End of Block are caused by matches to the byte just prior tolthe last byte in the block. j~ 1 |< Ta >|< 13 >| T >| ' ' +zcvcLe}-| EARLY ENDING a.cvcLe + FOR CONTROL SIGNALS < 4-cCLe _______}| Figure 5. Variable Cycle LengthThe DMA shares the Z80 Family's elaborate interrupt scheme, which provides fast interrupt service in real-time applications. In a Z80 CPU environment, the DMA passes its internally modifiable 8-bit interrupt vector to the CPU, which adds an additional eight bits to form the memory address of the interrupt-routine table. This table contains the address of the beginning of the interrupt routine itself. In this process, CPU control is transferred directly to the interrupt routine, so that the next instruction executed after an interrupt acknowledge is the first instruction of the interrupt routine itself. Pulse Generation. External devices can keep track of how many bytes have been transferred by using the DMA's pulse output, which provides a signal at 256-byte intervals. The interval sequence may be offset at the beginning by 1 to 255 bytes. The Interrupt line outputs the pulse signal in a manner that prevents misinterpretation by the CPU as an interrupt request, since it only appears when the Bus Request and Bus Acknowledge lines are both active. PIN DESCRIPTION Ap-A15. System Address Bus (output, 3-state). Addresses generated by the DMA are sent to both source and destination ports (main memory or I/O peripherals) on these lines. BAI. Bus Acknowledge In (input, active Low). Signals that the system buses have been released for DMA control. In multtiple-DMA configurations, the BAI pin of the highest priority DMA is normally connected to the Bus Acknowledge pin of the CPU. Lower-priority DMAs have their BAT connec- ted to the BAO of a higher-priority DMA. BAO. Bus Acknowledge Out (output, active Low). In a multiple-DMA configuration, this pin signals that no other higher-priority DMA has requested the system buses. BAI and BAO form a daisy chain for multiple-DMA priority resolution over bus control. BUSREQ. Bus Request (bidirectional, active Low, open- drain). As an output, it sends requests for control of the system address bus, data bus, and control bus to the CPU. As an input when multiple DMAs are strung together in a priority daisy chain via BAT and BAO, it senses when another DMA has requested the buses and causes this DMA to refrain from bus requesting until the other DMA is finished. Because it is a bidirectional pin, there cannot be any buffers _ between this DMA and any other DMA. It can, however, have a buffer between it and the CPU because it is unidirectional into the CPU. A pull-up resistor is connected to this pin. CE/WAIT. Chip Enable and Wait (input, active Low). Normally this functions only as a CE line, but it can also be programmed to serve a WAIT function. As a CE line from the CPU, it becomes active when WR or RD andIORQ are ac- tive and the I/O port address on the system address bus is the DMA's address, thereby allowing a transfer of control, command bytes from the CPU to the DMA, or status bytes from the DMA to the CPU. As a WAIT line from memory or VO devices, after the DMA has received a bus-request acknowledge from the CPU, it causes wait states to be inserted in the DMA's operation cycles thereby slowing the DMA to a speed that matches the memory or I/O device. CLK. System Clock (input). Standard Z80 single-phase clock. Do-D7. System Data Bus (bidirectional, 3-state). Commands from the CPU, DMA status, and data from memory or 1/0 peripherals are transferred on these lines. IE. Interrupt Enable in (input, active High). This is used with IEO to form a priority daisy chain when there is mote than one interrupt-criven device. A High on this line indicates that no other device of higher priority is being serviced by a CPU interrupt service routine. IEO. interrupt Enable Out (output, active High). EO is High only if tl is High and the CPU is not servicing an interrupt- from this DMA. Thus, this signal blocks lower-priority devices from interrupting while a higher-priority davice is _being serviced by its CPU interrupt service routine. INT/PULSE. interrupt Request (output, active Low, open- drain). While the CPU is the bus master, this output requests a CPU interrupt. The CPU acknowledges the interrupt by pulling its IORQ output Low during an M1 cycle. It is typically connected to the INT pin of the CPU with a pullup resistor and tied to all other INT pins in the system. This pin can also be used to generate periodic pulses to an mere device when the DMA is bus master (i.e., the CPU's B SREQ and BUSACK lines are both Low and the CPU cannot see interrupts). While the DMA is the bus master, this outout can be programmed to pulse each time 256 transfers have occurred. | TORQ. Input/Output Request (bidirectional, active Low, 3-state). As an input, this indicates that the lower half of the address bus holds a valid /O port address for transfer of contro! or status bytes from or to the CPU, respectivaly; this DMA is the addressed port if its CE pin and its WR or RD pins are simultaneously active. As an output, after the DMA has taken control of the system buses, it indicates that the lower half of the address bus holds a valid port address for another I/O device involved in a DMA transfer of data. When IORQ andM1 are both active simultaneously, an interrupt acknowledge is indicated. MT. Machine Cycle One (input, active Low). Indicates that the current CPU machine cycle is an instruction fetch. It is used by the DMA to decode the return-from-interrupt instruction (RETI, ED-4D) sent by the CPU. During two-byte instruction fetches, M7 is active as each opcode byte is fetched. An interrupt acknowledge is indicated when both M1 and IORQ are active. On CMOS DMA, M1 signal has another function. When Mi occurs without an active RD or (GRO for at least two clock cycles, the DMA is respt. 45MREQ. Memory Request (output, active Low, 3-state). This indicates that the address bus holds a valid address for a memory read or write operation. After the DMA has taken control of the system buses, it indicates a DMA transter request from or to memory. RD. Read (bidirectional, active Low, 3-state). As an input, this indicates that the CPU wants to read status bytes from the DMAs,read registers. As an output, after the DMA has taken control of the system buses, it indicates a DMA-controlled read from a memory or I/O port address. RESET. Reset (CMOS PLCC version only: input, active Low). A low on this line resets the DMA. RDY. Ready (input, programmable active Low or High). This is monitored by the DMA to determine when a peripheral device associated with a DMA port is ready for a read_or write operation. Depending on the mode of DMA operation (Byte, Burst, or Continuous), the RDY line indirectly controls DMA activity by causing the BUSREQ line to go Low or High. . WR. Write (bidirectional, active Low, 3-state). As an input, this indicates that the CPU wants to write control or command bytes to the DMA write registers. As an output, after the DMA has taken control of the system buses, it indicates a DMA-controlled write to a memory or I/O port address. INTERNAL STRUCTURE The internal structure of the Z80 DMA includes driver and receiver circuitry for interfacing with an 8-bit system data bus, a 16-bit system address bus, and system control lines (Figure 6). Ina 280 CPU environment, the DMA can be tied directly to the analogous pins on the CPU (Figure 7) with no additional buffering, except for the CE/WATT line. The DMASs internal data bus interfaces with the system data . bus and services all internal logic and registers. Addresses generated from this logic for Ports A and B (source and destination) of the DMAs single transfer channel are multiplexed onto the system address bus. Specialized logic circuits in the DMA are dedicated to the various functions of external bus interfacing, internal bus control, byte matching, byte counting, periodic pulse generation, CPU interrupts, bus requests, and address generation. A set of 21 writable control registers and seven readable status registers provides the means by which the CPU. governs and monitors the activities of these logic circuits, All registers are eight bits wide, with double-byte information stored in adjacent registers. The two address counters (two bytes each) for Ports A and B are buffered by the two starting addresses. The 21 writable control registers are organized into seven base-register groups, most of which have multiple registers. The base registers in each writable group contain both controlicommand bits and pointer bits that can be set to address other registers within the group. The seven readable status registers have no analogous second-level registers. The registers are designated as follows, according to their base-register groups: WRO-WR6Write Register groups O through 6 (7 base registers plus 14 associated registers) RRO-RR6Read Registers 0 through 6 Writing to a register within a write-register group involves first writing to the base register, with the appropriate pointer bits set, then writing to one or more of the other registers within the group. All seven of the readable status registers are accessed sequentially according to a programmable mask contained in one of the writable registers. The section entitled Programming explains this in more detail. A pipelining scheme is used for reading data in. The programmed block length is the number of bytes compared to the byte counter, which increments at the end of each cycle. in searches, data byte comparisons with the match byte are made during the read cycle of the next byte. Matches are, therefore, discovered only after the next byte is read in. PULSE Logic INTERRUPT AND BUS PRIORITY Loaic BYTE COUNTER PORTA ADDRESS tn <tr BUS INTERNAL BUS SYSTEM DATA ( {8-BiT) is SYSTEM ADDRESS Mi) Bus (16-BIT) CONTROL Bus AND CONTROL CONTROL STATUS LoGic REGISTERS Ls BYTE ADORESS MATCH LOGIC Figure 6. Block Diagram 46COMMON: iNT BUSREQ BUSACK CPU mM iOnG MREG ao ' WR CLK iN commot hows Do-7 SYSTEM BUSES COMMON COMMON DECODER Cewait __ ._ CEWAIT Lt BAI BAO BAI . BAO F- TO NEXT DMA OMA OMA FROM HIGHER-PRIORITY et 10 \er 1EO | TO LOWER-PRIORITY INTERRUPTING DEVICE INTERRUPTING DEVICE ROY ROY FROM FROM vo vO DEVICE OEVICE Figure 7. Multiple-DMA Interconnection to the Z80 CPU In muitiple-DMA configurations, interrupt-request daisy chains are prioritized by the order in which their IEl and IEO lines are connected. The system bus, however, may not be pre-empted. Any DMA that gains access to the system buses keeps them until it is finished. Read Registers RRO Status byte RR1 Byte counter (low byte) RR2 Byte counter (high byte) RR3 Port A address counter (low byte) RR4 Port A address counter (high byte) RR5 Port B address counter (low byte) RR6 Port B address counter (high byte) Write Registers WRO WR1 WR2 WR3 WR4 WRS WR6 Base register byte Port A starting address (low byte) Port A starting address (high byte) Block length (low byte) Block length (high byte) Base register byte Port A variable-timing byte Base register byte Port B variable-timing byte Base register byte Mask byte Match byte Base register byte ' Port B starting address (low byte) Port B starting address (high byte) Interrupt control byte Pulse control byte Interrupt vector Base register byte Base register byte Read mask 47PROGRAMMING The Z80 DMA has two programmable fundamental states: (1) an enabled state, in which it can gain control of the system buses and direct the transfer of data between ports, and (2) a disabled state, in which it can initiate neither bus requests nor data transfers. When the DMA is powered up or reset by any means, it is automatically placed into the disabled state. Program commands can be written to it by the CPU in either state, but this automatically puts the DMA in the disabled state, which is maintained until an enable commiandis issued by the CPU. The CPU must program the DMA in advance of any data search or transfer by addressing it as an I/O port and sending a sequence of control bytes using an Output instruction (such as OTIR for the Z80 CPU). Reading. (Figure 8a) The Read Registers (RRO-RR6) are read by the CPU by addressing the DMA as an I/O port using an Input instruction (such as INIR for the Z80 CPU). The readable bytes contain DMA status, byte-counter values, and port addresses since the last DMA reset. The registers are always read in a fixed sequence beginning with RRO and ending with RR6. However, the register read in this sequence is determined by programming the Read Mask in WRE6. The sequence of reading is initialized by writing an Initiate Read Sequence or Set Read Status command to WRE. After a Reset DMA, the sequence must be initialized with the Initiate Read Sequence command or a Read Status command. The sequence of reading all registers that are not excluded by the Read Mask register must be completed before a new Initiate Read Sequence or Read Status command. Writing. Control or command bytes are written into one or more of the Write Register groups (WRO-WRE6) by first writing to the base register byte in that group. All groups have base tegisters and most groups have additional associated registers. The associated registers in a group are sequentially accessed by first writing a byte to the base register containing register-group identification and pointer bits (1's) to one or more of that base registers associated registers. READ REGISTER O D, De O; D, D; Dz, 0, Dy STATUS BYTE | L_. 1 = DMA TRANSFEA HAS OCCURRED 0 = READY ACTIVE 0 = INTERAUPT PENDING 0 = MATCH FOUND O= END OF BLOCK READ REGISTER 1 This is illustrated in Figure 8b. In this figure, the sequence in which associated registers within a group can be written to is shown by the vertical position of the associated ragisters. For example, if a byte written to the DMA contains the bits that identify WRO (bits D0, D1 and D7), and also contains 1's in the bit positions that point to the associated Port A Starting Address (low byte) and Port A Starting Address (high byte), then the next two bytes written to the DMA will be stored in that order in these two registers. Fixed-Address Programming. A special circumstance arises when programming a destination port to have a fixed address. The load command in WR6 only loads a fixed address to a port selected as the source, not to a port selected as the destination. Therefore, a fixed destination address must be loaded by temporarily declaring it a fixed-source address and subsequently deciaring the true source as such, thereby implicitly making the other a destination. The following example illustrates the steps in this procedure, assuming that transfers are to occur from a variable-address source (Port A) to a fixed-address destination (Port B): 1. Temporarily declare Port B as source in WRO. 2. Load Port B address with LOAD command to WR6. 3. Declare Port A as a source in WRO. 4. Load Port A address with LOAD command to WR6. 5. Enable DMA in WR6. Figure 9 illustrates a program to transfer data from memory (Port A) to a peripheral device (Port B). In this example, the Port A memory starting address is 1050), and the Port B peripheral fixed address is 05,4. Note that the data flow is 1001}, bytesone more than specified by the block length. The table of DMA commands may be stored in consecutive memory locations and transferred to the DMA with an output instruction such as the Z80 CPU's OTIR instruction. READ REGISTER 2 READ REGISTER 3 CLITIIITL]) PORT A ADDRESS COUNTER (LOW BYTE) READ REGISTER 4 CLLILTLLELI4 PORT A ADDRESS COUNTER (HIGH BYTE) READ REGISTER 5 CLTIIITILI] PORT 8 ADDRESS COUNTER (LOW BYTE) READ REGISTER 6 CLITITIIL 4) PORT B ADDRESS COUNTER (HIGH BYTE) Figure 8a. Read RegistersWRITE REGISTER 0 GROUP BASE REGISTER BYTE 0 O00 NOT USE CH 1 = SEARCH/TRANSFEA 0 = PORT B PORTA 1 = PORT A -- PORT B (LOW BYTE) {HIGH BYTE) SLOCK LENGTH (LOW BYTE) BLOCK LENGTH (HIGH BYTE) WRITE REGISTER 1 GROUP D, 0, O, Dy Dy Dz Dy Oy WA ENDS % CYCLE EARLY = 0 | AD ENOS % CYCLE EARLY =0 MREQ ENDS % CYCLE EARLY = 0 BASE REGISTER BYTE | 0 = PORT AIS MEMORY Y= = PORT A ADDRESS DECREMENTS 1 0 1 PORT AIS UO = PORT A ADDRESS INCREMENTS | = PORT A ADDRESS FIXED | | __] PORT A VARIABLE TIMING BYTE @ = CYCLE LENGTH 1 = CYCLE LENGTH o=Cc 1s YCLE LENGTH = 2 DO NOT USE 0 = 1ORG ENDS : CYCLE EARLY WRITE REGISTER 2 GROUP 0, 0 D, D 0, D, 0, DB [0 | | o | 0 | 0 [ease neaistER BYTE WR ENDS % CYCLE EARLY =0 RD ENOS % CYCLE EARLY = 0 ENDS % CYCLE EARLY = 0 = PORT B IS MEMORY = PO! RT BIS VO 0 PORT 8 ADDRESS DECREMENTS 1 = PORT B ADDRESS INCREMENTS o 1 | = PORT B ADORESS FIXED 1 = CYCLE LENGTH = 3 0 = CYCLE LENGTH = 2 1 DO NOT USE 9 = iORO ENDS % CYCLE EARLY @ O = CYCLE LENGTH = 4 0 1 1 WRITE REGISTER 3 GROUP D, 0, 0; DB O DMA ENABLE = 1 | INTERRUPT ENABLE = 1 DO, 0, D, BASE REGISTER BYTE 1 = STOP ON MATCH MATCH BYTE PORT A STARTING ADDRESS PORT A STARTING ADORESS PORT B VARIABLE TIMING BYTE MASK BYTE (0 = COMPARE) WRITE REGISTER 4 GROUP 0, 0, DO, D, 0, 0, 0, O | o | + ] Base Recister eyte @YTE = CONTINUOUS = 0 BURST = 1 DO NOT PROGRAM = 1 2o4~0- PORT B STARTING ADORESS (LOW BYTE) PORT B STARTING ADDRESS (HIGH BYTE) INTERRUPT CONTROL BYTE = INTEARUPT AT END OF BLOCK | 1 = INTERRUPT ON MATCH 1 PULSE GENERATED INTERRUPT ON ROY = 14 | STATUS AFFECTS VECTOR = 1 1 PULSE CONTROL BYTE INTERRUPT VECTOR = INTERAUPT ON ROY 1 = INTERRUPT ON MATCH 0 = INTERRUPT ON END OF BLOCK 1. = INTERRUPT ON MATCH AND ENO OF BLOCK MODIFIED AS SHOWN IF STATUS VECTOR IS AUTOMATICALLY | Qo 0 ONL { 1 AFFECTS VECTOR" BITIS SET \1 WRITE REGISTER 5 GROUP 0, fs fo] [0] 1] 0 | ase necisTER avTe READY ACTIVE LOW READY ACTIVE HIGH INLY al rm 1o : WRITE REGISTER 6 GROUP 0, 0, DB; Dy 0, Or 0, Dy BASE REGISTER BYTE | | | | | MEX COMMAND NAME 1 0 6 O 0=C3 = RESET 1 8 0 1 = C7 = RESET PORT A TIMING 1 @ O +14 0 = CB = RESET PORT 6 TIMING 10 0 1 1=CF =LOAD 1 6 1 0 = 03 = CONTINUE 0 1 0 1 1 AF = DISABLE INTERRUPTS 1 0 1 O= AB = ENABLE INTERRUPTS 0 t = A3 = RESET AND DISABLE INTERRUPTS 6 141 #O 1 = 87 = ENABLE AFTER RET! 0 1 = 1 = 1 1 = BF = READ STATUS BYTE 0 0 1 0 = 88 = REINITIALIZE STATUS BYTE 0 1 0 0 1 = A? = INITIATE READ SEQUENCE 0 4 = 4 0 = B3 = FORCE READY 0 6 0 1 = 87 = ENABLE DMA 0 0 0 @ 0 = 83 = DISABLE DMA @ 1 #1 1 @ = BB = READ MASK FOLLOWS | L STATUS BYTE BYTE COUNTER (LOW @YTE) SYTE COUNTER (HIGH BYTE) PORT A ADDRESS (LOW BYTE) PORT A ADDRESS (HIGH BYTE) PORT 6 ADDRESS {LOW BYTE) PORT B ADDRESS (HIGH BYTE) Figure 8b. Write Registers 49wes5oig YING a[dwes * enbig SSJPPe UO!JEUNSAP Pax) & JO aSed ay) Ul AfUd AJeSSad9U ae SalJJUa Asal, yiBua yOO1q a4) Aq paiyioeds UeY) e10W BUC Ss! P|ss9}SUes) SA}AQ JO JaquUNU JeNNOe aul -JLON uotj}eiado 8 L L t 0 o 0 0 L WEIS O1 YW SAIQeUs SYM JAJUNDD 490/q S]asa. pue do 1 t I 4 0 0 t t ssaippe HOY Speo] SYM salhg yiBue7 Yoseag ON JaSuBLL gq=at y 490\g 10 SSauppy ON so t 0 t 9 0 0 0 0 + DINOS SB Y JO S18S OHM 19]UNOD Y90Ig S}asas pue dO 1 4 1 t 0 0 t L SSOJPPe g Og SPO) SYM UBIH aAnoy sales Vesey AQH veM ON ony ON ve 0 L 0 t 0 0 . 0 t y6IH aaloe Apeay sias GYM so b 0 b 0 0 0 0 0 (amo}) ssaippe g 10d SMOjIO4 SMO]OZ ssauppy ssauppy ajAg {ouuCD apow ising ssaippe JaMO7] Gg WOd saddn on ydnsaju] ON @ Og Joadxa 0) YING SI9s $9 \ 0 0 0 0 t |SING 0} POW SI@S PHM Oli ssauppy SMO}IO4 ssappe S| WOd pexig Built ON Pexi, Ulm jeraydiued 82 0 0 0 0 t oO 0 SB g W0d SaUuijap CHM Asoweayy SluawasouU| seBueyd SMO}IO4 ssauppe Buruawaiour SI Og ssalppy sseuppy Burm, ON paxiy uj Aouad vt 0 oO { 0 L 0 . 0 Q Se Y 10d SaUuljap LHM OL 0 0 0 0 0 0 0 (saddn) y6ua] 4901g 00 0 0 0 0 0 0 0 0 (Jamo) yy6ua} 401g ol 0 0 0 0 b 0 ie} 0 (uaddn) ssauppe y Woy os 0 0 0 0 I 0 b 0 (lamoj) ssauppe y Og SSOIPpY g 6uipeo} SMO||O4 SMO}104 . 104 ssauppy ssaippy SMO}IO3 SMmO}|IO4 Q0JNOS SB G Og Silas HOSBSS ON 119jSUEIL Asesodwa JaMO7 saddn JOMO] jaddn Ajuesodusa} pue ssazppe Bui V~=ta VW Od udog yyBue7z 40019 uj6ua7 4o01g Yeys y Og Yy6ua; 4901q 62 + 0 0 L t I t 0 8A19981 0] VYING S18S OM X3H %q g i) &q va sq 8q 4q syUEWIWODINACTIVE STATE TIMING (DMA as CPU Peripheral) In its disabled or inactive state, the DMA is addressed by the CPU as an I/O peripheral for write and read (control and status) operations. Write timing is illustrated in Figure 10. Reading of the DMA's status byte, byte counter, or port address counters is illustrated in Figure 11. These Figure 10. CPU-to-DMA Write Cycle operations require less than three Fcycles. The CE, IORQ, and RD lines are made active over two rising edges of CLK, and data appears on the bus approximately one Tcycle after they become active. JU LPL $e CLA cE a fone a 5D ry - Figure 11. CPU-to-DMA Read Cycle ACTIVE STATE TIMING (DMA as Bus Controller) Default Read and Write Cycles. By default, and after reset, the DMAs timing of read and write operations is exactly the same as the Z80 CPU's timing of read and write cycles for memory and 1/O peripherals, with one exception: during a read cycle, data is latched on the falling edge of T3 and held on the data bus across the boundary between read and write cycles, through the end of the following write cycle. Figure 12 illustrates the timing for memory-to-I/O port transfers and Figure 13 iliustrates 1/O-to-memory transfers. ~t MEMORY READ Memory-to-memory and [/O-to-i/O transfer timings are simply permutations of these diagrams. The default timing uses three T-cycles for memory transactions and four Fcycles for /O transactions, which include one automatically inserted wait cycle (Twa) between Ty and T3. Ifthe CE/WATT line is programmed to act as a WAIT line during the DMAs active state, it is sampled on the falling edge of Tz for memory transactions and the falling edge of Twa for I/O transactions. If CE/WAIT is Low during this time, another T-cycle is added, during which the UO WRITE \ [Ty Rois 7) a wre] [ wo | \ / peor Hameo DATA BUS DRIVEN BY DMA cera TOTTI od fms cas om hes or =F TTT I ~ sy pe ee te wee ff | A Figure 12. Memory-to-I/O Transfer 51CEMAIT line will again be sampled. The duration of transactions can thus be indefinitely extended. Variable Cycle and Edge Timing. The Z80 DMAs default operation-cycle length for the source (read) port and destination (write) port can be independently programmed. This variable-cycle feature allows read or write cycles consisting of two, three, or four T-cycles (more if Wait cycles are inserted), thereby increasing or decreasing the speed of all signals generated by the DMA. In addition, the trailing edges of the IORQ, MREQ, RD; and WR signals can be independently terminated one-half cycle early. Figure 14 illustrates this. In the variable-cycle mode, unlike default timing, [ORQ comes active one-half cycle before MREQ, RD, and WR. CE/MAIT can be used to extend only the 3 or 4 T-cycle variable memory cycles and only the 4-cycle variable 1/O cycle. The CE/WAIT line is sampled at the falling edge of To for 3- or 4-cycle memory cycles, and at the falling edge of T3 for 4-cycle I/O cycles. : , WO READ CLK 1 | Te | Tw | Ts | Ty | ot | 13 During transfers, data is latched on the clock edye causing the rising edge of RD and held until the end of the write cycie. Bus Requests. Figure 15 illustrates the bus request and acceptance timing. The RDY fine, which may be programmed active High or Low, is sampled on every rising edge of CLK. Ifitis found to be active and if the bus is not in use by any other device, the following rising edge of CLK drives BUSREQ Low. _After receiving BUSREG, the CPU acknowledges on the BAI input either directly or through a multipte-DMA daisy chain. When a Low is detected on BAI for two consecutive rising edges of CLK, the DMA will begin transferring data on the next rising edge of CLK. Bus Release Byte-at-a-Time. in Byte-at-a-Time mode, BUSREQ is brought High on the rising edge of CLK prior to the end of each read cycle (search-only) or write cycle (transfer and transfer/search) as illustrated in Figure 16. This is done regardless of the state of RDY. There is no possibility of confusion when a Z80 CPU is used since the CPU cannot | MEMORY WRITE | , Bods IA iona \ READ Do-D7z UO DRIVES DATA OMA DRIVES DATA BUS \ fy E--L_-U Y-- 4-7 YL. C7 Figure 13. 1/O-to-Memory Transfer ACTIVE Ao-Ais X i ROY i r wTF wr \ Og sUSREG i weg sn lo sey RG , Wi ea pa , t 2-CYCLE a-CYCLE 4CYCLE EARLY ENO EARLYEND EARLY ENO Figure 14. Variable-Cycle and Edge Timing DMA DMA INACTIVE |" ACTIVE Figure 15. Bus Request and Acceptance 2begin an operation until the following Fcycle. Most other CPUs are not bothered by this either, although note should be taken of it. The next bus request for the next byte will come after both BUSREQ and BAT have returned High. Bus Release at End of Block. In Burst and Continuous modes, an end of block causes BUSREQ to go High, usu- ally on the same rising edge of CLK in which the DMA completes the transfer of the data block (Figure 17). The last byte in the block is transferred even if RDY goes inactive before completion of the last byte transfer. Bus Release on Not Ready. In Burst mode, when RDY goes inactive it causes BUSREQ to go High on the next rising edge of CLK after the completion of its current byte operation (Figure 18). The action on BUSREQ is thus somewhat delayed from action on the RDY line. The DMA always completes its current byte operation in an orderly fashion before releasing the bus. By contrast, BUSREQ is not released in Continuous mode when RDY goes inactive. Instead, the DMA idles after completing the current byte operation, awaiting an active RDY again. Bus Release on Match. If the DMA is programmed to stop ~ on match in Burst or Continuous modes, a match causes BUSREQ to go inactive on the next DMA operatin, i.e., at the end of the next read in a search or at the end of the following write in a transfer (Figure 19). Due to the pipelining scheme, matches are determined while the next OMA read or write is being performed. The RDY line can go inactive after the matching operation begins without affecting this bus-release timing. interrupts. Timings for interrupt acknowledge and return from interrupt are the same as for the other Z80 peripherals. Interrupt on RDY (interrupt before requesting bus) does not directly affect the BUSREQ line. instead, the interrupt service routine must handle this by issuing the following commands to WR6: 1. Enable after Return From (RETI) CommandHex B7 2. Enable DMAHex 87 3. An RETI instruction that resets the Interrupt Under Service latch in the Z80 DMA. interrupt DMA ACTIVE >} DMA INACTIVE Figure 16. Bus Release (Byte-at-a-Time Mode) INACTIVE BUSREQ LAST BYTE | t-- OPERATION IN BLOCK INACTIVE Figure 17. Bus Release at End of Block (Burst and Continuous Modes)cLK | | f ACTIVE RDY INACTIVE BUSREQ |-cunsens BYTE ; OPERATION st eerivE Figure 18. Bus Release When Not Ready (Burst Mode) e TLL LLL, ACTIVE oS fo Too howe ele RDY L INACTIVE Ifa BUSREQ Sf BYTE yo BYTEn+1 READ oe READ IN AND INACTIVE MATCH FOUND ON BYTEn Figure 19. Bus Release on Match {Burst and Continuous Modes)ABSOLUTE MAXIMUM RATINGS Voltages on Voc with respect to Vsg ..... -0.3V to +7.0V Voltages on all inputs with respect toVgg oe eee 0.3V to Voc + 0.3V Storage Temperature.............. -65C to + 150C Stresses greater than those listed under Absolute Maximum Ritings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the Operational sections of these specifications is not implied. Exposure to absolute maximum tating conditions for extended periods tay affect device reliability. STANDARD TEST CONDITIONS The characteristics below apply for the following test conditions, unless otherwise noted. All voltages are referenced to GND (OV). Positive current flows into the referenced pin. Available operating temperature range is: a S=0C to +70C, V., Range NMOS: +4.75V S Voc $+5.25V CMOS: +4.50V SV,,.S+5.50V m E=-40C to 100C, +4.50V <V,, $+5.50V 2.1K FROM OUTPUT UNDEA TEST 250 100 pt | aA DC CHARACTERISTICS (z84C10 / CMOS Z80 DMA) Symbol Parameter Min Max Typ =s*sUnit_~s Test Condition Vitc Clock Input Low Voltage ~0.3 +0.45 V * Vin Clock Input High Voltage Voc - 0.6 Voc +0.3 Vv Vit Input Low Voltage -0.3 +08 Vv Vin Input High Voltage +2.2 Vec Vv Vor Output Low Voltage +0.4 Vv lo = 2.0mA VoH; Output High Voltage +2.4 Vv lon = 1.6mA VoH Output High Voltage Voc - 0.8 / V lon = 250 pA i] Input Leakage Current +10 pA Vin = 0.4 to Veo lLo * 3-State Output Leakage Current in Float +10 pA Vout = 0.4 to Vee ICC} Power Supply Current 25/35 mA Voc = 5V CLK = 6/8MHz Vic = ViH = Vee 0.2V Vitc = 0.2V ICCo Standby Supply Current 10 0.5 HA Voc = 5V CLK = (0) Vic = Vin = Vee - 0.2 Vicc = Vit = 0.2V Over specified temperature and voltage range. CAPACITANCE Symbol! Parameter Min Max Unit Cc Clock Capacitance 5 pf Cin Input Capacitance 5 pf Court . ~Output Capacitance 10 pf NOTES: Over specified temperature range; f = MHz. Unmeasured pins returned to ground. 55AC CHARACTERISTICS (z84C10 / CMOS Z80 DMA) (Inactive State) : CLK 2,-D, INTERRUPT CONDITION ACTIVE INACTIVE NOTE: Signals in this diagram bear no relation to one another unless specifically noted as a numbered item.AC CHARACTERISTICS (26410 / NMOS Z80 DMA) (inactive State) 20841004 Number Symbol Parameter Min Max Unit 1 TeC Clock Cycle Time 250 4000 ns 2 TwCh Clock Width (High) 110 = 2000 ns 3 TWh Clock Width (Low) 110 2000 ns 4 TC Clock Rise Time 30 ns 5 TIC Clock Fall Time 30 ns 6 Th Hold Time for Any Specified Setup Time 0 ns 7 TsC(Cr) TORG, WR, CE 4 to Clock t Setup 145 ns 8 TaDQ(RDA RO $ to Data Output Delay 380 ns 9 TsDK(Cr) Data In to Clock t Setup (WR or M1) 50 ns 10 TdADOION TORG 4 to Data Out Delay (INTA Cycle) 160 ns 1 TdROr(Dz) RD + to Data Float Delay (output buffer disable) 110 ns 12 TsIEI(IORQA) IE! to IORQ Setup (INTA Cycle) 140 ns 13 TdlEOr(lElr) IEI t to EO t Delay 160 ns 14 TdlEOKIEI) IE # to IEO + Delay . 130 ns 15 TdM 1f(IEOA Mi 4 to IEO 4 Delay (interrupt just prior to MT 4) 190 ns 16 TsM14(Cr) MT 4 to Clock t Setup 90 ns 17 TsM11(Cf) M1 t to Clock Setup -10 ns 18 TsRO((Cr) RD 4 to Clock t Setup (MT Cycle) 115 ns 19 TdKINTA , interrupt Cause to INT # Delay (INT generated . only when DMA is inactive) 500 ns 20 TdBAIr(BAOr) BAT t to BAO Delay 150 ns 21 TABAI(BAO) -BAT_ 4 to BAO 4 Delay 150 ns 22 TsRDY(Cr) RDY Active to Clock t Setup 100 ns NOTE: Negative minimum setup values mean that the first-mentioned event can come after the second-mentioned event.AC CHARACTERISTICS (Z84C10 / CMOS Z80 DMA) (Active State) -BRYDIANANADRADRS Ao-Ais lf a [+ @ ~ |X Do-b7 +1 +- Ti fe | +@ ourrur x i Hat @ t 3 SN Z 3 b o ae t 24 e[ : g a ey CDS a X NOTE: Signals in this diagram bear no relation to one another unless specitically noted as a numbered item. Z84C1006+ t Z84C1008 tt Number Symbol Parameter Min(ns) Max(ns) 1 TcC Clock Cycle Time 162 DC 125 bc 2 TwCh Clock Width (High) 65 DC 55 DC 3 Wel Clock Width (Low) 65 DC 55 DC 4 rc Clock Rise Time 20 10 5 TIC Clock Fall Time 20 10 NOTES: For clock periods other than the minimums shown, calcutate Parameters using the following table. + Calculated values above assumed TrC = TIC = 20ns (6 MHz version) or 10ns (8 MHz version). t Data must be enabled onto data bus when RD is active. * Parameter is not illustrated in the AC Timing Diagrams.AC CHARACTERISTICS (284C10 / CMOS Z80 DMA) (Active State) 284C 1006 Z84C 1008 Number Symbol Parameter Min(ns) Max(ns) = Min(ns) Max(ns) 6 TdA Address Output Delay 90 70 7 TdC(Az) Clock t to Address Float Delay 80 70 8 TsA(MREQ) Address to MREQ + Setup(Memory Cycle) 35 354 9 TsA(IRW) Address Stable to (ORO, RD,WR+Setup 1104 70# (VO Cycle) "10 TdRW(A) RD, WR t to Addr. Stable Delay 35t 15 4 TdRW(Az) RD, WR # to Addr. Fioat 60t 45+ 12 TdCKDO) Clock to Data Out Delay 130 110 *13 TdCxD2) Clock t to Data Float Delay (Write Cycle) 70 65 14 TsDI(Cr) Data In to Clock t Setup (Read cyclewhen 30 25 fising edge ends read) 15 TsDICH Data In to Clock 4 Setup (Read cyclewhen 40 falling edge ends read) 30 16 TsDO(WiM) Data Out to WR + Setup (Memory Cycle) 45". 408": 17 TsDO(Wfl) Data Out to WR 4 Setup (1/0 cycle) 55 40 "48 Tdwr(DO) WR t to Data Out Delay / 30t 10 19 Th Hold Time for Any Specified Setup Time 0 v 20 TdCiMf) Clock t to MREQ 4 Delay 70 60 21 TdC(Mh Clock + 1o MREQ 4 Delay 70 60 22 TdC(Mp Clock t to MREQ 1 Delay 70 60 23 TdCKMn) Clock | to MREQ t Delay 70 60 24 wm! MREG Low Pulse Width 135 95+ *25 TwMh MRE High Pulse Width 65t 454 26 TACKIf Clock 4 to FORG # Delay 70 60 27 TdCi(if) Clock t to TORG # Delay 65 55 28 TdCKir) Clock t to IORQ Delay 70 60 *29 TACK in) Clock 4 to TORO t Delay 70 60 30 TACK Clock t to RD $ Delay 70 60 31 TACKRA Clock $ to RD + Delay 80 70 32 TaCKRe) Clock t to RD t Delay 70 60 33 TdCK(Rr) Clock + to RD t Delay 70 60 34 TdCr(wh) Clock t to WR + Delay 60 55 35 TACKwh) Clock + to WR + Delay 70 60 36 TdCrwn Clock t to WR t Delay 70 60 37 Tdci(wr) Clock } to WR t Delay 70 60 38 Twwl WR Low Pulse Width 135 95 39 TsWA(Ch) WATT to Clock + Setup 60 50 40 TaCKB) Clock t to BUSREQ Delay 90 80 41 TdCr(iz) Clock t to TORQ, MREQ, AD, WR Float Delay 70 70 NOTES: + Al AC equations imply DMA defautt (standard) timing. + Data must be enabled onto data bus when RD is active. * Parameter is not Mlustrated in the AC Timing Diagrams. set-up time with respect to 1. From Figure 13, data is latched onto the bus by the rising edge of RD signal. These values are the Searadoriced minimum data out L. 59FOOTNOTES TO AC CHARACTERISTICS Number Symbol General Parameter Z84C1006 284C1008 8 TsA(MREQ) TwCh - TiC -35 -30 9 TsA(IRW) Tc -55 -55 10 TdRW(A) TwCl - TrC -50 -50 W TdRW(Z) TwC! - TrC -25 -20 16 TsDO(WIM) TeC -140 -120 18 TdWr(DO) TwCl - TrC -55 -55 24 TwM1 ToC -30 -30 25 TwMh TwCh - TIC -20 -20 38 TwWi TeC -30 -30DC CHARACTERISTICS (28410 NMOS Z80 DMA) Voe=5.0V + 10%, unless otherwise specified Sym Parameter Min Max Unit Test Condition Vec Clock Input Low Voltage 0.3 0.45 V Vatc Clock Input High Voltage Vog7 6 5.5 Vv Ve Input Low Voltage -0.3 0.8 Vv Va Input High Voltage 2.0 5.5 V Vo Output Low Voltage 0.4 Vv 1 =3-2 mA for /BUSREQ 1 =2.0 mA for all others Vou Output High Voitage 2.4 V 1Q4=200 pA loc Power Supply Current 2-80 DMA 150 mA Z-80A DMA 200 mA la Input Leakage Current 10 pA Vy=0 tO Von ho 3-State Ouput Leakage Current in Float +10 pA Vour=0.4V to VQ. lo Data Bus Leakage Current in Input Mode 10 BA S VaeS Veo Note: Vec=5V +5% unless otherwise specified, over specified temperature range. CAPACITANCE Symbol Parameter > Min - Max Unit Test Condition Cc Clock Capacitance 35 pF Unmeasured pins C,, Input Capacitance 10 pF returned to ground. Cour Output Capacitance 10 pF Note: Over specified temperature range; f =1 MHz 61AC CHARACTERISTICS (z8410 / NMOS Z80 DMA) (Inactive State) D,b, (NTERRUPT ACTIVE INACTIVE NOTE: Signals in this diagram bear no retation to one another unless specifically noted as a numbered item.AC CHARACTERISTICS (28410 / NMOS Z80 DMA) (Active State) * LP PIAA DDR AS KO aD, < x |~<(4) >} _ (5) INPUT x x x Do-D7 te a _ + ee) OUTPUT _ im \ lon am @ }+_@>| Lo iB \ y \ / Sf > wa Z @ f/f >| | @ L285 *@) _ _/ tora =a an Lo \ f\ L i \ [S_ <(9)__>| f-e~ ) @ want LG) @ susREG x NOTE: Signats In this diagram bear no relation to one another unless specifically noted as a numbered Item. 20841004 Ft Number Symbol Parameter Min(ns) Max(ns) 1 TeC Clock Cycle Time 250 2 TWCh Clock Width (High) 110 2000 3 WCl Clock Width (Low) 410 2000 4 re Clock Rise Time 30 5 TIC Clock Fall Time 30 NOTES: Numbers in parentheses are other parameter-numbers in this table; their values should be substituted in equations. + All equations imply DMA default (standard) timing. t+ Data must be enabled onto data bus when RD is active. * Parameter is not illustrated in the AC Timing Diagrams.AC CHARACTERISTICS (28410 / NMOS Z80 DMA) (Active State) 20841004 *tt Number Symbol Parameter Min(ns) Max(ns) 6 TdA Address Output Delay 110 7 TdC(Az) Clock t to Address Float Delay 90 8 TsA(MREQ) Address to MREQ $ Setup (Memory Cycle) (2) + (5)- 75 9 TsA(IRW) Address Stable to ORO, RD, WR Setup (I/O Cycle) (1)-70 "10 TdRW(A) RD, WR t to Addr. Stable Delay (3) +(4)~50 11 TdRW(Az) RD, WR t to Addr. Float (3) +(4)~45 42 TdCt(DO) Clock 4 to Data Out Delay 150 "13 TdCr(Dz) Clock t to Data Float Delay (Write Cycle) 90 14 TsDI(Cr) Data In to Clock t Setup (Read cycle when . rising edge ends read) 35 15 TsDK(Cf) Data In to Clock 4 Setup (Read cycle when falling edge ends read) 50 "16 TsDO(WfM) Data Out to WR Setup (Memory Cycle) (1)-170 17 TsDO(WE) Data Out to WR 4 Setup (I/O cycle) 100 "18 TdWr(DO) WR to Data Out Delay (3) +(4)-70 19 Th Hold Time for Any Specified Setup Time 0 20 TdCr(Mf) Clock t to MREQ + Delay 85 21 TdaCh(Mf) Clock $10 MREQ $ Delay 85 22 TdCr(Mr) Clock t to MREO Delay 85 23 TdCt(Mn) Clock + to MREO Delay 85 24 TwM1 MREG Low Pulse Width (1)-30 *25 TwMh MREO High Pulse Width (2)+(5)- 20 26 TACK Ciock + to IORG + Delay 85 27 TdCri(If} Clock t to (ORG + Delay 75 28 TdCri(ir) Clock to IORG Delay 85 29 TdCi(tr) Clock + to TORO t Delay 85 30 TACr(RA) Clock t to RD | Delay 85 31 TdCKRA Clock $ to RD 4 Delay 95 32 TdCr(Rr) Clock t to RD t Delay 85 33 TdCi(Rr) Clock $ to RD t Delay 85 34 TdCriwh) Clock t to WR 4 Delay 65 35 TdcKws Clock 4 to WR Delay 80 36 TdCrwr) Clock t to WR t Delay 80 37 TACKWr) Clock 4 to WR t Delay 80 38 Ww WR Low Pulse Width (1)-30 39 TswaA(Ch WAIT to Clock 4 Setup 70 40 TdCr(B) Clock t to BUSREQ Delay 100 41 TdCr(lz) Clock t to ORO, MREQ, RD, WR Float Delay 80 NOTES: + All AC equations imply DMA dofautt (standard) timing. * Numbers In parenth ers in this table; their values should be substituted in equations. 64AC CHARACTERISTICS (284010 / CMOS 280 DMA) (Inactive State) 284C 1006 Z84C 1008 Number Symbol! Parameter Min Max Min Max _- Unit 1 TcC Clock Cycle Time 162 DC 125 DC 2 TwCh Clock Width (High) 65 pc 55 oc 3 Wel Clock Width (Low) 65 oC 55 DC 4 TC Clock Rise Time 20 10 5 TiC Clock Fall Time 20 10 6 Th Hold Time for Any Specified Setup Time 0 0 ns 7 TsC(Cr) TORG, WR, CE } to Clock t Setup 60 45 ns 8 TdDO(RDF) RD } to Data Output Delay 300 220 ns 9 TsDI(Cr) Data In to Clock t Setup (WR or M1) 30 20 ns 10 TADOWIOf) TORQ 4 to Data Out Delay (INTA Cycle) 110 85 ns 1 TdRDr(Dz) RD t to Data Float Delay (output buffer disable) 70 50 ns 12 TsIEKIORQ/ IEI to IORQ + Setup (INTA Cycle) 100 80 ns 13 TdlEOr(tEir) IEI t to IEO t Delay 100 70 ns 14 TdlEOKIEIf) IEI + to IEO Delay 100 70 ns 15 TdM1K(IEOR) MT 4 to 1EO 4 Delay (interrupt just prior to MT 4) 100 80 ns 16 TsM1f(Cr) M7 4 to Clock t Setup 70 45 ns 17 TsM1r(Cf) M7 t to Clock Setup -15 -15 ns 18 TsRDI(CH) RD } to Clock t Setup (M7 Cycle) 60 45 ns 19 Tdl(INTA Interrupt Cause to INT + Delay (INT generated only when DMA is inactive) 450 400 ns 20 TdBAIr(BAOr) BAT t to BAO t Delay 100 70 ns 21 TABAI(BAO?) BAI + to BAO $ Delay 100 70 ns 22 TsRDY(Cr) RDY Active to Clock t Setup 50 50 ns NOTE: Negative minimum setup values mean that the first-mentioned event can come after the second-mentioned event. * M1 must be active for a minimum of two clock cycles to reset the DMA (This feature Is only with C-MOS Z80 DMA). 65