1
RT8106/A
DS8106/A-04 April 2011 www.richtek.com
Applications
zGraphic Card
zMotherboard, Desktop Servers
zIA and Telecom Equipment
zGeneral High Power DC/DC Regulator
5V/12V Synchronous Buck PWM DC-DC Controller
General Description
The RT8106/A is a DC/DC synchronous buck PWM
controller with embedded driver support up to 12V+12V
boot-strapped voltage for high efficiency power driving. The
part integrates full functions of voltage regulation, power
monitoring and protection into a single small footprint
WDFN-10L 3x3 (Exposed Pad) package.
The RT8106/A adopts a high-gain voltage mode PWM
control for simple application design. An internal 0.8V
reference allows the output voltage to be precisely
regulated for low voltage requirement. Based on all
RT8106/A features, the part provides an optimum
compromise between efficiency, total B.O.M. count, and cost.
Features
zz
zz
zSingle 5 to 12V Bias Supply
zz
zz
zDrive All Low Cost N-MOSFETs
zz
zz
zSupport High Current Application up to 30A
zz
zz
zHigh-Gain Voltage Mode PWM Control
zz
zz
z300kHz/600kHz Fixed Frequency Oscillator
zz
zz
zFa st T ra nsient Re sponse :
``
``
` High-Speed EA Amplifier
``
``
` 0 to 85% Duty Ratio
``
``
` External Compensation in The Control Loop
zz
zz
zInternal Soft-Start
zz
zz
zAdaptive Non-Overlapping Gate Driver
zz
zz
zOver Current Fault Monitor on low side MOSFET
zz
zz
zRoHS Compliant and 100% Lead (Pb)-Free
Pin Configurations
(TOP VIEW)
WDFN-10L 3x3
BOOT
LX
GND
LGATE
PGOOD
VOS
FB
VCC
COMP/EN
UGATE
9
8
7
9
1
2
3
4
5
10
GND
11
Ordering Information
Note :
Richtek products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
DY=YM
DNN
RT8106GQW
DY= : Product Code
YMDNN : Date Code EP=YM
DNN
RT8106AGQW
EP= : Product Code
YMDNN : Date Code
RT8106/A
Package Type
QW : WDFN-10L 3x3 (W-Type)
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
Z : ECO (Ecological Element with
Halogen Free and Pb free)
600kHz
300kHz
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RT8106/A
www.richtek.com DS8106/A-04 April 2011
Functional Pin Description
Pi n No. Pin N am e Pi n Funct i on
1 BOOT
This pin is boot-strapped by external capacitor and is applied for the embedded
High Side gate driver power.
2 LX Phase node of PWM.
3 UGATE High Side gate drive.
4 LGATE
Low Side gate drive. It also acts as OC setup pin by adjusting a resistor
connecting to GND.
5,
11 (Exposed Pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
6 VCC
VCC is generally applied for bias power for IC logics and gate driver control. To
connect a 1μF bypass capacitor to GND is recommended.
7 COMP/EN
Compensation pin of PWM and Output of the PWM error amplifier. Connect
compensation network between this pin and FB. This pin is also applied as
Enable pin.
8 FB PWM Feedback. The output feedback of PWM. The pin is applied for voltage
regulation.
9 VOS
The pin is scaled to be 0.8v and provides under voltage protection, over voltage
protection and PGOOD function.
10 PGOOD This pin is an open drain driver and Indicates PWM output regulated in +/-10%.
7
3
2
4
8
COMP/EN
UGATE
FB
RT8106/A
LGATE
1
BOOT
LX
L1
V
IN
PGOOD
10
PGOOD
GND
5, Exposed Pad (11)
R
BOOT
Q1
Q2R7
C7
C
OUT
V
OUT
VOS
EN
VCC
6
V
CC
C
BOOT
R
UGATE
R
OCSET
R
FB
R
FB
R
B
C
B
R
L
R
OFFSET
R
OFFSET
C
P
C
f
R
f
9
C
BP
C4
D1
V
GD
Typical Application Circuit
DY YM
DNN
RT8106ZQW
DY : Product Code
YMDNN : Date Code EP YM
DNN
RT8106AZQW
EP : Product Code
YMDNN : Date Code
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RT8106/A
DS8106/A-04 April 2011 www.richtek.com
Function Block Diagram
UGATE
LX
LGATE
BOOT
+
-
+
-
0.8V
Control
Logic
+
-
+
-
-
+
+
-
-
+
OC
UV
OV
UV_level
OV_level
PGH_level
PGL_level
EN
-1
LGATE
PGOOD
GND
COMP/EN
FB
VOS
LX
IOC
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RT8106/A
www.richtek.com DS8106/A-04 April 2011
Electrical Characteristics
(VCC = 12V, TA = 25°C, unless otherwise specified)
Absolute Maximum Ratings (Note 1)
zSupply Voltage, VCC -------------------------------------------------------------------------------------- 15V
zBOOT to LX ------------------------------------------------------------------------------------------------- 15V
zInput, Output or I/O Voltage ----------------------------------------------------------------------------- (GND−0.3V) to 7V
zLX to GND
DC ------------------------------------------------------------------------------------------------------------- −5V to 18V
< 200ns ------------------------------------------------------------------------------------------------------ −10V to 30V
zBOOT to GND
DC ------------------------------------------------------------------------------------------------------------- −0.3V to 30V
< 200ns ------------------------------------------------------------------------------------------------------ −0.3V to 42V
zUGATE ------------------------------------------------------------------------------------------------------- (VLX − 0.3V) to (VBOOT + 0.3V)
< 200ns ------------------------------------------------------------------------------------------------------ (VLX − 5V) to (VBOOT + 5V)
zLGATE ------------------------------------------------------------------------------------------------------- (GND − 0.3V) to( VCC + 0.3V)
< 200ns ------------------------------------------------------------------------------------------------------ (GND − 5V) to (VCC + 5V)
zPower Dissipation, PD @ TA = 25°C (Note 2)
WDFN-10L 3x3 --------------------------------------------------------------------------------------------- 1.429W
zPackage Thermal Resistance
WDFN-10L 3x3, θJA --------------------------------------------------------------------------------------- 70°C/W
WDFN-10L 3x3, θJC --------------------------------------------------------------------------------------- 8.2°C/W
zJunction Temperature ------------------------------------------------------------------------------------- 150°C
zLead Temperature (Soldering, 10 sec.) --------------------------------------------------------------- 260°C
zStorage Temperature Range ---------------------------------------------------------------------------- −65°C to 150°C
zESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------------ 2kV
MM (Machine Mode) -------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 4)
zSupply Voltage, VCC -------------------------------------------------------------------------------------- 12V ± 10%, 5V ± 5%
zJunction Temperature Range ---------------------------------------------------------------------------- −40°C to 125°C
zAmbient Temperature Range ---------------------------------------------------------------------------- −40°C to 85°C
Parameter Symbol Test Conditions Min Typ Max Unit
General
Supply Input Voltage VCC 4.75 12 13.2 V
Nominal Supply Current ICC No Load for UGATE/ LGATE -- 4 -- mA
VCC POR Threshold VPOR V
CC Rising 3.9 4.1 4.35 V
VCC POR Hysteresis VPOR_Hys -- 0.3 -- V
Soft-Start Interval TSS FB rising from 10% to 90% 1.5 2.7 4 ms
Reference Voltage VREF -- 0.8 -- V
Output Voltage Accuracy −0.8 -- 0.8 %
Thermal Shutdown Limit -- 140 -- °C
To be continued
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RT8106/A
DS8106/A-04 April 2011 www.richtek.com
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard. The case point of θJC is on the expose pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Parameter Symbol Test Conditions Min Typ Max Unit
PWM Controller
EA Open Loop Gain GEA -- 80 -- dB
EA Bandwidth BW -- 15 -- MHz
RT8106 -- 85 -- %
Maximum Duty RT8106A -- 80 -- %
UGATE Drive Source IUGATEsr 1.5 -- -- A
LGATE Drive Source ILGATEsr 1.5 -- -- A
UGATE Drive Sink RUGATEsk -- 1.1 -- Ω
LGATE Drive Sink RLGATEsk -- 0.65 -- Ω
Ramp Valley -- 1.6 -- V
Ramp Amplitude ΔVOSC -- 1.2 -- V
RT8106 270 300 330
PWM Frequency RT8106A fOSC 540 600 660
kHz
Over Voltage Threshold OVP Relative to VOS 115 125 135 %
Under Voltage Threshold UVP Relative to VOS 65 75 80 %
PGOOD Threshold PGOOD Relative to VOS 90 -- 110 %
OC Current Source IOC 9 10 11 μA
OC Preset Trigger Voltage VOC_Preset R
OCSET is not Connected -- 0.55 -- V
Disable Threshold VDIS -- -- 0.5 V
Relative to VOS Rising 85 -- 95 %
PGOOD Active Threshold Relative to VOS Falling 105 -- 115 %
PGOOD Low Level VOL_PGOOD Sink 4mA -- -- 0.4 V
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RT8106/A
www.richtek.com DS8106/A-04 April 2011
Typical Operating Characteristics
Dead Time
Time (25ns/Div)
(5V/Div)
VIN = 12V, VOUT = 1.6V, ILOAD = 5A
LGATE
UGATE
PHASE
UGATE-PHASE
Rising
Output Voltage vs. Temperature
1.6020
1.6025
1.6030
1.6035
1.6040
1.6045
1.6050
1.6055
1.6060
1.6065
-20 0 20 40 60 80 100 120 140
Temperature (°C)
Output Voltage (V)
VIN = 12V, ILOAD = 0A
Switching Frequency vs. Tempe rature
250
260
270
280
290
300
310
320
330
340
350
-20 0 20 40 60 80 100 120 140
Temperature (°C)
Switching Frequency (kHz) 1
VIN = 12V, VOUT = 1.6V, ILOAD = 0A
Load Transient Response
Time (200μs/Div)
ILOAD
(10A/Div)
VOUT
(100mV/Div)
VIN = 12V, VOUT = 1.6V, ILOAD = 0A to 20A to 0A
LGATE
(10V/Div)
UGATE
(20V/Div)
Load Transient Response
Time (10μs/Div)
ILOAD
(10A/Div)
VOUT
(100mV/Div)
VIN = 12V, VOUT = 1.6V, ILOAD = 0A to 20A
LGATE
(10V/Div)
UGATE
(20V/Div)
Load Transient Response
Time (10μs/Div)
ILOAD
(10A/Div)
VOUT
(100mV/Div)
VIN = 12V, VOUT = 1.6V, ILOAD = 20A to 0A
LGATE
(10V/Div)
UGATE
(20V/Div)
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RT8106/A
DS8106/A-04 April 2011 www.richtek.com
Dead Time
Time (25ns/Div)
(5V/Div)
VIN = 12V, VOUT = 1.6V, ILOAD = 5A
LGATE
UGATE
PHASE
UGATE-PHASE
Falling
Efficiency vs. Load Current
50
55
60
65
70
75
80
85
90
95
0 5 10 15 20 25 30
Load Current (A)
Efficiency (%)
VIN = VCC = 12V, VOUT = 1.6V, f = 300kHz
COMP Enable Power On
Time (1ms/Div)
VOUT
(2V/Div) VIN = 12V, VOUT = 1.6V, ILOAD = 10A
LGATE
(10V/Div)
UGATE
(20V/Div)
VCOMP
(1V/Div)
COMP Disable Power Off
Time (1ms/Div)
VOUT
(2V/Div)
VIN = 12V, VOUT = 1.6V, ILOAD = 10A
LGATE
(10V/Div)
UGATE
(20V/Div)
VCOMP
(1V/Div)
VIN = VCC Power Off
Time (1ms/Div)
VOUT
(2V/Div)
VCC = VIN = 12V, VOUT = 1.6V, ILOAD = 10A
LGATE
(10V/Div)
UGATE
(20V/Div)
VCC
(10V/Div)
VIN = VCC Power On
Time (2.5ms/Div)
VOUT
(2V/Div) VCC = VIN = 12V, VOUT = 1.6V, ILOAD = 10A
LGATE
(10V/Div)
UGATE
(20V/Div)
VCC
(10V/Div)
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RT8106/A
www.richtek.com DS8106/A-04 April 2011
Application Information
Overview
The RT8106/A is a high efficiency synchronous buck PWM
controller that can generate adjustable DC output voltage.
This device is embedded with high current High Side and
Low Side MOSFET drivers, and many protection functions
(OCP, UVP, OVP) into a tiny package. Simple board
design and low BOM cost can be easily achieved by the
high integration feature to make this part to be an ideal
solution for general applications.
Chip Enable/Disable
Pull pin 7 (COMP/EN) to be lower than 0.5V can shut
down the device. This allows flexible power sequence
control for specified application. Setting free this pin can
enable the RT8106/A again.
Power On Reset (POR)
The RT8106/A automatically initializes upon applying of
input power (at the VCC) pin. The power on reset function
(POR) continually monitors the VCC supply voltage. The
POR threshold is typically 4.1V at VCC rising.
Input Power (Vin) Detection
The RT8106/A continuously generates a 10kHz pulse train
with 1us pulse width to turn on the upper MOSFET for
detecting the existence of VIN after VCC POR and Comp/
EN pin enabled. As shown in Figure 1. the LX pin voltage
is monitored during the detection period. If the LX pin
voltage exceeds 1.5V threshold for four times, the VIN
existence is recognized and the RT8106/A initiates its
soft start cycle.
+
-
LX
UGATE
1.5V
Internal Counter will count (VLX > 1.5V)
four times (rising & falling) to recognize
VIN is ready.
1st 2nd 3rd 4th LX
waveform
Figure 1. VIN Power Detection
Soft Start
A built-in soft-start is used to prevent surge current from
VIN to VOUT during power on. The soft-start (SS)
automatically begins once the existence of VIN is detected.
The internal soft-start capacitor is charged and generates
a linear ramping voltage across the capacitor. This voltage
clamps the feedback voltage at the FB pin, causing PWM
pulse width increasing slowly to reduce the output surge
current. The soft-start cycle stops while the voltage across
SS capacitor is higher than the nominal feedback voltage
0.8V.
Output Voltage Setting
The RT8106/A can regulate an output voltage as low to as
0.8V and maintains it within ±0.8% accuracy. Higher output
voltage can be achieved by adding an offset resistor ROFFSET
between FB pin and GND. The steady state output voltage
will be set as the formula :
FB
OUT REF OFFSET
R
V = V 1+
R
⎛⎞
×⎜⎟
⎝⎠
Under Voltage Protection (UVP)
The VOS pin voltage is monitored for under voltage
protection after soft-start completes. If the VOS voltage
drops to below UV threshold (typically 75% x VREF), the
UVP is triggered and the RT8106/A turns off High Side
and Low Side gate drivers. The RT8106/A will not be
released from this latch condition unless VCC POR is
recognized.
Over Voltage Protection (OVP)
The VOS pin is also acted as over voltage detection after
POR. If the VOS voltage rises above OVP threshold
(typically 125% x VREF), OVP is triggered. The RT8106/
A turns off High Side gatedriver and turns Low Side gate
drivers always on. The Low Side gate driver will not be
turned off until VOS falls below 0.4V. The RT8106/A will
not be released from this latch condition unless VCC POR
is recognized.
PGOOD
The RT8106/A will assert PGOOD signal after the soft-
start completes and the VOS voltage is within power good
range. If VOS voltage runs outside of the range, the
RT8106/A de-asserts the PGOOD signal but continues
switching and regulating. The PGOOD is an open drain
output pin and thus requires an external pull-up resistor.
9
RT8106/A
DS8106/A-04 April 2011 www.richtek.com
Over Current Protection
While the High Side MOSFET is off and Low Side on, the
output current (IOUT) flowing through the Low Side
MOSFET results in a negative voltage drop (IOUT x
MOSFET RDS(ON)) between the LX pin and GND. The
RT8106/A senses IOUT by monitoring the LX pin voltage.
The maximum current is set by adjusting an external
resistor ROCSET connecting between LGATE and GND. The
OCP is triggered if the LX voltage is lower than the LGATE
voltage when low side MOSFET conducting. Because
there is an internal current source 10uA flowing from the
RT8106/A to the ROCSET, the maximum current (IMAX) can
be easily derived from below equation :
MAX DS(ON) OCSET
I R R 10A
μ
×=×
Figure 2. Pre-Bias Function
In case ROCSET is not connected, RT8106/A can detect
this condition and set the OC trigger voltage to a preset
value (typ. 0.55V).
When the OCP is triggered, the RT8106/A will turn off
both UGATE and LGATE drivers and latches in the
condition unless VCC POR is recognized.
Pre-Bias Start Up
In order to prevent any potential negative spike on VOUT
during start-up, the RT8106/A performs a special UGATE/
LGATE warm-up sequence. The UGATE keeps normal
switching but the LGATE will turn on with a short pulse
train instead of turning on for a long period. The Figure 2.
shows that VOUT rises from its initial value and no negative
undershoot will happen.
Feedback Compensation
The RT8106/A is a voltage mode controller. The control
loop is a single voltage feedback path including a
compensator and a modulator as shown in Figure 3. The
modulator consists of the PWM comparator and power
stage. The PWM comparator compares error amplifier EA
output (COMP) with oscillator (OSC) sawtooth wave to
provide a pulse-width modulated (PWM) with an amplitude
of VIN at the LX node. The PWM wave is smoothed by the
output filter LOUT and COUT. The output voltage (VOUT) is
sensed and fed to the inverting input of the error amplifier.
A well-designed compensator regulates the output voltage
to the reference voltage VREF with fast transient response
and good stability. In order to achieve fast transient
response and accurate output regulation, an adequate
compensator design is necessary. The goal of the
compensation network is to provide adequate phase
margin (usually greater than 45 degrees) and the highest
bandwidth (0dB crossing frequency). It is also
recommended to manipulate loop frequency response that
its gain crosses over 0dB at a slope of -20dB/dec.
Figure 3. Closed Loop
-
+
+
-
OSC
ΔVOSC
ZFB
ZIN
VIN
Driver
Driver
REF
PWM
Comparator
COMP
EA
+
-
REF
EA
ZFB ZIN VOUT
FB
COMP
C1
C2
C3
R1
R2 R3
ESR
LX
COUT
VOUT
L
Time (1ms/Div)
LGATE
(5V/Div)
VOUT
(500mV/Div)
UGATE
(20V/Div)
VIN = 12V, VOUT = 1.6V, ILOAD = 0A
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RT8106/A
www.richtek.com DS8106/A-04 April 2011
The ESR zero is contributed by the ESR associated with
the output capacitance. Note that this requires that the
output capacitor should have enough ESR to satisfy
stability requirements. The ESR zero of the output
capacitor is expressed as follows :
ESRC2
1
f
OUT
ESR ××
=
π
2) Compensation Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks ZC and ZF as shown in Figure
4.
Figure 4. Compensation Loop
C2 x R2 x 2
1
fZ1
π
=
C2C1
C2 x C1
x R2 x 2
1
fP1
+
=
π
Figure 5. shows the DC-DC converter's magnitude Bode
Plot. The compensation gain uses external impedance
networks ZC and ZF to provide a stable, high bandwidth
loop. High crossover frequency is desirable for fast
transient response, but it often jeopardize the system
stability. In order to cancel one of the LC filter poles, place
the zero before the LC filter resonant frequency. In the
experience, place the zero at 75% of the LC filter resonant
frequency. Crossover frequency should be higher than the
ESR zero but less than 1/5 of the switching frequency.
The second pole is placed at half the switching frequency.
Figure 5. Bode Plot
Frequency
10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz
vdb(vo) vdb(comp2) vdb(lo)
-40
0
40
80
-60
10 100 1k 10k 100k 1M
80
40
0
20
60
-20
-40
-60
Loop Gain
Compensation
Gain
Modulator
Gain
Frequency (Hz)
G a in (d B)
Component Selection
1) Inductor Selection
The selection of output inductor is based on the
considerations of efficiency, output power and operating
frequency. Low inductance value has smaller size, but
results in low efficiency, large ripple current and high output
ripple voltage. Generally, an inductor that limits the ripple
current (ΔIL) between 20% and 50% of output current is
appropriate. Figure 6. shows the typical topology of the
synchronous step-down converter and its related
waveforms.
+
S1
S2
VIN
iS1
iS2
IOUT
VOUT
+
-
RL
rC
COUT
iC
VOR
+
-
VOC
+
-
VL
+-
LIL
1) Modulator Frequency Equations
The modulator transfer function is the small-signal transfer
function of VOUT/VCOMP (output voltage over the error
amplifier output). This transfer function is dominated by a
DC gain, a double pole, and an ESR zero as shown in
Figure 3. The DC gain of the modulator is the input voltage
(VIN) divided by the peak to peak oscillator voltage VOSC.
The output LC filter introduces a double pole, 40dB/decade
gain slope above its corner resonant frequency, and a total
phase lag of 180 degrees. The resonant frequency of the
LC filter is expressed as :
OUTOUT
LC CL2
1
f×
=
π
+
-FB
VREF
COMP EA
ZC
ZF
C1
C2
R2 R1 VOUT
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RT8106/A
DS8106/A-04 April 2011 www.richtek.com
VL
VIN - VOUT
- VOUT
iL
IL = IOUT
ΔIL
iS1
iS2
TS
TON TOFF
Vg1
Vg2
Figure 6. The Waveforms of Synchronous Step-Down
Converter
OUT
L
IN OUT
IN
OUT
IN OUT
IN L
V
ΔID
VV L ; Δt; D
ΔtfsV
V
L(V V )
VfsΔI
−= = =
=− ×
××
According to Figure 6. the ripple current of inductor can
be calculated as follows :
(1)
Where :
VIN = Maximum input voltage
VOUT = Output Voltage
Δt = S1 turn on time
ΔIL = Inductor current ripple
fS = Switching frequency
D = Duty Cycle
rC = Equivalent series resistor of output capacitor
L
dt =dt L
VOUT
=
VOR
iL
iC
diL
ΔIL
1/2
0
0
ΔIL x rc
VOC
t1 t2
ΔVOC
ΔIL
VIN-VOUT
TS
IOUT
diL
Figure 7. The Related Waveforms of Output Capacitor
2) Output Capacitor Selection
The selection of output capacitor depends on the output
ripple voltage requirement. Practically, the output ripple
voltage is a function of both capacitance value and the
equivalent series resistance (ESR) rC. Figure 7. shows
the related waveforms of output capacitor.
The AC impedance of output capacitor at operating
frequency is quite smaller than the load impedance, so
the ripple current (ΔIL) of the inductor current flows mainly
through the output capacitor. The output ripple voltage is
described as :
t2
t1
OUT OR OC
OUT L C
O
2
OUT
OUT L L S
OL
ΔVΔVΔV
1
ΔVΔIrc i dt
C
1V
ΔVΔIΔIrc (1D)T
8C
=+
=×+
=××+ −
∫
where ΔVOR is caused by ESR and ΔVOC by capacitance.
For electrolytic capacitor application, typically 90% to 95%
of the output voltage ripple is contributed by the ESR of
the output capacitor. So Equation (4) can be simplified
as: ΔVOUT = ΔIL x rC
(2)
(3)
(4)
(5)
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RT8106/A
www.richtek.com DS8106/A-04 April 2011
Users can connect capacitors in parallel to get calculated
ESR.
Input Capacitor
The selection of input capacitor is mainly based on its
maximum ripple current capability. The buck converter
draws pulsewise current from the input capacitor during
the on time of the S1 as shown in Figure 6. The RMS
value of ripple current flowing through the input capacitor
is described as :
(A) D)D(1IIrms OUT −= (6)
The input capacitor must be cable of handling this ripple
current. Sometime, for higher efficiency, the low ESR
capacitor is necessary.
PCB Layout Considerations
MOSFETs switch very fast and efficiently. The current
transition speed between different derices causes voltage
spikes across the interconnecting impedances and
parasitic circuit elements. The voltage spikes can degrade
efficiency and radiate noise that results in over-voltage
stress on devices. Careful component placement layout
and printed circuit design can minimize the voltage spikes
induced in the converter. For example, during the period
of upper MOSFETs turn-off transition, the upper MOSFET
was carrying the full load current. During turn-off, current
stops flowing in the upper MOSFET and is picked up by
the low side MOSFET or schottky diode. Any inductance
in the switched current path generates a large voltage
spike during the switching interval. Careful component
selections, layout of the critical components, and use
shorter and wider PCB traces help in minimizing the
magnitude of voltage spikes. The RT8106/A DC-DC
converter integrates two sets of critical components just
as follows. The switching power components are most
critical because they switch large amounts of energy, and
as such, they tend to generate equally large amounts of
noise. The critical small signal components are those
connected to sensitive nodes or those supplying critical
bypass current.
For the proper layout of the RT8106/A the power
components and the PWM controller should be placed
firstly. And than place the input capacitors, especially the
high-frequency ceramic decoupling capacitors, close to
the power switches. Place the output inductor and output
capacitors between the MOSFETs and the load. Also
locate the PWM controller near by the MOSFETs. A multi-
layer printed circuit board is recommended. Figure 8
shows the connections of the critical components in the
converter.
Note that the capacitors CIN and COUT each of them
represents numerous physical capacitors. Use a dedicated
grounding plane and use vias to ground all critical
components to this layer. Apply another solid layer as a
power plane and cut this plane into smaller islands of
common voltage levels. The power plane should support
the input power and output power nodes. Use copper filled
polygons on the top and bottom circuit layers for the LX
node, but it is not necessary to oversize this particular
island. Since the LX node is subjected to very high dV/dt
voltages, the stray capacitance formed between these
islands and the surrounding circuitry will tend to couple
switching noise. Use the remaining printed circuit layers
for small signal routing. The PCB traces between the PWM
controller and the gate of MOSFET and also the traces
connecting source of MOSFETs should be sized to carry
2A peak currents.
Figure 8. The Connections of the Critical Components in
the Converter
+
+
LOAD
+
VCC GND
RT8106/A
FB
LGATE
UGATE
IL
IQ1
VOUT
Q2
Q1
IQ2
5V/12V
GND
13
RT8106/A
DS8106/A-04 April 2011 www.richtek.com
Figure 9. RT8106/A PCB (Component Side) Figure 10. RT8106/A PCB (Back-Side)
14
RT8106/A
www.richtek.com DS8106/A-04 April 2011
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com
Outline Dimension
Dimensions In Millimeters Dimensions In Inches
Symbol Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.180 0.300 0.007 0.012
D 2.950 3.050 0.116 0.120
D2 2.300 2.650 0.091 0.104
E 2.950 3.050 0.116 0.120
E2 1.500 1.750 0.059 0.069
e 0.500 0.020
L 0.350 0.450
0.014 0.018
W-Type 10L DFN 3x3 Package
11
2
2
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
DETAIL A
Pin #1 ID and Tie Bar Mark Options
D
1
E
A3
A
A1
D2
E2
L
b
e
SEE DETAIL A
