FN7532 Rev 7.00 Page 1 of 29
July 27, 2015
FN7532
Rev 7.00
July 27, 2015
ISL28118, ISL28218
40V Precision Single-Supply, Rail-to-rail Output, Low-power Operational
Amplifiers
DATASHEET
The ISL28118, ISL28218 are single and dual, low-power
precision amplifiers optimized for single-supply applications.
These devices feature a common mode input voltage range
extending to 0.5V below the V- rail, a rail-to-rail differential
input voltage range for use as a comparator and rail-to-rail
output voltage swing, which makes them ideal for
single-supply applications where input operation at ground is
important.
These op amps feature low power, low offset voltage and low
temperature drift, making them the ideal choice for
applications requiring both high DC accuracy and AC
performance. These amplifiers are designed to operate over a
single supply range of 3V to 40V or a split supply voltage range
of +1.8V/-1.2V to ±20V. The combination of precision and
small footprint provides the user with outstanding value and
flexibility relative to similar competitive parts.
Applications for these amplifiers include precision
instrumentation, data acquisition, precision power supply
controls and industrial controls.
Both parts are offered in 8 Ld SOIC and 8 Ld MSOP packages. All
devices are offered in standard pin configurations and operate
across the extended temperature range of -40°C to +125°C.
Related Literature
•AN1595, “ISL28218SOICEVAL1Z Evaluation Board User’s
Guide”
Features
• Rail-to-rail output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mV
•Below-ground (V
-) input capability to -0.5V, ground sensing
• Single-supply range . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 40V
• Low current consumption . . . . . . . . . . . . . . . . . . . . . . . 850µA
• Low noise voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6nV/Hz
• Low noise current. . . . . . . . . . . . . . . . . . . . . . . . . . . 355fA/Hz
•Low input offset voltage
- ISL28118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150µV (max)
- ISL28218 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230µV (max)
• Superb offset voltage temperature drift
- ISL28118 . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2µV/°C (max)
- ISL28218 . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4µV/°C (max)
• Operating temperature range. . . . . . . . . . . -40°C to +125°C
• No phase reversal
Applications
• Precision instruments
• Medical instrumentation
• Data acquisition
•Power supply control
• Industrial process control
FIGURE 1. TYPICAL APPLICATION: SINGLE-SUPPLY, LOW-SIDE
CURRENT SENSE AMPLIFIER
FIGURE 2. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE
VOLTAGE, VS = ±15V
IN-
IN+
Rf
RREF+
ISL28118
+3V
V-
V+
RIN-
10kΩ
RIN+
10kΩ
-
+
100kΩ
VREF
100kΩ
VOUT
LOAD
RSENSE
GAIN = 10
to 40V
VOS (µV)
INPUT COMMON MODE VOLTAGE (V)
-400
-300
-200
-100
0
100
200
300
400
-16 -15 -14 -13 13 14 15 16
-40°C
+25°C
+125°C
ISL28118, ISL28218
FN7532 Rev 7.00 Page 2 of 29
July 27, 2015
Table of Contents
Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications (VS ±15V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications (VS ±5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input Stage Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Output Drive Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Output Phase Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Single Channel Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ISL28118 and ISL28218 SPICE Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Characterization vs Simulation Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
M8.15E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
M8.118B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ISL28118, ISL28218
FN7532 Rev 7.00 Page 3 of 29
July 27, 2015
Pin Configurations
ISL28118
(8 LD SOIC, 8 LD MSOP)
TOP VIEW
ISL28218
(8 LD SOIC, 8 LD MSOP)
TOP VIEW
NC
-IN
+IN
V-
1
2
3
4
8
7
6
5
NC
V+
VOUT
NC
+-
VOUT_A
-IN_A
+IN_A
V-
1
2
3
4
8
7
6
5
V+
VOUT_B
-IN_B
+IN_B
+-
+-
Pin Descriptions
ISL28118
(8 LD SOIC, MSOP)
ISL28218
(8 LD SOIC, MSOP)
PIN
NAME
EQUIVALENT
CIRCUIT DESCRIPTION
3 3 +IN, +IN_A 1 Amplifier A noninverting input
2 2 -IN, -IN_A 1 Amplifier A inverting input
6 1 VOUT, VOUT_A 2 Amplifier A output
44V
-3 Negative power supply
5 +IN_B 1 Amplifier B noninverting input
6 -IN_B 1 Amplifier B inverting input
7 VOUT_B 2 Amplifier B output
78V
+3 Positive power supply
1, 5, 8 - NC - No Connect
V+
V-
OUT
CIRCUIT 2CIRCUIT 1
V+
V-
CIRCUIT 3
IN-
V+
V-
IN+
CAPACITIVELY
TRIGGERED ESD
CLAMP
ISL28118, ISL28218
FN7532 Rev 7.00 Page 4 of 29
July 27, 2015
Ordering Information
PART NUMBER
(Notes 1, 2, 3)PART MARKING
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL28118FBZ 28118 FBZ -40 to +125 8 Ld SOIC M8.15E
ISL28118FUZ 8118Z -40 to +125 8 Ld MSOP M8.118B
ISL28218FBZ 28218 FBZ -40 to +125 8 Ld SOIC M8.15E
ISL28218FUZ 8218Z -40 to +125 8 Ld MSOP M8.118B
ISL28218SOICEVAL1Z Evaluation Board
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information pages for ISL28118, ISL28218. For more information on MSL, please see
Technical Brief TB363.
ISL28118, ISL28218
FN7532 Rev 7.00 Page 5 of 29
July 27, 2015
Absolute Maximum Ratings Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . . . . . . 42V or V- - 0.5V to V+ + 0.5V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . 42V or V- - 0.5V to V+ + 0.5V
Max/Min Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
Output Short-circuit Duration (1 output at a time) . . . . . . . . . . . . . . Indefinite
ESD Tolerance
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-CI0ID). . . . . . . . . . . . . . . 2kV
ESD Tolerance (ISL28118 SOIC package only)
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . 5.5kV
Machine Model (Tested per JESD22-A115-C) . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-CI0ID). . . . . . . . . . . . . . . 2kV
Thermal Resistance (Typical) JA (°C/W) JC (°C/W)
ISL28118
8 Ld SOIC Package (Notes 4, 5) . . . . . . . . . 120 60
8 Ld MSOP Package (Notes 4, 5) . . . . . . . . 165 57
ISL28218
8 Ld SOIC Package (Notes 4, 5) . . . . . . . . . 120 55
8 Ld MSOP Package (Notes 4, 5) . . . . . . . . 150 58
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . -40°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . +150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 3V (+1.8V/-1.2V) to 40V (±20V)
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For JC, the “case temp” location is taken at the package top center.
Electrical Specifications (VS ±15V) VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface entries apply
across the operating temperature range, -40°C to +125°C. Temperature data established by characterization.
PARAMETER DESCRIPTION TEST CONDITIONS
MIN
(Note 6)TYP
MAX
(Note 6)UNIT
VOS Input Offset Voltage ISL28118 -150 25 150 µV
-270 270 µV
ISL28218 -230 40 230 µV
-290 290 µV
TCVOS Input Offset Voltage Temperature
Coefficient
ISL28118 -1.2 0.2 1.2 µV/°C
ISL28218 -1.4 0.3 1.4 µV/°C
VOS Input Offset Voltage Match
(ISL28218 only)
All packages -280 44 280 µV
SOIC -365 365 µV
MSOP -390 390 µV
IBInput Bias Current -575 -230 nA
-800 nA
TCIBInput Bias Current
Temperature Coefficient
-0.8 nA/°C
IOS Input Offset Current -50 4 50 nA
-75 75 nA
CMRR Common Mode Rejection Ratio VCM = V- - 0.5V to V+ - 1.8V 118 dB
VCM = V- to V+ -1.8V
ISL28118 SOIC
102 118 dB
98 dB
VCM = V- to V+ -1.8V
ISL28218 SOIC
103 118 dB
99 dB
VCM = V- to V+ -1.8V
ISL28118 and ISL28218 MSOP
102 118 dB
97 dB
VCMIR Common Mode Input Voltage
Range
Guaranteed by CMRR test V- - 0.5 V+ - 1.8 V
V- V
+ - 1.8 V
ISL28118, ISL28218
FN7532 Rev 7.00 Page 6 of 29
July 27, 2015
PSRR Power Supply Rejection Ratio VS = 3V to 40V, VCMIR = Valid Input Voltage 109 124 dB
105 dB
AVOL Open-loop Gain VO = -13V to +13V, RL = 10kΩ to ground,
ISL28118 SOIC
125 136 dB
120 dB
VO = -13V to +13V, RL = 10kΩ to ground,
ISL28218 SOIC
125 136 dB
122 dB
VO = -13V to +13V, RL = 10kΩ to ground,
ISL28118 and ISL28218 MSOP
120 136 dB
116 dB
VOL Output Voltage Low, VOUT to V-
(see Figure 32)
ISL28118
RL = 10kΩ
70 mV
85 mV
ISL28218
RL = 10kΩ
70 mV
73 mV
VOH Output Voltage High, V+ to VOUT
(see Figure 32)
ISL28118
ISL28218
RL = 10kΩ
110 mV
120 mV
ISSupply Current/Amplifier ISL28118
RL = Open
0.85 1.2 mA
1.6 mA
ISL28218
RL = Open
0.85 1.1 mA
1.4 mA
ISC+ Output Short-circuit Source
Current
RL = 10Ωto V-16 mA
ISC- Output Short-circuit Sink Current RL = 10Ωto V+28 mA
VSUPPLY Supply Voltage Range Guaranteed by PSRR 3 40 V
AC SPECIFICATIONS
GBWP Gain Bandwidth Product ACL = 101, VOUT = 100mVP-P; RL = 2k 4 MHz
enp-p Voltage Noise 0.1Hz to 10Hz, VS = ±18V 300 nVP-P
enVoltage Noise Density f = 10Hz, VS = ±18V 8.5 nV/Hz
enVoltage Noise Density f = 100Hz, VS = ±18V 5.8 nV/Hz
enVoltage Noise Density f = 1kHz, VS = ±18V 5.6 nV/Hz
enVoltage Noise Density f = 10kHz, VS = ±18V 5.6 nV/Hz
in Current Noise Density f = 1kHz, VS = ±18V 355 fA/Hz
THD + N Total Harmonic Distortion + Noise 1kHz, G = 1, VO = 3.5VRMS, RL = 10kΩ0.0003 %
TRANSIENT RESPONSE
SR Slew Rate AV = 1, RL = 2kΩVO = 10VP-P ±1.2 V/µs
tr, tf, Small
Signal
Rise Time
10% to 90% of VOUT
AV
= 1,
VOUT = 100mVP-P
, Rf = 0Ω
R
L
=2k
Ωto VCM
100 ns
Fall Time
90% to 10% of VOUT
AV
= 1,
VOUT = 100mVP-P
, Rf = 0Ω
R
L
= 2k
Ωto VCM
100 ns
tsSettling Time to 0.01%
10V Step; 10% to VOUT
AV
= 1,
VOUT = 10VP-P
, Rf = 0Ω
R
L
=2k
Ωto VCM
8.5 µs
Electrical Specifications (VS ±15V) VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface entries apply
across the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued)
PARAMETER DESCRIPTION TEST CONDITIONS
MIN
(Note 6)TYP
MAX
(Note 6)UNIT
ISL28118, ISL28218
FN7532 Rev 7.00 Page 7 of 29
July 27, 2015
Electrical Specifications (VS ±5V) VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface entries apply across
the operating temperature range, -40°C to +125°C. Temperature data established by characterization.
PARAMETER DESCRIPTION TEST CONDITIONS
MIN
(Note 6) TYP
MAX
(Note 6) UNITS
VOS Input Offset Voltage ISL28118 -150 25 150 µV
-270 270 µV
ISL28218 -230 40 230 µV
-290 290 µV
TCVOS Input Offset Voltage Temperature
Coefficient
ISL28118 -1.2 0.2 1.2 µV/°C
ISL28218 -1.4 0.3 1.4 µV/°C
VOS Input Offset Voltage Match
(ISL28218 only)
-280 44 280 µV
-365 365 µV
IBInput Bias Current -575 -230 nA
-800 nA
TCIBInput Bias Current
Temperature Coefficient
-0.8 nA/°C
IOS Input Offset Current -50 4 50 nA
-75 75 nA
CMRR Common Mode Rejection Ratio VCM = V- - 0.5V to V+ - 1.8V 119 dB
VCM = V- to V+ -1.8V
ISL28118 and ISL28218 SOIC
101 117 dB
97 dB
VCM = V- to V+ -1.8V
ISL28118 and ISL28218 MSOP
101 117 dB
96 dB
VCMIR Common Mode Input Voltage
Range
Guaranteed by CMRR test V- - 0.5 V+ - 1.8 V
V-V+ - 1.8 V
PSRR Power Supply Rejection Ratio VS = 3V to 10V, VCMIR = Valid Input Voltage,
ISL28118 and ISL28218 SOIC
109 124 dB
105 dB
ISL28118 MSOP 108 124 dB
ISL28218 MSOP 107 124 dB
ISL28118 and ISL28218 MSOP 103 dB
AVOL Open-loop Gain VO = -3V to +3V, RL = 10kΩ to ground,
ISL28118 and ISL28218 SOIC
122 132 dB
117 dB
ISL28118 and ISL28218 MSOP 120 132 dB
115 dB
VOL Output Voltage Low, VOUT to V-
(see Figure 32)
RL = 10kΩ38 mV
45 mV
VOH Output Voltage High, V+ to VOUT
(see Figure 31)
RL = 10kΩ65 mV
70 mV
ISSupply Current/Amplifier RL = Open 0.85 1.1 mA
1.4 mA
ISC+ Output Short-circuit Source Current RL = 10Ωto V-13 mA
ISC- Output Short-circuit Sink Current RL = 10Ωto V+20 mA
ISL28118, ISL28218
FN7532 Rev 7.00 Page 8 of 29
July 27, 2015
AC SPECIFICATIONS
GBWP Gain Bandwidth Product ACL = 101, VOUT = 100mVP-P; RL = 2k 3.2 MHz
enp-p Voltage Noise 0.1Hz to 10Hz 320 nVP-P
enVoltage Noise Density f = 10Hz 9 nV/Hz
enVoltage Noise Density f = 100Hz 5.7 nV/Hz
enVoltage Noise Density f = 1kHz 5.5 nV/Hz
enVoltage Noise Density f = 10kHz 5.5 nV/Hz
in Current Noise Density f = 1kHz 380 fA/Hz
THD + N Total Harmonic Distortion + Noise 1kHz, G = 1, VO = 1.25VRMS, RL=10kΩ0.0003 %
TRANSIENT RESPONSE
SR Slew Rate AV = 1, RL = 2kΩVO = 4VP-P ±1 V/µs
tr, tf, Small
Signal
Rise Time
10% to 90% of VOUT
AV
= 1,
VOUT = 100mVP-P , Rf = 0Ω
R
L
=
2kΩ to VCM
100 ns
Fall Time
90% to 10% of VOUT
AV
= 1,
VOUT = 100mVP-P , Rf = 0Ω,
R
L
=2kΩ to VCM
100 ns
tsSettling Time to 0.01%
4V Step; 10% to VOUT
AV
= 1,
VOUT = 4VP-P
, Rf = 0Ω,
R
L
=2kΩ to VCM
4µs
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Electrical Specifications (VS ±5V) VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface entries apply across
the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued)
PARAMETER DESCRIPTION TEST CONDITIONS
MIN
(Note 6) TYP
MAX
(Note 6) UNITS
ISL28118, ISL28218
FN7532 Rev 7.00 Page 9 of 29
July 27, 2015
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified.
FIGURE 3. ISL28118 INPUT OFFSET VOLTAGE DISTRIBUTION FIGURE 4. ISL28118 INPUT OFFSET VOLTAGE DISTRIBUTION
FIGURE 5. ISL28218 INPUT OFFSET VOLTAGE DISTRIBUTION FIGURE 6. ISL28218 INPUT OFFSET VOLTAGE DISTRIBUTION
FIGURE 7. ISL28118 TCVOS vs NUMBER OF AMPLIFIERS ±15V FIGURE 8. ISL28118 TCVOS vs NUMBER OF AMPLIFIERS ±5V
VOS (µV)
NUMBER OF AMPLIFIERS
0
50
100
150
200
-120
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
VS = ±15V
VOS (µV)
NUMBER OF AMPLIFIERS
0
50
100
150
200
-120
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
VS = ±5V
0
50
100
150
200
250
-125
-100
-75
-50
-25
0
25
50
75
100
125
150
175
200
VOS (µV)
NUMBER OF AMPLIFIERS
VS = ±15V
0
50
100
150
200
250
-125
-100
-75
-50
-25
0
25
50
75
100
125
150
175
200
VOS (µV)
NUMBER OF AMPLIFIERS
VS = ±5V
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NUMBER OF AMPLIFIERS
TCVOS (µV/C)
0
2
4
6
8
10
12
14
16
18 VS = ±15V
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NUMBER OF AMPLIFIERS
TCVOS (µV/C)
0
2
4
6
8
10
12
14
16
18 VS = ±5V
ISL28118, ISL28218
FN7532 Rev 7.00 Page 10 of 29
July 27, 2015
FIGURE 9. ISL28218 TCVOS vs NUMBER OF AMPLIFIERS ±15V FIGURE 10. ISL28218 TCVOS vs NUMBER OF AMPLIFIERS ±5V
FIGURE 11. VOS vs TEMPERATURE FIGURE 12. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE
VOLTAGE, VS = ±15V
FIGURE 13. IBIAS vs VSFIGURE 14. IBIAS vs TEMPERATURE vs SUPPLY
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
0
5
10
15
20
25
30
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NUMBER OF AMPLIFIERS
TCVOS (µV/C)
VS = ±15V
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NUMBER OF AMPLIFIERS
TCVOS (µV/C)
0
5
10
15
20
25
30
35 VS = ±5V
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
0
10
20
30
40
50
60
70
80
90
100
VOS (µV)
VS = ±5V
VS = ±15V
VOS (µV)
INPUT COMMON MODE VOLTAGE (V)
-400
-300
-200
-100
0
100
200
300
400
-16 -15 -14 -13 13 14 15 16
-40°C
+25°C
+125°C
-200
IBIAS (nA)
-500
-450
-400
-350
-300
-250
-200
-150
-100
-50
0
2 4 6 8 10121416182022242628303234363840
VS (V)
IBIAS (nA)
-400
-350
-300
-250
-200
-150
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
VS = ±2.25V
VS = ±5V
VS = ±15V
VS = ±20V
VS = +2V/-1V
ISL28118, ISL28218
FN7532 Rev 7.00 Page 11 of 29
July 27, 2015
FIGURE 15. ISL28118 CMRR vs TEMPERATURE, VS = ±15V FIGURE 16. ISL28118 CMRR vs TEMPERATURE, VS = ±5V
FIGURE 17. ISL28218 CMRR vs TEMPERATURE, VS = ±15V FIGURE 18. ISL28218 CMRR vs TEMPERATURE, VS = ±5V
FIGURE 19. CMRR vs FREQUENCY, VS = ±15V FIGURE 20. PSRR vs TEMPERATURE, VS = ±15V
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
CMRR (dB)
110
112
114
116
118
120
122
124
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
CMRR (dB)
110
112
114
116
118
120
122
124
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
CMRR (dB)
110
112
114
116
118
120
122
124
126
128
130
132
CHANNEL-A
CHANNEL-B
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
CMRR (dB)
110
112
114
116
118
120
122
124
126
128
130
132
CHANNEL-A
CHANNEL-B
CMRR (dB)
FREQUENCY (Hz)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
1m 1 10 100 1k 10k 100k 1M 10M 100M 1G0.1
0.01
VS = ±15V
SIMULATION
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
100
105
110
115
120
125
130
135
140
PSRR (dB)
ISL28218
ISL28118
ISL28118, ISL28218
FN7532 Rev 7.00 Page 12 of 29
July 27, 2015
FIGURE 21. PSRR vs FREQUENCY, VS = ±15V FIGURE 22. PSRR vs FREQUENCY, VS = ±5V
FIGURE 23. OPEN-LOOP GAIN, PHASE vs FREQUENCY, VS = ±15V FIGURE 24. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
FIGURE 25. GAIN vs FREQUENCY vs RL, VS = ±15V FIGURE 26. GAIN vs FREQUENCY vs RL, VS = ±5V
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
-10
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
VS = ±15V
CL = 4pF
VCM = 1VP-P
RL = 10k
AV = 1 PSRR-
PSRR+
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
-10
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
VS = ±5V
CL = 4pF
VCM = 1VP-P
RL = 10k
AV = 1 PSRR-
PSRR+
50
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
140
160
180
200
1m 1 10 100 1k 10k 100k 1M 10M100M
1G
GAIN (dB)
FREQUENCY (Hz)
0.1
GAIN
VS = ±15V
RL = 1MΩ
PHASE
0.01
-10
0
10
20
30
40
50
60
70
1k 10k 100k 1M 10M
GAIN (dB)
FREQUENCY (Hz)
Rf = 0, RG = ∞
ACL = 1
ACL = 10
ACL = 100
ACL = 1000 Rf = 10kΩ, RG = 10Ω
Rf = 10kΩ, RG = 100Ω
Rf = 10kΩ, RG = 1kΩ
VS = ±5V AND ±15V
CL = 4pF
VOUT = 100mVP-P
RL = 2k
100
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
100k 1M 10M10k1k
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
100
VS = ±15V
AV = +1
VOUT = 100mVp-p
CL = 4pF
RL = 1k
RL = 499
RL = 100
RL = 49.9
RL = OPEN, 100k, 10k
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
100k 1M 10M10k1k
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
100
VS = ±5V
AV = +1
VOUT = 100mVp-p
CL = 4pF RL = 100
RL =
RL = OPEN, 100k, 10k
RL = 1k
RL = 49.9
RL = 499
ISL28118, ISL28218
FN7532 Rev 7.00 Page 13 of 29
July 27, 2015
FIGURE 27. GAIN vs FREQUENCY vs OUTPUT VOLTAGE FIGURE 28. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
FIGURE 29. OUTPUT OVERHEAD VOLTAGE vs TEMPERATURE,
VS = ±15V, RL=10k
FIGURE 30. OUTPUT OVERHEAD VOLTAGE vs TEMPERATURE,
VS = ±5V, RL=10k
FIGURE 31. OUTPUT OVERHEAD VOLTAGE HIGH vs LOAD CURRENT,
VS = ±5V AND ±15V
FIGURE 32. OUTPUT OVERHEAD VOLTAGE LOW vs LOAD CURRENT,
VS = ±5V AND ±15V
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
100k 1M 10M10k1k
-
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
100
VS = ±5V
AV = +1
RL = INF
CL = 4pF
VOUT = 10mVP-P
VOUT = 50mVP-P
VOUT = 100mVP-P
VOUT = 500mVP-P
VOUT = 1VP-P
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
100 1k 10k 100k 1M 10M
CL = 4pF
RL = 10k
AV = +1
VOUT = 100mVP-P
VS = ±1.5V
VS = ±15V
VS = ±5V
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
40
50
60
70
80
90 VS = ±15V
RL = 10k
VOH AND VOL (mV)
VOL
VOH
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
20
22
24
26
28
30
32
34
36
38
40 VS = ±5V
RL = 10k
VOH AND VOL (mV)
VOH
VOL
V
+
- V
OH
(V)
LOAD CURRENT (mA)
0.001
0.01
0.1
1
0.001 0.01 1 10
VS = ±5V and ±15V
+125°C
-40°C
+25°C
0.1
LOAD CURRENT (mA)
0.001
0.01
0.1
1
0.001 0.01 0.1 1 10
VS = ±5V and ±15V
V
OL
- V
-
(V)
-40°C
+25°C
+125°C
ISL28118, ISL28218
FN7532 Rev 7.00 Page 14 of 29
July 27, 2015
FIGURE 33. OUTPUT VOLTAGE SWING vs LOAD CURRENT VS = ±15V FIGURE 34. OUTPUT VOLTAGE SWING vs LOAD CURRENT VS = ±5V
FIGURE 35. ISL28118 SUPPLY CURRENT vs TEMPERATURE vs
SUPPLY VOLTAGE
FIGURE 36. ISL28218 SUPPLY CURRENT vs TEMPERATURE vs
SUPPLY VOLTAGE
FIGURE 37. SUPPLY CURRENT vs SUPPLY VOLTAGE
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
V
OH
0
VOL
I-FORCE (mA)
11
12
13
14
15
-15
-14
-13
-12
-11
20
18
16
1412
10
8
64
2
10
-10
VS = ±15V
AV = 2
VIN = ±7.5VDC
Rf = RG = 100k
-40°C
+25°C
0°C +75°C
+125°C
V
OH
0
VOL
I-FORCE (mA)
1
2
3
4
5
-5
-4
-3
-2
-1
20
18
16
1412
10
8
64
2
+125°C
-40°C
VS = ±5V
AV = 2
VIN = ±2.5VDC
Rf = RG = 100k
0°C
+25°C
+75°C
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
CURRENT (µA)
400
600
800
1000
1200
1400
VS = ±2.25V
VS = ±15V
VS = ±21V
800
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
CURRENT (µA)
400
600
800
1000
1200
1400
VS = ±2.25V
VS = ±21V
VS = ±15V
VSUPPLY (V)
0 2 4 6 8 1012141618202224262830323436384042
0
100
200
300
400
500
600
700
800
900
1000
1100
ISUPPLY PER AMPLIFIER (µA)
ISL28218
ISL28118
ISL28118, ISL28218
FN7532 Rev 7.00 Page 15 of 29
July 27, 2015
FIGURE 38. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs
FREQUENCY, VS = ±18V
FIGURE 39. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs
FREQUENCY, VS = ±5V
FIGURE 40. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS= ±18V FIGURE 41. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS= ±5V
FIGURE 42. THD+N vs FREQUENCY vs TEMPERATURE, AV = 1, 10,
RL= 2k
FIGURE 43. THD+N vs FREQUENCY vs TEMPERATURE, AV= 1, 10,
RL= 10k
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
0.1
1
10
100
0.1
1
10
100
0.1 1 10 100 1k 10k 100k
INPUT NOISE VOLTAGE (nV/√Hz)
FREQUENCY (Hz)
INPUT NOISE CURRENT (fA/√Hz)
INPUT NOISE VOLTAGE
INPUT NOISE CURRENT
VS = ±18V
0.1
1
10
100
0.1
1
10
100
0.1 1 10 100 1k 10k 100k
INPUT NOISE VOLTAGE (nV/√Hz)
FREQUENCY (Hz)
INPUT NOISE CURRENT (fA/√Hz)
INPUT NOISE VOLTAGE
INPUT NOISE CURRENT
VS = ±5V
INPUT NOISE VOLTAGE (nV)
012345678910
TIME (s)
-500
-400
-300
-200
-100
0
100
200
300
400
500
VS = ±18V
AV = 10k
INPUT NOISE VOLTAGE (nV)
012345678910
TIME (s)
-500
-400
-300
-200
-100
0
100
200
300
400
500
VS = ±5V
AV = 10k
0.0001
0.001
0.01
0.1
10 100 1k 10k 100k
THD + N (%)
FREQUENCY (Hz)
AV = 1
AV = 10
+125°C
+25°C
+125°C +25°C
VS = ±15V
CL = 4pF
VOUT = 10VP-P
RL = 2k
C-WEIGHTED
22Hz TO 500kHz
+40°C
+25°C
-40°C
0.0001
0.001
0.01
0.1
10 100 1k 10k 100k
THD + N (%)
FREQUENCY (Hz)
AV = 1
AV = 10
+125°C
VS = ±15V
CL = 4pF
VOUT = 10VP-P
RL = 10k
C-WEIGHTED
22Hz TO 500kHz
-40°C
+125°C
+25°C
+25°C
-40°C
ISL28118, ISL28218
FN7532 Rev 7.00 Page 16 of 29
July 27, 2015
FIGURE 44. THD+N vs OUTPUT VOLTAGE (VOUT) vs TEMPERATURE,
AV= 1, 10, RL = 2k
FIGURE 45. THD+N vs OUTPUT VOLTAGE (VOUT) vs TEMPERATURE,
AV= 1, 10, RL = 10k
FIGURE 46. LARGE SIGNAL 10V STEP RESPONSE, VS= ±15V FIGURE 47. LARGE SIGNAL 4V STEP RESPONSE, VS= ±5V
FIGURE 48. SMALL SIGNAL TRANSIENT RESPONSE,
VS = ±5V, ±15V
FIGURE 49. NO PHASE REVERSAL
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
0.0001
0.001
0.01
0.1
1
0 5 10 15 20 25 30
VOUT (VP-P)
THD + N (%)
AV = 1
AV = 10
+125°C -40°C
+125°C
-40°C
+25°C
VS = ±15V
CL = 4pF
f = 1kHz
RL = 2k
C-WEIGHTED
22Hz TO 22kHz
+25°C
0.0001
0.001
0.01
0.1
1
0 5 10 15 20 25 30
VOUT (VP-P)
THD + N (%)
AV = 1
AV = 10
-40°C
+125°C
-40°C +25°C
VS = ±15V
CL = 4pF
f = 1kHz
RL = 10k
C-WEIGHTED
22Hz TO 22kHz
+125°C
+25°C
-6
-4
-2
0
2
4
6
0 102030405060708090100
V
OUT
(V)
TIME (µs)
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
-2
0 102030405060708090100
V
OUT
(V)
TIME (µs)
-2.4
-2.0
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
1.6
2.0
2.4
VS = ±5V
AV = 1
RL = 2k
CL = 4pF
V
OUT
(mV)
TIME (µs)
-100
-80
-60
-40
-20
0
20
40
60
80
100
0 0.20.40.60.81.01.21.41.61.8 2
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
VS = ±5V
AND
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
01234
INPUT AND OUTPUT (V)
TIME (ms)
INPUT
VS = ±5V
VIN = ±5.9V
OUTPUT
ISL28118, ISL28218
FN7532 Rev 7.00 Page 17 of 29
July 27, 2015
FIGURE 50. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±15V
FIGURE 51. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±15V
FIGURE 52. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±5V
FIGURE 53. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±5V
FIGURE 54. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±15V FIGURE 55. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±5V
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
OUTPUT (V)
INPUT (mV)
TIME (µs)
0
4
8
12
16
20
0
40
80
120
160
200
0 4 8 1216202428323640
VS = ±15V
AV = 100
VIN = 100mVP-P
OVERDRIVE = 1V
RL = 10k
OUTPUT
INPUT
OUTPUT (V)
INPUT (mV)
TIME (µs)
-20
-16
-12
-8
-4
0
-200
-160
-120
-80
-40
0
0 4 8 12 16 20 24 28 32 36 40
VS = ±15V
AV = 100
VIN = 100mVP-P
OVERDRIVE = 1V
RL = 10k
OUTPUT
INPUT
OUTPUT (V)
INPUT (mV)
TIME (µs)
0
1
2
3
4
5
6
0
10
20
30
40
50
60
0 4 8 1216202428323640
INPUT
OUTPUT
VS = ±5V
AV = 100
VIN = 50mVP-P
OVERDRIVE = 1V
RL = 10k
OUTPUT (V)
INPUT (mV)
TIME (µs)
0 4 8 12 16 20 24 28 32 36 40-6
-5
-4
-3
-2
-1
0
-60
-50
-40
-30
-20
-10
0
VS = ±5V
AV = 100
VIN = 50mVP-P
OVERDRIVE = 1V
RL = 10k
OUTPUT
INPUT
0.01
0.10
1
10
100
10 100 1k 10k 100k 1M 10M
Z
OUT
(Ω)
FREQUENCY (Hz)
1
VS = ±15V
AV = 1
AV = 100
AV = 10
0.01
0.10
1
10
100
10 100 1k 10k 100k 1M 10M
Z
OUT
(Ω)
FREQUENCY (Hz)
1
VS = ±5V AV = 10
AV = 100
AV = 1
ISL28118, ISL28218
FN7532 Rev 7.00 Page 18 of 29
July 27, 2015
FIGURE 56. OVERSHOOT vs CAPACITIVE LOAD, VS=±15V FIGURE 57. OVERSHOOT vs CAPACITIVE LOAD, VS= ±5V
FIGURE 58. ISL28118 SHORTCIRCUIT CURRENT vs TEMPERATURE,
VS = ±15V
FIGURE 59. ISL28218 SHORTCIRCUIT CURRENT vs TEMPERATURE,
VS = ±15V
FIGURE 60. MAX OUTPUT VOLTAGE vs FREQUENCY FIGURE 61. CHANNEL SEPARATION vs FREQUENCY, RL= INF,
VS = ±15V
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
OVERSHOOT (%)
LOAD CAPACITANCE (nF)
0
10
20
30
40
50
60
0.001 0.010 0.100 1 10 100
VS = ±15V
VOUT = 100mVP-P
AV = 1
AV = -1
AV = 10
OVERSHOOT (%)
LOAD CAPACITANCE (nF)
0
10
20
30
40
50
60
0.001 0.01 0.1 1 10 100
VS = ±5V
VOUT = 100mVP-P
AV = 10
AV = 1
AV = -1
TEMPERATURE (°C)
-40-200 20406080100120
10
12
14
16
18
20
22
24
26
28
30
I
SC
(mA)
VS = ±15V
RL = 10k
ISC-SOURCE
ISC-SINK
TEMPERATURE (°C)
-40-20 0 20406080100120
10
12
14
16
18
20
22
24
26
28
30
I
SC
(mA)
VS = ±15V
RL = 10k
ISC-SINK
ISC-SOURCE
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1k 10k 100k 1M
V
OUT
(V
P-P
)
FREQUENCY (Hz)
VS = ±15V
AV = 1
10 100 1k 10k 100k 1M 10M
CROSSTALK (dB)
FREQUENCY (Hz)
RL_TRANSMIT = 2k
RL_RECEIVE = 10k
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
RL_TRANSMIT = ∞
RL_RECEIVE = 10k
VS = ±15V
CL = 4pF
VCM = 1VP-P
ISL28118, ISL28218
FN7532 Rev 7.00 Page 19 of 29
July 27, 2015
Applications Information
Functional Description
The ISL28118 and ISL28218 are single and dual, 3.2MHz,
single-supply, rail-to-rail output amplifiers with a common mode
input voltage range extending to a range of 0.5V below the V- rail.
Their input stages are optimized for precision sensing of
ground-referenced signals in single-supply applications. The input
stage is able to handle large input differential voltages without
phase inversion, making these amplifiers suitable for
high-voltage comparator applications. Their bipolar design
features high open loop gain and excellent DC input and output
temperature stability. These op amps feature very low quiescent
current of 850µV and low temperature drift. Both devices are
fabricated in a new precision 40V complementary bipolar DI
process and are immune from latch-up.
Operating Voltage Range
The op amp is designed to operate over a single supply range of 3V
to 40V or a split supply voltage range of +1.8V/-1.2V to ±20V. The
device is fully characterized at 10V (±5V) and 30V (±15V). Both DC
and AC performance remain virtually unchanged over the complete
operating voltage range. Parameter variation with operating voltage
is shown in the “Typical Performance Curves” on page 9.
The input common mode voltage to the V+ rail (V+ -1.8V over the
full temperature range) may limit amplifier operation when
operating from split V+ and V- supplies. Figure 12 on page 10
shows the common mode input voltage range variation over-
temperature.
Input Stage Performance
The ISL28118 and ISL28218 PNP input stage has a common
mode input range extending up to 0.5V below ground at +25°C
(Figure 12). Full amplifier performance is guaranteed down for
input voltage down to ground (V-) over the -40°C to +125°C
temperature range. For common mode voltages down to -0.5V
below ground (V-), the amplifiers are fully functional, but
performance degrades slightly over the full temperature range.
This feature provides excellent CMRR, AC performance and DC
accuracy when amplifying low-level, ground-referenced signals.
The input stage has a maximum input differential voltage equal
to a diode drop greater than the supply voltage (max 42V) and
does not contain the back-to-back input protection diodes found
on many similar amplifiers. This feature enables the device to
function as a precision comparator by maintaining very high
input impedance for high-voltage differential input comparator
voltages. The high differential input impedance also enables the
device to operate reliably in large signal pulse applications,
without the need for anti-parallel clamp diodes required on
MOSFET and most bipolar input stage op amps. Thus, input
signal distortion caused by nonlinear clamps under high slew
rate conditions is avoided.
In applications where one or both amplifier input terminals are at
risk of exposure to voltages beyond the supply rails,
current-limiting resistors may be needed at each input terminal
(see Figure 62, RIN+, RIN-) to limit current through the
power-supply ESD diodes to 20mA.
Output Drive Capability
The bipolar rail-to-rail output stage features low saturation levels
that enable an output voltage swing to less than 15mV when the
total output load (including feedback resistance) is held below
50µA (Figures 31 and 32). With ±15V supplies, this can be
achieved by using feedback resistor values >300kΩ.
The output stage is internally current limited. Output current limit
over-temperature is shown in Figures 33 and 34. The amplifiers
can withstand a short-circuit to either rail as long as the power
dissipation limits are not exceeded. This applies to only one
amplifier at a time for the dual op amp. Continuous operation
under these conditions may degrade long-term reliability.
The amplifiers perform well when driving capacitive loads
(Figures 56 and 57). The unity gain, voltage follower (buffer)
configuration provides the highest bandwidth but is also the most
sensitive to ringing produced by load capacitance found in BNC
cables. Unity gain overshoot is limited to 35% at capacitance values
to 0.33nF. At gains of 10 and higher, the device is capable of driving
more than 10nF without significant overshoot.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply voltage.
The ISL28118 and ISL28218 are immune to output phase reversal
out to 0.5V beyond the rail (VABS MAX) limit (Figure 49).
Single Channel Usage
The ISL28218 is a dual op amp. If the application requires only
one channel, the user must configure the unused channel to
prevent it from oscillating. The unused channel oscillates if the
input and output pins are floating. This results in higher than
expected supply currents and possible noise injection into the
channel being used. The proper way to prevent oscillation is to
short the output to the inverting input and ground the positive
input (Figure 63).
FIGURE 62. INPUT ESD DIODE CURRENT LIMITING
-
+
RIN-
RL
VIN-
V+
V-
RIN+
VIN+
RF
RG
FIGURE 63. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
-
+
ISL28118, ISL28218
FN7532 Rev 7.00 Page 20 of 29
July 27, 2015
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
Where
•PD
MAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
•T
MAX = Maximum ambient temperature
•JA = Thermal resistance of the package
PDMAX for each amplifier can be calculated using Equation 2:
Where
•PD
MAX = Maximum power dissipation of 1 amplifier
•V
S = Total supply voltage
•I
qMAX = Maximum quiescent supply current of one amplifier
•V
OUTMAX = Maximum output voltage swing of the application
•R
L = Load resistance
ISL28118 and ISL28218 SPICE Model
Figure 64 on page 21 shows the SPICE model schematic and
Figure 65 on page 22 shows the net list for the SPICE model. The
model is a simplified version of the actual device and simulates
important AC and DC parameters. AC parameters incorporated
into the model are: 1/f and flatband noise voltage, slew rate,
CMRR and gain and phase. The DC parameters are IOS, total
supply current and output voltage swing. The model uses typical
parameters given in the “Electrical Specifications” table beginning
on page 5. The AVOL is adjusted for 136dB with the dominant pole
at 0.6Hz. The CMRR is set at 120dB, f = 50kHz. The input stage
models the actual device to present an accurate AC
representation. The model is configured for an ambient
temperature of +25°C.
Figures 66 through 80 show the characterization vs simulation
results for the noise voltage, open loop gain phase, closed loop
gain vs frequency, gain vs frequency vs RL, CMRR, large signal
10V step response, small signal 0.1V step and output voltage
swing ±15V supplies.
LICENSE STATEMENT
The information in the SPICE model is protected under United
States copyright laws. Intersil Corporation hereby grants users of
this macro-model, hereto referred to as “Licensee”, a
nonexclusive, nontransferable licence to use this model, as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to anyone
outside the Licensee’s company. The Licensee may modify the
macro-model to suit his/her specific applications and the
Licensee may make copies of this macro-model for use within
their company only.
This macro-model is provided “AS IS, WHERE IS AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral, incidental, or
consequential damages in connection with, or arising out of, the use
of this macro-model. Intersil reserves the right to make changes to
the product and the macro-model without prior notice.
TJMAX TMAX JAxPDMAXTOTAL
+= (EQ. 1)
PDMAX VSIqMAX VS
- VOUTMAXVOUTMAX
RL
----------------------------
+=(EQ. 2)
FN7532 Rev 7.00 Page 21 of 29
July 27, 2015
ISL28118, ISL28218
FIGURE 64. SPICE SCHEMATIC
Vout
V--
V++
Common Mode
Gain Stage
with Zero
Correction Current SourcesOutput Stage
Input Stage 1st Gain Stage
Mid Supply ref V2nd Gain Stage
19
27
VOUT
5
14
23
Vmid
V--
V++ V++
V--
6
12
17
V+
Vg
16
11
Vin-
Vin+
8
V--
4
3
107
9
22
21
24
18
Vcm
Vc
25
1
13
26
V-
2
15
20
V--
0
0
0
0
Q6
PNP_input
Q6
+
-
G4
+
-
G4
DY
D12
DY
D12
-
++
-
En
GAIN = 0.3
-
++
-
En
GAIN = 0.3
R16
80
+
-
G13
GAIN = 12.5e-3
-
R13
795.7981795.7981
L1
3.18319E-09
-
+
+
--
+
+
-
GAIN = 0.5
+
-
G6
GAIN = 1
-
G6
C4
10e-12
C4
10e-12
L3
3.18319E-09
L3
3.18319E-09
D1DBREAK
Q8
PNP_LATERAL
Q8
DX
D5
DX
D5
C3
10e-12
C3
10e-12
I3
54E-6
I3
CinDif
1.33E-12
IOS
4e-9
IOS
+
-
GAIN = 1
+
-
Q9
PNP_LATERAL
Q9
PNP_LATERAL
R18
750
R18
750 R1
5e115e11
ISY
2.5E-3
ISY
R9
1e-3
R6
11
V1
-0.91 V1
DN
D14
DN
D14
+
-
G8
GAIN = 1
-
G8
-
+
+
-
E3
GAIN = 1
-
+
-
V5
-0.4
V5
-0.4
+
-
G12
GAIN = 12.5e-3
+
-
GAIN = 12.5e-3
I2
54E-6
I2
I1
80e-6
I1
DX
D4
DX
D4
795.7981
Cin2
4.02e-12
V4
-0.96
V4
Cin1
4.02e-124.02e-12
DY
D9
DY
D9
V6
-0.4
V6
DX
D6
DX
D6
DX
D7
DX
D7
-
G2
G
GAIN = 0.65897
-
G2
G
GAIN = 0.65897
+
-
G9
GAIN = 1.2566e-3
+
-80
V7
0.10.1
R2
5e115e11
R10
1e-3
+
-
GAIN = 1.69138e-3
+
-
C2
6.6667E-11
C2
6.6667E-11
V3
-0.91 V3
DN
D13
DN
D13
V2
-0.96 V2
R5
11
+
-
G14
GAIN = 12.5e-3
-
L2
3.18319E-09
+
-
G11
GAIN = 12.5e-3
+
-
+
-
G5
GAIN = 1
+
-
L4
3.18319E-09
L4
3.18319E-09
R7
3.7304227e9
DX
D10
DX
D10
R12
1e-3
R12
DX
D3
DX
D3
DX
D8
DX
D8
DX
D11
DX
D11
C1
6.6667E-11
C1
6.6667E-11
D2DBREAK
R17
750
R17
750
+
-
G10
GAIN = 1.2566e-3
+
-
G10
Q7
PNP_input
Q7
R3
1k
R3
+
-
G1
GAIN = 0.65897
-
G1
GAIN = 0.65897
-
++
-
EOS
GAIN = 1
-
++
-
EOS
V8
0.10.1
R4
1k
R4
R11
1e-3
R11
1e-3
-
+
+
-
E2
GAIN = 1
-
+
+
-
E2
3.7304227e9 R14
GAIN = 1.69138e-3
R15
ISL28118, ISL28218
FN7532 Rev 7.00 Page 22 of 29
July 27, 2015
*ISL28118_218 Macromodel - covers
following *products
*ISL28118
*ISL28218
*
*Revision History:
* Revision B, LaFontaine January 22 2014
* Model for Noise, supply currents, CMRR
*120dB f = 40kHz, AVOL 136dB f = 0.5Hz
* SR = 1.2V/us, GBWP 4MHz.
*Copyright 2011 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT”
*Use of this model indicates your acceptance
*with the terms and provisions in the License
*Statement.
*
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performance
characteristics *under a wide range of
external circuit *configurations using
compatible simulation *platforms – such as
iSim PE.
*
*Device performance features supported by
this *model:
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances,
*Open loop gain and phase,
*Closed loop bandwidth and frequency
*response,
*Loading effects on closed loop frequency
*response,
*Input noise terms including 1/f effects,
*Slew rate,
*Input and Output Headroom limits to I/O
*voltage swing,
*Supply current at nominal specified supply
*voltages,
*
*Device performance features NOT
supported *by this model:
*Harmonic distortion effects,
*Output current limiting (current will limit at
*40mA),
*Disable operation (if any),
*Thermal effects and/or over-temperature
*parameter variation,
*Limited performance variation vs. supply
*voltage is modeled,
*Part to part performance variation due to
*normal process parameter spread,
*Any performance difference arising from
*different packaging,
*Load current reflected into the power supply
*current.
* source ISL28118_218 SPICEmodel
*
* Connections: +input
* | -input
* | | +Vsupply
* | | | -Vsupply
* | | | | output
.subckt ISL28118_218 Vin+ Vin-V+ V- VOUT
* source ISL28118_218_presubckt_0
*
*Voltage Noise
E_En VIN+ 6 2 0 0.3
D_D13 1 2 DN
D_D14 1 2 DN
V_V7 1 0 0.1
V_V8 4 0 0.1
R_R17 2 0 750
*R_R18 3 0 750
*
*Input Stage
Q_Q6 11 10 9 PNP_input
Q_Q7 8 7 9 PNP_input
Q_Q8 V-- VIN- 7 PNP_LATERAL
Q_Q9 V-- 12 10 PNP_LATERAL
I_I1 V++ 9 DC 80e-6
I_I2 V++ 7 DC 54E-6
I_I3 V++ 10 DC 54E-6
I_IOS 6 VIN- DC 4e-9
D_D1 7 10 DBREAK
D_D2 10 7 DBREAK
R_R1 5 6 5e11
R_R2 VIN- 5 5e11
R_R3 V-- 8 1000
R_R4 V-- 11 1000
C_Cin1 V-- VIN- 4.02e-12
C_Cin2 V-- 6 4.02e-12
C_CinDif 6 VIN- 1.33E-12
*
*1st Gain Stage
G_G1 V++ 14 8 11 0.65897
G_G2 V-- 14 8 11 0.65897
V_V1 13 14 -0.91
V_V2 14 15 -0.96
D_D3 13 V++ DX
D_D4 V-- 15 DX
R_R5 14 V++ 1
R_R6 V-- 14 1
*
*2nd Gain Stage
G_G3 V++ VG 14 VMID 1.69138e-3
G_G4 V-- VG 14 VMID 1.69138e-3
V_V3 16 VG -0.91
V_V4 VG 17 -0.96
D_D5 16 V++ DX
D_D6 V-- 17 DX
R_R7 VG V++ 3.7304227e9
R_R8 V-- VG 3.7304227e9
C_C1 VG V++ 6.6667E-11
C_C2 V-- VG 6.6667E-11
*
*Mid supply Ref
E_E2 V++ 0 V+ 0 1
E_E3 V-- 0 V- 0 1
E_E4 VMID V-- V++ V-- 0.5
I_ISY V+ V- DC 0.85E-3
*
*Common Mode Gain Stage with Zero
G_G5 V++ 19 5 VMID 1
G_G6 V-- 19 5 VMID 1
G_G7 V++ VC 19 VMID 1
G_G8 V-- VC 19 VMID 1
E_EOS 12 6 VC VMID 1
L_L1 18 V++ 3.18319E-09
L_L2 20 V-- 3.18319E-09
L_L3 21 V++ 3.18319E-09
L_L4 22 V-- 3.18319E-09
R_R9 19 18 1e-3
R_R10 20 19 1e-3
R_R11 VC 21 1e-3
R_R12 22 VC 1e-3
*
*Pole Stage
G_G9 V++ 23 VG VMID 1.2566e-3
G_G10 V-- 23 VG VMID 1.2566e-3
R_R13 23 V++ 795.7981
R_R14 V-- 23 795.7981
C_C3 23 V++ 10e-12
C_C4 V-- 23 10e-12
*
*Output Stage with Correction Current
Sources
G_G11 26 V-- VOUT 23 12.5e-3
G_G12 27 V-- 23 VOUT 12.5e-3
G_G13 VOUT V++ V++ 23 12.5e-3
G_G14 V-- VOUT 23 V-- 12.5e-3
D_D7 23 24 DX
D_D8 25 23 DX
D_D9 V-- 26 DY
D_D10 V++ 26 DX
D_D11 V++ 27 DX
D_D12 V-- 27 DY
V_V5 24 VOUT -0.4
V_V6 VOUT 25 -0.4
R_R15 VOUT V++ 80
R_R16 V-- VOUT 80
.model PNP_LATERAL pnp(is=1e-016
bf=250 va=80
+ ik=0.138 rb=0.01 re=0.101 rc=180 kf=0
af=1)
.model PNP_input pnp(is=1e-016 bf=100
va=80
+ ik=0.138 rb=0.01 re=0.101 rc=180 kf=0
af=1)
.model DBREAK D(bv=43 rs=1)
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28118_218
FIGURE 65. SPICE NET LIST
ISL28118, ISL28218
FN7532 Rev 7.00 Page 23 of 29
July 27, 2015
Characterization vs Simulation Results
FIGURE 66. CHARACTERIZED INPUT NOISE VOLTAGE FIGURE 67. SIMULATED INPUT NOISE VOLTAGE
FIGURE 68. CHARACTERIZED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
FIGURE 69. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY
FIGURE 70. CHARACTERIZED CLOSED-LOOP GAIN vs FREQUENCY FIGURE 71. SIMULATED CLOSED-LOOP GAIN vs FREQUENCY
0.1
1
10
100
0.1
1
10
100
0.1 1 10 100 1k 10k 100k
INPUT NOISE VOLTAGE (nV/√Hz)
FREQUENCY (Hz)
INPUT NOISE CURRENT (fA/√Hz)
VS = ±18V
INPUT NOISE VOLTAGE
INPUT NOISE CURRENT
0.1
1
10
100
0.1 1 10 100 1k 10k 100k
INPUT NOISE VOLTAGE (nV/√Hz)
FREQUENCY (Hz)
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
140
160
180
200
1m 1 10 100 1k 10k 100k 1M 10M100M 1G
GAIN (dB)
FREQUENCY (Hz)
0.1
VS = ±15V
RL = 1MΩ
0.01
GAIN
PHASE
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
140
160
180
200
1m 1 10 100 1k 10k 100k 1M 10M100M 1G
GAIN (dB)
FREQUENCY (Hz)
0.1
0.01
VS = ±15V
RL = 1MΩ
PHASE
GAIN
-10
0
10
20
30
40
50
60
70
1k 10k 100k 1M 10M
GAIN (dB)
FREQUENCY (Hz)
ACL = 1
ACL = 10
ACL = 100
ACL = 1000 Rf = 10kΩ, RG = 10Ω
VS = ±5V AND ±15V
CL = 4pF
VOUT = 100mVP-P
RL = 2k
100
Rf = 10kΩ, RG = 100Ω
Rf = 10kΩ, RG = 1kΩ
Rf = 0, RG = ∞
-10
0
10
20
30
40
50
60
70
1k 10k 100k 1M 10M
GAIN (dB)
FREQUENCY (Hz)
ACL = 1
ACL = 10
ACL = 1000
RF = 10kΩ, RG = 1kΩ
VS = ±5V & ±15V
CL = 4pF
VOUT = 100mVP-P
RL = 2k
100
ACL = 100
Rf = 10kΩ, RG = 10Ω
RF = 0, RG = ∞
Rf = 10kΩ, RG = 100Ω
ISL28118, ISL28218
FN7532 Rev 7.00 Page 24 of 29
July 27, 2015
FIGURE 72. CHARACTERIZED GAIN vs FREQUENCY vs RLFIGURE 73. SIMULATED GAIN vs FREQUENCY vs RL
FIGURE 74. CHARACTERIZED CMRR vs FREQUENCY FIGURE 75. SIMULATED CMRR vs FREQUENCY
FIGURE 76. CHARACTERIZED LARGE-SIGNAL 10V STEP RESPONSE FIGURE 77. SIMULATED LARGE-SIGNAL 10V STEP RESPONSE
Characterization vs Simulation Results (Continued)
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
100k 1M 10M10k1k
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
VS = ±15V
AV = +1
VOUT = 100mVp-p
CL = 4pF
RL = OPEN, 100k, 10k
100
R
L
= 499k
RL = 1k
RL = 100k
RL = 49.9k
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
100k 1M 10M10k1k
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
100
RL = 1k
RL = 499k
RL = 100k
RL = 49.9k
RL = OPEN, 100k, 10k
VS = ±15V
AV = +1
VOUT = 100mVp-p
CL = 4pF
CMRR (dB)
FREQUENCY (Hz)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
1m 1 10 100 1k 10k 100k 1M 10M 100M 1G0.1
0.01
VS = ±15V
SIMULATION
CMRR (dB)
FREQUENCY (Hz)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
1m 1 10 100 1k 10k 100k 1M 10M 100M 1G0.1
0.01
VS = ±15V
SIMULATION
-6
-4
-2
0
2
4
6
0 102030405060708090100
V
OUT
(V)
TIME (µs)
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
-6
-4
-2
0
2
4
6
0 102030405060708090100
V
OUT
(V)
TIME (µs)
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
ISL28118, ISL28218
FN7532 Rev 7.00 Page 25 of 29
July 27, 2015
FIGURE 78. CHARACTERIZED SMALL-SIGNAL TRANSIENT RESPONSE FIGURE 79. SIMULATED SMALL-SIGNAL TRANSIENT RESPONSE
FIGURE 80. SIMULATED OUTPUT VOLTAGE SWING
Characterization vs Simulation Results (Continued)
V
OUT
(mV)
TIME (µs)
-100
-80
-60
-40
-20
0
20
40
60
80
100
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
VS = ±5V
AND
V
OUT
(V)
TIME (µs)
-100
-80
-60
-40
-20
0
20
40
60
80
100
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
VS = ±5V
AND
00.5 1.0 1.5 2.0
-20V
-10V
0V
10V
20V
OUTPUT VOLTAGE SWING (V)
TIME (ms)
VS = ±15V
RL = 10kΩ VOL = -14.93V
VOH = 14.88V
ISL28118, ISL28218
FN7532 Rev 7.00 Page 26 of 29
July 27, 2015
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE REVISION CHANGE
July 27, 2015 FN7532.7 Page 1 under Features:
Removed bullet 3 (Rail-to-rail input differential voltage range for comparator application).
Added to the end of bullet 2 "ground sensing".
July 15, 2015 FN7532.6 Figures 48 and 78 changed Y-axis from (V) to (mV).
May 1, 2014 FN7532.5 Updated Spice model netlist on page 22.
Absolute Maximum Ratings table on page 5: Added ESD Tolerance (ISL28118 SOIC package only).
Changed POD:
FROM M8.118: Corrected lead width dimension in side view 1 from "0.25 - 0.036" to "0.25 - 0.36"
To M8.118B: Correct lead dimension in side view 2 from 0.15 - 0.05mm to 0.15+/-0.05mm.
January 24, 2013 FN7532.4 Added ISL28218 MSOP specifications, and removed references to ISL28118 and ISL28218 TDFN options.
page 1: Removed “8 Ld TDFN” from last paragraph of description.
page 3: Removed TDFN “Pin Configurations”, and TDFN columns and the “PAD” row from “Pin Descr” table.
Moved Ordering Information table from pg 3 to page 2. Removed “Coming Soon” from ISL28218FUZ and added “Note
1” reference, and deleted 2 TDFN offerings in “Ordering Info” table.
page 5: Removed TDFN entries from “Thermal Resistance” section, and removed notes 5 and 6.
Added delta Vos MSOP row, with limits of ±390µA, and added “ISL28218” to the CMRR MSOP entry.
page 6: added “ISL28218” to the existing AVOL MSOP entry.
page 7: added new +25°C 28218 MSOP row with 107dB min limit, and added “ISL28218 MSOP” to the existing
ISL28118 MSOP full temp row for PSRR.
page 7: added “ISL28218” to the existing CMRR SOIC and MSOP rows, and deleted the “ISL28218” rows.
page 7: added “ISL28218 MSOP” to the existing ISL28118 MSOP rows for AVOL.
page 9: added “+25°C” to “default conditions” info at top of page.
Moved “sales Info” from p25 to p23.
Removed TDFN package outline drawing.
August 31, 2011 FN7532.3 Page 7: Electrical Spec Table for Supply Current/Amplifier
Change from: 1.4µA Full Temp Max
Change to: 1.4mA Full Temp Max
Page 28: Updated POD M8.118 to current revision. Corrected lead width dimension in side view 1 from "0.25 - 0.036" to
"0.25 - 0.36".
May 9, 2011 FN7532.2 Page 2: Added NC pin to Pin Descriptions table.
Page 3: Added ISL28218EVAL1Z evaluation board to the Ordering Information table.
Page 12: Added new Output Overhead Voltage plots (Figs. 31,32)
Pages 19 through 24: Added SPICE model schematic, netlist, description and Figs. 66 through 80.
November 12, 2010 FN7532.1 On page 1: Features Section, added Low input offset voltage and superb offset voltage temperature drift for
ISL28118.
Updated Intersil trademark statement (bottom of page)
On page 4: Removed “coming soon” from ISL28118FBZ. Updated tape & reel note.
On page 5: Change ISL28118 Theta JA value from 158 to 165. Added ISL28118 min/max specs to VOS (input
offset voltage), TCVOS and min specs to CMRR.
On page 6: Added AVOL MIN spec for ISL28118 in dB. Changed existing AVOL spec from V/mV to dB. Added VOL
max spec for ISL28118, IS Typ and Max spec for ISL28118. Changed TS from 18µs to 8.5µs.
On page 7: Added Min Max VOS spec, TCVOS spec for ISL28118. Changed AVOL specs from V/mV to dB.
On page 8: Changed Slew Rate TYP from ±1.2V/µs to ±1V/µs. Added for TS TYP spec = 4µs. Changed min/max
note 6 to “Compliance to datasheet limits is assured by one or more methods: production test, characterization
and/or design.” Added Figs 3 & 4 for ISL28118. Figures 5 & 6 moved to page 9.
On page 9: Added Figures 7 & 8
On page 11: Added Figures 15 & 16 for ISL28118
On page 11, in Figure 19, changed VS from ±5V to ±15V
On page 13 and page 14: Added Figures 27, 28, 31 & 34 for ISL28118
On page 14: Added Figure 35 for ISL28118
On page 15: Figure 41 changed VS from ±18V to ±5V, Figure 42 added RL = 2k, Figure 43 added RL = 10k and
corrected "HD+N" to "THD+N"
On page 16, Figure 44 added RL = 2k, Figure 45 RL = 10k.
On page 18: Added Figure 58 for ISL28118
On page 18, Figure 58 and 59, graph upper left corner changed VS = ±5V to VS = ±15V
On page 18, Figure 61, deleted VS = ±5V
September 16, 2010 FN7532.0 Initial Release
FN7532 Rev 7.00 Page 27 of 29
July 27, 2015
ISL28118, ISL28218
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
For additional products, see www.intersil.com/en/products.html
© Copyright Intersil Americas LLC 2010-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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Reliability reports are also available from our website at www.intersil.com/support
ISL28118, ISL28218
FN7532 Rev 7.00 Page 28 of 29
July 27, 2015
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
Unless otherwise specified, tolerance : Decimal ± 0.05
The pin #1 identifier may be either a mold or mark feature.
Interlead flash or protrusions shall not exceed 0.25mm per side.
Dimension does not include interlead flash or protrusions.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "A"
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
A
B
4
4
0.25 AMC B
C
0.10 C
5
ID MARK
PIN NO.1
(0.35) x 45°
SEATING PLANE
GAUGE PLANE
0.25
(5.40)
(1.50)
4.90 ± 0.10
3.90 ± 0.10
1.27 0.43 ± 0.076
0.63 ±0.23
4° ± 4°
DETAIL "A" 0.22 ± 0.03
0.175 ± 0.075
1.45 ± 0.1
1.75 MAX
(1.27) (0.60)
6.0 ± 0.20
Reference to JEDEC MS-012.
6.
SIDE VIEW “B”
ISL28118, ISL28218
FN7532 Rev 7.00 Page 29 of 29
July 27, 2015
Package Outline Drawing
M8.118B
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 3/12
DETAIL "X"
SIDE VIEW 2
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
PIN# 1 ID
0.23 - 0.36mm
DETAIL "X"
0.10 ± 0.05mm
(4.40)
(3.00)
(5.80)
H
C
1.10 MAX
3°±3°
GAUGE
PLANE 0.25
0.95 REF
0.53 ± 0.10mm
B
3.0±0.10mm
12
8
0.86±0.05mm
SEATING PLANE
A
0.65mm BSC
3.0±0.10mm
(0.40)
(1.40)
(0.65)
D
5
5
0.15±0.05mm
SIDE VIEW 1
0.08 C A-B D
M0.10 C
Dimensioning and tolerancing conform to JEDEC MO-187-AA
Plastic interlead protrusions of 0.15mm max per side are not
Dimensions in ( ) are for reference only.
Dimensions are measured at Datum Plane "H".
Plastic or metal protrusions of 0.15mm max per side are not
Dimensions are in millimeters.
3.
4.
5.
6.
NOTES:
1.
2.
and AMSEY14.5m-1994.
included.
included.
4.9±0.20mm
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Intersil:
ISL28118FBZ ISL28118FBZ-T13 ISL28118FBZ-T7 ISL28118FBZ-T7A ISL28118FUZ-T7A ISL28218FBZ
ISL28218FBZ-T13 ISL28218FBZ-T7A ISL28218FUZ-T7 ISL28218FUZ ISL28218FUZ-T7A ISL28218FUZ-T13
ISL28118FUZ ISL28118FUZ-T7 ISL28118FUZ-T13