DS34LV87T
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SNLS116D –JULY 2006–REVISED APRIL 2013
DS34LV87T Enhanced CMOS Quad Differential Line Driver
Check for Samples: DS34LV87T
1FEATURES DESCRIPTION
The DS34LV87T is a high speed quad differential
• Meets TIA/EIA-422-B (RS-422) and ITU-T V.11 CMOS driver that meets the requirements of both
Recommendation TIA/EIA-422-B and ITU-T V.11. The CMOS
• Interoperable With Existing 5V RS-422 DS34LV87T features low static ICC of 100 μA max
Networks which makes it ideal for battery powered and power
conscious applications. The TRI-STATE enable, EN,
• Ensured VOD of 2V Min Over Operating allows the device to be disabled when the device is
Conditions not in use to minimize power. The dual enable
• Balanced Output Crossover for Low EMI scheme allows for flexibility in turning devices on or
(Typical Within 40 mV of 50% Voltage Level) off.
• Low Power Design (330 μW @ 3.3V Static) Protection diodes protect all the driver inputs against
• ESD ≥7 kV on Cable I/O Pins (HBM) electrostatic discharge. The driver and enable inputs
• Industrial Temperature Range (DI and EN) are compatible with LVTTL and
LVCMOS devices. Differential outputs have the same
• Ensured AC Parameter: VOD (≥2V) ensure as the 5V version. The outputs
– Maximum Driver Skew: 2 ns have enhanced ESD Protection providing greater
– Maximum Transition Time: 10 ns than 7 kV tolerance.
• Pin Compatible With DS26C31
• Available in SOIC Packaging
TRUTH TABLE(1)
Connection Diagram Enables Input Outputs
EN DI DO+ DO−
L X Z Z
H H H L
H L L H
(1) L = Low logic state
X = Irrelevant
Figure 1. Dual-In-Line Package (Top View) H = High logic state
See Package Number D0016A Z = TRI-STATE
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS34LV87T
SNLS116D –JULY 2006–REVISED APRIL 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Supply Voltage (VCC)−0.5V to +7V
Enable Input Voltage (EN) −0.5V to VCC + 0.5V
Driver Input Voltage (DI)−0.5V to VCC + 0.5V
Clamp Diode Current ±20 mA
DC Output Current, per pin ±150 mA
Driver Output Voltage (Power Off: DO+, DO−)−0.5V to +7V
Maximum Package Power Dissipation D Package
@+25°C 1226 mW
Derate D Package 9.8 mW/°C above +25°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range (Soldering, 4 sec.) +260°C
ESD Ratings (HBM, 1.5k, 100 pF) Driver Outputs ≥7 kV
Other Pins ≥2.5 kV
(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(2) Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that
the device should be operated at these limits. The table of Electrical Characteristics specifies conditions of device operation.
RECOMMENDED OPERATING CONDITIONS Min Typ Max Units
Supply Voltage (VCC) 3.0 3.3 3.6 V
Operating Free Air Temperature Range (TA)−40 25 +85 °C
DS34LV87T
Input Rise and Fall Time 500 ns
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SNLS116D –JULY 2006–REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS(1)(2)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified
Symbol Parameter Conditions Pin Min Typ Max Units
VOD1 Output Differential Voltage RL=∞, (No Load) DO+, 3.3 4.0 V
DO−
VOD2 Output Differential Voltage RL= 100ΩSee Figure 2 2 2.6 V
ΔVOD2 Change in Magnitude of −400 7 400 mV
Output Differential Voltage
VOD3 Output Differential Voltage RL= 3900Ω(V.11), See 3.2 3.5 V
Figure 2(3)
VOC Common Mode Voltage RL= 100ΩSee Figure 2 1.5 2 V
ΔVOC Change in Magnitude of −400 6 400 mV
Common Mode Voltage
IOZ TRI-STATE Leakage Current VOUT = VCC or GND ±0.5 ±20 μA
Drivers Disabled
ISC Output Short Circuit Current VOUT = 0V −40 −70 −150 mA
VIN = VCC or GND(4)
IOFF Output Leakage Current VCC= 0V, VOUT = 3V 0.03 100 μA
VCC = 0V, VOUT =−0.25V −0.08 −100 μA
VIH High Level Input Voltage DI, 2.0 VCC V
EN
VIL Low Level Input Voltage GND 0.8 V
IIH High Level Input Current VIN= VCC 10 μA
IIL Low Level Input Current VIN = GND −10 μA
VCL Input Clamp Voltage IIN =−18 mA −1.5 V
ICC Power Supply Current No Load, VIN (all) = VCC or GND VCC 100 μA
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except differential voltages VOD1, VOD2, VOD3.
(2) All typical values are given for VCC= 3.3V and TA= +25°C.
(3) This specification limit is for compliance with TIA/EIA-422-B and ITU-T V.11.
(4) Only one output shorted at a time. The output (true or complement) is configured High.
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SWITCHING CHARACTERISTICS(1)(2)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
tPHLD Differential Propagation Delay RL= 100Ω, CL= 50 pF 6 10.5 16 ns
High to Low See Figure 3 and Figure 4
tPLHD Differential Propagation Delay 6 11 16 ns
Low to High
tSKD Differential Skew 0.5 2.0 ns
|tPHLD–tPLHD|
tSK1 Skew, Pin to Pin (same device) 1.0 2.0 ns
tSK2 Skew, Part to Part(3) 3.0 5.0 ns
tTLH Differential Transition Time 4.2 10 ns
Low to High (20% to 80%)
tTHL Differential Transition Time 4.7 10 ns
High to Low (80% to 20%)
tPHZ Disable Time High to Z See Figure 5 and Figure 6 12 20 ns
tPLZ Disable Time Low to Z 9 20 ns
tPZH Enable Time Z to High 22 32 ns
tPZL Enable Time Z to Low 22 32 ns
fMAX Maximum Operating Frequency(4) 32 MHz
(1) f = 1 MHz, trand tf≤6 ns (10% to 90%).
(2) See TIA/EIA-422-B specifications for exact test conditions.
(3) Devices are at the same VCC and within 5°C within the operating temperature range.
(4) All channels switching, output duty cycle criteria is 40%/60% measured at 50%. This parameter is ensured by design and
characterization.
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SNLS116D –JULY 2006–REVISED APRIL 2013
PARAMETER MEASUREMENT INFORMATION
Figure 2. Differential Driver DC Test Circuit
Figure 3. Differential Driver Propagation Delay and Transition Time Test Circuit
Generator waveform for all tests unless otherwise specified: f = 1 MHz, Duty Cycle = 50%, Zo= 50Ω, tr≤10 ns, tf≤
10 ns.
CLincludes probe and fixture capacitance.
Figure 4. Differential Driver Propagation Delay and Transition Time Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
Figure 5. Driver Single-Ended Tri-state Test Circuit
Figure 6. Driver Single-Ended Tri-state Waveforms
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DS34LV87T
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SNLS116D –JULY 2006–REVISED APRIL 2013
TYPICAL APPLICATION INFORMATION
General application guidelines and hints for differential drivers and receivers may be found in the following
application notes:
• Transmission Line Drivers and Receivers for TIA/EIA Standards RS-422 and RS-423(SNLA137)
• A Comparison of Differential Termination Techniques(SNLA304)
Power Decoupling Recommendations:
Bypass caps must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1 μF in
parallel with 0.01 μF at the power supply pin. A 10 μF or greater tantalum or electrolytic should be connected at
the power entry point on the printed circuit board.
RTis optional although highly recommended to reduce reflection
Figure 7. Typical Driver Connection
Figure 8. Typical Driver Output Waveforms
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SNLS116D –JULY 2006–REVISED APRIL 2013
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REVISION HISTORY
Changes from Revision C (April 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 7
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS34LV87TM/NOPB ACTIVE SOIC D 16 48 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS34LV87
TM
DS34LV87TMX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS34LV87
TM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS34LV87TMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS34LV87TMX/NOPB SOIC D 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2018
Pack Materials-Page 2
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