CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
PRELIMINARY
256/512/1K/4K/16K x36/x18x2 Tri Bus FIFO
Cypress Semiconductor Corporation • 3901 Nort h First Street • San Jose • CA 95134 • 408-943-2 600
October 6
,
1998
Features
• High-speed, low-power, first-in first-out (FIFO) memo-
rie s w/ th ree indepe ndent po rt s (one bid irecti onal x36,
and two unidirectional x18)
• 256 x36/x18x2 (CY7C43626)
• 512 x36/x18x2 (CY7C43636)
• 1K x36/x18x2 (CY7C43646)
• 4K x36/x18x2 (CY7C43666)
• 16K x36/x18x2 (CY7C43686)
• 0.35-mic ron CMOS for optimum speed/power
• High speed 83-MH z operation (12 ns read/write cycle
times)
• Low power
—ICC= 100 m A
—ISB= 5.0 mA
• Fully asynchronous and simultaneous read and write
operati on permitted
• Mailbox bypass register for eac h FIFO
• P arallel and Serial Progr am ma ble Al m ost-Full and Al-
most-Empty flags
• Retransm it functi on
• Standard or FWFT mode user selectabl e
• Partial Reset
• Big or little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Pin-compatible, feature enhanced, density up grade to
IDT723626/36/46 fami ly
• Easily expandable in width and depth
Logic Block Diagra m
Port-A
Control
Logic
Port-B
Control
Logic
Mail 1
Register
Input
Register
Write
Pointer Read
Pointer
Status
Flag Logic
Programmable Flag
Offset Registers Timing
Mode
Status
Flag Logic
Read
Pointer Write
Pointer
256/512/1K
4K/16K x36
Dual Ported
Memory
256/512/1K
4K/16K x36
Dual Ported
Memory
Mail 2
Register
Output
Register
Input
Register
FIFO1,
Mail 1
Reset
Logic
FIFO2,
Mail 2
Reset
Logic
CLKA
CSA
W/RA
ENA
MBA
RT2
MRS1
PRS1
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A0−35
EFA/ORA
AEA
MBF2
MRS2
PRS2
FFC/IRC
AFC
BE/FWFT
B0−17
CLKB
CSB
RENB
MBB
SIZEB
RTI
EFB/ORB
AEB
MBF1
Output
Register
Bus Matching
Common
Port Logic
(B and C) BE
Output
C0−17
Port-C
Control
Logic
CLKC
WENC
MBC
SIZEC
Bus Matching
Input
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
2
PRELIMINARY
Pin Configurations
CY7C43626
CY7C43636
CY7C43646
CY7C43666
CY7C43686
TQFP
Top View
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
436X6–3
112
111
110
109
108
107
106
105
104
103
FS0/SD
MRS2
FS1/SEN
GND
CLKC
MRS1
MBA
MBF2
AEA
AFA
VCC
PRS1
EFA/ORA
FFA/IRA
CSA
RENB
WENC
CSB
GND
FFC/IRC
EFB/ORB
AFC
AEB
VCC
MBF1
MBB
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
C12
C8
C9
C10
C11
C13
MBC
GND
C14
C15
C16
C17
VCC
PRS2
CLKB
GND
SIZEC
B16
B17
C0
C1
C2
C3
C4
C5
GND
SIZEB
C6
C7
RT1
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A2
B0
GND
A0
A1
VCC
SPM
A3
A4
A5
GND
A6
A7
A8
A9
B9
B8
B7
VCC
B6
GND
B5
B4
B3
B2
B1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
VCC
A29
GND
A30
A31
A32
A34
A35
GND
CLKA
ENA
W/RA
A12
A20
GND
A18
A19
A21
VCC
A22
GND
BE/FWFT
A23
A24
A25
A26
A27
A28
A33
72
71
70
69
68
67
66
65
B12
B10
B11
GND
B13
B14
B15
VCC
30
31
32
33
34
35
36
37
38
RT2
A10
A11
GND
A13
A14
A15
A16
A17
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
3
PRELIMINARY
Functional Description
The CY7C436X6 is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous (clocked) FIFO memory
which s upports cl ock frequencies up to 83-MHz and has read
access times as fast as 9 ns. Two independent
256/512/1K/4K/16K x 36 dual-port SRAM FIFOs on board
each c hip buf f er d ata in opp osite direc tions . FIFO dat a o n P ort
B can be input and output in 36 -bit, 18-bit, or 9-bit format s with
a choice of big- or little-end ian c onfiguarions.
The CY7C436X6 is a synchronous (clocked) FIFO, meaning
each port employs a synchronous in ter face. All dat a transfers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each por t are in-
dependent of one another and can be asynchronous or coin-
cident. The enables for each port are arranged to provide a
simpl e bidirec tiona l interf ace bet ween microprocessor s and/or
buses with synchronous control.
Commu nicati on betw een eac h port ma y bypas s th e FIFOs vi a
two mailbox registers. The mailbox registers’ width matches
the sel ected P ort B bu s width. Each mai lb ox regis ter has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
Two kinds of reset are available on the CY7C436X6: Master
Reset and P artial Reset . Master Rese t initi aliz es the read and
write point ers to the first location of the mem ory arr ay, co nfig-
ures the FIFO for big- or little-endian byte arrangement and
selects serial f lag progr am m ing, par allel flag progr am m ing, or
one of the three possible default flag offset settings, 8, 16, or
64. Each FIFO has its own independent Master Reset pin,
MRS1 and MRS2.
Partial Reset also sets the read and write pointers to the first
location of the mem ory. Unlike Master Reset, an y settings ex-
ist in g prior to P artial Reset (i.e., pr ogramming meth od and par-
tial flag default offsets) are retained. Partial Reset is useful
sinc e it permits f lushi ng of th e FIFO m emory witho ut chang in g
any configuration settings. Each FIFO has its own, indepen-
dent Partial Reset pin, PRS1 and PRS2.
The CY7C436X6 have two modes of operation: In the CY
Standard Mode, the first word written to an em pty F IFO is de-
posited into the memory array. A read operation is required t o
access that word (along with all other words residing in mem-
ory). In the First Word Fall Through Mode
(FWFT), the first
long-word ( 36-bit- wide) written t o an empty FIFO appears au-
tomatically on the outputs , no read operat ion r equired (never-
theless, accessing subsequent words does necessitate a for-
mal read request). The state of the FWFT/STAN pin during
FIFO operation det ermines t he mode in use.
Each FIFO has a combined Empty/Output Ready flag
(EFA/ORA and EFB/ORB) and a combined Full/Input Ready
flag (FFA/IRA and FFC/IRC). The EF and FF functions are
selected in the CY Standard Mode. EF indicates whether the
memory is full or not . The IR and OR funct ions are se lected in
the First Word Fall Through Mode. IR indicate s whether or not
the FIFO has available memory l ocations. OR shows whether
the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
Each FIFO has a programmable Almo st Empty fl ag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFC).
AEA and AEB indicate when a selected number of words writ-
ten to FIFO memory achieve a predetermined “almost empty
state”. AFA and AFC indicate when a selected number of
words wri tten to t he memory ac hie v e a pr edet ermi ned “a lmos t
full state”.
IRA, IRC, AFA, and AFC are synchronized to the port clock
that writes data into its array. ORA, O RB, AEA, and AEB are
synchronized to the port clock that reads data from its array.
Programmable offset for AEA, AE B , AF A, and AF C are loaded
in parallel using Port A or in serial via the SD input. Three
default offset settings are also provided. The AEA and AEB
threshold can be set at 8, 16, or 64 locations from the empty
boundary and AFA and AFC threshold can be set at 8, 16, or
64 loc ations f rom t he full boundary. All these ch oices are made
using the FS0 and FS1 inputs during Master Reset.
Two or more devices may be used i n parallel to create wider
data paths. Such a width expansion requires no additional,
external components.
If at any time the FIFO is not a ctive ly p erf orming a fu nction, the
chip will automatically power down. During the power down
state, suppl y current consumption (ICC) is at a minimum. Ini ti-
ating any operation (by activating control inputs) will immedi-
ately take the device out of the power-down state.
The CY7C436X6 are characterized for operation from 0οC to
70οC . I nput ESD pr otectio n is greater than 2 001V, and latch-up is
prev ented by the use of guard rings.
Selectio n Gu ide
CY7C43626/36/46/66/86−12 CY7C43626/36/46/66/86−15
Maximum Frequency (MHz) 83 66.7
Maximum Access Time (ns) 910
Minimum Cycle Time (ns) 12 15
Minimum Data or Enable Set-Up (ns) 4 5
Minimum Data or Enable Hold (ns) 0 0
Maxim u m Flag Delay (ns) 8 8
Active Power Supply
Current (ICC1) ( mA ) Commercial 100 100
Industrial 100 100
CY7C43626 CY7C43636 CY7C43646 CY7C43666 CY7C43686
Density 256 x 36 512 x 36 1K x 36 4K x 36 16K x 36
Package 128 TQFP 128 TQFP 128 TQ FP 128 TQFP 128 TQFP
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
4
PRELIMINARY
Pin Definitions
Signal Name Description I/O Function
A0–35 Po rt A Da ta I/O 36-bit bidirectional data port for side.
AEA Port A Almost
Empty Flag O Programmable almo st-empty f lag synchronized to CLKA. It is L OW when t he number
of words in FIFO2 is less than or equal to the value in the almost-empty A offset register,
X2.
AEB Port B Almost
Empty Flag O Programmable almos t- em pty flag synchronized to CLKB. I t is LOW when the number
of words in FIFO1 is less than or equal to the value in the almost-empty B offset register,
X1.
AFA Port A Al most
Full Flag O Programmable almost-full flag synchronized to CLKA. It is LOW when the num ber of
empty locations in FIFO1 is less than or equal to the value in the almost-full A offset
regist er, Y1.
AFC Port C Almost
Full Flag O Programmable almost-full flag s ynchronized to CLKC. It is LOW when the nu mb er of
empty locations in FIFO2 is less than or equal to the value in the almost-full B offset
regist er, Y2.
B0–17 Po rt B Data O 18-bit output data port for port B.
BE/FWFT Big Endian/First
Word F all
Through Select
I This is a dual- purpose pin. Durin g Maste r Reset, a HIGH on BE will se lect Big Endi an
operat io n. In this case, depending on the bus siz e, the most significant byt e or wor d on
P ort A is read from Port B fi rst (A-to-B data flow) or written to Port C fi rst (C-to-A data
flo w). A L OW on BE will s elect Litt le Endian oper ation. In this case , the lea st s ig nif icant
byte or word on Port A is r ead from Port B first (for A- to-B data flow) or written to Port
C first (C-to-A dat a flow). Afte r Master Reset, this pin select s the timing mode. A HIGH
on FWFT selects CY Standard mode, a LOW selects First Word Fall Through mode.
Once the t iming m ode has been se lected, the le vel on FWFT m ust be st atic thr oughout
device operation.
BM Bus Match
Select (Port A) I A HIG H on t his pin enab les ei ther b yte or wor d bus widt h on P ort B, depen ding on the
state of SIZE. A LOW selects long word operation. BM works with SIZE and BE to
select the bus s ize and endian arr angem ent for Port B. The level of BM must be stati c
throughout device operation.
C0–17 Po rt B Data I 18-bit input dat a port f or po rt C.
CLKA Port A Cloc k I CLKA is a cont in uous cloc k that sy nchroniz es all dat a transf ers t hrough P ort A and can
be asynchronous or coincident to CLKB. FFA/I R A , EFA /ORA, AFA, and AEA are all
synchronized to the LOW -to-HI G H tr ansition of CLKA.
CLKB Port B Cloc k I CLKB is a cont in uous cloc k that sy nchroniz es all dat a transf ers t hrough P ort B and can
be asynchronous or coincident to CLKA. EFB/ORB and AEB are all synchronized to
the LOW-to-HIG H tr ansition of CLKB.
CLKC Port C Cloc k I CLKC is a co ntinuous cloc k that synchroniz es all data tr ansfe rs throu gh P ort C and can
be asynchronous or coincident to CLKA. FFC/IRC, and AFC are all synchronized to
the LOW-to-HIG H tr ansition of CLKC.
CSA Port A Chip
Select ICSA must be LOW to enable a LOW -t o HIGH transition of CLKA to read or write on
Port A. The A0−35 outputs are in the high-impedan ce state when CSA is HIGH.
CSB Port B Chip
Select ICSB must be LOW to enable a LOW -t o HIGH transition of CLKB to read or write on
Port B. The B0–17 outputs are i n the high-i mpedance state when CSB is HI GH .
EFA/ORA Por t A Emp-
ty/Output
Ready Flag
O This i s a dual- fun ction pi n. In th e CY Standard Mode , the EFA f unction is selected. EF A
indicat es whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA
functi on is sele cted. ORA indi cates the presence o f vali d data on A0−35 outputs, avail-
able for reading. EFA/ORA is synchroni zed to the LOW -t o-HIGH tran sit ion of CLKA.
EFB/ORB Port B
Empty/Output
Ready Flag
O This is a dual-function pin. In the CY Standard Mode, the EFB function is selected. EFB
indicat es whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB
functi on is sel ected. ORB indi cates the presence of valid data on B0–17 outputs, avail-
able for reading. EFB/ORB is synchr onized to t he LOW-to-H IGH tr ansiti on of CLKB.
ENA Po rt A Enab le I ENA m ust be HI GH to enabl e a L O W -to-HIGH tr a nsition of CLKA to rea d or write dat a
on P ort A.
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
5
PRELIMINARY
ENB Po rt B Enab le I ENB m ust be HI GH to enabl e a L O W -to-HIGH tr a nsition of CLKB to rea d or write dat a
on P ort B .
FFA/IRA Port A Full/Input
Ready Flag O This i s a dual-function pi n. In the CY Stand ard Mode, t he FFA f unction i s s ele cted. FF A
indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA fun ction
is selected. IRA indicates whether or not there is space available for writing to the FIFO1
memory. F FA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
FFC/IRC Port C Full/Input
Ready Flag O This is a dual-function pin. In the CY Standard Mode, the FFC function is selected. FFC
indicates whether or not the FIFO2 memory is full. In th e FWFT mode, the IRC function
is selected. IRC indicates whether or not there is space available for writing to the FIFO2
memory. F FC/IRC is synchronized to the LOW -to-HIGH transition of CLKB.
FS1/SEN Flag Offet
Select 1/ Seri al
Enable
I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register program-
ming. During M aster Re set, FS1/ SEN and FS0/SD, together with SPM , select t he flag
offset programming method. Three offset register programming methods are available:
automatically load one of three preset values ( 8, 16, or 64), parallel load from Port A,
and serial load. Whe n serial load is sele cted for fl ag offset register prog ramming,
FS1/SEN is used as an enabl e synchronous to the LOW-t o-HIGH transition of CLKA.
W hen F S 1/ S E N is L OW, a rising edge on CLKA load the bit presen t on FS0/ SD into
the X and Y register s. The number of bit writes requir ed to prog ram the offse t reg is ters
is 32 for the CY7C43626, 36 for the CY7C43636, 40 for the CY7C43646, 48 for the
CY7C43666, and 56 for the CY7 C4 3686. The first b it writ e stores the Y-register MSB
and the last bit writ e stores the X-register LSB .
FS0/SD Flag Offset
Select 0/ Seri al
Data
I
M BA Port A M ailbox
Select I A HIGH level on M BA chooses a m ailbox regi ster for a Port A read or write operation.
When the A0−35 outputs are active, a HIGH level on MBA select s data from th e Ma il 2
regist er for output and a LOW level select s FIFO2 output reg ister data for output .
M BB Port B M ailbox
Select I A HIGH level on M BB chooses a m ailbox regi ster for a Port B read or write operation.
When the B0−17 outputs are active, a HIGH level on MBB select s data from th e Ma il 1
regist er for output and a LOW level select s FIFO1 output reg ister data for output .
M BC Port C M ailbox
Select I A HIGH level on MBB chooses a mailbox register for a Port C read or write operati on.
When the C 0−17 outputs are active, a HIGH level on MB C selects dat a from the Mail1
regist er for output and a LOW level select s FIFO1 output reg ister data for output .
MBF1 Mail1 Register
Flag OMBF1
is set LOW by a L OW-to-H IGH tr ansition of CLKA tha t writes data to the Mail1
regist er. Writes to t he Ma il 1 register are i nhibited while MBF1 is LOW. MBF1 is set
HIGH by a LOW-to-HI GH tr ansi tion of CLKB when a P o rt B r ead is select ed and MBB
is HIGH. MBF1 is set HIGH fol lowing ei ther a Master or Partial Reset of FI FO 1.
MBF2 Mail2 Register
Flag OMBF2
is set LOW by a L OW-to-H IGH tr ansition of CLKB tha t writes data to the Mail2
regist er. Writes to t he Ma il 2 register are i nhibited while MBF2 is LOW. MBF2 is set
HIGH by a LOW-to-HI GH tr ansi tion of CLKA when a P o rt A r ead is select ed and MBA
is HIGH. MBF2 is set HIGH fol lowing ei ther a Master or Partial Reset of FI FO 2.
MRS1 FIFO1 Master
Reset I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of
memory and sets the P ort B output register to all zeroes. A LOW pulse on MRS1 selects
the programming method (serial or parallel) and one of three programmable flag def ault
offset s f or FIFO1. I t also conf igur es P ort B fo r bus si z e a nd endian arr a ngement. F ou r
LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur whil e MRS1 is LOW.
MRS2 FIFO2 Master
Reset I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of
memory and sets the P ort A output register to all zeroes. A LOW pulse on MRS2 selects
one of thre e programma ble flag default offsets f or FIFO2. Four LOW -to-HIGH tr ansi-
tions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is
LOW.
PRS1 FIFO1 Partial
Reset I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of
memory and sets the Port B output register to all zero es. During P arti al Reset, the
current ly select ed bus size, endian arran gem ent, program m ing method (serial or par-
allel), and progr am m able fl ag settings are al l retained .
Pin Definitions (continued)
Signal Name Description I/O Function
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
6
PRELIMINARY
Maximum Ratings[1]
(Above which the usefu l l ife may be impa ired. For user guide-
li nes, not tes ted.)
Storage Temperature .......................................−65°C to +150°C
Ambient Temper ature with
Po wer Applied....................................................−55°C to +125°C
Supply Voltage to Ground Potential..................−0.5V to +7.0V
DC Voltag e Applied to Outputs
in High Z State[2] ..........................................−0.5V to VCC+0.5V
DC Input Voltage[2].......................................−0.5V to VCC+0.5V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage... .. ...... ....... .. ....... ............. ...>2001V
(per MIL- STD-883, Method 3015 )
La tc h -U p C u rre n t.. ..... .. .. ..... ... ..... .. ..... .. ..... ... .... ... .. ....>2 00m A
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operationg conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed
PRS2 FIFO2 Partial
Reset I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of
memory and sets the Port A output register to all zero es. During P arti al Reset, the
current ly select ed bus size, endian arran gem ent, program m ing method (serial or par-
allel), and progr am m able fl ag settings are al l retained .
RENB Port B Re ad
Enable I RENB m us t be HIGH to e nable a LO W- to-HIGH tra nsition of CLKB to re ad data on P ort
B.
RT1 FIFO1
Retransmit I A LOW str obe on this pin will ret ransmit dat a on FIFO1 from the loc ati on of the write
pointer at the last P artial or Master reset.
RT2 FIFO2
Retransmit I A LOW str obe on this pin will ret ransmit dat a on FIFO2 from the loc ati on of the write
pointer at the last P artial or Master reset.
SIZEB Bus Size Sel ect I A HIGH on thi s pin when BM is HIGH selects byte bus (9-bi t) size on Port B. A LOW
on this pin when BM is HIGH sele cts word (18-bit) bus size. SIZE works wit h BM and
BE to select the bus siz e and endian arrangement f or P ort B. The level of SIZE must
be static throughout device operation.
SIZEC Bus Size Sel ect I A HIGH on thi s pin when BM is HIGH selects byte bus (9-bi t) size on Port B. A LOW
on this pin when BM is HIGH sele cts word (18-bit) bus size. SIZE works wit h BM and
BE to select the bus siz e and endian arrangement f or P ort B. The level of SIZE must
be static throughout device operation.
SPM Serial
Programming I A LO W on this pin se lects seri al programming of partial flag offsets . A HIGH on thi s pin
selects paral lel program ming or def ault off sets ( 8, 1 6, or 64).
W/RA Port A
Write/Read
Select
I A HIG H selects a write operation and a LOW selects a read o peration on Port A for a
LOW-to-HIGH trans ition o f CLKA. The A 0−35 out put s are in t he HIG H impedan ce sta te
when W/RA is H IGH.
WENC Port C Write
Enable I WENC must be HIGH to enable a LOW -t o-HIGH trans it ion of CLKC to wri te dat a on
Port C.
Pin Definitions (continued)
Signal Name Description I/O Function
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70 °C 5.0V±0.5V
Industrial −40°C to +85°C 5.0V±0.5V
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
7
PRELIMINARY
Electrical Characte ristics Ov er the Operating Range
Parameter Description Test Conditions
7C43626/36/46/66/86
UnitMin. Max.
VOH Output HIGH Voltage VCC = 4. 5V., IOH = −4.0 mA 2.4 V
VOL Output LOW Voltage VCC = 4. 5V., IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage 2.0 VCC V
VIL Input LOW Voltage −0.5 0.8 V
IIX Input Leakage Current VCC = Max. −10 +10 µA
IOZL
IOZH Output OFF, High Z
Current VSS < VO< VCC −10 +10 µA
ICC1[3] Active Power Supply
Current Com’l 100 mA
Ind 100 mA
ISB[4] Average Standby
Current Com’l 5mA
Ind 5mA
Capacitance[5]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C , f = 1 MHz,
VCC = 5.0V 4pF
COUT Ou tput Capacitance 8pF
Notes:
3. This is the supply current when each input is at least one of the specified TTL voltage levels rather than 0V or VCC.
4. All inputs = VCC– 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
5. Tested initially and after any design or process changes that ma y affect these parameters.
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R2=680ΩCL=30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤3ns ≤3ns
OUTPUT 1.910V
Equivalentto: THÉ VENIN EQUIVALENT
410 Ω
ALL INPUT PULSES
R1=1.1KΩ
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
8
PRELIMINARY
Switching Characteristics Over t he Operating Range
Parameter Description
7C43626/36/46/66/86
-12 7C43626/36/46/66/86
-15
UnitMin. Max. Min. Max.
fSClock Frequency, CLKA,CLKB, or CLKC 83 67 MHz
tCLK Clock Cycle Time, CLKA,CLKB, or CLKC 12 15 ns
tCLKH Pulse Duration, CLKA,CLKB, or CLKC HIGH 5 6 ns
tCLKL Pulse Dur ation, CLKA,CLKB, or CLKC LOW 5 6 ns
tDS Set-Up Time, A0–35 before CL K A ↑ B0–17 before
CLKB↑, and C0–17 before CLKC↑4 5 ns
tENS Set-Up Time, CSA, W/RA, ENA, and MBA before
CLKA↑; RENB and MBB before CLKB↑ and WENC
and MBC before CLKC↑
4 5 ns
tRSTS Set-Up Time, MRS1, M RS 2, PRS1, or PRS2 LOW
before CLKA↑ or CLKB↑[6] 4 5 ns
tFSS Set-Up T ime, F S0 and F S1 bef or e MRS1 and MRS2
HIGH 77.5 ns
tBES Set-Up Time, BE/FWFT before MRS1 and MRS2
HIGH 77.5 ns
tSPMS Set-Up Time, SPM before MRS1 and MRS2 HIGH 77.5 ns
tSDS Set-Up Time, FS0/SD bef ore CLKA↑4 5 ns
tSENS Set-Up Time, FS1/SEN before CL KA↑4 5 ns
tFWS Set-Up Time, FWFT before CLKA↑0 0 ns
tDH Hold Time, A0–35 before CLKA↑ B0–17 bef ore CLKB↑,
and C0–17 bef ore CLKC↑0 0 ns
tENH Hold Time, CSA, W/R A , ENA, and MBA before
CLKA↑ RENB and MBB before CLKB↑ and WENC
and MBC before CLKC↑
0 0 ns
tRSTH Hol d Time , MRS1, MRS2, PRS1, or PRS2 LOW after
CLKA↑ or CLKB↑[6] 4 4 ns
tFSH Hold Time, FS0 and FS1 after MRS1 and MRS2
HIGH 2 2 ns
tBEH Hold Time, BE/FW FT after MRS1 and M RS2 HIGH 2 2 ns
tSPMH Hold Time, SPM after MRS1 and MRS2 HIGH 2 2 ns
tSDH Hold Time, FS0/SD after CLKA↑0 0 ns
tSENH Hold Time, FS1/SEN afte r C L K A↑0 0 ns
tSPH Hold Time, FS1/SEN HIGH after MRS1 and MRS2
HIGH 2 2 ns
tSKEW1[7] Skew Time between CLKA↑ and CLKB↑ for
EFA/ORA , E F B/ORB, FFA/IRA, and FFC/IRC 67.5 ns
tSKEW2[7] Skew Time between CLKA↑ and CLKB↑ for AEA,
AEB, AFA, AFC 10 12 ns
tAAcce ss Time, CLKA↑ to A0–35 and CLKB ↑ to B0–17 1 9 3 10 ns
tWFF Propagation Delay Time, CLKA↑ to FFA/IRA and
CLKB↑ to FFC/IRC 1 8 2 8 ns
tREF Pro pagation Delay Time , CLKA↑ to EFA/ORA and
CLKB↑ to EFB/ORB 1 8 1 8 ns
Notes:
6. Requirement to count the clock edge as one of at least four needed to reset a FIFO
7. Skew time is not a ti ming constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
9
PRELIMINARY
tPAE Propa gat ion Dela y T ime, CLKA↑ t o AEA and CLKB↑
to AEB 1 8 1 8 ns
tPAF P ropagat ion Del ay Time , CLKA ↑ to A FA a nd CLKC↑
to AFC 1 8 1 8 ns
tPMF Propagation Delay Time, CLKA ↑ to MBF1 LOW or
MBF2 HIGH and CLKB↑ to MBF2 LO W or MBF1
HIGH
0 9 0 12 ns
tPMR Propagation Delay Time, CLKA ↑ to B0–17[8] and
CLKB↑ to A0–35[9] 211 312 ns
tMDV P ropagation Delay Time, MBA to A0–35 valid and
MBB to B0–17 vali d 210 311 ns
tRSF Propagation Delay Time, MRS1 or PR S1 LOW to
AEB LOW, AFA HIGH, and MBF1 HIGH and MRS2
or PRS2 LOW to AEA LOW, AFC HIGH, and MBF2
HIGH
112 115 ns
tEN Enable Ti me, CSA or W/RA LOW to A0–35 Acti ve and
CSB LOW and RENB HIGH to B0–17 Active 210 210 ns
tDIS Disable Time, CSA or W/RA HIG H to A0–35 at high
imped ance and CSB HIGH or RenB LOW to B0–17 at
HIGH impedance
1 7 1 8 ns
Notes:
8. Writing data to the Mail1 register when the B0–17 outputs are active and MBB is HIGH.
9. Writing data to the Mail2 register when the A0–35 outputs are active and MBA is HIGH.
Switching Charac teris t ics Ov er the Operating Range
Parameter Description
7C43626/36/46/66/86
-12 7C43626/36/46/66/86
-15
UnitMin. Max. Min. Max.
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
10
PRELIMINARY
Switching Wavefor ms
Notes:
10. PRS1 and MBC must be HIGH during Master Reset until the rising edge of FFA/IRA goes HIGH.
11. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than the case where BE/FWFT is LOW.
FIFO1 Master Reset Loading X1 and Y1 with a Preset Value of Eight
CLKA
tRSF
tRSF
tRSF
tWFF
tFSS tFSH
tSPMS tSPMH
tBES tBEH
tRSTS
tRSTS
tFWS
CLKB
MRS1
BE/FWFT
SPM
FS1, FS0
FFA/IRA
EFB/ORB
AEB
AFA
MBF1
[10, 11]
tRSF
tRSF
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
11
PRELIMINARY
Notes:
12. PRS2 and MBC must be HIGH during Master Reset until the rising edge of FFC/IRC goes HIGH.
13. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than the case where BE/FWFT is LOW.
Switching Wavefor ms (continued)
FIFO2 Master Reset Loading X1 and Y1 with a Preset Value of Eight
CLKC
tRSF
tRSF
tRSF
tWFF
tFSS tFSH
tSPMS tSPMH
tBES tBEH
tRSTS
tRSTS
tFWS
CLKA
MRS2
BE/FWFT
SPM
FS1, FS0
FFC/IRC
EFA/ORA
AEB
AFA
MBF2
[12, 13]
tRSF
tRSF
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
12
PRELIMINARY
Notes:
14. MRS1 must be HIGH during Partial Reset.
15. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than the case where BE/FWFT is LOW.
16. MRS2 must be HIGH during Partial Reset.
17. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKAycle earlier than the case where BE/FWFT is LOW.
Switching Wavefor ms (continued)
FIFO1 Partial Reset (CY Standard and FWFT Modes)
tRSF
tRSF
tRSF
tRSTS tRSTH
CLKA
CLKB
PRS1
FFA/IRA
EFB/ORB
AEB
AFA
MBF1
[14, 15]
tWFF
tRSF
tRSF
FIFO2 Partial Reset (CY Standard and FWFT Modes)
tRSF
tRSF
tRSF
tRSTS tRSTH
CLKC
CLKA
PRS2
FFC/IRC
EFA/ORA
AEA
AFC
MBF1
[16, 17]
tWFF
tRSF
tRSF
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
13
PRELIMINARY
Notes:
18. CSA=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
19. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB f or FFC/IRC to transition HIGH in the next cycle. If the time betw een the rising
edge of CLKA and rising edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one cycle later than shown.
Switching Wavefor ms (continued)
Parallel Program ming of the Alm ost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Mo des)
tWFF
tFSS
tDS
tFSS tFSH
tFSH
tENS tENH
tDH
tSKEW1[19]
AFA Offset (Y1) AFC Offset (Y2) First Word to FIFO1
CLKA
MRS1
MRS2
SPM
FS1
FS0
FFA/IRA
ENA
A0 − 35
CLKB
FFC/IRC
[18]
AEB Offset (X1) AEA Offset (X2)
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
14
PRELIMINARY
Notes:
20. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH.
21. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKCfor FFC/IRC to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one cycle later than show.
22. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFC offset (Y2), and AEA offset (X2).
Switching Wavefor ms (continued)
Serial Programm ing of the Almost-Full Flag and Almost -Empty Flag
Offset Values (CY Standard and FWFT Mod es)
tFSS tSPH tSENS tSENH tSEN
tSENS
tSDH
tSDS tSDH
tSDS
tSKEW1[21] tWFF
AFA Offset (Y1) MSB
tFSStFSH
tWFF
CLKA
MRS1
MRS2
SPM
FFA/IRA
FS1/SEN
CLKB
FFA/IRA
[18]
FS0/SD[22]
AEA Offset (X2) LSB
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
15
PRELIMINARY
Note:
23. Written to FIFO1.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENS tENH
tENS tENH
tENS tENH
tENS tENH
tDS tDH
tENS tENH tENS tENH
HIGH
W1[23] W2[23]
tCLK
CLKA
FFA/IRA
CSA
W/RA
MBA
ENA
A0–35
Port A Write Cycle Timing f or FIFO1 (CY Standard and FWFT Mod es)
tENS
tENS tENH
tENS tENH
tDS tDH
tENS
HIGH tENH
tENH
CLKC
FFC/IRC
MBC
WENC
C0–17
P ort C Wo rd Write Cycle Timing for FI FO2 (CY Standard and FWFT Modes)
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
16
PRELIMINARY
Switching Wavefor ms (continued)
Port C Byte Write Cycle Tim ing for FIFO2 (CY Standard and FW FT Modes)
tENS tENH
tENS tENH
tDS tDH
tENS
HIGH tENH
tENH
CLKC
FFC/IRC
MBC
WENC
C0–8
OR
tENStENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
tA
tA
tA
tA
Previous
Read
Read
Read
Read
Read
Read
Read
Read
Read
No Operation
HIGH
CLKB
EFB/ORB
CSB
MBB
RENB
B0–8
(Standard
B0–8
(FWFT Mode)
Port B Word Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
tDIS
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
17
PRELIMINARY
Notes:
24. Unused bytes B9–17 contain all zeroes for byte-size reads.
25. Read From FIFO2.
Switching Wavefor ms (continued)
OR
tDIS
tEN tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
Previous Data
Read 1
Read 1
Read 2
Read 2
Read 3
No Operation
CLKB
EFB/ORB
CSB
W/RB
MBB
ENB
B0–17
(Standard
B0–17
(FWFT Mode)
Port B Byte Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)[24
OR
tCLKH tCLKL
tENS
tDIS
tENS tENH
tCLK
tDIS
tENH
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV
W1[25] W2[25]
W1[25] W2[25]
W3[25]
Previous No Operat ion
CLKA
EFA/ORA
CSA
W/RA
MBA
ENA
A0−35
(Standard
A0−35
(FWFT Mode)
Port A Read Cycle Timing for FIFO2 (CY Standard and FW FT Modes)
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
18
PRELIMINARY
Notes:
26. If Port B size is word or byte, ORB is set LO W by the last word or byte read from FIFO2, respectively.
27. TSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and
load of the first word to the output register may occur one CLKB cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENS
tCLK
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO1 Empty
LOW
LOW
Old Data i n FIFO1 Output Register W1
tENS tENH
tREF tREF
tCLKH tCLKL
tCLK
tSKEW[27]
CLKA
CSA
W/RA
MBA
ENA
IRA
A0–35
CLKB
ORB
CSB
MBB
RENB
B0–17
ORB Flag Timi ng and Fir st Da ta Word Fall Through when FI FO1 is Empty (FWFT Mode)[26]
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
19
PRELIMINARY
28. If Port B size is word or byte, EFB is set LOW by the last word or b yte read from FIFO1, respectively.
29. TSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO1 Empty
LOW
LOW
W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tCLK
tSKEW[29]
CLKA
CSA
W/RA
MBA
ENA
FFA
A0–35
CLKB
EFB
CSB
MBB
RENB
B0–17
EFB Flag Timing an d First Data Read F all Through when FIFO1 is Empty (CY Standard Mode)[28]
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
20
PRELIMINARY
Notes:
30. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
31. TSKEW1 is the minimum time between a rising CLKCedge and a rising CLKA edge for ORA to transition HIGH and to cloc k the next word to the FIFO2 output
register in three CLKA cycles. If the time between the rising CLKC edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and
load of the first word to the output register may occur one CLKA cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tA
W1
LOW
tDH
LOW
HIGH
FIFO2 Empty
LOW
LOW
LOW
Old Data in FIFO2 Output Register W1
tENS
tENH
tREF tREF
tCLKH tCLKL
tCLK
tSKEW1[31]
tCLK
tDS
CLKC
CSC
WENC
IRC
C0–17
CLKA
ORA
CSA
W/RA
MBA
ENA
A0–35
ORA Flag Timi ng and Fir st Da ta Word F all Through when FIFO2 is Empty (FWFT Mode)[30]
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
21
PRELIMINARY
Notes:
32. If Port C size is word or byte, tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
33. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between
the rising CLKC edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Switching Wavefor ms (continued)
EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
tDS
W1
tDH
HIGH
FIFO2 Empty
LOW
LOW
LOW
W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[33]
CLKC
MBC
WENC
FFC
C0–17
CLKA
EFA
CSA
W/RA
MBA
ENA
A0–35
[32]
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
22
PRELIMINARY
Notes:
34. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.
35. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
HIGH
FIFO1 Full
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[35]
tDH
tDS
tENH
tENS
Previous Word in
FIFO1 Output Register Next Wo rd From FIFO1
To FIFO1
CLKB
CSB
MBB
ENB
ORB
B0–17
CLKA
IRA
CSA
W/RA
MBA
ENA
A0–35
IRA Flag Tim ing and Fi rst Available Write when FIFO1 i s Full (FWFT Mo de)[34]
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
23
PRELIMINARY
Notes:
36. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively
37. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for F F A to transition HIGH in the ne xt CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FFA HIGH may occur one CLKA cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENtENH
tA
LOW
HIGH
HIGH
FIFO1 Full
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[37]
tDH
tDS
tENH
tENS
Previous Word in
FIFO1 Output Register Next Word From FI FO1
CLKB
CSB
W/RB
MBB
ENB
ORB
B0–17
CLKA
IRA
CSA
W/RA
MBA
ENA
A0−35
FFA Flag Timing and Fir st Available Write when FIFO1 is Full (CY Standard Mode)[36]
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
24
PRELIMINARY
Notes:
38. If Port C size is word or byte, IRC is set LOW by the last word or byte write of the long word, respectiv e ly.
39. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKC edge for IRC to transition HIGH in the ne xt CLKB cycle. If the time between the
rising CLKA edge and rising CLKC edge is less than tSKEW1, then the transition of IRC HIGH may occur one CLKC cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENS
tENH
tA
LOW
LOW
HIGH
FIFO2 Full
LOW
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[39]
tDH
tDS
tENH
tENS
Pre vious Word in
FIFO2 Output Register Next Word From FIFO2
To FIFO2
LOW
CLKA
CSA
W/RA
MBA
ENA
ORA
A0–35
CLKC
IRC
W/RB
MBC
WENC
C0–17
IRC Flag T iming and First Available Wri te when FI FO2 is Full (FWFT Mode)[38]
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
25
PRELIMINARY
Notes:
40. If Port C size is word or byte, FFC is set LOW by the last word or byte write of the long word, respectively.
41. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFC to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKC edge is less than tSKEW1, then the transition of FFC HIGH may occur one CLKC cycle later than shown.
Switching Wavefor ms (continued)
tCLKH tCLKL
tENS
tENH
tA
LOW
LOW
HIGH
FIFO2 Full
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[41]
tDH
tDS
tENH
tENS
Previous Word in FIFO2
Output Register Next Wo rd From FIFO2
To FIFO2
LOW
CLKA
CSA
W/RA
MBA
ENA
EFA
A0–35
CLKC
FFC
MBC
ENC
C0–17
FFC Flag Timing and Fi rst Avail able Write when FIFO2 is Full (CY Standard Mode)[40]
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
26
PRELIMINARY
Notes:
42. FIFO1 Write (CSA = LO W, W/RA = LO W, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been
read from the FIFO.
43. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
44. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
45. FIFO2 Write (MBB = LOW), FIFO2 read (CSA = LO W, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO
46. If Port C size is word or byte, tSKEW2 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
47. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between
the rising CLKC edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
Switching Wavefor ms (continued)
tPAE
tPAE
tENH
tENS
tSKEW2[44]
tENS tENH
X1 Word in FIFO1 (X1+1)Words in FIFO1
CLKA
ENA
CLKB
AEB
RENB
Timing for AEB when FIFO2 i s Almost Empty (C Y Standard and FWFT Modes)[42, 43]
tPAE
tPAE
tENH
tENS
tSKEW2[47]
tENS tENH
X2 Word in FIFO2 (X2+1) Words in FIFO2
CLKC
ENC
CLKA
AEA
ENA
Tim ing f or AEA when FIFO2 is Almost Em pty (CY Standard and FWFT Modes)[45, 46 ]
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
27
PRELIMINARY
Notes:
48. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW ), FIFO1 read (CSB = LOW , MBB = LOW). Data in the FIFO1 output register has been read from the
FIFO.
49. D = Maximum FIFO Depth = 256 f or the CY7C43626, 512 f or the CY7C43636, 1K for the CY7C43646, 4K for the CY7C43666, and 16K for the CY7C43686.
50. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
51. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF A to transition HIGH in the nex t CLKA cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown.
52. FIFO2 Write (MBB = LOW), FIFO2 read (CSA = LO W, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
53. D = Maximum FIFO Depth = 256 f or the CY7C43626, 512 f or the CY7C43636, 1K for the CY7C43646, 4K for the CY7C43666, and 16K for the CY7C43686.
54. If Port C size is word or byte, AFC is set LOW by the last word or byte write of the long word, respectively.
55. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AFC to transition HIGH in the next CLKC cycle. If the time between
the rising CLKC edge and rising CLKA edge is less than tSKEW2, then AFC may transition HIGH one CLKA cycle later than shown.
Switching Wavefor ms (continued)
Timing for AFA when FIFO1 is Almost Full (C Y Standard and FWFT Modes)
tPAF
tENH
tENS
tPAF
tENS tENH
[D–(Y1+1)] Words in FIFO1 (D –Y 1 ) W o rd s i n FIF O 1
tSKEW2[51]
CLKA
ENA
AFA
CLKB
ENB
[48, 49, 50]
tPAF
tENH
tENS
tPAF
tENS tENH
[D -(Y2+ 1)] Word s in FIFO2 (D–Y2)Words in FIFO2
tSKEW2[55]
CLKC
ENC
AFC
CLKA
ENA
Timing for AFC when FIFO2 is Al m ost Ful l (CY St andard and FWFT Modes)[ 52, 53 , 54 ]
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
28
PRELIMINARY
Note:
56. If P ort B is configured for word size, data can be written to the Mail1 register using A0–17 (A 18–35 are don’t care inputs). In this first case B0–17 will have valid
data ). If Port B is configured for byte size, data can be written to the Mail1 Register using A0–8 (A9–35 are don’t care inputs). In this second case, B0–8 will
have valid data (B 9–17 will be indeterminate).
Switching Wavefor ms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO1 Output Register W1 (Remains valid in Mail1 Register after read)
CLKA
CSA
W/RA
MBA
ENA
A0–35
CLKB
MBF1
CSB
W/RB
MBB
RENB
Timing for Mail1 Register and MBF1 Fl ag (CY Standard and FWFT Modes)[56]
B0–17
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
29
PRELIMINARY
Notes:
57. If Port C is configured for word size, data can be written to the Mail2 register using C0–17. In this first case A0–17 will have valid data (A18–35 will be
indeterminate). If Port C is configured for byte size, data can be written to the Mail2 Register using B0–8 (B9–17 are don’t care inputs). In this second case,
A0–8 will have valid data (A9–35 will be indeterminate).
58. Retransmit is performed in the same manner for FIFO2
59. Clocks are free running in this case.
60. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
61. For the synchronous PAE and PAF flags ( SMODE), a n appr opriate cloc k cycle i s nec essary after tRTR to upda te the se flags .
Switching Wavefor ms (continued)
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO2 Output Register W1 (Remains valid in Mail2 Register after read)
CLKC
MBC
ENC
C0–17
CLKA
MBF2
CSA
W/RA
MBA
ENA
A0−35
Timing for Mail2 Regi ster and MBF2 Flag (CY Standard and FWFT Modes) [57]
FIFO1 Retransmit Timing
ENB
RT1
tPRT tRTR
EFB/FFA
[58, 59, 60 , 61]
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
30
PRELIMINARY
Signal Description
Master Reset (MRS1, MRS2)
Each of the two FIFO memories of the CY7C436X6 undergoes
a complete reset by taking its associated Master Reset
(MRS1, MRS2) input LO W f or at leas t f our P ort A cloc k (CLKA)
and four Port B clocks (CLKB) LOW-to-HIGH transitions. The
Mast er Reset i nputs can switch async hronously to the cl ocks.
A Master Reset initializes the inter nal read and write pointers
and f orces the Full/In put Ready flag (FF A/IRA, FFC/IRC) LO W ,
the Empty /Out put Ready flag (EFA/ORA, EFB/ORB) LOW , the
Almost Empty flag (AEA, AEB) LOW, and the Al mo st Ful l f lag
(AFA, AFC) HIGH. A Master Reset al so for ces the Mailb ox fla g
(MBF1, MBF2) of the parallel mailbox register HIGH. After a
Master Reset, the FIFO’s Full/Input Ready flag is set HIGH
aft er tw o cl ock cyc les t o begin normal oper at ion. A Master Re-
set m ust be p erf ormed on the FIFO after power up , b efore data
is written to its memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latches the value of the Big Endian (BE) input or
determining the order by which bytes are transferred through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Fl ag select (FS0, FS1) and Se-
rial Programming Mode (SPM) inputs for cho osing the Al m ost
Full and Almost Empty offset programming method (see Al-
most Empty and Almost Full flag offset programming below).
P art ial Reset (PRS1, PRS2)
Each of the two FIFO memories of the CY7C436X6 undergoes
a limited reset by taking its associated Partial Reset (PRS1,
PRS2) input LOW for at least four Port A clock (CLKA) and
f our P ort B cloc k (CLKB) LO W-t o-HIGH tran sitions. The Pa rtial
Reset inputs can switch asynchronously to the clocks. A Par-
tial Rest initializes the internal read and write pointers and forc-
es the Full/Input Ready flag (FFA/IRA, FFC/IRC) LOW, the
Empty/ Outp ut Ready fl ag (EFA/ORA, EFB/ORB ) L O W, the Al-
most Empty flag (AEA, AEB) LOW, and the Almost Full flag
(AFA, AFC) HIGH. A Partial Reset also forces the Mailbo x flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a
Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH
after two clock cycl es to begin normal operati on.
Whatever flag offsets, programming method (parallel or seri-
al), and timing mode (FWFT or CY Standard mode) are cur-
rently selected at the time a Partial Reset is initiated, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be
inconvenient.
Big Endian/First Word Fall Through (BE/FW FT)
This i s a dual-purpose pin. At the t ime of Master Reset, the BE
select function is active, permitting a choice of big or little en-
dian byte arrangement for data written to or read from Port B.
This select ion determi nes the order by which bytes (or words)
of data are trans f err ed thr ough this po rt. F o r the f ol low ing ill us-
trations, assume that a byte (or word) bus size has been se-
lected for Port B. (Note that when Port B is configured for a
long wor d siz e , the Big Endi an func tion has n o appli cati on an d
the BE input is a “don’t care”.)
A HIGH on the BE/FWFT inpu t when the Mas ter Re set (MRS1
and MRS2) inputs go from LOW to HIGH will select a Big En-
dian arrangem ent. When data is moving in the direction from
Port A to Port B, the most significant byte (word) of the long
word written to Port A will be read from Por t B first; the least
signi fican t by te (wor d) of the lo ng wo rd written to Port A will be
read from Port B last. When data is moving in the direction
from Port B to Port A, the byte (word) written to Port B first will
be read from Por t A as the most significant byte (word) of the
long word; the byte (word) written to Port B last will be read
from Port A as the least significant byte (word) of the long
word.
A LO W on th e BE/FWFT inp ut when the Mast er Reset (MRS1
and MRS2) inputs go from LOW to HIGH will select a Little
Endian arrangement. When data is moving in the direction
from Port A to Port B, the least significant byte (word) of the
long word written to Port A will be read from Por t B first; the
most significant byte (word) of the long word written to Port A
will be r ead from Port B l ast . When dat a is movi ng in the direc -
tion fro m P o rt B to Port A, t he by te (wor d) written to P ort B firs t
will be read from port A as the least significant byte (word) of
the long word; the b yte (word ) writt en to P ort B last will be read
from Port A as the most significant byte (word) of the long
word.
After Master Reset, the FWFT select function is activ e, permit -
ting a choice between two possible timing modes: CY Stan-
dard Mode or First Word Fall Thro ugh (FWFT) Mode. On ce the
Master Reset (MRS1, MRS2) input is HIGH, a HIGH on the
BE/FWFT input during the next LOW-to-HIGH transition of
CLKA (for FIFO1) and CLKB (for FIFO2) will select CY Stan-
dard Mode. This mode uses the Empty Flag function (EFA,
EFB) to indi cat e whether or no t ther e a re any wo rds pr esent in
the FIFO memory. It uses the Full Fl ag functi on (FFA, FFC) to
indicate whether or not the FIFO memory has any free space
for writing. In CY Standard mode, every word read from the
FIFO, including the first, must be requested using a formal
read operation.
Once t he Master Res e t (MRS1 , MRS2) input is HIGH, a LOW
on the BE/ FWFT input duri ng the ne xt LO W- to -HI GH transi tion
of CLKA (for FIFO1) and CLKB (for FIFO2) will select FWFT
Mode. This mode uses the Output Ready function (ORA,
ORB) to indi cate whether or not there is valid data at the dat a
outputs (A0–35 or B0–17). It also uses t he Input Ready f uncti on
(IRA, IRC) to indicate whether or not the FIFO memory has
any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes direct ly to data outp uts , no read
request necessary. Subsequent words must be accessed by
performing a f ormal r ead operati on.
Following Master Reset, the level applied to the BE/FWFT in -
put to choose the desired timing mode must remain static
throughout the FIFO ope ration.
Programming the Almost Empty and Almost F ull F lags
Four registers in the CY7C436X6 are used to hold the offset
values for the Al mo st Empty and Almost Full flags. The Port B
Almost Empty flag (AEB) offset register is labeled X1 and the
Port A Almost Em pty flag (AEA) offset register is labeled X2.
The Pos t A Almost Ful l f lag (AFA) off set register is la beled Y1
and the P ort C Al most Full fl ag (AF C) off set regi ster is label ed
Y2. The index of each register name corresponds with preset
values during the reset of a FIFO, programmed in parallel us-
ing the FIFO’s Port A data inputs, or programmed in serial
using the Ser ial Data (SD) input (see
Table 1
).
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
31
PRELIMINARY
To load a FI FO’ s Al most Emp ty fl ag and Almost Full flag of f set
registers with one of the three preset values listed in
Table 1
,
the Serial Program Mode (SPM) and at least one of the
fl ag-s elect inputs must b e HIGH during th e LOW -to-HI GH tran-
sit ion of its M aster Reset inpu t (MRS1 and MRS2). For exam-
ple, to load the preset value of 64 into X1 and Y1, SPM, FS0,
and FS1 must be HIGH when FIFO1 reset (MRS1) returns
HIGH . Fl ag-offs et regist ers associated with FIFO2 are loaded
with one of the preset values in the same way with Master
Reset (MRS2). When using one of the preset values for the
flag offsets, the FIFO’s can be reset simultaneously or at dif-
ferent times.
To program the X1, X2, Y1, an d Y2 registers f rom Port A, per-
form a Master Reset on both FI FOs simultaneously with SPM
HIGH and FS0 and FS1 LOW during the LOW-to-HIGH tran-
sition of MRS1 and MRS2. After this reset is complete, the first
four writes to FIFO1 do not store data in RAM but load the
offset registers in t he order Y1, X1, Y2, X2. The Port A data
inputs used by the offset registers are (A7–0), (A8–0), (A 9–0),
(A11–0), or (A13–0), f or the CY7C4 36X6, respec tively . The high-
est numbered input is used as the most significant bit of the
binary n umber in each ca se . Valid prog ramm ing v al ues f or the
registers range fr om 1 to 252 for the CY7C43626; 1 to 508 for
the CY7C43636; 1 to 1012 for the CY7C43646; 1 to 4092 for
the CY7C43666; 1 to 16380 for the CY7C43686. After all the
offset registers are programmed from Port A, the Port C
Full /Inpu t Ready (FFC/I RC) is set HI GH and both FIF Os begi n
normal operation.
To program the X1, X2, Y1, and Y2 registers s eria ll y, in itiate a
Master Reset with SPM LOW, FS0/SD LOW and FS1/SEN
HIGH d uring t he LO W -t o-HIGH t rans iti on of MRS1 and MRS2.
After this reset is complete, the X and Y register values are
loaded bit-wise through the FS0/SD input on each
LOW-to-HIGH transition of CLKA that the FS1/SEN input is
LOW. Thirty-two, thirty-six, forty, forty-eight, or fifty-six bit
writes are needed to complete the programming for the
CY7C436X6, respect iv el y. The four regis ters ar e written i n the
order Y1, X1, Y2, and, finally, X2. The first-bit write stores the
most significant bit of the Y1 register and the last-bit write
stores the l east significant bit of the X2 r egister. Each regist er
value can be programmed from 1 to 252 (CY7C43626), 1 to
508 (CY7C43636), 1 to 1020 (CY7C43646), 1 to 4092
(CY7C43666), or 1 to 16380 (CY7C43686).
When the opt ion t o p rogr am t he off set r egist ers seriall y is cho-
sen, the Port A Full/Input Ready (FFA/IRA) flag remains LOW
until all register bits are written. FFA/IRA is set HIGH by the
LOW-to-HIGH transition of CLKA after the last bit is loaded to
allow normal FIFO1 operation. The Port C Full/Input ready
(FFC/IRC) flag also remains LOW throughout the serial pro-
gramming process, until all register bits are written. FFC/IRC
is set HIGH by the LOW-to-HIGH transition of CLKC after the
last bit is loade d to al low normal FIFO2 operati on.
SPM, FS0/SD, and FS1/SEN function the same way in both
CY Standard a nd FWFT modes .
FIFO Write/Read Operat ion
The state of the Por t A data (A 0–35) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the High-impedance state when either
CSA or W/RA is HIGH. The A0–35 lines are active outputs
when bo th CS A and W/RA are LOW.
Data is loaded into FIFO1 from the A0–35 inputs on a
LO W-to-HIGH transit ion of CLKA when CSA is LOW, W/RA is
HIGH, ENA is HIGH, MBA is LOW , an d FF A/IRA is HI GH. Data
is read from FIFO2 to the A0–35 outputs by a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is LOW, ENA is
HIGH, MBA is LOW, and EFA/ORA is HIGH (see
Ta bl e 2
).
FIFO reads and wri tes on Port A are independent of an y con-
current Port B operation.
The state of the Por t B data (B0–17) lines is controlled by the
P ort B Chip Select (CSB) and P ort B Read se lect (RENB). The
B0–17 lines are in the high-impedance state when either CSB
is HIGH or RENB is LOW. The B0–17 lines are active outputs
when CSB is LOW and RENB is HIGH.
Data is loaded into FIFO2 from the C0–17 inputs on a
LOW-to-HIGH transition of CLKC when CSC is LOW, WENC
is LOW, ENC is HIGH, MBC is LOW, and FFC/IRC is HIGH.
Data is read from FIFO1 to the B0–17 outputs by a
LOW-to-HIGH transition of CLKB when CSB is LOW, RENB
is HIGH, ENB is HI GH, MBB is LOW, and EFB/ORB is HIGH
(see
Table 3
). FIFO reads o n Port B A and writes t o P ort C are
independent of any concurrent Por t A operation.
The set-up and hold t ime constraints t o the port clocks for the
port Chip Sel ects a nd Write/ rea d sele cts ar e only for ena bli ng
write and read operations and are not related to high-imped-
ance cont rol of t he data outp uts. If a port e nable i s LOW during
a clock cycle, the port’s Chip Select and Write/Read select
ma y change s tat es during the set-up and hold ti me window of
the cycle.
When operating the FIFO in FWFT Mode and the Output
Ready flag i s LO W, the next word wri tten is automatically sent
to the FIFO’s output register by the LOW-to-HIGH t ransition o f
the port clock that sets the Output Ready flag HIGH, data re-
sidi ng in t he F IFO’s memory arra y i s cl oc ked t o t he out put reg -
ister only when a read i s selec ted usi ng t he port’ s Ch ip Sel ect ,
Write/Rea d select, Enab le, and Mailbox select.
When ope rati ng the FIF O in CY St andard M ode, r egardle ss of
whether t he Emp ty Fl ag is LOW or HIGH, data r esiding in the
FIFO’s memory array is clocked to the output register only
when a read is selected using the port’s Chip Select,
Write/Rea d select, Enab le, and Mailbox select.
Synchronized FIFO Fla gs
Each FIFO is synchronized to its port clock through at least
two flip- flop stages . This is done to improv e flag-signal reliabi l-
ity by reducing the probability of the metastable events when
CLKA , CLKB, and CLKC operate asynchronously to one an-
other. EFA/ORA, AEA, FFA/IRA , an d AFA are sync hron ized t o
CLKA. EFB/ORB and AEB are synchronized to CLKB.
FFC/IRC and AFC are synchronized to CLKC.
Ta bl e 5
and
Table 6
show the relationship of each port flag to FIFO1 and
FIFO2.
Empty/Output Ready Fla gs (EFA/ORA, EFB/ORB)
These are dual-purpose flags. In the FWFT Mode , the Output
Ready (ORA, ORB) function is selected. When the Output
Ready flag is HIGH, new data is present in the FIFO output
regis ter . When the Output read y flag is LOW, the pr ev iou s dat a
word is present in the FIFO output register and attempted
FIFO reads are i gnored.
In the CY Standard Mode , t he Empty Flag (EFA, EFB) function
is select ed. When the Empty Flag is HIGH, data is av ailab le in
the FIFO’s RAM memory for reading to the output register.
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
32
PRELIMINARY
When Em pty Flag is LOW, the previous data word is present
in the FIFO output register and attempted FIFO reads are ig-
nored.
The Empty/ Output Ready flag of a FIFO is synchroniz ed to the
port clock that reads data from its array. For both the FWFT
and CY Standard modes, t he FIFO read point er is incremen t-
ed each time a new word is clocked to its output register. The
state machine that controls an Output Ready flag monitors a
write pointer and read pointer com parator that indicate s when
the FIFO SRAM stat us is empty, em pty+1, or empty+ 2.
In FWFT Mode, from the time a word is written to a FIFO , it can
be shifted to the FIFO output register in a minimum of three
cycles of the Output Ready flag synchronizing clock. There-
fore, an Output Ready flag is LOW if a word in memory is the
next data to be sent to the FIFO output register and three cy-
cles have not elapse d since the t ime the word was writ ten . Th e
Output Ready flag of the FIFO remains LOW until the third
LO W-to-HI G H transition of the sync hronizin g clock occurs, si-
mu ltaneo usly forc ing the Out put Ready f l ag HIGH and shif tin g
the word to the FIFO output r egister.
In the CY Standard Mode, f rom the time a word is written to a
FIFO, the Empty Flag will indicate the presence of data avail-
able for reading in a minimum of two cycles of the Emp ty Flag
synchronizing clock. Therefore, an Empty Flag is LOW if a
w ord in memory is t he next data to be sent to the FIFO output
register and two cycles have not elapsed since the time the
word was written. The Em pty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing
cloc k occurs , forcing t he Empty Fl ag HIGH ; onl y then can data
be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synchronizing clo ck beg ins the first synchronization cycle of a
write if the clock transition occurs at time tSKEW1 or greater
after the write. Otherwi se, the subsequent clock cycle can be
the fi rst synchronizat ion cycle .
Full/Input Ready Flags (FFA/IRA, FFC/IRC)
This is a dual-pur pose flag. In FWFT Mode, the Input Ready
(IRA and IRC) function is selected . I n CY Standard Mode, the
Full Flag (FFA and FFC) function is selected. For both timing
modes, when the Full/Input Ready flag is HIGH, a memory
location i s free in the SRAM to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and
attempted writes to the FIFO are ignored.
The Ful l/Input Ready fl ag of a FIFO is synchroni zed to t he port
cloc k that writes dat a to its arra y. For both FWFT and CY Stan-
dard modes, each time a word is written to a FIFO, its write
pointer is incremented. The state machine that controls a
Full /Inpu t Ready f l ag monit ors a wri te poi nter an d re ad point er
comp arator th at i ndicates when t he FIFO SRAM status is f ull ,
full–1, or full–2. From the time a word is read from a FIFO, its
previous memory location is ready to be written to in a mini-
mum of two cycles of the Full/Input Ready flag synchronizing
clock. Therefore, an Full/Input Ready flag is LOW if less than
two cycles of the Full/Input Ready flag synchronizing clock
have elapsed since the next memory wri te location has been
read. The second LOW-to-HIGH transition on the Full/Input
Read y fl ag synchronizing cl ock after t he read sets the Ful l/In-
put Ready flag HIGH.
A LO W -to -HIGH tr ansiti on on a Full /Input Ready flag s ynchro-
nizing clock begins the first synchronization cycle of a read if
the clock transition occurs at tim e tSKEW1 or greater after t he
read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle.
Almost Empty Flags (AEA, A E B )
The Almost-Empty flag of a FIFO is synchronized to the port
clock that reads data from its array. The state machine that
controls an Almost Empty flag monitors a write pointer and
read pointer com parator that indicates when the FIFO SRAM
status is almost empty, almost empty+1, or almost empty+2.
The Almost Empty state is defined by the contents of register
X1 for AEB and regi ster X2 for AEA. These registers are load-
ed with preset values during a FIFO reset, programmed from
Port A, or programmed serially (see Almost Empty flag and
Almost Full flag offset pr ogram ming abo v e). An Almost Empty
flag is LOW when its FIFO contains X or less words and is
HIGH when its FIFO contains (X+1) or more words. A data
word present in the FIFO output register has been read from
memory.
Two LOW-to-HIGH transitions of the Almost Empty flag syn-
chronizing clock are required after a FIFO write for its Almost
Empty flag to refl ect the new level of fi ll. Therefore, the Almost
Full flag of a FIFO containing (X+1) or more words remains
LO W if t w o cycles of i ts synchronizing clock have not el apsed
since the write that filled the memory to the (X+1) level. An
Almost Empty flag is set HIGH by the second LOW-to-HIGH
transition of its synchronizing clock after the FIFO write that
fills memory to t he (X+1) lev el. A LO W-to-HIGH transition of an
Almost Empty flag synchronizing clock begins the first syn-
chronization cycle if it occurs at time tSKEW2 or greater after
the write that fills the FIFO to (X+1) words. Otherwise, the sub-
sequent synchronizing clock cycle may be the first synchroni-
zation cycle.
Almost Full Flags (AFA, A F C)
The Almost Full flag of a FIFO is sync hronized to the port clock
that writ es da ta to i ts ar ra y. The s tate mac hine t hat contr ols an
Almost Full fla g mon itors a write po inter a nd read po inter c om-
parator that indicates when the FIFO SRAM status is almost
full, almost full–1, or almost full–2. The Almost Full state is
defin ed b y the cont ents of regist er Y1 f or AFA and regi ster Y2
for AFC. These registers are loaded wi th preset val ues during
a FIFO reset, programmed from Por t A, or programmed seri-
ally (see Almost Empty flag and Almost Full flag offset pro-
gramm ing above). An Almost Full flag is LOW when the n um -
ber of words in its FIFO is greater than or equal to (256–Y),
(512–Y), (1024–Y), (4096–Y), or (16384–Y) for the
CY7C436X6 respectively. An Almost Full flag is HIGH when
the number of words in its FIFO is less than or equal to
[256–(Y+1)], [512–(Y+1)], [1024–(Y+1)], [4096–(Y+1)], or
[16384–(Y+1)] for the CY7C436X6 respectively. Note that a
data word present in the FIFO output register has been read
from memor y.
Two LOW-to-HIGH transiti ons of the Almost Full fl ag synchro-
nizing clock are required after a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [256/512/1024/4096/16384–(Y+1)]
or less words remains LOW if two cycles of its synchronizing
clock have not elapsed since the read that reduced the number
of words in memory to [ 256/512/1024/4096/16384–(Y+1)]. An
Almost Ful l flag is set HIGH by th e second LO W- to-HIGH tran -
siti on of its s ynch ronizing cl ock aft er th e FIFO r ead t hat r educ -
es the number of words in memory to
[256/512/1024/4096/16384–(Y+1)]. A LOW-to-HIGH transition
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
33
PRELIMINARY
of an Almost Full fl ag synchronizing clock begins the first syn-
chr oni zation cycle if it occur s at time tSKEW2 o r great er a fter
the read that reduces the number of words in memory to
[256/512/1024/4096/16384–(Y+1)]. Otherwise, the subse-
quent synchronizing cl ock cycle may be the first synchroniza-
tion cycle.
Mailbox Registers
Each FI FO ha s a 36-bit byp ass regist er t o pas s com mand an d
control inform ation between Por t A and Por t B/Por tC without
putting it in queue. The Mailbox Select (MBA, MBB, MBC) in-
puts choose betwee n a mail reg ister and a FIFO for a port data
transfer operation. The usable width of both the Mail1 and
Mail2 regist ers matche s the sel ected bu s size for Port C.
A LOW-to-HIGH transition on CLKA writes A0−35 data to the
Mail 1 Regist er when a Port A write is select ed by CSA , W/RA,
and ENA with MBA HIGH.
When sending data from Port C to Port A via the Mai l2 Regis-
ter, the following is the case: A LOW-to-HIGH transition on
CLKC wr ites C0−17 data to the Mail2 Register when a Por t C
write is selected by WENC with MBC HIGH. If the selected
Port C bus size is also 18 bits, then the usable width of the
Mail2 Register employs data lines C 0–17. If the selected Por t
C bus si ze is 9 bits , then the usable width of the Mail2 Register
employs data lines C0−8. (In this case, C9−17 are don’t care
inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LO W. Attempt ed writes to a mail regist er are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the por t
Ma ilbox Sele c t in pu t is HIG H .
The Mail1 Register Flag (MBF1) is set HIGH by a
LOW-to-HIGH transition on CLKB when a Port B read is se-
lect ed by CSB, RENB, and ENB with MBB HIGH. For an 18-bit
bus size, 18 bits of mailbox data are placed on B0–17. For a
9-bit bus size, 9 bits of mailbox data are placed on B0–8. (In
this case, B9–17 are indeterminate.)
The Mail2 register Flag ( MBF2) is set HIGH by a LOW-to-HIGH
transition on CLKA when a Port A read is selected by CSA,
W/RA, and ENA wit h MBA HIGH.
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the m ailbox data.
Bus Sizi ng
The Port B and P ort C buses can be configured in a 18-bit word
or 9-bit byte format for data read from FIFO1 or written to
FIFO2. The levels applied to the Por t B Bus Size Select (SI-
ZEB) and the Por t C Bus Size Select (SIZEC) determine the
widt h of the buses . T he bus siz e can be selected independen t-
ly f or P orts B and C. These l ev els should be static throug hout
FIFO operation. Both bus size selections are implemented at
the completion of Master Reset, by the time the Full/Input
Ready flag is set HIG H.
Two differ ent methods for sequencing data transfer are avai l-
able for Port B when the bus size selection is either byte-or
word-siz e. They ar e ref erred t o as Big Endian (most sign ificant
byte first) and Little Endian (least significant byte first). The
level applied to the Big Endian Select (BE) input during the
LOW-to-HIGH tr ansi tion of M R S 1 and M RS2 select s th e endi-
an method that will be active during FIFO operation. BE is a
don’t care input when the bus size selected for Por t B is long
word. The endian m ethod i s implement ed at th e compl etion o f
Master Res et, by t he time th e Full/Input ready f lag is se t HIGH.
Only 36-bit long word data is written to or read from the two
FIFO memo ries on the CY7C436X6 . Bus-matching oper ations
are done after data is read from the FIFO1 RAM and before
data is written to FIFO2 RAM. Thes e bus -matching operations
are not availab le when tr ansferring dat a via mailbox registers.
Furt hermo re, b oth the w ord - and by te-si z e bus s ele ctions limi t
the width of the data bus that can be used for mail register
operat ions. In thi s case, only those byt e lan es belonging to the
selected word- or byte-size bus can carry mailbox data. The
remaining data outputs will be indeterminate. The remaining
data inputs will be don’t care inputs. For example, when a
word-size b us is sel ected, then mailbox data can be transmit -
ted only between A0–17 and B0–17. When a byte-size bus is
selected, then mailbox data can be transmitted only between
A0–8 and B0–8.
Bus-Matching FIFO1 Reads
Data is read from the FIFO1 RAM in 36-bit long word incre-
ments. If by te or word size i s implemented o n Po rt B, only the
first one or two bytes appear on the selected portion of the
FIFO1 output register, with the rest of the long word stored in
auxil iary reg is ters. In this case, subsequent FIFO1 reads out -
put the res t of the long word to the FIFO1 output register.
When reading data from FIFO1 in the byte, the unused B 9-17
outputs are indeterm inate.
Bus-Matching FIFO2 Writes
Data is written to the FIFO2 RAM in 18-bit word increments.
Data written to FIFO2 with a byte or word bus size stores the
initial bytes or words in auxiliary registers. The CLKC rising
edge that writes the word to FI FO2 also stores the entire long
word in FIFO2 RAM.
When reading data from FIFO2 in byte format, the unused
C8–17 outputs are LOW.
Retransmit (RT1, RT2)
The retransmit feature is beneficial when transferr ing packets
of data. It enables the receipt of data to be acknowledged by
the recei ver and ret ransmitted if necessary.
The retransmit feature is intended for use when a number of
writes equal to or less than the depth of the FIFO have oc-
curred and at l east one word has be en read si nce the l ast rese t
cycle . A LO W pu ls e on RT1, RT2 resets the internal read point-
er to the first physical location of the FIFO. CLKA and CLKB
ma y be free runni ng but mu st be disabled during and tRTR after
the retransmi t pulse. With every v alid read cycle after retrans -
mit, previously accessed data is read and the read pointer is
incremented until it is equal to the write pointer. Flags are gov-
er ned by the relative locations of the read and write pointers
and are updated duri ng a retransmit cyc le. Data writ ten to the
FIFO after activation of RT1, RT2 are transm itted also.
The full depth of the FIFO can be repeatedly retransmitted.
.
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
34
PRELIMINARY
A
B17–9
B
B8–0
C
B17–9
D
B8–0
C
B17–9
D
B8–0
A
B17–9
B
B8–0
A
B8–0
B
B8–0
C
B8–0
D
B8–0
B17–9
B17–9
B17–9
B17–9
(A) WORD SIZE – BIG ENDIAN
(B) WO RD SIZE – LITTLE ENDIAN
(C) BYTE SIZE – BIG ENDIAN
BE SIZEB
HL
BE SIZEB
LL
BE SIZEB
HH
1st: Read from
FIFO1
2nd: Read from
FIFO1
1st: Read from
FIFO1
2nd: Read from
FIFO1
1s t: Re ad fro m
FIFO1
2nd: Read from
FIFO1
3rd: Read from
FIFO1
4th: Read from
FIFO1
BYTE ORDER ON
PORT A:
D
B8–0
C
B8–0
B
B8–0
A
B8–0
B17–9
B17–9
B17–9
B17–9
(D) BYTE SIZE – LITTLE ENDIAN
BE SIZEB
LH 1st: Read from
FIFO1
2nd: Read from
FIFO1
3rd: Read from
FIFO1
4th: Read from
FIFO1
PORT B BUS SIZING
A
A35–27
B
A26–18
C
A17–9
D
A8–0 Write to FIFO1
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
35
PRELIMINARY
A
C17–9
B
C8–0
C
C17–9
D
C8–0
C
C17–9
D
C8–0
A
C17–9
B
C8–0
A
C8–0
B
C8–0
C
C8–0
D
C8–0
C17–9
C17–9
C17–9
C17–9
(A) WORD SIZE – BIG ENDIAN
(B) WO RD SIZE – LITTLE ENDIAN
(C) BYTE SIZE – BIG ENDIAN
BE SIZEC
HL
BE SIZEC
LL
BE SIZEC
HH
1st: Read from
FIFO2
2nd: Read from
FIFO2
1st: Read from
FIFO2
2nd: Read from
FIFO2
1s t: Re ad fro m
FIFO2
2nd: Read from
FIFO2
3rd: Read from
FIFO2
4th: Read from
FIFO2
D
C8–0
C
C8–0
B
C8–0
A
C8–0
C17–9
C17–9
C17–9
C17–9
(D) BYTE SIZE – LITTLE ENDIAN
BE SIZEC
LH 1st: Read from
FIFO2
2nd: Read from
FIFO2
3rd: Read from
FIFO2
4th: Read from
FIFO2
PORT C BUS SIZING
BYTE OR DER ON
PO R T A : A
A35–27
B
A26–18
C
A17–9
D
A8–0 Write to FIFO2
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
36
PRELIMINARY
Notes:
62. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
63. X2 register holds the offset for AEA; Y2 register holds the offset for AFC.
Table 1. Flag Programming
SPM FS1/SEN FS0/SD MRS1 MRS2 X1 and Y1 Regi sters[62] X2 and Y2 Registers[63]
H H H ↑X64 X
H H H X ↑X64
H H L ↑X16 X
H H L X ↑X16
H L H ↑X 8 X
H L H X ↑X 8
H L L ↑ ↑ Parallel program m ing via Port A P arall el pr ogram ming via Port A
L H L ↑ ↑ Serial programming via SD Serial programmi ng via SD
L H H↑ ↑ Reserved Reserved
L L H↑ ↑ Reserved Reserved
L L L↑ ↑ Reserved Reserved
Table 2 . Po rt A Enable Function Table
CSA W/RA ENA MBA CLKA A0–35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance stat e No ne
L H L X X In high- impedance state No ne
LHHL↑In high-impedance state FIFO1 write
LHHH↑In high- impedance stat e Mail1 write
L L L L X Active, FIFO2 output register None
LLHL↑Active, FIFO2 output register FIFO2 read
L L L H X Active, Mail 2 register None
LLHH
↑Active, Mail2 reg ister Mail2 read (set MBF2 HIGH)
Table 3 . P ort B Enabl e Function Table
CSB RENB MBB CLKB B0–17 OUTPUTS PORT FUNCTION
H X X X In high- impedance state None
L L L X Acti ve , FIFO1 output register None
LH L ↑Active, FIFO1 output register FIFO1 read
L L H X Active, Mail1 register None
LHH ↑Active, Mail1 register Mail1 read (set MBF1 HIGH)
Table 4 . P ort C Enabl e Function Table
WENC MBC CLKC C0–17 OUTPUTS PORT FUNCTION
HL
↑In high- impedance state FIFO2 writ e
HH
↑In high- impedance state Mail2 write
L L X In high-impedance stater None
L H X Active, Mail1 register None
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
37
PRELIMINARY
Table 5. FIFO1 Flag Operation (CY Standard and FWFT modes)
Number of Wor ds in FIFO Memory[64,65,66,67] Synchronized to
CLKB Synchronized to
CLKA
CY7C43626 CY7C43636 CY7C43646 CY7C43666 CY7C43686 EFB/ORB AEB AFA FFA/IRA
0 0 0 0 0 L L H H
1 TO X1 1 TO X1 1 TO X1 1 TO X1 1 TO X1 H L H H
(X1+1) to
[256–(Y1+1)] (X1+1) to
[512–(Y1+1)] (X1+1) to
[1024–(Y1+1)] (X1+1) to
[4096–(Y1+1)] (X1+1) to
[16384–(Y1+1)] H H H H
(256–Y1) to
255 (512–Y1) to
511 (1024–Y1) to
1023 (4096–Y1) to
4095 (16384–Y1) to
16383 H H L H
256 512 1024 4096 16384 H H L L
Table 6. FIFO 2 FLAG OPERATION (CY Standard and FWFT modes)
Number of Words in FIFO Memory[68,69,70,71] Synchr onized to
CLKA Synchronized to
CLKC
CY7C43626 CY7C43636 CY7C43646 CY7C43666 CY7C43686 EFA/ORA AEA AFC FFC/IRC
0 0 0 0 0 L L H H
1 TO X2 1 TO X2 1 TO X2 1 TO X2 1 TO X2 H L H H
(X2+1) to
[256–(Y2+1)] ( X 2+1) to
[512–(Y2+1)] (X2+1) to
[1024–(Y2+1)] (X2+1) to
[4096–(Y2+1)] (X2+1) to
[16384–(Y2+)1] H H H H
(256–Y2) to
255 (512–Y2) to
511 (1024–Y2) to
1023 (4096–Y2) to
4095 (16384–Y2) to
16383 H H L H
256 512 1024 4096 16384 H H L L
Table 7 . Data Size for Word Writes to FIFO2
Size Mode[72] Wri te No. Data Writt en to FI FO 2 Data Read From FIFO2
BM SIZE BE C17–9 C8–0 A35–27 A26–18 A17–9 A8–0
HLH1ABABCD
2CD
HLL1CDABCD
2AB
Notes:
64. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset
or port A programming.
65. When a word loaded to an empty FIFO is shifted to the output register, its pre vious FIFO memory location is free.
66. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT mode, the first word written to an empty FIFO goes unrequested to
the output register (no read operation necessary), it is not included in the FIFO memory count.
67. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in CY Standard mode.
68. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFC. Both X2 and Y2 are selected during a FIFO2 reset
or port A programming.
69. When a word loaded to an empty FIFO is shifted to the output register, its pre vious FIFO memory location is free.
70. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT mode, the first word written to an empty FIFO goes unrequested to
the output register (no read operation necessary), it is not included in the FIFO memory count.
71. The ORA and IRC functions are active during FWFT mode; the EFA and FFC functions are active in CY Standard mode.
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
38
PRELIMINARY
Table 8. Data Size for Byte Writes to FIFO2
Size Mode [72] Write No. Da ta W ri tten to
FIFO2 Data Read From FIFO2
BM SIZE BE C8–0 A35–27 A26–18 A17–9 A8–0
HHH1 A ABCD
2B
3C
4D
HHL1 D ABCD
2C
3B
4A
Table 9 . Data Size for Word Reads from FIFO1
Size Mode[73] Data Writt en to FIFO1 Read No. Data Read Fr om
FIFO1
BM SIZE BE A35–27 A26–18 A17–9 A8–0 B17–9 B8–0
HLHABCD1AB
2CD
HLLABCD1CD
2AB
Table 10. D ata Siz e for Byte Reads from FIFO1
Size Mode[73] Data Written to FIFO1 Read No. Data Read From
FIFO1
BM SIZE BE A35–27 A26–18 A17–9 A8–0 B8–0
HHHABCD1 A
2B
3C
4D
HHLABCD1 D
2C
3B
4A
Note:
72. BE is selected at Master Reset. SIZEC must be static throughout device operation.
73. BE is selected at Master Reset. SIZEC must be static throughout device operation.
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
39
PRELIMINARY
Document #: 38-00701
Ordering Information
256 x36/18x2 Tr i Bus Synchronous FIFO
Speed
(ns) O rd e ring C ode Package
Name Package
Type Operating
Range
12 CY7C43626-12AC A128 128-Lead Thi n Q uad Flat Package Commercial
12 CY7C43626-12AI A128 128-Lead Thin Quad Flat Package Industrial
15 CY7C43626-15AC A128 128-Lead Thin Quad Flat Package Commercial
512 x36/18x2 Tr i Bus Synchronous FIFO
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
12 CY7C43636-12AC A128 128-Lead Thin Quad Flat Package Commerci al
12 CY7C43636-12AI A128 128-Lead Thin Quad Flat P ac kage Industrial
15 CY7C43636-15AC A128 128-Lead Thin Quad Flat Package Commerci al
1K x36/18x2 Tri Bus Synchronous FIFO
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
12 CY7C43646-12AC A128 128-Lead Thin Quad Flat Package Commercial
12 CY7C43646-12AI A128 128-Lead Thin Quad Flat Package Industrial
15 CY7C43646-15AC A128 128-Lead Thin Quad Flat Package Commercial
4K x36/18x2 Tri Bus Synchronous FIFO
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
12 CY7C43666-1 2AC A128 128-Lead Thin Quad Flat Package Com m ercial
12 CY7C43666-1 2AI A128 128-Lead Thin Quad Flat Package Industrial
15 CY7C43666-1 5AC A128 128-Lead Thin Quad Flat Package Com m ercial
16K x36/18x2 Tri Bus Synchronous FIFO
Speed
(n s ) Or d e ring C o de Package
Name Package
Type Operating
Range
12 CY7C43686-12AC A128 128- Lead Thi n Q uad Flat Package Commercial
12 CY7C43686-12AI A128 128- Lead Thi n Q uad Flat Package Industrial
15 CY7C43686-15AC A128 128- Lead Thi n Q uad Flat Package Commercial
PRELIMINARY
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Cor poration assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Sem iconduc tor product. Nor does it conv ey or im ply an y lice nse under patent or other rights. Cypress Semi conductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inj ury to the user. The i nclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Di ag r am
128-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128
51-85101
