ADZS-BF526-EZBRD - Analog Devices

ADSP-BF526 EZ-Board®

Evaluation System Manual

Revision 1.2, July 2012

Part Number

82-000208-01

Analog Devices, Inc.

One Technology Way

Norwood, Mass. 02062-9106

ment may not be reproduced in any form without prior, express written

consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without

prior notice. Information furnished by Analog Devices is believed to be

accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use; nor for any infringement of patents or other rights of

third parties which may result from its use. No license is granted by impli-

cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, CrossCore, EngineerZone, EZ-Board,

EZ-Extender, Lockbox, and VisualDSP++ are registered trademarks of

Analog Devices, Inc.

All other brand and product names are trademarks or service marks of

their respective owners.

Regulatory Compliance

The ADSP-BF526 EZ-Board is designed to be used solely in a laboratory

environment. The board is not intended for use as a consumer end prod-

uct or as a portion of a consumer end product. The board is an open

system design which does not include a shielded enclosure and therefore

may cause interference to other electrical devices in close proximity. This

board should not be used in or near any medical equipment or RF devices.

The ADSP-BF526 EZ-Board has been certified to comply with the essen-

tial requirements of the European EMC directive 2004/108/EC and

therefore carries the “CE” mark.

The ADSP-BF526 EZ-Board has been appended to Analog Devices, Inc.

EMC Technical File (EMC TF) referenced DSPTOOLS1, issue 2 dated

June 4, 2008 and was declared CE compliant by an appointed Notified

Body (No.0673) as listed below.

Notified Body Statement of Compliance: Z600ANA2.030 dated June 4,

2008.

Issued by: Technology International (Europe) Limited

60 Shrivenham Hundred Business Park

Shrivenham, Swindon, SN6 8TY, UK

The EZ-Board evaluation system contains ESD (electrostatic discharge) sen-

sitive devices. Electrostatic charges readily accumulate on the human body

and equipment and can discharge without detection. Permanent damage may

occur on devices subjected to high-energy discharges. Proper ESD precau-

tions are recommended to avoid performance degradation or loss of func-

tionality. Store unused EZ-Boards in the protective shipping package.

ADSP-BF526 EZ-Board Evaluation System Manual v

CONTENTS

PREFACE

Product Overview ......................................................................... xiii

Purpose of This Manual ................................................................. xvi

Intended Audience ......................................................................... xvi

Manual Contents .......................................................................... xvii

What’s New in This Manual .......................................................... xvii

Technical Support ........................................................................ xviii

Supported Processors ...................................................................... xix

Product Information ...................................................................... xix

Analog Devices Web Site .......................................................... xix

EngineerZone ............................................................................ xx

Related Documents .................................................................. xxi

Notation Conventions .................................................................... xxi

Contents

vi ADSP-BF526 EZ-Board Evaluation System Manual

USING THE ADSP-BF526 EZ-BOARD

Package Contents ......................................................................... 1-3

Default Configuration .................................................................. 1-3

CCES Install and Session Startup .................................................. 1-5

Session Startup ........................................................................ 1-6

VisualDSP++ Install and Session Startup ....................................... 1-9

Session Startup ...................................................................... 1-10

CCES Evaluation License ........................................................... 1-12

VisualDSP++ Evaluation License ................................................. 1-13

Lockbox Key Security Features .................................................... 1-13

Memory Map ............................................................................. 1-14

SDRAM Interface ....................................................................... 1-16

Parallel Flash Memory Interface .................................................. 1-17

NAND Flash Interface ................................................................ 1-18

SPI Interface .............................................................................. 1-19

Parallel Peripheral Interface (PPI) ................................................ 1-20

Rotary Encoder Interface ............................................................ 1-20

Ethernet Interface ....................................................................... 1-21

Audio Interface ........................................................................... 1-22

USB OTG Interface .................................................................... 1-23

UART Interface .......................................................................... 1-24

ADSP-BF526 EZ-Board Evaluation System Manual vii

Contents

RTC Interface ............................................................................. 1-26

LEDs and Push Buttons .............................................................. 1-26

JTAG Interface ........................................................................... 1-28

Land Grid Array ......................................................................... 1-29

Expansion Interface II ................................................................. 1-29

Power Architecture ...................................................................... 1-30

Power Setup ................................................................................ 1-33

Power Saving Features ................................................................. 1-35

Power Measurements ................................................................... 1-36

Power-On-Self Test ..................................................................... 1-37

Board Design Database ............................................................... 1-37

Example Programs ...................................................................... 1-37

ADSP-BF526 EZ-BOARD HARDWARE REFERENCE

System Architecture ...................................................................... 2-2

Programmable Flags ...................................................................... 2-3

Push Button and Switch Settings ................................................... 2-9

Boot Mode Select Switch (SW1) ............................................ 2-10

SPORT0A ENBL Switches/I2C ENBL (SW2 and SW7) ........ 2-11

Gauge Signals Switch (SW4) .................................................. 2-11

Rotary Encoder with Momentary Switch (SW5) ..................... 2-11

Flash Enable Switch (SW6) .................................................... 2-12

MIC Gain Switch (SW9) ....................................................... 2-12

Contents

viii ADSP-BF526 EZ-Board Evaluation System Manual

Audio LPBK (Loopback) Switch (SW10) ............................... 2-13

ETH Mode/Flash CS Switch (SW11) .................................... 2-13

ETH Enable Switch (SW12) ................................................. 2-14

Rotary/NAND Enable Switch (SW13) .................................. 2-14

UART Setup Switch (SW14) ................................................. 2-15

Programmable Flag Push Buttons (SW15 and SW19) ............. 2-15

Power-Down and Wake Push Buttons (SW16–17) ................. 2-15

Reset Push Button (SW18) .................................................... 2-16

GPIO Enable Switch (SW20) ................................................ 2-16

SPORT1 Enable (SW21) ....................................................... 2-18

Battery Switch (SW22) .......................................................... 2-18

Jumpers ...................................................................................... 2-19

UART Loopback Jumper (JP2) .............................................. 2-20

UART Enable Jumper (JP3) .................................................. 2-20

LED Enable Jumper (JP5) ..................................................... 2-20

MIC Select Jumper (JP6) ...................................................... 2-21

CFG WP Jumper (JP7) ......................................................... 2-21

EXP 5V Select Jumper (JP8) ................................................. 2-21

VR7 Enable Jumper (JP9) ..................................................... 2-21

SENSE2 Select Jumper (JP10) ............................................... 2-22

RST/ETH LED Jumper (JP11) ............................................. 2-22

UART SD Jumper (JP14) ...................................................... 2-23

CHG GPIO Jumper (JP15) ................................................... 2-23

OTP Flag Enable Jumper (JP16) ........................................... 2-23

ADSP-BF526 EZ-Board Evaluation System Manual ix

Contents

CHG Control Jumper (JP17) ................................................ 2-24

VDDEXT Power Jumper (P11) .............................................. 2-25

VDDMEM Power Jumper (P12) ............................................ 2-25

VDDINT Power Jumper (P13) .............................................. 2-25

ETH PWR Jumpers (P21–22) ............................................... 2-25

R274 JMP Jumper (P23) ....................................................... 2-26

BATT Installed Jumper (P25) ................................................ 2-26

LEDs .......................................................................................... 2-27

Ethernet LEDs (LED1–2) ...................................................... 2-28

GPIO LEDs (LED3–5) ......................................................... 2-28

Reset LED (LED7) ................................................................ 2-28

Batt GD LED (LED8) ........................................................... 2-28

Batt Low LED (LED9) .......................................................... 2-29

Charging LED (LED10) ........................................................ 2-29

Connectors ................................................................................. 2-30

Expansion Interface II Connector (J1) ................................... 2-31

RS-232 Connector (J2) .......................................................... 2-31

Dual Audio Connectors (J3–4) .............................................. 2-31

Ethernet Connector (J5) ........................................................ 2-32

Battery Holder (J6) ............................................................... 2-32

JTAG Connector (P1) ........................................................... 2-32

Expansion Interface II Connectors (P2 and P4) ...................... 2-33

Expansion Interface II Connector (P3) ................................... 2-33

DMAX Land Grid Array Connectors (P5–7) .......................... 2-33

Contents

x ADSP-BF526 EZ-Board Evaluation System Manual

USB OTG Connector (P8) .................................................... 2-34

Host Interface Connector (P9) .............................................. 2-34

Power Connector (P14) ......................................................... 2-35

Battery Connector (P24) ....................................................... 2-35

Standalone Debug Agent Connector (ZP1) ............................ 2-35

ADSP-BF526 EZ-BOARD BILL OF MATERIALS

ADSP-BF526 EZ-BOARD SCHEMATIC

INDEX

ADSP-BF526 EZ-Board Evaluation System Manual xi

PREFACE

Thank you for purchasing the ADSP-BF526 EZ-Board®, Analog Devices,

Inc. evaluation system for Blackfin® processors.

Blackfin processors embody a type of embedded processor designed specif-

ically to meet the computational demands and power constraints of

today’s embedded audio, video, and communications applications. They

deliver breakthrough signal-processing performance and power efficiency

within a reduced instruction set computing (RISC) programming model.

Blackfin processors support a media instruction set computing (MISC)

architecture. This architecture is the natural merging of RISC, media

functions, and digital signal processing (DSP) characteristics. Blackfin

processors deliver signal-processing performance in a microprocessor-like

environment.

Based on the Micro Signal Architecture (MSA), Blackfin processors com-

bine a 32-bit RISC instruction set, dual 16-bit multiply accumulate

(MAC) DSP functionality, and eight-bit video processing performance

that had previously been the exclusive domain of very-long instruction

word (VLIW) media processors.

xii ADSP-BF526 EZ-Board Evaluation System Manual

The evaluation board is designed to be used in conjunction with the

CrossCore® Embedded Studio (CCES) and VisualDSP++® development

environments to test the capabilities of the ADSP-BF526 Blackfin proces-

sors. The development environment aids advanced application code

development and debug, such as:

• Create, compile, assemble, and link application programs written

in C++, C, and assembly

• Load, run, step, halt, and set breakpoints in application programs

• Read and write data and program memory

• Read and write core and peripheral registers

• Plot memory

Access to the ADSP-BF526 processor from a personal computer (PC) is

achieved through a USB port or an external JTAG emulator. The USB

interface of the standalone debug agent gives unrestricted access to the

processor and evaluation board’s peripherals. Analog Devices JTAG emu-

lators offer faster communication between the host PC and target

hardware. To learn more about Analog Devices emulators and processor

development tools, go to http://www.analog.com/dsp/tools.

The ADSP-BF526 EZ-Board provides example programs to demonstrate

the product capabilities.

ADSP-BF526 EZ-Board Evaluation System Manual xiii

Preface

Product Overview

The board features:

• Analog Devices ADSP-BF526 Blackfin processor

• Core performance up to 400 MHz

• External bus performance up to 80 MHz

• 208-pin BGA package

•25MHz crystal

• Programmable VDDINT core power

• Analog Devices AD5258 TWI digital potentiometer

• Analog Devices ADP1715 low dropout linear regulator

• Battery-powered operation

• 950 mAh lithium ion battery

• Analog Devices ADP2291 battery charge circuit

• Benchmarq BQ27500 fuel gauge for battery monitoring

• Mobile synchronous dynamic random access memory (SDRAM)

• Micron MT48H32M16 – 64 MB (8M x 16 bits x 4 banks)

• Parallel flash memory

• Numonyx M58WR032KB – 32 Mb (2M x 16 bits)

• NAND flash memory

• Numonyx NAND02 – 2 Gb

Product Overview

xiv ADSP-BF526 EZ-Board Evaluation System Manual

• SPI flash memory

• SST SST25WF040 – 4 Mb

• Analog audio interface

• ADI SSM2603 low-power audio codec

• One stereo LINE OUT jack

• One headphone LINE IN

• One input MIC jack

• One input stereo LINE IN jack

• Ethernet interface

• SMSC LAN8700 PHY device

• 10-BaseT and 100-BaseTX Ethernet controller

• Auto-MDIX

• Thumbwheel

• Panasonic EVQ-WKA001 rotary encoder

• Universal asynchronous receiver/transmitter (UART)

• ADM1385 RS-232 line driver/receiver

• DB9 female connector

ADSP-BF526 EZ-Board Evaluation System Manual xv

Preface

•LEDs

• Nine LEDs: one board reset (red), three general-purpose

(amber), one PHY link (amber), one PHY activity (green),

one battery charging (amber), one battery low (amber), and

one battery good (green)

• Push buttons

• Five push buttons: one reset, two programmable flags with

debounce logic, wake and sleep with debounce logic

• Expansion interface II™:

• Next generation of the expansion interface design, provides

access to most of the ADSP-BF526 processor signals

• Land grid array

• Easy probing of all port pins and most EBIU signals

• Other features

• JTAG ICE 14-pin header

• USB on-the-go (OTG) connector

• Host interface connector

• Blackfin and SDRAM power measurement jumpers

For information about the hardware components of the EZ-Board, refer

to Chapter 2, “ADSP-BF526 EZ-Board Hardware Reference”.

Purpose of This Manual

xvi ADSP-BF526 EZ-Board Evaluation System Manual

Purpose of This Manual

The ADSP-BF526 EZ-Board Evaluation System Manual provides instruc-

tions for installing the product hardware (board). The text describes

operation and configuration of the board components and provides guide-

lines for running your own code on the ADSP-BF526 EZ-Board. Finally,

a schematic and a bill of materials are provided as a reference guide for

future designs.

Intended Audience

The primary audience for this manual is a programmer who is familiar

with Analog Devices processors. This manual assumes that the audience

has a working knowledge of the appropriate processor architecture and

instruction set.

Programmers who are unfamiliar with Analog Devices processors can use

this manual, but should supplement it with other texts that describe your

target architecture. For the locations of these documents, see “Related

Documents”.

Programmers who are unfamiliar with CCES or VisualDSP++ should refer

to the online help and user’s manuals.

ADSP-BF526 EZ-Board Evaluation System Manual xvii

Preface

Manual Contents

The manual consists of:

• Chapter 1, “Using The ADSP-BF526 EZ-Board” on page 1-1

Describes EZ-Board functionality from a programmer’s perspective

and provides an easy-to-access memory map.

• Chapter 2, “ADSP-BF526 EZ-Board Hardware Reference” on

page 2-1

Provides information on the EZ-Board hardware components.

• Appendix A, “ADSP-BF526 EZ-Board Bill Of Materials” on

page A-1

Provides a list of components used to manufacture the EZ-Board.

• Appendix B, “ADSP-BF526 EZ-Board Schematic” on page B-1

Provides resources for board-level debugging, can be used as a ref-

erence guide.

What’s New in This Manual

This is revision 1.2 of the ADSP-BF526 EZ-Board Evaluation System Man-

ual. The manual has been updated to include CCES information. In

addition, modifications and corrections based on errata reports against the

previous manual revision have been made.

For the latest version of this manual, please refer to the Analog Devices

Web site.

Technical Support

xviii ADSP-BF526 EZ-Board Evaluation System Manual

Technical Support

You can reach Analog Devices processors and DSP technical support in

the following ways:

• Post your questions in the processors and DSP support community

at EngineerZone®:

http://ez.analog.com/community/dsp

• Submit your questions to technical support directly at:

http://www.analog.com/support

• E-mail your questions about processors, DSPs, and tools develop-

ment software from CrossCore Embedded Studio or

VisualDSP++:

Choose Help > Email Support. This creates an e-mail to

processor.tools.support@analog.com and automatically attaches

your CrossCore Embedded Studio or VisualDSP++ version infor-

mation and license.dat file.

• E-mail your questions about processors and processor applications

to:

processor.support@analog.com or

processor.china@analog.com (Greater China support)

•In the USA only, call 1-800-ANALOGD (1-800-262-5643)

• Contact your Analog Devices sales office or authorized distributor.

Locate one at:

www.analog.com/adi-sales

ADSP-BF526 EZ-Board Evaluation System Manual xix

Preface

• Send questions by mail to:

Processors and DSP Technical Support

Analog Devices, Inc.

Three Technology Way

P.O. Box 9106

Norwood, MA 02062-9106

USA

Supported Processors

This evaluation system supports Analog Devices ADSP-BF526 Blackfin

embedded processors.

Product Information

Product information can be obtained from the Analog Devices Web site

and the online help system.

Analog Devices Web Site

The Analog Devices Web site, www.analog.com, provides information

about a broad range of products—analog integrated circuits, amplifiers,

converters, and digital signal processors.

To access a complete technical library for each processor family, go to

http://www.analog.com/processors/technical_library. The manuals

selection opens a list of current manuals related to the product as well as a

link to the previous revisions of the manuals. When locating your manual

title, note a possible errata check mark next to the title that leads to the

current correction report against the manual.

Product Information

xx ADSP-BF526 EZ-Board Evaluation System Manual

Also note, myAnalog is a free feature of the Analog Devices Web site that

allows customization of a Web page to display only the latest information

about products you are interested in. You can choose to receive weekly

e-mail notifications containing updates to the Web pages that meet your

interests, including documentation errata against all manuals.

myAnalog provides access to books, application notes, data sheets, code

examples, and more.

Visit myAnalog to sign up. If you are a registered user, just log on. Your

user name is your e-mail address.

EngineerZone

EngineerZone is a technical support forum from Analog Devices. It allows

you direct access to ADI technical support engineers. You can search

FAQs and technical information to get quick answers to your embedded

processing and DSP design questions.

Use EngineerZone to connect with other DSP developers who face similar

design challenges. You can also use this open forum to share knowledge

and collaborate with the ADI support team and your peers. Visit

http://ez.analog.com to sign up.

ADSP-BF526 EZ-Board Evaluation System Manual xxi

Preface

Related Documents

For additional information about the product, refer to the following

publications.

Notation Conventions

Text conventions used in this manual are identified and described as

follows.

Table 1. Related Processor Publications

Title Description

ADSP-BF522/ADSP-BF523/ADSP-BF524/

ADSP-BF525/ADSP-BF526/ADSP-BF527

Blackfin Embedded Processor Data Sheet

General functional description, pinout, and

timing of the processor

ADSP-BF52x Blackfin Processor Hardware

Reference

Description of internal processor architecture

and all register functions

Blackfin Processor Programming Reference Description of all allowed processor assembly

instructions

Example Description

Close command

(File menu)

Titles in reference sections indicate the location of an item within the

development environment’s menu system (for example, the Close com-

mand appears on the File menu).

{this | that} Alternative required items in syntax descriptions appear within curly

brackets and separated by vertical bars; read the example as this or

that. One or the other is required.

[this | that] Optional items in syntax descriptions appear within brackets and sepa-

rated by vertical bars; read the example as an optional this or that.

[this,…] Optional item lists in syntax descriptions appear within brackets delim-

ited by commas and terminated with an ellipse; read the example as an

optional comma-separated list of this.

Notation Conventions

xxii ADSP-BF526 EZ-Board Evaluation System Manual

.SECTION Commands, directives, keywords, and feature names are in text with

letter gothic font.

filename Non-keyword placeholders appear in text with italic style format.

Note: For correct operation, ...

A Note provides supplementary information on a related topic. In the

online version of this book, the word Note appears instead of this

symbol.

Caution: Incorrect device operation may result if ...

Caution: Device damage may result if ...

A Caution identifies conditions or inappropriate usage of the product

that could lead to undesirable results or product damage. In the online

version of this book, the word Caution appears instead of this symbol.

Warning: Injury to device users may result if ...

A Warning identifies conditions or inappropriate usage of the product

that could lead to conditions that are potentially hazardous for the

devices users. In the online version of this book, the word Warning

appears instead of this symbol.

Example Description







ADSP-BF526 EZ-Board Evaluation System Manual 1-1

1 USING THE ADSP-BF526

EZ-BOARD

This chapter provides specific information to assist you with development

of programs for the ADSP-BF526 EZ-Board evaluation system.

The following topics are covered.

•“Package Contents” on page 1-3

•“Default Configuration” on page 1-3

•“CCES Install and Session Startup” on page 1-5

•“VisualDSP++ Install and Session Startup” on page 1-9

•“CCES Evaluation License” on page 1-12

•“VisualDSP++ Evaluation License” on page 1-13

•“Lockbox Key Security Features” on page 1-13

•“Memory Map” on page 1-14

•“SDRAM Interface” on page 1-16

•“Parallel Flash Memory Interface” on page 1-17

•“NAND Flash Interface” on page 1-18

•“SPI Interface” on page 1-19

•“Parallel Peripheral Interface (PPI)” on page 1-20

•“Rotary Encoder Interface” on page 1-20

1-2 ADSP-BF526 EZ-Board Evaluation System Manual

•“Ethernet Interface” on page 1-21

•“Audio Interface” on page 1-22

•“USB OTG Interface” on page 1-23

•“UART Interface” on page 1-24

•“RTC Interface” on page 1-26

•“LEDs and Push Buttons” on page 1-26

•“JTAG Interface” on page 1-28

•“Land Grid Array” on page 1-29

•“Expansion Interface II” on page 1-29

•“Power Architecture” on page 1-30

•“Power Setup” on page 1-33

•“Power Saving Features” on page 1-35

•“Power Measurements” on page 1-36

•“Power-On-Self Test” on page 1-37

•“Board Design Database” on page 1-37

•“Example Programs” on page 1-37

For information about the graphical user interface, including boot load-

ing, target options, and other facilities of the EZ-Board system, refer to

the online help.

For more information about the ADSP-BF526 Blackfin processor, see

documents referred to at “Related Documents”.

ADSP-BF526 EZ-Board Evaluation System Manual 1-3

Using The ADSP-BF526 EZ-Board

Package Contents

Your ADSP-BF526 EZ-Board evaluation system package contains the fol-

lowing items.

• ADSP-BF526 EZ-Board

• Universal 5.0V DC power supply

• Ethernet patch cable

• Two 3.5 mm male-to-male audio cables

• Two mini USB 2.0 cables for USB on-the-go (OTG)

If any item is missing, contact the vendor where you purchased your

EZ-Board or contact Analog Devices, Inc.

Default Configuration

The ADSP-BF526 EZ-Board is designed to run outside your personal

computer as a standalone unit. You do not have to open your computer

case.

When removing the EZ-Board from the package, handle the board care-

fully to avoid the discharge of static electricity, which can damage some

components. Figure 1-1 show the default jumper and switch settings, con-

nector locations, and LEDs used in installation. Confirm that your board

in the default configuration before using the board.

The EZ-Board evaluation system contains ESD (electrostatic discharge) sen-

sitive devices. Electrostatic charges readily accumulate on the human body

and equipment and can discharge without detection. Permanent damage may

occur on devices subjected to high-energy discharges. Proper ESD precau-

tions are recommended to avoid performance degradation or loss of function-

ality. Store unused EZ-Boards in the protective shipping package.

Default Configuration

1-4 ADSP-BF526 EZ-Board Evaluation System Manual

Figure 1-1. Default EZ-Board Hardware Setup

ADSP-BF526 EZ-Board Evaluation System Manual 1-5

Using The ADSP-BF526 EZ-Board

CCES Install and Session Startup

For information about CCES and to download the software, go to

www.analog.com/CCES. A link for the ADSP-BF526 EZ-KIT Lite Board

Support Package (BSP) for CCES can be found at

http://www.analog.com/Blackfin/EZKits.

Follow these instructions to ensure correct operation of the product soft-

ware and hardware.

Step 1: Connect the EZ-KIT Lite board to a personal computer (PC) run-

ning CCES using one of two options: an Analog Devices emulator or via

the debug agent.

Using an Emulator:

1. Plug one side of the USB cable into the USB connector of the emu-

lator. Plug the other side into a USB port of the PC running

CCES.

2. Attach the emulator to the header connector P1 (labeled JTAG) on

the EZ-Board.

Using the standalone Debug Agent:

1. Attach the standalone debug agent to connectors P1 (labeled JTAG)

and ZP1 of the EZ-Board.

2. Plug one side of the USB cable into the USB connector of the

debug agent P4. Plug the other side of the cable into a USB port of

the PC running CCES.

CCES Install and Session Startup

1-6 ADSP-BF526 EZ-Board Evaluation System Manual

Step 2: Attach the provided cord and appropriate plug to the power

adaptor.

1. Plug the jack-end of the power adaptor into the power connector

P14 (labeled 5.0V) on the EZ-Board.

2. Plug the other side of the power adaptor into a power outlet. The

power LED (labeled LED4) is lit green when power is applied to the

board.

3. Power the emulator (if used). Plug the jack-end of the assembled

power adaptor into the emulator and plug the other side of the

power adaptor into a power outlet. The enable/power is lit green

when power is applied.

Step 3 (if connected through the debug agent): Verify that the yellow

USB monitor LED (labeled LED2) and the green power LED (labeled

LED1) on the debug agent are both on. This signifies that the board is com-

municating properly with the host PC and ready to run CCES.

Session Startup

It is assumed that the CrossCore Embedded Studio software is installed

and running on your PC.

Note: If you connect the board or emulator first (before installing

CCES) to the PC, the Windows driver wizard may not find the

board drivers.

1. Navigate to the CCES environment via the Start menu.

Note that CCES is not connected to the target board.

ADSP-BF526 EZ-Board Evaluation System Manual 1-7

Using The ADSP-BF526 EZ-Board

2. Use the system configuration utility to connect to the EZ-Board.

If a debug configuration exists already, select the appropriate

configuration and click Apply and Debug or Debug. Go to step 8.

To create a debug configuration, do one of the following:

• Click the down arrow next to the little bug icon, select

Debug Configurations

• Choose Run > Debug Configurations.

The Debug Configuration dialog box appears.

3. Select CrossCore Embedded Studio Application and click

(New launch configuration).

The Select Processor page of the Session Wizard appears.

4. Ensure Blackfin is selected in Processor family. In Processor type,

select ADSP-BF526. Click Next.

The Select Connection Type page of the Session Wizard appears.

5. Select one of the following:

• For standalone debug agent connections, EZ-Board and

click Next.

• For emulator connections, Emulator and click Next.

The Select Platform page of the Session Wizard appears.

CCES Install and Session Startup

1-8 ADSP-BF526 EZ-Board Evaluation System Manual

6. Do one of the following:

• For standalone debug agent connections, ensure that the

selected platform is ADSP-BF526 EZ-Board via Debug

Agent.

• For emulator connections, choose the type of emulator that

is connected to the board.

7. Click Finish to close the wizard.

The new debug configuration is created and added to the pro-

gram(s) to load list.

8. In the Program(s) to load section, choose the program to load

when connecting to the board. If not loading any program upon

connection to the target, do not make any changes.

Note that while connected to the target, there is no way to choose a

program to download. To load a program once connected, termi-

nate the session.

To delete a configuration, go to the Debug Configurations dialog

box and select the configuration to delete. Click and choose Yes

when asked if you wish to delete the selected launch configuration.

Then Close the dialog box.

To disconnect from the target board, click the terminate button

(red box) or choose Run > Terminate.

To delete a session, choose Target > Session > Session List. Select

the session name from the list and click Delete. Click OK.

ADSP-BF526 EZ-Board Evaluation System Manual 1-9

Using The ADSP-BF526 EZ-Board

VisualDSP++ Install and Session Startup

For information about VisualDSP++ and to download the software, go to

www.analog.com/VisualDSP.

There are two options to connect the EZ-Board hardware to a personal

computer (PC) running VisualDSP++: via an Analog Devices emulator or

via a standalone debug agent module. The standalone debug agent allows

a debug agent to interface to the ADSP-BF526 EZ-Board. The standalone

debug agent is shipped with the kit.

To connect the EZ-Board to a PC via an emulator:

1. Set up the EZ-Board for either battery power or wall/USB power;

see “Power Setup” on page 1-33.

2. Attach the emulator header to connector P1 (labeled JTAG) on the

back side of the EZ-Board.

3. Depending on the power source for the EZ-Board, do one of the

following.

• Turn ON switch SW22 (battery)

• Plug the 5V wall adaptor into connector P14 (labeled 5.0V)

4. Plug the mini plug of the provided USB cable into connector P8

(labelled USB OTG). Plug the standard USB plug into a USB port of

the PC running VisualDSP++.

VisualDSP++ Install and Session Startup

1-10 ADSP-BF526 EZ-Board Evaluation System Manual

To connect the EZ-Board to a PC via a standalone debug agent:

The debug agent can be used only when power is supplied from the

wall adaptor.

1. Attach the standalone debug agent to connectors P1 (labeled JTAG)

and ZP1 on the backside of the EZ-Board, watching for the keying

pin of P1 to connect correctly. Plug the 5V adaptor into connector

P14 (labeled 5.0V).

2. Plug one side of the provided USB cable into the USB connector

(ZP1) of the standalone debug agent. Plug the other side of the

cable into a USB port of the PC running VisualDSP++.

The other USB connector on the ADSP-BF526 EZ-Board (labelled

USB OTG,P8) is for applications use.

3. Verify that the yellow USB monitor LED on the standalone debug

agent (LED4, located near the USB connector) is lit. This signifies

that the board is communicating properly with the host PC and

ready to run VisualDSP++.

Session Startup

1. If you are running VisualDSP++ for the first time, navigate to the

VisualDSP++ environment via the Start > Programs menu. The

main window appears. Note that VisualDSP++ is not connected to

any session. Skip the rest of this step to step 2.

If you have run VisualDSP++ previously, the last opened session

appears on the screen. You can override the default behavior and

force VisualDSP++ to start a new session by pressing and holding

down the Ctrl key while starting VisualDSP++. Do not release the

Ctrl key until the Session Wizard appears on the screen. Go to

step 3.

ADSP-BF526 EZ-Board Evaluation System Manual 1-11

Using The ADSP-BF526 EZ-Board

2. To connect to a new EZ-Board session, start Session Wizard by

selecting one of the following.

• From the Session menu, New Session.

• From the Session menu, Session List. Then click New Ses-

sion from the Session List dialog box.

• From the Session menu, Connect to Target.

3. The Select Processor page of the wizard appears on the screen.

Ensure Blackfin is selected in Processor family. In Choose a target

processor, select ADSP-BF526. Click Next.

4. The Select Connection Type page of the wizard appears on the

screen. For standalone debug agent connections, select EZ-Board

and click Next. For emulator connections select Emulator, and

click Next

5. The Select Platform page of the wizard appears on the screen.

For standalone debug agent connections, ensure that the selected

platform is ADSP-BF526 EZ-Board via Debug Agent. For emula-

tor connections, choose the type of emulator that is connected.

Specify your own Session name for the session or accept the default

name.

The session name can be a string of any length; although, the box

displays approximately 32 characters. The session name can

include space characters. If you do not specify a session name,

VisualDSP++ creates a session name by combining the name of the

selected platform with the selected processor. The only way to

change a session name later is to delete the session and open a new

session.

Click Next.

CCES Evaluation License

1-12 ADSP-BF526 EZ-Board Evaluation System Manual

6. The Finish page of the wizard appears on the screen. The page dis-

plays your selections. Check the selections. If you are not satisfied,

click Back to make changes; otherwise, click Finish. VisualDSP++

creates the new session and connects to the EZ-Board. Once con-

nected, the main window’s title is changed to include the session

name set in step 5.

To disconnect from a session, click the disconnect button

or select Session > Disconnect from Target.

To delete a session, select Session > Session List. Select the session

name from the list and click Delete. Click OK.

CCES Evaluation License

The ADSP-BF526 EZ-Board software is part of the Board Support Pack-

age (BSP) for the Blackfin ADSP-BF52x family. The EZ-Board is a

licensed product that offers an unrestricted evaluation license for 90 days

after activation. Once the evaluation period ends, the evaluation license

becomes permanently disabled. If the evaluation license is installed but

not activated, it allows 10 days of unrestricted use and then becomes dis-

abled. The license can be re-enabled by activation.

An evaluation license can be upgraded to a full license. Licenses can be

purchased from:

• Analog Devices directly. Call (800) 262-5645 or 781-937-2384 or

go to:

http://www.analog.com/buyonline.

• Analog Devices, Inc. local sales office or authorized distributor. To

locate one, go to:

http://www.analog.com/salesdir/continent.asp.

ADSP-BF526 EZ-Board Evaluation System Manual 1-13

Using The ADSP-BF526 EZ-Board

The EZ-Board hardware must be connected and powered up to use

CCES with a valid evaluation or full license.

VisualDSP++ Evaluation License

The ADSP-BF526 EZ-Board installation is part of the VisualDSP++

installation. The EZ-Board is a licensed product that offers an unrestricted

evaluation license for the first 90 days. Once the initial unrestricted

90-day evaluation license expires:

• VisualDSP++ restricts a connection to the ADSP-BF526 EZ-Board

via the USB port of the standalone debug agent interface only.

Connections to simulators and emulation products are no longer

allowed.

• The linker restricts a user’s program to 20 KB of memory for code

space with no restrictions for data space.

To avoid errors when opening VisualDSP++, the EZ-KIT Lite

hardware must be connected and powered up. This is true for using

VisualDSP++ with a valid evaluation or full license.

Lockbox Key Security Features

Blackfin processors feature Lockbox® secure technology: hard-

ware-enabled code security and content protection for one-time

programmable (OTP) memory. Customers purchasing Blackfin processors

can program their own customer public key in OTP.

The ADSP-BF526 EZ-Boards are evaluation boards with the Lockbox key

pre-programmed and publicly documented—the burden of key generation

and OTP programming of public keys is removed from the customer.

Customers can still program other areas of OTP memory on the

ADSP-BF526 EZ-Board. Analog Devices publicly document the

Memory Map

1-14 ADSP-BF526 EZ-Board Evaluation System Manual

EZ-Board’s public and private key pair for customer evaluation and sup-

port of the Lockbox feature, all while avoiding any keys information

exchange. As a result, there is no confidentiality associated with the Lock-

box key on EZ-Boards.

To demonstrate Lockbox features using an EZ-Board, you must use the

keys that are provided pre-programmed on your EZ-Board.

Use the EZ-Board key pair to generate a demo and then provide

the keys to the demo users. Note that the EZ-Board cannot be used

to secure any confidential information. If you wish to create a

demo with confidential keys, you must build your own Blackfin

board and personalize it with your own keys.

Memory Map

The ADSP-BF526 processor has internal static random access memory

(SRAM) used for instructions and data storage. See Table 1-1. The inter-

nal memory details can be found in the ADSP-BF52x Blackfin Processor

Hardware Reference.

The ADSP-BF526 EZ-Board includes four types of external memory: syn-

chronous dynamic random access memory (SDRAM), serial peripheral

interconnect (SPI), parallel flash, and NAND flash. See Table 1-2. For

more information about a specific memory type, go to the respective sec-

tion in this chapter.

ADSP-BF526 EZ-Board Evaluation System Manual 1-15

Using The ADSP-BF526 EZ-Board

Table 1-1. EZ-Board Internal Memory Map

Start Address Content

0xEF00 0000 BOOT ROM (32K BYTE)

0xEF00 8000

0xFEB0 0000

0xFEB2 0000

0xFF40 0000

0xFF40 4000

0xFF40 8000

0xFF50 0000

0xFF50 4000

0xFF50 8000

0xFF60 0000

0xFF60 4000

0xFF60 8000

0xFF60 C000

0xFF61 0000

0xFF61 4000

0xFF70 0000

0xFF70 1000

Reserved

0xFF80 0000 L1 DATA BANKA SRAM (16K BYTE)

0xFF80 4000 L1 DATA BANKA SRAM/CACHE (16K BYTE)

0xFF80 8000 Reserved

0xFF90 0000 L1 DATA BANKB SRAM (16K BYTE)

0xFF90 4000 L1 DATA BANKB SRAM/CACHE (16K BYTE)

0xFF90 8000 Reserved

0xFFA0 0000 L1 INSTRUCTION BANKA LOWER SRAM (16K BYTE)

0xFFA0 4000 L1 INSTRUCTION BANKA UPPER SRAM (16K BYTE)

0xFFA0 8000 L1 INSTRUCTION BANKB LOWER SRAM (16K BYTE)

0xFFA0 C000 Reserved

0xFFA1 0000 L1 INSTRUCTION SRAM/CACHE (16K BYTE)

SDRAM Interface

1-16 ADSP-BF526 EZ-Board Evaluation System Manual

SDRAM Interface

The ADSP-BF526 processor connects to a 64 MB Micron

MT48H32M16-75 chip through the external bus interface unit (EBIU).

The SDRAM chip can operate at a maximum clock frequency of 80 MHz,

which is the ADSP-BF526 processor limitation when operating VDDEXT

at 1.8V.

With a CCES or VisualDSP++ session running and connected to the

EZ-Board via the USB standalone debug agent, the SDRAM registers are

0xFFA1 4000

0xFFA1 8000

0xFFA1 C000

0xFFA2 0000

0xFFA2 4000

Reserved

0xFFB0 0000 L1 SCRATCHPAD SRAM (4K BYTE)

0xFFB0 1000 Reserved

0xFFC0 0000 SYSTEM MMR REGISTERS

0xFFE0 0000 CORE MMR REGISTERS

Table 1-2. EZ-Board External Memory Map

Start Address End Address Content

0x0000 0000 0x03FF FFFF SDRAM bank 0 (SDRAM)

0x2000 0000 0x200F FFFF ASYNC memory bank 0 (flash)

0x2010 0000 0x201F FFFF ASYNC memory bank 1 (flash)

0x2020 0000 0x202F FFFF ASYNC memory bank 2 (flash)

0x2030 0000 0x203F FFFF ASYNC memory bank 3 (flash)

0x2040 0000 0xEEFF FFFF Reserved

Table 1-1. EZ-Board Internal Memory Map (Cont’d)

Start Address Content

ADSP-BF526 EZ-Board Evaluation System Manual 1-17

Using The ADSP-BF526 EZ-Board

configured automatically each time the processor is reset. The values are

used whenever SDRAM is accessed through the debugger (for example,

when viewing memory windows or loading a program).

To disable the automatic setting of the SDRAM registers, do one of the

following:

• CCES users, choose Target > Settings > Target Options and clear

the Use XML reset values check box.

• VisualDSP++ users, choose Settings > Target Options and clear

the Use XML reset values check box.

For more information on changing the reset values, refer to the online

help.

An example program is included in the EZ-Board installation directory to

demonstrate how to setup and access the SDRAM interface. For more

information on how to initialize the registers after a reset, search the

online help for “reset values”.

Parallel Flash Memory Interface

The parallel flash memory interface of the ADSP-BF526 EZ-Board con-

tains a 4 MB (2M x 16 bits) 1.8V Numonyx M58WR032KB chip. Flash

memory connects to the 16-bit data bus and address lines 1 through 19.

Chip enable is decoded by the AMS0—3 select lines through NAND and

AND gates. The address range for flash memory is 0x2000 0000 to

0x203F FFFF.

Flash memory is pre-loaded with boot code for the blink and

power-on-self test (POST) programs. For more information, refer to

“Power-On-Self Test” on page 1-37. Flash memory also is preloaded with

configuration flash information, which contains board revision, BOM

revision, and other data.

NAND Flash Interface

1-18 ADSP-BF526 EZ-Board Evaluation System Manual

By default, the EZ-Board boots from the 16-bit parallel flash memory.

The processor boots from flash memory if the boot mode select switch

(SW1) is set to a position of 1 (see “Boot Mode Select Switch (SW1)” on

page 2-10).

Flash memory code can be modified. For instructions, refer to the online

help and example program included in the EZ-Board installation

directory.

NAND Flash Interface

The ADSP-BF526 processor is equipped with an internal NAND flash

controller, which allows the 2 Gb 1.8V ST Micro’s NAND02 device to be

attached gluelessly to the processor. NAND flash is attached via the pro-

cessor’s specific NAND flash control and data lines. NAND flash shares

pins with the Ethernet PHY, host connector, and expansion interface II.

The NAND chip enable signal (NDCE#_HOSTD10) can be disconnected from

NAND flash by turning SW13.4 (switch 13 position 4) OFF. This ensures

that NAND flash is not driving data when HOSTD10 changes state. See

“Rotary/NAND Enable Switch (SW13)” on page 2-14 for more

information.

The Ethernet PHY (U29) must be disabled in order for NAND flash to

function properly. This is accomplished by setting switch SW12 to OFF, OFF,

ON, OFF.

For more information about the NAND02 device, refer to the Numonyx

Web site: http://www.numonyx.com.

An example program is included in the EZ-Board installation directory to

demonstrate how to setup and access the NAND flash interface.

ADSP-BF526 EZ-Board Evaluation System Manual 1-19

Using The ADSP-BF526 EZ-Board

SPI Interface

The ADSP-BF526 processor has one serial peripheral interface (SPI) port

with multiple chip select lines. The SPI port connects directly to serial

flash memory, audio codec, and expansion interface II.

Serial flash memory is a 4 Mb SST SST25WF040 device, which is selected

using the SPISEL1 line of the processor.

SPI flash memory is factory programmed with Das U-Boot—the universal

boot loader. Das U-Boot (U-Boot for short) is open source firmware for

embedded processors, including the ADSP-BF526 Blackfin processors.

U-Boot can load files from a variety of peripherals, such as a serial connec-

tion, an Ethernet network connection, or flash memories. U-Boot is

executed at system reset, which automatically loads up another application

(such as the Linux kernel or a stand alone application). U-Boot can parse

many types of files on many types of storage devices.

U-Boot is controlled via a serial communications, the default setting is

56700 baud, 8 data bits, No parity, 1 stop bit. See “RS-232 Connector

(J2)” on page 2-31 for information on the serial connector.

For more information about U-Boot, refer to the online documentation:

http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot.

For U-Boot support on the Blackfin processors, refer to the online help

forums:

http://blackfin.uclinux.org/gf/proj-

ect/u-boot/forum/?action=ForumBrowse&forum_id=51.

SPI flash can be modified. For instructions, refer to the online help, exam-

ple program included in the EZ-Board installation directory, and U-Boot

documentation. U-Boot includes an SPI flash driver and can be used to

download a new file over Ethernet or serial connection, and write that to

SPI flash.

Parallel Peripheral Interface (PPI)

1-20 ADSP-BF526 EZ-Board Evaluation System Manual

By default, the EZ-Board boots from the 16-bit flash parallel memory. SPI

flash can be selected as the boot source by setting the boot mode select

switch (SW1) to position 3 (see “Boot Mode Select Switch (SW1)” on

page 2-10).

Parallel Peripheral Interface (PPI)

The ADSP-BF526 processor provides a parallel peripheral interface (PPI),

supporting data widths up to 16 bits. The PPI interface provides three

multiplexed frame syncs, a dedicated clock input, and 16 data lines. The

full PPI port is accessible on the expansion interface II connector (P3).

The PPI signals connect to multi-function pins; the upper eight data bit

signals are configured for the rotary, SPI, UART1, and LED0 interfaces. To

use the upper eight PPI data lines at connector P3, change the board as fol-

lows: disable rotary switch (SW13 positions 1–3 OFF) and disable the UART1

interface (remove a jumper from JP3). LED0 mimics the PPID8 data pin.

The PPI has a dedicated clock, generated from the expansion interface II.

The PPI is not used on the EZ-Board, intended for use on the expansion

interface II.

Rotary Encoder Interface

The ADSP-BF526 processor has a built-in, up-down counter with support

for a rotary encoder. The three-wire rotary encoder interface connects to

the thumbwheel rotary switch (SW13) and expansion interface II connector

(P3). The rotary encoder can be turned clockwise for the up function,

counter clockwise for the down function, or can be pushed towards the

center of the board to clear the counter.

The rotary switch is a two-bit quadrature (gray code) counter with a

detent, meaning that both the down signal (CDG) and up signal (CUD)

ADSP-BF526 EZ-Board Evaluation System Manual 1-21

Using The ADSP-BF526 EZ-Board

toggle when the count register increases on a rotation to the right. Upon

rotating to the left, CDG and CUD toggle, and the overall count decreases.

If the processor pins are needed for the expansion interface II, disconnect

the rotary encoder switch via the four-position rotary/NAND enable

switch (SW13). For more information, see “Rotary/NAND Enable Switch

(SW13)” on page 2-14.

An example program is included in the EZ-Board installation directory to

demonstrate how to set up and access the rotary encoder interface.

Ethernet Interface

The ADSP-BF526 processor has an integrated Ethernet MAC with media

independent interface (MII) and reduced media independent interface

(RMII), which connects to an external PHY. The EZ-Board provides a

SMSC LAN8700 RMII Ethernet PHY with Auto-MDIX, fully compliant

with IEEE 802.2/802.2u standards. The SMSC LAN8700 chip supports

10BASE-T and 100BASE-TX operations. The part is attached gluelessly

to the processor.

The Ethernet signals are shared with NAND flash; by default, the Ether-

net mode is set OFF (SW12 OFF, OFF, ON, OFF). See “ETH Enable Switch

(SW12)” on page 2-14 for more information.

It is important not to run code that accesses NAND flash while

using the Ethernet interface.

The Ethernet mode is set by the SW11 switch and defaults to all capable,

auto negotiation with settings OFF, OFF, OFF, ON. See “ETH Mode/Flash

CS Switch (SW11)” on page 2-13 for more information.

The Ethernet chip is pre-loaded with a MAC address. The MAC address

for the EZ-Board is stored in the configuration flash section of the parallel

flash memory and can be found on a sticker on the bottom side of the

board.

Audio Interface

1-22 ADSP-BF526 EZ-Board Evaluation System Manual

The PHY portion of the Ethernet chip connects to a Pulse HX1188 mag-

netics (U28), then to a standard RJ-45 Ethernet connector (J5). For more

information, see “Ethernet Connector (J5)” on page 2-32.

Example programs are included in the EZ-Board installation directory to

demonstrate how to use the Ethernet interface.

In low-power consumption applications that do not require Ethernet, the

P21—22 jumpers can be removed to disconnect the power from the

LAN8700 PHY and Ethernet oscillator. For more information, see “ETH

PWR Jumpers (P21–22)” on page 2-25.

Audio Interface

The audio interface of the EZ-Board consists of a low-power stereo codec,

ADI SSM2603, with an integrated headphone driver and associated pas-

sive components. There are two inputs, a stereo line in, and a mono

microphone, as well as two outputs, a headphone, and a stereo line out.

The codec has integrated stereo analog-to-digital converters (ADCs) and

digital-to-analog converters (DACs) and requires minimal external

circuitry.

The codec connects to the ADSP-BF526 processor via the processor’s

serial port 0A (alternate). The SPORT0A port and 2-wire interface (TWI)

are disconnected from the codec by turning switches SW2 and SW7 OFF,

which enable SPORT0A on the expansion interface II. See “SPORT0A

ENBL Switches/I2C ENBL (SW2 and SW7)” on page 2-11 for more

information.

The TWI of the ADSP-BF526 processor is used to setup and control the

codec. The default TWI address is 0011011. The TWI can be disconnected

from the codec by turning positions 3 and 4 of SW2 OFF. Refer to

“SPORT0A ENBL Switches/I2C ENBL (SW2 and SW7)” on page 2-11

for more information.

ADSP-BF526 EZ-Board Evaluation System Manual 1-23

Using The ADSP-BF526 EZ-Board

Mic gain values of 14 dB, 0 dB, or –6 dB are selectable through the SW9

switch by turning ON position 1, 2, or 3 (respectively). All other positions

must be OFF to achieve the desired gain. For more information, see “MIC

Gain Switch (SW9)” on page 2-12.

Microphone bias is provided through a low-noise reference voltage. A

jumper on positions 2 and 3 of JP6 connects the MICBIAS signal to the

audio jack. Placing a jumper on positions 1 and 2 of JP6 connects the bias

directly to the mic signal. For more information, see “MIC Select Jumper

(JP6)” on page 2-21.

J3 and J4 are 3.5 mm connectors for the audio portion of the board. J4

connects the mic on the top portion and line-in on the bottom. J3 con-

nects the headphone on the top portion and line-out on the bottom. If

there is no 3.5 mm cable plugged into the bottom of either J3 or J4, the

signals are looped back inside the connector. For more information, see

“Dual Audio Connectors (J3–4)” on page 2-31.

For testing, SW10 positions 1 and 2 connect the MICIN signal to either the

left or right headphone. Do not connect the left and right to the MICIN sig-

nal at the same time—only position 1 or 2 of SW10 should be ON at the

same time. For more information, see “Audio LPBK (Loopback) Switch

(SW10)” on page 2-13. Positions 3 and 4 of SW10 disconnect the line in

from line out loopback.

The EZ-Board is shipped with two 3.5 mm cables, which allow you to run

the example programs provided in the EZ-Board installation directory and

learn about the audio interface.

USB OTG Interface

The ADSP-BF526 processor has a built-in, high-speed USB OTG inter-

face and integrated PHY. The interface connects to a 24 MHz crystal (Y2),

has a surge protector, and can be configured as a host or a device. When in

UART Interface

1-24 ADSP-BF526 EZ-Board Evaluation System Manual

device mode, the USB 5V FET switch (U23) is turned OFF. When in host

mode, the ADSP-BF526 EZ-Board can supply 5V to a device, if desired.

A 5V, 500 mA current can be supplied only when the EZ-Board is

powered from the 5V wall source.

The 5V supplied to an external USB device is controlled by the PG13 flag

pin of the processor. PG13 must be connected on the board to signal

USB_VRSEL through switch SW20. The USB_VRSEL signal controls an Analog

Devices ADM869L p-channel FET, which has an active low ON pin. By

default, USB_VRSEL is held high or a logic ‘1’ via a pull-up resistor and dis-

connects the 5V wall supply to VBUS. To set host mode and provide 5V to

a device, set SW20 positions 2 and 5 OFF and position 6 ON. This disables

push button 2. Note that signal HOSTADDR is shared with push button 2; do

not use the push button when controlling the USB_VRSEL signal.

By default, SW20 positions 2, 5, and 6 are ON, OFF, and OFF (respectively)

and shut off the p-channel FET (U23). For more information, see “GPIO

Enable Switch (SW20)” on page 2-16.

The USB OTG interface has a mini-AB connector (P8); a cable that plugs

into P8 is shipped with the EZ-Board.

Use the example programs in the EZ-Board installation directory to learn

about the ADSP-BF526 processor’s device and host modes. For more

information about the USB interface, refer to the ADSP-BF52x Blackfin

Processor Hardware Reference.

UART Interface

The ADSP-BF526 processor has two built-in universal asynchronous

receiver transmitters (UARTs). UART0—1 share the processor pins with

other peripherals on the EZ-Board.

UART1 has full RS-232 functionality via the Analog Devices 3.3V

ADM1385 line driver and receiver (U21). The ADSP-BF526 processor is

ADSP-BF526 EZ-Board Evaluation System Manual 1-25

Using The ADSP-BF526 EZ-Board

running at the VDDEXT voltage of 1.8V, requiring a voltage translator

(U32) to translate the 1.8V processor signals to the UART 3.3V line

transceiver.

The UART1 interface is disconnected from the ADM1385 transceiver by

ensuring that no jumper is installed on JP3. The ADM1385 transceiver is

shut down by placing a jumper on JP14. The UART1 interface is controlled

by the inverted WAKEUP_OUT signal, WAKEUP_OUT. To set up WAKEUP_OUT,

place a jumper on the JP3 positions 1 and 2. A jumper on positions 1

and 2 of JP3 disables the voltage translator, disconnecting the ADM1385

device from the UART1 interface of the processor. This JP3 setting does not

shut down the transceiver. For more information on power saving capabil-

ities of the EZ-Board, see “UART Enable Jumper (JP3)” on page 2-20 and

“UART SD Jumper (JP14)” on page 2-23.

SW14 allows the flow control signals to be looped back. See “UART Setup

Switch (SW14)” on page 2-15 for more information.

When using UART1, do not install jumper JP2. JP2 is a UART loopback

jumper and should be installed only when running the POST program. If

signals RTS and CTS are needed for flow control, the UART1RTS port pin

PF10 can be configured as a general-purpose I/O (GPIO) pin for RTS. The

HWAIT port pin PG0 can be used for CTS by setting up the pin accordingly;

see “UART Loopback Jumper (JP2)” on page 2-20 and “UART Enable

Jumper (JP3)” on page 2-20 for more information.

UART0 and UART1 are connected to the expansion interface II at connectors

P2 and P4. For more information, see “Expansion Interface II Connectors

(P2 and P4)” on page 2-33.

Example programs are included in the EZ-Board installation directory to

demonstrate UART and RS-232 operations.

On the processor, UART1 shares pins with the PPI interface; conse-

quently, do not use UART1 at the same time as the PPI interface. To

disable the UART line drive, ensure that JP3 has no jumpers on.

RTC Interface

1-26 ADSP-BF526 EZ-Board Evaluation System Manual

For more information on the UART interface, refer to the ADSP-BF52x

Blackfin Processor Hardware Reference.

RTC Interface

The ADSP-BF526 processor has a real-time clock (RTC) and a watchdog

timer. Typically, the RTC interface is used to implement a real-time

watchdog or a life counter of the time elapsed since the last system reset.

The EZ-Board is equipped with a Panasonic CR1632 lithium coin, 3V

battery supplying 125 mAh. The 3V battery and 3.3V supply of the board

connect to the RTC power pin of the processor. When the EZ-Board is

powered, the RTC circuit uses the board power to supply voltage to the

RTC pin. When the EZ-Board is not powered, the RTC circuit uses the

lithium battery to maintain the power to the RTC pin. After removing the

mylar, the battery lasts for about one year with the EZ-Board unpowered.

Example programs are included in the EZ-Board installation directory to

demonstrate the RTC features.

The EZ-Board is shipped with a protective Mylar sheet placed

between the coin battery and positive pin of the battery holder.

Remove the Mylar sheet before using the RTC in the processor.

For more information on the RTC and watchdog timer, refer to the

ADSP-BF52x Blackfin Processor Hardware Reference.

LEDs and Push Buttons

The EZ-Board provides two push buttons and three LEDs for gen-

eral-purpose I/O and two additional push buttons intended for power

down and wake functionality, which also can be used as GPIO flag pins.

The three LEDs, labeled LED0 through LED2, are accessed via the PF8, PG11,

and PG12 pins of the processor (respectively). For information on how to

ADSP-BF526 EZ-Board Evaluation System Manual 1-27

Using The ADSP-BF526 EZ-Board

program the flag pins, refer to the ADSP-BF52x Blackfin Processor Hard-

ware Reference.

LED1 is shared with the HOSTWR# signal, while LED2 is shared with the

HOSTACK signal. The LED0 signal is shared with the PPID8 signal. When

using the PPI 16-bit data interface, LED0 mimics PPID8.

The LED1 and LED2 signals also connect to the expansion interface II (con-

nectors J1, P2, and P4). See “Expansion Interface II Connector (J1)” on

page 2-31 and “Expansion Interface II Connectors (P2 and P4)” on

page 2-33 for more information.

The two general-purpose push buttons are labeled PB1 and PB2. The status

of each individual button can be read through programmable flag inputs

PG0 and PG13. The flag reads ‘1’ when a corresponding switch is being

pressed. When the switch is released, the flag reads ‘0’. A connection

between the push buttons and processor inputs is established through

positions 1 and 2 of the DIP switch, SW20.

Push buttons 1 and 2 of SW20 are used as GPIO signals on the expansion

interface II connectors (J1, P2, P4). To use the PG0 and PG13 port pins as

GPIO signals on the expansion interface II, turn SW20 positions 1 and 2

OFF.

Push button 1 cannot be used when PG0 is set up to control the charge

rate, when charging the battery over USB. To set this up, turn SW20.1 OFF.

See “CHG GPIO Jumper (JP15)” on page 2-23 for more information.

Push button 2 can be connected to the USB_VRSEL signal by setting

switches SW13.2 OFF, SW20.5 OFF, and SW20.6 ON. The USB_VRSEL signal

allows the USB OTG interface to power an external USB device with 5V.

Push button 2 also can be connected to the OTP_FLAG signal, which is nec-

essary to supply 7V for writing to OTP. To set up the EZ-Board to

control the OTP_FLAG signal, set switches SW13.2 OFF, SW20.5 ON, and

SW20.6 OFF. Push button 2 is shared with signal HOSTADDR. See “USB OTG

Interface” on page 1-23 and “GPIO Enable Switch (SW20)” on page 2-16

for more information.

JTAG Interface

1-28 ADSP-BF526 EZ-Board Evaluation System Manual

For a power down interrupt, signal LED2_HOSTACK is wired to SW20.3

(GPIO enable switch), which allows a push button (SW16) to drive an

interrupt to the ADSP-BF526 processor. The PG12 port pin of the proces-

sor should be set up as a GPIO pin. Turning switch SW20.3 ON connects

the push button (SW16) to the processor. By default, SW20.3 is OFF.

A wake interrupt can be set up by turning switch SW20.4 ON and setting the

processor’s flag pin PG15 as the wake interrupt. When push button SW17

(labelled WAKE) is pressed, PG15 receives a low-to-high transition. The PG15

processor pin is shared with the audio codec (U31), Ethernet PHY (U29),

and HOSTCE signal. Do not use these features when using the wake inter-

rupt push button.

An example program is included in the ADSP-BF526 installation direc-

tory to demonstrate functionality of the LEDs and push buttons.

JTAG Interface

The JTAG connector (P1) allows the standalone debug agent to connect a

debug session to the ADSP-BF526 processor. The debug agent operates

only when the external 5V wall adaptor is used (P14). When operating the

EZ-Board from a battery or USB bus power, the debug agent is not

powered.

The standalone debug agent can be removed, and an external emulator

can be attached to the EZ-Board. Be careful not to damage the connectors

when removing the debug agent. The emulator connects to P1 on the back

side of the board. See “CCES Install and Session Startup” on page 1-5 or

“VisualDSP++ Install and Session Startup” on page 1-9 for more

information.

For more information about emulators, contact Analog Devices or go to:

http://www.analog.com/processors/tools/blackfin.

ADSP-BF526 EZ-Board Evaluation System Manual 1-29

Using The ADSP-BF526 EZ-Board

Land Grid Array

The ADSP-BF526 EZ-Board has provisions for probing every port pin

and the EBIU interface of the processor on connectors P5, P6, and P7. The

connector locations are intended for use with a Tektronix DMAX logic

analyzer connector, but can be probed with any oscilloscope or logic ana-

lyzer. Connectors P5 and P6 require the primary retention posts, while

connector P7 can use either the primary or secondary retention post. For

pinout information, refer to“ADSP-BF526 EZ-Board Schematic” on

page B-1.

For more information on the Tektronix DMAX logic analyzer interface,

go to the Tektronix Web site.

Expansion Interface II

The expansion interface II allows an Analog Devices EZ-Extender® or a

custom-design daughter board to be tested across various hardware plat-

forms that have the same expansion interface.

The expansion interface II implemented on the ADSP-BF526 EZ-Board

consists of four connectors, three of which are 0.1 in. shrouded headers

(P2—4) and the last of which is a Samtec QMS series header (J1). The con-

nectors contain a majority of the ADSP-BF526 processor signals. For the

pinout of the connectors, go to “ADSP-BF526 EZ-Board Schematic” on

page B-1. The mechanical dimensions of the expansion connectors can be

obtained by contacting Technical Support.

For more information about daughter boards, visit the Analog Devices

Web site at: http://www.analog.com/processors/tools/blackfin.

Limits to current and interface speed must be taken into consideration

when using the expansion interface II. Current for the expansion interface

II is sourced from the EZ-Board, therefore, the current should be limited

to 1A for 5V and 500 mA for the 1.8V planes. When a battery supplies

Power Architecture

1-30 ADSP-BF526 EZ-Board Evaluation System Manual

power to the EZ-Board, the expansion interface II 5V current is reduced

to 400mA. If more current is required, then a separate power connector

and a regulator must be designed on a daughter card. Additional circuitry

can add extra loading to signals, decreasing their maximum effective

speed.

Analog Devices does not support and is not responsible for the

effects of additional circuitry.

Power Architecture

The ADSP-BF526 EZ-Board has three primary voltage sources, a lithium

ion battery (740 mAh), a 5V wall adaptor, and VBUS supplied over a USB

cable. There is an OR’ing opamp circuit, which allows the board to draw

power from any supply source that has the highest voltage potential. For

example, if the battery is turned on while the board is plugged into the 5V

wall adaptor (P14), the board runs from the 5V wall adaptor.

The VDDEXT, VDDMEM, and SDRAM power are 1.8V and supplied

by an ADP2105 regulator (VR3).

The ADSP-BF526 core voltage, VDDINT, is selected via the I2C inter-

face of the processor. The default is 1.4V. An I2C voltage translator (U39)

interfaces the 1.8V signals SDA and SCL of the processor to the AD5258

digital potentiometer (digipot, U34). The digipot sets the feedback resis-

tors for a low drop-out (LDO) regulator ADP1715 (VR5). See the POST

example located in the ADSP-BF526 directory of CCES or VisualDSP++

to learn how to change the VDDINT voltage. Table 1-3 shows the appro-

priate step settings for the digipot and corresponding voltage values.

ADSP-BF526 EZ-Board Evaluation System Manual 1-31

Using The ADSP-BF526 EZ-Board

The 3.3V power for the board is regulated by an ADP2105 converter

(VR2).

The 1.8V power for the audio ADI SSM2603 audio codec (U31) is regu-

lated by an ADP1205 device (VR1).

The expansion interface II is equipped with three voltage domains: 5V,

3.3V, and 1.8V. The 1.8V and 3.3V are provided directly through the VR2

and VR3 regulators. The 5V is sourced from the wall adaptor when jumper

JP8 is set to positions 1, 2 and 3, 4, and JP9 is ON. The 5V also can be pro-

vided by the on-board ADP1611 converter when using the lithium ion

battery. To set up the ADP1611 converter (VR7), install jumpers on posi-

tions 5, 6 and 7, 8 of JP8 and ensure JP9 is OFF.

To write to the OTP memory inside the processor, turn SW20.2 OFF,

SW20.5 ON, and SW20.6 OFF. Also install a jumper on JP16. Now the PG13

flag pin of the processor, when driven high, provides a precise 7.0V for

OTP writes. Ensure that the PG13 flag pin is driven low when not writing

to the OTP memory: there is a limited amount of time that the OTP cir-

cuit can be supplied 7V. Refer to the ADSP-BF522/523/524/525/526/527

Blackfin Embedded Processor Data Sheet for more information.

Table 1-3. Voltage Values

Step Value Voltage (V)

57 1.10

46 1.15

36 1.20

27 1.25

18 1.30

10 1.35

31.40

Power Architecture

1-32 ADSP-BF526 EZ-Board Evaluation System Manual

Leaving JP16 ON when not writing to the OTP memory can damage

the processor. See the ADSP-BF522/523/524/525/526/527 Blackfin

Embedded Processor Data Sheet.

In USB host mode, if the host must provide 5V to a device, the PG13 flag

pin must be set low to turn on the p-channel mosfet (U23). To connect

PG13 of the processor to the mosfet, set SW20.2 OFF, SW20.5 OFF, and

SW20.6 ON.

The lithium ion battery leads are inserted into the P24 connector. The

SW22 switch connects the battery to the EZ-Board when SW22 is ON. To

change the battery, press in the white tabs and slide out the battery lead.

The EZ-Board is intended to be used at room temperature

(approximately 21oC).

An ADP2291 lithium ion battery charger IC charges the 740 mAh bat-

tery. The charge rate is selected based on a jumper placement and whether

the battery is charging from a wall adaptor or from a USB port. See

Table 1-4 for details.

The lithium battery is monitored by the BQ27500 fuel gauge (U38). All

battery statistics can be read from the fuel gauge, including time to empty,

current voltage, and current consumption rate. SW4 positions 1 and 2 dis-

connect the fuel gauge LED signals. SW4 positions 3 and 4 disconnect the

TWI signals from the processor and fuel gauge. For more information

about SW4, refer to “Gauge Signals Switch (SW4)” on page 2-11. An exam-

ple program in the POST directory of the ADSP-BF526 EZ-Board

installation demonstrates how to use the fuel gauge.

Change jumper and switch settings only when power is OFF.

ADSP-BF526 EZ-Board Evaluation System Manual 1-33

Using The ADSP-BF526 EZ-Board

Power Setup

The EZ-Board is shipped with the default configuration for 5V power

from a wall adaptor or a USB port (see Table 1-5).

Change jumper and switch settings only when power is OFF.

Table 1-4. Charge Rate Selection

Mode WALL USB JP17 P23 Resistance Charge Rate

Full Charge YES NO X1X OPEN 750 mA

Low NO YES OFF OFF 32K 100 mA

Medium NO YES 2 and 3 X 169K 375 mA

Selectable2NO YES 1 and 2 OFF 32/169K 100/375 mA

Shutdown NO YES OFF ON 0 NONE

Control Shut-

down3

NO YES 1 and 2 ON 0/169K 0/375mA

1 Any jumper setting has no affect.

2 Rate is selectable by the processor’s flag: use JP15 to chose the flag pin. Setting the flag high se-

lects 83 mA and setting the flag low selects 375 mA charge rates.

3 JP15 needs to be set to positions 1and 2 (PG0), 3 and 4 (PG11), or 5 and 6 (PG12), selecting

the processor port pin to control the selection. See “CHG GPIO Jumper (JP15)” on page 2-23

for more information.

Table 1-5. 5V Power Settings

Switch/Jumper 5V Setting

JP8 Positions 1 and 2, 3 and 4

JP9 Installed

JP10 Positions 2 and 3

JP15 Uninstalled

P17 Positions 1 and 2

Power Setup

1-34 ADSP-BF526 EZ-Board Evaluation System Manual

To set up the board for battery operation, the settings in Table 1-6 are a

good starting point.

Refer to the individual switch and jumper descriptions for alternate

settings.

Note that complying with USB current limitations requires limit-

ing the charging rate and implementation of power saving features.

P23 OFF

P25 OFF

SW22 OFF

Table 1-6. Battery Power Settings

Switch/Jumper Battery Setting

JP8

(if 5V needed on the expansion interface II)

Positions 5 and 6, 7 and 8

JP9

(if 5V needed on expansion interface II)

Uninstalled

JP10 Positions 1 and 2

JP15 See Table 1-4

P17 See Table 1-4

P23 OFF; see Table 1-4

P25 ON

SW22 ON

Table 1-5. 5V Power Settings (Cont’d)

Switch/Jumper 5V Setting

ADSP-BF526 EZ-Board Evaluation System Manual 1-35

Using The ADSP-BF526 EZ-Board

Power Saving Features

The ADSP-BF526 EZ-Board is designed for low-power application evalu-

ations; use the following settings to enable the board’s power saving

features.

• Jumper-controlled power savings

• The Ethernet PHY (SMSC LAN8700) can be totally pow-

ered down by removing jumpers P21 and P22.

• The UART line drivers can be powered down by placing a

jumper on JP14 and then removing any jumper from JP3.

• The reset and Ethernet LED voltage translator can be dis-

abled by removing any jumper from JP11.

• The GPIO LED’s and OTP flag voltage translator can be

disabled by removing any jumper from JP5.

• Processor-controlled power savings

The VDDINT regulator (VR5) can be shut down with the EXT_WAKE

signal of the processor. EXT_WAKE also controls:

• The OTP flag and LED voltage translator (U3) via JP5

• The Ethernet LED and reset voltage translator (U4) via JP11

• The UART1 voltage translator (U32) via JP3

Refer to the ADSP-BF52x Blackfin Processor Hardware Reference for

more information about EXT_WAKE; refer to “Jumpers” on page 2-19

for more information about the jumpers.

Power Measurements

1-36 ADSP-BF526 EZ-Board Evaluation System Manual

• Low-power mode capable ICs of the EZ-Board

• ADI SSM2603 audio codec (U31)

• Micron MT48H32M16-75 SDRAM memory (U14)

• Numonyx M58WR032KB parallel flash (U16)

• SST 25WF040 SPI flash memory (U6)

• Numonyx NAND02 flash memory (U15)

Some of the low-power modes are entered by inactivity on-chip select

lines. Consult the product data sheets for details.

Power Measurements

Several locations are provided for measuring the current draw from vari-

ous power planes. Precision 0.1 ohm shunt resistors are available on the

VDDINT, VDDEXT, VDDMEM, and SDRAM voltage domains. For

current draw measuments, the associated jumper (P13, P11, P12, or P19)

should be removed. Once the jumper is removed, the voltage across the

resistor can be measured using an oscilloscope. Once voltage is measured,

current can be calculated by dividing the voltage by 0.1. For the highest

accuracy, a differential probe should be used for measuring voltage across

the resistor.

For more information, see “VDDINT Power Jumper (P13)” on

page 2-25, “VDDEXT Power Jumper (P11)” on page 2-25, and “VDD-

MEM Power Jumper (P12)” on page 2-25.

ADSP-BF526 EZ-Board Evaluation System Manual 1-37

Using The ADSP-BF526 EZ-Board

Power-On-Self Test

The power-on-self-test program (POST) tests all EZ-Board peripherals

and validates functionality as well as connectivity to the processor. Once

assembled, each EZ-Board is fully tested for an extended period of time

with a POST. All EZ-Boards are shipped with the POST preloaded into

one of its on-board flash memories. The POST is executed by resetting the

board and pressing the proper push button(s). The POST also can be used

for reference for a custom software design or hardware troubleshooting.

Note that the source code for the POST program is included in the instal-

lation directory along with the readme file, which describes how the board

is configured to run POST.

The POST program is only available when using VisualDSP++.

Board Design Database

A .zip file containing all of the electronic information required for the

design, layout, fabrication and assembly of the product is available for

download from the Analog Devices board design database at:

http://www.analog.com/board-design-database.

Example Programs

Example programs are provided with the ADSP-BF526 EZ-KIT Lite to

demonstrate various capabilities of the product. The programs are

included in the product installation kit and can be found in the Examples

folder of the installation. Refer to a readme file provided with each exam-

ple for more information.

CCES users are encouraged to use the example browser to find examples

included with the EZ-KIT Lite Board Support Package.

Example Programs

1-38 ADSP-BF526 EZ-Board Evaluation System Manual

ADSP-BF526 EZ-Board Evaluation System Manual 2-1

2 ADSP-BF526 EZ-BOARD

HARDWARE REFERENCE

This chapter describes the hardware design of the ADSP-BF526

EZ-Board.

The following topics are covered.

•“System Architecture” on page 2-2

Describes the ADSP-BF526 EZ-Board configuration and explains

how the board components interface with the processor.

•“Programmable Flags” on page 2-3

Shows the locations and describes the programming flags (PFs).

•“Push Button and Switch Settings” on page 2-9

Shows the locations and describes the push buttons and switches.

•“Jumpers” on page 2-19

Shows the locations and describes the configuration jumpers.

•“LEDs” on page 2-27

Shows the locations and describes the LEDs.

•“Connectors” on page 2-30

Shows the locations and provides part numbers for the on-board

connectors. In addition, the manufacturer and part number infor-

mation is provided for the mating parts.

System Architecture

2-2 ADSP-BF526 EZ-Board Evaluation System Manual

System Architecture

This section describes the processor’s configuration on the EZ-Board

(Figure 2-1).

This EZ-Board is designed to demonstrate the capabilities of the

ADSP-BF526 Blackfin processors. The processor has an I/O voltage of

1.8V. The core voltage of the processor is controlled by an Analog Devices

ADP1715 low dropout regulator (LDO) and an Analog Devices AD5258

Figure 2-1. System Architecture

ADSP-BF525

DSP

400 MHz

12mmX12mm/0.5 pitch

LEDs (3)

1.8 Volts

EBIU

JTAG

Port

32.768 KHz

Crystal

3.3 volt

RTC

SPI

64 MB

SDRAM

(32M x 16)

1.8 Volts

High

Density

EBIU

Expansion

Interface

4 MB

Flash

(2M x 16 )

1.8 Volts

25 MHz

Crystal

1.8 Volts

UARTs

PBs (2)

1.8 Volts

RS-232

Female

RS-232

TX/RX

3.3 Volts

SPORT PPI

MAC USB

Ethernet Phy RMII

1.8 Volts (MAC to Phy)

3.3 Volts (Phy to Mag)

RJ11

TWI

IDC

Conn

IDC

Conn

IDC

Conn

IDC

Conn

USB OTG Conn

3.3 Volts

5 Volts source when

in Host Mode

IDC

Conn

Rotary

1.8 Volts

2 Gb

NAND Flash

(512M x 8 )

1.8 Volts

4 Mb

SPI Boot

Flash

1.8 Volts

HOST

PORT

IDC

Conn

NAND

24 MHz

Crystal

3.3 Volts

+3.0

LI-ION

Battery

CLKIN

UP/DN

CNTR

12 MHz

Crystal

1.8 Volts

Power Regulation

1.8 Volt, 3.3 Volt,

2.5 Volt, 5.0 Volt

Li Battery

Charge Circuit

GPIO

Audio

Codec

1.8 Volts

Mic/

Line

Head/

Line

Out

IDC

Conn

Fuel

Gauge

ADSP-BF526 EZ-Board Evaluation System Manual 2-3

ADSP-BF526 EZ-Board Hardware Reference

digipot, which is configurable over the 2-wire interface (TWI) signals.

Refer to the power-on-self test (POST) example in the ADSP-BF526

installation directory for information on how to set up the TWI interface.

The core voltage and clock rate can be set on the fly by the processor. The

input clock is 25 MHz. A 32.768 kHz crystal supplies the real-time clock

(RTC) inputs of the processor. The default boot mode for the processor is

external parallel flash boot. See “Boot Mode Select Switch (SW1)” on

page 2-10 for information on how to change the default boot mode.

Programmable Flags

The processor has 50 general-purpose input/output (GPIO) signals spread

across four ports (PF, PG, PH, and PJ). The pins are multi-functional and

depend on the ADSP-BF526 processor setup. The following tables show

how the programmable flag pins are used on the EZ-Board.

•PF programmable flag pins in Table 2-1

•PG programmable flag pins in Table 2-2

•PH programmable flag pins in Table 2-3

•PJ programmable flag pins in Table 2-4

Table 2-1. PF Port Programmable Flag Connections

Processor Pin Other Processor Function EZ-Board Function

PF0 PPID0/DR0PRI/ND_D0A Default: PPID0 on P3.18 via RN1.

Land grid array via P7.A.

PF1 PPID1/RFS0/ND_D1A Default: PPID1 on P3.17 via RN1.

Land grid array via P7.A2.

PF2 PPID2/RSCLK0/ND_D2 Default: PPID2 on P3.20 via RN1.

Land grid array via P7.A4.

PF3 PPID3/DT0PRI/ND_D3A Default: PPID3 on P3.19 via RN1.

Land grid array via P7.A5.

Programmable Flags

2-4 ADSP-BF526 EZ-Board Evaluation System Manual

PF4 PPID4/TFS0/ND_D4A/

TACLK0

Default: PPID4 on P3.22 via RN1.

Land grid array via P7.A10.

PF5 PPID5/TSCLK0/ND_D5A/

TACLK1

Default: PPID5 on P3.21 via RN1.

Land grid array via P7.A11.

PF6 PPID6/DT0SEC/ND_D6A/

TACI0

Default: PPID6 on P3.24 via RN1.

Land grid array via P7.A13.

PF7 PPID7/DR0SEC/ND_D7A/

TACI1

Default: PPID7 on P3.23 via RN1.

Land grid array via P7.A14.

PF8 PPID8/DR1PRI Default: LED0 via RN2.

Expansion interface II P3.26 (PPID8), P4.14 via

SW21.8, land grid array via P7.A16.

PF9 PPID9/RSCLK1/SPISEL6# Default: PPID9 via RN2.

Expansion interface II (P3.25, P4.18) via SW21.7, land

grid array via P7.A17.

PF10 PPID10/PRFS1/SPISEL7# Default: UART1RTS (U21) via U32, SW14.3 and RN2.

Expansion interface II (P3.28, P4.20) via SW21.6, land

grid array via P7.A17.

PF11 PPID11/TFS1/CZM Default: CZM rotary (SW5) via SW13.3 and RN2.

Expansion interface II (P3.27, P4.19) via SW21.5, land

grid array via P7.A20.

PF12 PPID12/DT1PRI/

SPISEL2#/CDG

Default: CDG rotary (SW5) via SW13.2 and RN2.

Expansion interface II (P3.30, P4.13) via SW21.4, land

grid array via P7.A22.

PF13 PPID13/TSCLK1/

SPISEL3#/CUD

Default: CUD rotary (SW5) via SW13.1 and RN2.

Expansion interface II (P3.29, P4.17) via SW21.3, land

grid array via P7.A23.

PF14 PPID14/DT1SEC/UART1TX Default: UAR1TX (U21) via U32 and RN2.

Expansion interface II (P3.32, P4.15) via SW21.2, land

grid array via P7.A25.

PF15 PPID15/DR1SEC/

UART1RX/TACI3

Default: UAR1RX (U21) via U32, SW14.2 and RN2.

Expansion interface II (P3.31, P4.16 via SW21.1,

P4.32) via SW21.1, land grid array via P7.A26.

Table 2-1. PF Port Programmable Flag Connections (Cont’d)

Processor Pin Other Processor Function EZ-Board Function

ADSP-BF526 EZ-Board Evaluation System Manual 2-5

ADSP-BF526 EZ-Board Hardware Reference

Table 2-2. PG Port Programmable Flag Connections

Processor Pin Other Processor Function EZ-Board Function

PG0 HWAIT Default: PB1 via SW21.1 and RN5.

UART1 CTS (HWAIT) via U32, SW14.1, host connector

P9.12, CHG GPIO JP15.1, expansion interface II

(P2.37, P4.37, J1.52), land grid array via P7.B27.

PG1 SPISS#/SPISEL1# Default: SPI flash (U6) CS via SW11.4 and RN3.

Expansion interface II (P2.21, P4.21, P4.26, P2.26),

land grid array via P7.B26.

PG2 SPISCK Default: SPI flash (U6).

Expansion interface II (P2.24, P4.24), land grid array

via P7.B9.

PG3 SPIMISO/DR0SECA Default: SPI flash (U6) via RN3.

Expansion interface II (P2.16, P2.27, P4.27), land

grid array via P7.B23.

PG4 SPIMOSI/DT0SECA Default: SPI flash (U6).

Expansion interface II (P2.15, P2.25, P4.25), land

grid array via P7.B24.

PG5 TMR1/PPIFS2/TFS0A Default: PPIFS2 P3.14.

Land grid array via P7.B17.

PG6 DT0PRIA/TMR2/PPIFS3 Default: DT0PRIA codec (U31) via SW7.2.

Expansion interface II (P2.13, P3.15), land grid array

via P7.B18.

PG7 TMR3/DR0PRIA/UART0TX Default: DR0PRIA codec (U31) via SW7.3.

Expansion interface II (P2.14, P2.31, P3.36), land

grid array via P7.B14.

PG8 TMR4/RFS0A/UART0RX/

TACI4

Default: RFS0A codec (U31) via SW7.4.

Expansion interface II (P3.35, P2.20, P2.32), land

grid array via P7.B15.

PG9 TMR5/RSCLK0A/TACI5 Default: RSCLK0A codec (U31) via SW2.2.

Expansion interface II (P2.18, P3.38), land grid array

via P7.B11.

PG10 TMR6/TSCLK0A/TACI6 Default: TSCLK0A codec (U31) via SW2.1.

Expansion interface II P2.17, land grid array via

P7.B12.

Programmable Flags

2-6 ADSP-BF526 EZ-Board Evaluation System Manual

PG11 TMR7/HOST_WR# Default: LED1 via U3 and RN5.

CHG GPIO JP15.3, host connector P9.4, expansion

interface II (J1.51, P2.28, P2.38, P4.28, P4.38), land

grid array via P7.B6.

PG12 DMAR1/UART1TXA/

HOST_ACK

Default: LED2 via U3 and RN5.

Power down PB via SW20.3, CHG GPIO JP15.5, host

connector P9.10, expansion interface II (J1.54,

P2.39, P4.39), land grid array via P7.B8.

PG13 DMAR0/UART1RXA/

HOST_ADDR/TACI2

Default: PB2 via SW21.2 and RN5.

OTP_FLAG_1P8V via SW20.5, USB_VRSEL via SW20.6,

host connector P9.8, expansion interface II (J1.53,

P2.40, P4.40), land grid array via P7.B5.

PG14 TSCLK0A/MDC/HOST_RD# Default: host connector P9.2.

MDC PHY (U29) via SW12.2, land grid array via P7.B2.

PG15 TFS0A/MIIPHYINT#/

RMIIMDINT#/HOST_CE#

Default: TFS0A codec (U31) via SW7.1 and RN5

RMIIMDINT# PHY (U29), wake via SW20.4, host con-

nector P9.6, expansion interface II P2.19, land grid

array via P7.B3.

Table 2-3. PH Port Programmable Flag Connections

Processor Pin Other Processor Function EZ-Board Function

PH0 ND_D0/MIICRS/

RMIICRSDV/HOST_D0

Default: NAND data 0 (U15) via RN4.

RMII carrier sense/receive data valid (U29.36), host

connector data 0 (P9.31), land grid array via P6.B3.

PH1 ND_D1/ERXER/HOST_D1 Default: NAND data 1 (U15) via RN4.

PHY receive error (U29.21), host connector data 1

(P9.29), land grid array via P6.B2

PH2 ND_D2/MDIO/HOST_D2 Default: NAND data 2 (U15) via RN4.

PHY management bus MDIO U29 via SW12.1, host con-

nector data 2 (P9.27), land grid array via P6.B6.

PH3 ND_D3/ETXEN/HOST_D3 Default: NAND data 3 (U15) via RN4.

PHY transmit enable (U29.6), host connector data 3

(P9.25), land grid array via P6.B5.

Table 2-2. PG Port Programmable Flag Connections (Cont’d)

Processor Pin Other Processor Function EZ-Board Function

ADSP-BF526 EZ-Board Evaluation System Manual 2-7

ADSP-BF526 EZ-Board Hardware Reference

PH4 ND_D4/MIITXCLK/

RMIIREF_CLK/HOST_D4

Default: NAND data 4 (U15) via RN4.

PHY RMII ref clock U29 via SW12.3 and U20, host con-

nector data 4 (P9.23), land grid array via P6.B9.

PH5 ND_D5/ETXD0/HOST_D5 Default: NAND data 5 (U15) via RN4.

PHY RMII transmit data 0 (U29.23), host connector

data 5 (P9.21), land grid array via P6.B8.

PH6 ND_D6/ERXD0/HOST_D6 Default: NAND data 6 (U15) via RN4.

PHY RMII receive data 0 (U29.18), PHY mode via

SW11.3, host connector data 6 (P9.19), land grid array

via P6.B11.

PH7 ND_D7/ETXD1/HOST_D7 Default: NAND data 7 (U15) via RN4.

PHY RMII transmit data 1 (U29.24), host connector

data 7 (P9.17), land grid array via P6.B12.

PH8 SPISEL4#/ERXD1/

HOST_D8/TACLK2

Default: PHY RMII receive data 1 (U29.17) via RN5.

PHY mode via SW11.2, host connector data 8 (P9.15),

expansion interface II (P2.22, P4.22), land grid array

via P6.B15.

PH9 SPISEL5#/ETXD2/

HOST_D9/TACLK3

Default: host connector P9.13, expansion interface II

P2.23, P4.23, land grid array via P6.B27.

PH10 ND_CE#_ERXD2/HOST_D10 Default: NAND chip (U15) enable via SW13.4

Host connector data 10 (P9.11), land grid array via

P6.B26.

PH11 ND_WE/ETXD3/HOST_D11 Default: NAND write enable (U15).

Host connector data 11 (P9.9), land grid array via

P6.B24.

PH12 ND_RE/ERXD3/HOST_D12 Default: NAND output enable (U15).

Host connector data 12 (P9.7), land grid array via

P6.B21.

PH13 ND_BUSY/ERXCLK/

HOST_D13

Default: NAND busy (U15).

Host connector data 13 (P9.5), land grid array via

P6.B23.

Table 2-3. PH Port Programmable Flag Connections (Cont’d)

Processor Pin Other Processor Function EZ-Board Function

Programmable Flags

2-8 ADSP-BF526 EZ-Board Evaluation System Manual

PH14 ND_CLE/ERXDV/HOST_D14 Default: NAND command latch enable (U15).

Host connector data 14 (P9.3), land grid array via

P6.B18.

PH15 ND_ALE/COL/HOST_D15 Default: NAND address latch enable (U15).

Host connector data 15 (P9.1), land grid array via

P6.B17.

Table 2-4. PJ Port Programmable Flag Connections

Processor Pin Other Processor Function EZ-Board Function

PJ0 PPIFS1/TMR0 Default: PPIFS1 P3.13.

Land grid array P7.B21.

PJ1 PPICLK/TMRCLK Default: PPICLK P3.16.

Land grid array P7.A7.

PJ2 SCL Default: fuel gauge U38 via switch SW4.3, digipot U34

via U39 via RN5.

Codec via SW2.4, expansion interface II (P2.29, P3.63,

P4.29).

PJ3 SDA Default: fuel gauge U38 via switch SW4.4, digipot U34

via U39 via RN5.

Codec via SW2.2, expansion interface II (P2.30, P3.61,

P4.30).

Table 2-3. PH Port Programmable Flag Connections (Cont’d)

Processor Pin Other Processor Function EZ-Board Function

ADSP-BF526 EZ-Board Evaluation System Manual 2-9

ADSP-BF526 EZ-Board Hardware Reference

Push Button and Switch Settings

This section describes operation of the push buttons and switches. The

push button and switch locations are shown in Figure 2-2.

Figure 2-2. Push Button and Switch Locations

Push Button and Switch Settings

2-10 ADSP-BF526 EZ-Board Evaluation System Manual

Boot Mode Select Switch (SW1)

The rotary switch (SW1) determines the boot mode of the processor.

Table 2-5 shows the available boot mode settings. By default, the

ADSP-BF526 processor boots from the on-board parallel flash memory.

The selected position of SW1 is marked by the notch down the

entire rotating portion of the switch, not the small arrow.

Table 2-5. Boot Mode Select Switch (SW1)

SW1 Position Processor Boot Mode

0Reserved

1 Boot from 8-bit external flash memory (default)

2 Boot from 16-bit asynchronous FIFO

3 Boot from serial SPI memory

4 Boot from SPI host device

5 Boot from serial TWI memory

6 Boot from TWI host

7 Boot from UART0 host

8 Boot from UART1 host

9Reserved

A Boot from SDRAM

B Boot from 8-bit NAND flash PORTF

C Boot from 8-bit NAND flash PORTH

DReserved

E Boot from 16-bit host DMA

F Boot from 8-bit host DMA

ADSP-BF526 EZ-Board Evaluation System Manual 2-11

ADSP-BF526 EZ-Board Hardware Reference

SPORT0A ENBL Switches/I2C ENBL (SW2 and SW7)

The SPORT0A enable switches (SW2 and SW7) connect the SPORT0A and TWI

interfaces of the processor to the audio codec, SSM2603 (U31). When the

SPORT0A interface is used on the expansion interface II, turn SW2 and SW7

positions 1 and 2 all OFF. To disconnect TWI to the audio codec turn SW2

positions 3 and 4 OFF. By default, SW2 and SW7 are set to all ON.

Gauge Signals Switch (SW4)

The gauge signals switch (SW4) positions 1 and 2 disconnect the fuel gauge

status LEDs from the BQ27500 fuel gauge device. Positions 3 and 4 dis-

connect the I2C signals from the fuel gauge. If the I2C bus hangs when

performing fast bus operations, it may be necessary to turn positions 3 and

4 OFF. By default, SW4 is set to all ON.

Rotary Encoder with Momentary Switch (SW5)

The rotary encoder (SW5) can be turned clockwise for an up count or

counter-clockwise for a down count. The encoder also features a momen-

tary switch, activated by pushing the switch towards the processor, which

resets the counter to zero. The rotary encoder is a two-bit quadrature (gray

code) encoder. Refer to the Rotary Counter section of the ADSP-BF52x

Blackfin Processor Hardware Reference for more information.

The rotary encoder is disconnected from the processor by setting SW13

positions 1, 2 and 3 to OFF. See “Rotary/NAND Enable Switch (SW13)”

on page 2-14 for more information.

Push Button and Switch Settings

2-12 ADSP-BF526 EZ-Board Evaluation System Manual

Flash Enable Switch (SW6)

The flash enable switch (SW6) disconnects the AMSx signals from parallel

flash memory (U16), allowing other devices to utilize the signals via the

expansion interface II. For each switch listed in Table 2-6 that is turned

OFF, the size of available flash memory is reduced by 1 MB.

MIC Gain Switch (SW9)

The microphone gain switch (SW9) sets the gain of the MIC signal, which is

connected to the top 3.5 mm jack (J4). The gain can be set to 14 dB,

0 dB, or –6 dB by turning ON position 1, 2, or 3 of SW9 (see Table 2-7).

When the corresponding position for the desired gain is ON, the remaining

positions must be OFF. Refer to “Audio Interface” on page 1-22 for more

information about the audio codec.

Table 2-6. Flash Enable Switch (SW6)

SW6 Switch Position (Default) Processor Signal

1 (ON)AMS0

2 (ON)AMS1

3 (ON)AMS2

4 (ON)AMS3

Table 2-7. MIC Gain Switch (SW9)

Gain SW9 Switch Settings

5 (14 dB) ON, OFF, OFF, OFF

1 (0 dB) OFF, ON, OFF, OFF

0.5 (–6 dB) OFF, OFF, ON, OFF (default)

Unused OFF, OFF, OFF, OFF

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ADSP-BF526 EZ-Board Hardware Reference

Audio LPBK (Loopback) Switch (SW10)

The SW10 switch places the EZ-Board in a loopback to test the board for

signal/circuit continuity and functionality. SW10 positions 1 and 2 connect

the MICIN signal to the headphone’s left and right outputs for audio

loopback. Do not turn SW10 positions 1 and 2 ON at the same time. See

“Power-On-Self Test” on page 1-37 for more information.

SW10 positions 3 and 4 connects the line in to line out loopback. By

default, SW10 is set to OFF, OFF, ON, ON.

ETH Mode/Flash CS Switch (SW11)

The Ethernet mode flash CS switch (SW11) sets the bootstrapping option

for the LAN8700 RMII PHY chip (U29). The mode settings for the PHY

utilize internal chip pull-ups. Setting a position 1–3 of SW11 ON connects a

pull-down resistor. Table 2-8 shows the default as well as the alternate

switch settings.

SW11 position 4 disconnects the SPISEL1 pin from the SPI flash chip (U6).

Setting SW11 position 4 OFF is useful when using SPISEL1 on the expansion

interface II. By default, SW11 is set to OFF, OFF, OFF, ON.

Table 2-8. ETH Mode Flash CS Switch (SW11 Positions 1–3)

MODE[2:0] Setting Mode Definitions

OFF, OFF, OFF All capable, auto negotiation (default)

OFF, OFF, ON Power down mode

OFF, ON, OFF Repeater mode, auto negotiation

OFF, ON, ON 100Base-TX half duplex advertised, auto negotiation

ON, OFF, OFF 100Base-TX full duplex

ON, OFF, ON 100Base-TX half duplex

ON, ON, OFF 10Base-T full duplex

ON, ON, ON 10Base-T half duplex

Push Button and Switch Settings

2-14 ADSP-BF526 EZ-Board Evaluation System Manual

ETH Enable Switch (SW12)

The Ethernet enable switch (SW12) enables the Ethernet interface. The

Ethernet and NAND flash share the same lines and cannot operate at the

same time. By default, the SW12 settings are OFF, OFF, ON, OFF (see

Table 2-9). Ethernet is enabled by setting the switch to ON, ON, OFF, ON.

SW12 positions 1and 2 connect the PHY management bus (MDIO and MDC).

SW12 position 3 ON enables the 50 MHz RMII clock. SW12 position 4 holds

the PHY in reset (set to OFF) or connects the PHY reset to the EZ-Board

reset (set to ON).

Rotary/NAND Enable Switch (SW13)

The rotary/NAND enable switch (SW13) disconnects the rotary encoder

signals from the GPIO pins of the processor. When SW13 is OFF, its associ-

ated GPIO signals can be used on the expansion interface II (see

Table 2-10). Position 4 of SW13 disconnects the chip enable for the

NAND flash memory (U4).

Table 2-9. ETH Enable Switch (SW12)

SW12 Switch Setting Ethernet Mode

OFF, OFF, ON, OFF OFF (default)

ON, ON, OFF, ON ON

Table 2-10. Rotary NAND Enable Switch (SW13)

SW13 Position (Default) From To

1 (ON)Encoder (SW5)Processor (U1, PF13)

2 (ON)Encoder (SW5)Processor (U1, PF12)

3 (ON)Encoder (SW5)Processor (U1, PF11)

4 (ON)Processor (U1, PH10) NAND (U15)

ADSP-BF526 EZ-Board Evaluation System Manual 2-15

ADSP-BF526 EZ-Board Hardware Reference

UART Setup Switch (SW14)

The UART setup switch (SW14) configures the UART1 signals from the

GPIO pins of the processor. By default, SW14 is OFF, ON, OFF, ON. Flow con-

trol is not implemented in the POST program, so SW14 positions 1 and 3

should be OFF and position 4 should be ON for loopback flow control.

Refer to the ADM1385 data sheet on the Analog Devices Web Site for

more information about the UART interface.

Programmable Flag Push Buttons (SW15 and SW19)

Two momentary push buttons (SW15 and SW19) are provided for gen-

eral-purpose user input. The buttons connect to the PG0 and PG13 GPIO

pins of the processor. The push buttons are active high and, when pressed,

send a high (1) to the processor. The GPIO enable switch (SW20) discon-

nects the push buttons from the corresponding push button signals. Refer

to “GPIO Enable Switch (SW20)” on page 2-16 for more information.

Power-Down and Wake Push Buttons (SW16–17)

Two momentary push buttons (SW16—17) are provided for optional power

feature inputs. The buttons connect to the PG12 and PG15 GPIO pins of

the processor. The push buttons are active high and, when pressed, send a

high (1) to the processor. The GPIO enable switch (SW20) disconnects the

push buttons from the corresponding push buttons signals. Refer to

“GPIO Enable Switch (SW20)” on page 2-16 for more information.

The power-down push button (SW16) is intended as an GPIO input to the

processor and can be configured to put the processor in any one of the

sleep modes.

The wake push button (SW17) is connected to the flag pin (PG15), which

can be configured as the dedicated WAKE input signal from hibernation.

Refer to the ADSP-BF52x Blackfin Processor Hardware Reference Manual

for more information.

Push Button and Switch Settings

2-16 ADSP-BF526 EZ-Board Evaluation System Manual

Reset Push Button (SW18)

The reset push button (SW18) resets the following ICs.

• Processor (U1), parallel flash (U16), PHY (U29) if SW12 position 4 is

ON, SPI flash (U6)

The reset push button does not reset the following ICs.

•SDRAM (U14), NAND flash (U15)

• Audio codec (U31), UART1 (U21), voltage translators (U3, U4, U32,

U39) schmitt trigger hex inverter (U5)

• Fuel gauge (U38), digipot (U34), battery charger (U37), power (VR2—

3, VR5, VR9, VR10, U23)

The reset push button does not reset the standalone debug agent once the

debug agent is connected to a personal computer (PC). After communica-

tion between the debug agent and PC is initialized, pushing a reset button

does not reset the USB chip on the debug agent. The only way to reset the

USB chip on the debug agent is to power down the EZ-Board.

GPIO Enable Switch (SW20)

The general-purpose input/output switch (SW20) disconnects the associ-

ated push buttons and LED circuits from the GPIO pins of the processor

and allows the signals to be used for other purposes. Depending on the

switch configuration, the signals can be used as push buttons,

one-time-programmable memory (OTP) flag for writing, or on-the-go

(OTG) host mode 5V (see Table 2-11).

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ADSP-BF526 EZ-Board Hardware Reference

The OTP memory writes require a precise 7V supply, which is turned on

by setting high the OTP_FLAG_1P8V signal. The OTP flag is connected to

the processor by setting positions 2 and 6 of SW20 to OFF and position 5 ON.

These settings connect the PG13 flag pin of the processor to the shutdown

pin of the precise 7V circuit VR9.

The USB_VRSEL provides 5V to a device connected over the USB OTG

interface when running in host mode. A connection to the USB_VRSEL sig-

nal is set by the SW13 switch (positions 2 and 5 OFF and position 6 ON).

Then the PG13 programmable flag pin of the processor can be used to con-

trol the p-channel mosfet (U23). Refer to “USB OTG Interface” on

page 1-23 for more information.

Table 2-11. GPIO Enable Switch (SW20)

SW20 Position

(Default)

From To Function

1 (ON) Push button 1

(SW19)

Processor

(U1, PG0)

ON (PB1)

OFF (UART1 CTS U21, host connector P9.12,

expansion interface II P2.37, P4.37, J1.52)

2 (ON) Push button 2

(SW15)

Processor

(U1, PG13)

ON (PB2)

OFF (host connector P9.8, OTP flag for writes

SW20.8, OTG voltage select SW13.7, expansion

interface II P2.40,P4.40, J1.53)

3 (OFF)Power down push

button

(SW16)

Processor

(U1, PG12)

OFF (LED2 not driven by the power down push

button)

ON (SW16 drives PG12)

4 (OFF)Wake push but-

ton (SW17)

Processor

(U1, PG15)

ON (connects the wake push button SW17 to

PG15)

5 (OFF)OTP_FLAG_1P8V

(U3)

Processor

(U1, PG13)

ON (PG13 controls the OTP flag for OTP

writes)

Requires SW20.2 OFF, SW20.6 OFF, and JP16

installed

6 (OFF)USB_VRSEL

(U23)

Processor

(U1, PG13)

ON (PG13 controls USB_VRSEL PG13 for OTG

host power)

Requires SW20.2 OFF and SW20.5 OFF

Push Button and Switch Settings

2-18 ADSP-BF526 EZ-Board Evaluation System Manual

A power-down push button can be connected to the processor’s flag pin

PG12 if position 3 of SW20 is ON.

Turning SW20 position 2 ON allows the SW16 push button to control

LED2.

A wake signal can be driven to the processor’s dedicated hibernate wake

flag PG15 by turning SW20 position 4 ON. This setting can conflict with the

SPORT0A, Ethernet, and host interfaces. See “Power-Down and Wake Push

Buttons (SW16–17)” on page 2-15 for more information.

The PG0 flag pin of the processor can be used as an GPIO or other func-

tions if SW20 position 1 is turned OFF. By default, the SW20 is set to ON, ON,

OFF, OFF, OFF, OFF.

SPORT1 Enable (SW21)

The SPORT1 enable switch (SW21) disconnects the following processor

interfaces from the P4 connector of the EZ-Board expansion interface II:

UART1RX, UART1TX, CUD, CDG, CZM, UART1RTS, PPID9, and LED0. To enable the

SPORT1 interface at P4, turn SW21 all ON. By default, SW21 is all OFF.

Battery Switch (SW22)

The battery switch (SW22) connects and disconnects the ADP2291 lithium

ion battery from the EZ-board power. When SW22 is ON, the board can run

and charge from the battery attached to the back of the board. Jumper P25

should be removed when SW22 is OFF. SW22 is OFF by default.

ADSP-BF526 EZ-Board Evaluation System Manual 2-19

ADSP-BF526 EZ-Board Hardware Reference

Jumpers

This section describes functionality of the configuration jumpers.

Figure 2-2 shows the configuration jumper locations.

Figure 2-3. Configuration Jumper Locations

Jumpers

2-20 ADSP-BF526 EZ-Board Evaluation System Manual

UART Loopback Jumper (JP2)

The UART loopback jumper (JP2) is used to place the UART1 port of the pro-

cessor in a loopback condition. The jumper connects the UART1_TX line of

the processor to the UART1_RX signal of the processor. The jumper is

required when the POST program is run to test the serial port interface.

By default, JP2 is uninstalled.

UART Enable Jumper (JP3)

The UART enable jumper (JP3) is a three-pin jumper that controls the

output enable (OE) of the UART1 voltage translator. When JP3 is unin-

stalled, the voltage translator outputs are tri-stated. When a jumper is

placed on positions 1 and 2 of JP3, the inverted copy of the WAKEUP_OUT

signal (WAKEUP_OUT) controls the output enable of the voltage translator.

When the EZ-board boots, the processor enables the voltage translator;

when the processor is in hibernate, the translator outputs are tri-stated. A

jumper on positions 2 and 3 of JP3 allows the translator to drive the out-

puts. See “Power Architecture” on page 1-30 for more information on

power saving capabilities of the ADSP-BF526 EZ-Board. By default, JP3

is installed on positions 1 and 2.

LED Enable Jumper (JP5)

The LED enable jumper (JP5) enables the power saving feature of the

board through control of the voltage translator’s output enable pins.

When no jumper is installed on JP5, the voltage translator (U3), which

controls the GPIO LEDs, and the OTP_FLAG signals are tri-stated. Placing a

jumper on positions 1 and 2 of JP5 allows the inverted WAKEUP_OUT signal

(WAKEUP_OUT) to control the output enable of the translator. When the

processor is not in hibernate, the translator is enabled; when the processor

is in hibernate, the translator outputs are tri-stated. Placing a jumper on

positions 2 and 3 of JP5 enables the translator outputs. See “Power Archi-

tecture” on page 1-30 and “Power Saving Features” on page 1-35 for more

ADSP-BF526 EZ-Board Evaluation System Manual 2-21

ADSP-BF526 EZ-Board Hardware Reference

information about the power saving capabilities of the EZ-Board. By

default, JP5 is installed on positions 1 and 2.

MIC Select Jumper (JP6)

The microphone select jumper (JP6) connects the MICBIAS signal to the

MICIN signal (JP6 on positions 1and 2) or connects the MICBIAS signal to

the 3.5 mm connector J4 (JP6 on positions 2 and 3). By default, JP6 is

installed on positions 2 and 3.

CFG WP Jumper (JP7)

The CFG WP jumper (JP7) is used to write-protect block 70 of the paral-

lel flash chip. Block 70 contains 64 KB of configuration data at address

range 0x203 F0000—0x203 FFFFF. When a jumper is installed on JP7, and

the parallel flash driver from Analog Devices is used, block 70 is

read-only. By default, JP7 is installed.

EXP 5V Select Jumper (JP8)

The EXP 5V select jumper (JP8) selects the 5V voltage source for the

expansion interface II connectors J1, P2, P3, and P4. JP8 must have either

no jumpers or two jumpers installed, never one or three jumpers. When

jumpers are placed on positions 1, 2 and 3, 4 of JP8, the 5V power rail for

the expansion interface II is sourced from the wall adaptor. When jumpers

are placed on positions 5, 6 and 7, 8 of JP8, 5V is sourced by the boost

regulator VR7. By default, JP8 is installed on positions 1, 2 and 3, 4.

VR7 Enable Jumper (JP9)

The VR7 enable jumper (JP9) controls the shut-down pin of the ADP1611

boost regulator, which is a 5V source for the expansion interface II. When

installed, JP9 disables VR7. Install JP9 when using positions 1,2 and 3,4 of

JP8 because the 5V source for the expansion interface II is the wall

Jumpers

2-22 ADSP-BF526 EZ-Board Evaluation System Manual

adaptor. Removing JP9 allows VR7 to drive 5V to the expansion

interface II; the battery is providing the input to VR7. This setting drains

the battery at a much faster rate. See “EXP 5V Select Jumper (JP8)” on

page 2-21 for more information. By default, JP9 is installed (VR7 is

disabled).

SENSE2 Select Jumper (JP10)

The SENSE2 select jumper (JP10) selects between the 3.3V regulator (VR2)

and battery voltage as a monitored input for the reset signal. When a

jumper is on positions 1 and 2 of JP10, the BAT_P signal is monitored,

which is useful when using the 740 mAh lithium ion battery. When a

jumper is on positions 2 and 3 of JP10, the 3.3V regulator (VR2) is moni-

tored. This setting must be used when no battery is wired to connector

P24. The SENSE2 input pin of the ADM13305 voltage reset supervisor is

set to drive the RESET_3V signal low when a voltage of less than 3.16V is

measured. By default, JP10 is installed on positions 2 and 3.

RST/ETH LED Jumper (JP11)

The RST/ETH LED jumper (JP11) enables the power saving feature of

the board through control of the voltage translator’s output enable pins.

When JP11 is not installed, the voltage translator (U4), which controls

Ethernet LEDs, and RESET_3V signals are tri-stated. Placing a jumper on

positions 1and 2 of JP11 allows the inverted WAKEUP_OUT signal

(WAKEUP_OUT) to control the output enable of the translator. When the

processor is not in hibernate, the translator is enabled; when the processor

is in hibernate, the translator outputs are tri-stated. Placing a jumper on

positions 2 and 3 of JP11 enables the translator outputs. See “Power

Architecture” on page 1-30 and “Power Saving Features” on page 1-35 for

more information about the power saving capabilities of the EZ-Board. By

default, JP11 is installed on positions 1 and 2.

ADSP-BF526 EZ-Board Evaluation System Manual 2-23

ADSP-BF526 EZ-Board Hardware Reference

UART SD Jumper (JP14)

The UART SD jumper (JP14) enables the power saving feature of the

ADM1385 UART line driver by controlling the driver’s shut-down pin.

When installed, JP14 disables the transmitters and receivers of the UART

line driver. See “Power Architecture” on page 1-30 and “Power Saving

Features” on page 1-35 for more information on the power saving capabil-

ities of the EZ-Board. By default, JP14 is uninstalled.

CHG GPIO Jumper (JP15)

The CHG GPIO jumper (JP15) selects the flag pin of the processor to

control the ADP2291 single cell lithium ion charge rate (see Table 2-12).

Note that only settings that are listed in the table are supported. For an

explanation of each setting, see “Power Architecture” on page 1-30. JP15

is used in conjunction with the P23 and JP17 jumper settings. See the fol-

lowing sections for more information: “R274 JMP Jumper (P23)” on

page 2-26, “CHG Control Jumper (JP17)” on page 2-24, and “Power

Measurements” on page 1-36. By default, JP15 is uninstalled.

OTP Flag Enable Jumper (JP16)

The OTP flag enable jumper (JP16) controls the precise 7V OTP voltage

regulator (VR9). When installed, JP16 allows OTP writes. JP16 must be

used in conjunction with the SW20 GPIO enable switch. Refer to “GPIO

Enable Switch (SW20)” on page 2-16 for more information.

Table 2-12. CHG GPIO Settings

JP15 Setting Signal FLAG pin

Uninstalled PUSHBUTTON1_HWAIT Not applicable (default)

1 and 2 PUSHBUTTON1_HWAIT PG0

3 and 4 LED1_HOSTWR# PG11

5 and 6 LED2_HOSTACK PG12

Jumpers

2-24 ADSP-BF526 EZ-Board Evaluation System Manual

JP16 must be installed for OTP writes to be successful. The nominal 2.5V

for OTP is temporarily raised to 7V when SW20 is configured properly and

PG13 is set high. Care must be taken when SW20 is configured for the

OTP_FLAG signal in order to avoid VR9 driving 7V for an extended amount

of time.

There is a limited amount of time that 7V can be applied to the

processor’s OTP interface. Violating the specifications listed in the

ADSP-BF522/523/524/525/526/527 Blackfin Embedded Processor

Data Sheet can damage the processor.

Configured properly, SW20 and JP16 connect the processor’s PG13 flag pin

to the shut-down pin of the ADP1611 switching converter (VR9). Refer to

“GPIO Enable Switch (SW20)” on page 2-16, the ADSP-BF52x Blackfin

Processor Hardware Reference Manual, and the

ADSP-BF522/523/524/525/526/527 Blackfin Embedded Processor Data

Sheet for more information about OTP writes.

CHG Control Jumper (JP17)

The CHG control jumper (JP17) selects the control line for the mosfet

attached to the charge rate adjustment pin of the ADP2291 linear charger.

When no jumper is installed, the on-board pull-up holds the gate of the

mosfet ON. Placing a jumper on positions 1 and 2 of JP17 allows the pro-

cessor’s flag pin, selectable by JP15, to control the gate of the mosfet.

Placing a jumper on positions 2 and 3 of JP17 pulls the mosfet gate to

ground, disconnecting the drain and the source. For more information on

the ADP2291 single cell lithium ion battery charger, see “Power Architec-

ture” on page 1-30.

The JP17 jumper is used in conjunction with the P23 and JP15 jumpers;

see the following sections for more information: “R274 JMP Jumper

(P23)” on page 2-26, “CHG GPIO Jumper (JP15)” on page 2-23, and

“Power Measurements” on page 1-36. By default, JP17 is installed on

positions 2 and 3.

ADSP-BF526 EZ-Board Evaluation System Manual 2-25

ADSP-BF526 EZ-Board Hardware Reference

VDDEXT Power Jumper (P11)

The VDDEXT power jumper (P11) is used to measure the processor’s I/O

voltage and current. By default, JP11 is ON: the power flows through the

two-pin IDC header. To measure power, remove the jumper and measure

voltage across the 0.1 ohm resistor. Once voltage is measured, power can

be calculated. For more information, refer to “Power Measurements” on

page 1-36.

VDDMEM Power Jumper (P12)

The VDDMEM power jumper (P12) is used to measure the voltage and

current supplied to the memory interface of the processor. By default, P12

is ON: the power flows through the two-pin IDC header. To measure

power, remove P12 and measure voltage across the 0.1 ohm resistor. Once

voltage is measured, power can be calculated. For more information, refer

to “Power Measurements” on page 1-36.

VDDINT Power Jumper (P13)

The VDDINT power jumper (P13) is used to measure the core voltage

and current supplied to the processor core. P13 is ON by default, and the

power flows through the two-pin IDC header. To measure power, remove

P13 and measure voltage across the 0.1 ohm resistor. Once voltage is mea-

sured, power can be calculated. For more information, refer to “Power

Measurements” on page 1-36.

ETH PWR Jumpers (P21–22)

The ETH PWR jumpers (P21—22) disconnect the SMSC LAN8700 Ether-

net PHY from the 1.8V and 3.3V power supplies. When P21—22 are

removed, all power is disconnected from the PHY, which is a great benefit

for low-power consumption applications that do not require Ethernet. See

“Power Architecture” on page 1-30 and “Power Saving Features” on

Jumpers

2-26 ADSP-BF526 EZ-Board Evaluation System Manual

page 1-35 for more information about the power saving capabilities of the

EZ-Board. By default, P21—22 are installed.

R274 JMP Jumper (P23)

The R274 JMP jumper (P23) provides a means to short out a R274 set

resistor in the charge rate circuit of the ADP2291 single cell lithium ion

battery. P23 bypasses R274 when installed and effectively makes a

zero ohm connection to the WALL_SENSE signal. For more information on

the ADP2291 battery charger, see “Power Architecture” on page 1-30. P23

is used in conjunction with the JP17 and JP15 jumpers; see the following

sections for more information: “CHG Control Jumper (JP17)” on

page 2-24, “CHG GPIO Jumper (JP15)” on page 2-23, and “Power Mea-

surements” on page 1-36. By default, P23 is uninstalled.

BATT Installed Jumper (P25)

The BATT installed jumper (P25) serves as an indication to the BQ27500

fuel gauge that a lithium ion battery is installed. When using the battery,

install a jumper on P25 before turning ON the battery’s power switch

(SW22). By default, P25 is uninstalled.

ADSP-BF526 EZ-Board Evaluation System Manual 2-27

ADSP-BF526 EZ-Board Hardware Reference

LEDs

This section describes the on-board LEDs. Figure 2-4 shows the LED

locations.

Figure 2-4. LED Locations

LEDs

2-28 ADSP-BF526 EZ-Board Evaluation System Manual

Ethernet LEDs (LED1–2)

When LED2 is lit solid, it indicates that the SMSC LAN8700 chip (U29)

detects a valid link. When transmit or receive activity is sensed, LED1

flashes as an activity indicator. For more information on the LEDs, refer

to the LAN8700 chip data sheet provided by the product manufacturer.

GPIO LEDs (LED3–5)

Three LEDs connect to three general-purpose I/O pins of the processor

(see Table 2-13). The LEDs are active high and are lit by writing a 1 to the

correct programmable flag signal.

Reset LED (LED7)

When LED7 is lit, it indicates that the master reset of all major ICs is

active. The reset LED is controlled by the Analog Devices ADM13305

supervisory reset circuit. You can assert the reset push button (SW18) to

assert a master reset and activate LED7. For more information, see “Reset

Push Button (SW18)” on page 2-16.

Batt GD LED (LED8)

When LED8 is lit (green), it indicates that the BQ27500 fuel gauge (U38)

has successfully initialized the lithium ion battery. This is not an indica-

tion of the battery capacity. When the battery switch (SW22) is OFF, but the

Table 2-13. GPIO LEDs

LED Reference Designator Processor Programmable Flag Pin

LED0 PF8

LED1 PG11

LED2 PG12

ADSP-BF526 EZ-Board Evaluation System Manual 2-29

ADSP-BF526 EZ-Board Hardware Reference

battery installed jumper (P25) is ON, the battery GD LED still illuminates.

Ensure that P25 is installed only when SW22 is ON.

Batt Low LED (LED9)

When LED9 is lit (yellow), it indicates that the BQ27500 fuel gauge (U38)

has detected that the lithium ion battery is low. The low threshold can be

programmed; for more information, refer to the BQ27500 data sheet pro-

vided by the product manufacturer.

Charging LED (LED10)

When LED10 illuminates, it indicates that the lithium ion battery is receiv-

ing a charge from either the 5V wall adaptor (P14) or the USB OTG

connector (P8).

Connectors

2-30 ADSP-BF526 EZ-Board Evaluation System Manual

Connectors

This section describes connector functionality and provides information

about mating connectors. Figure 2-5 shows the connector locations.

Figure 2-5. Connector Locations

Connectors shown with a dotted line are on the backside of the PCB

ADSP-BF526 EZ-Board Evaluation System Manual 2-31

ADSP-BF526 EZ-Board Hardware Reference

Expansion Interface II Connector (J1)

J1 is a board-to-board connector providing signals from the external bus

interface unit (EBIU) of the processor. The connector is located on the

left edge of the board. For more information, see “Expansion Interface II”

on page 1-29. For availability and pricing of the connector, contact

Samtec.

RS-232 Connector (J2)

Dual Audio Connectors (J3–4)

Part Description Manufacturer Part Number

104-position 0.025”, SMT header SAMTEC QMS-052-11-L-D-A

Mating Connector

104-position 0.025”, SMT socket SAMTEC QFS-052-01-L-D-A

Part Description Manufacturer Part Number

DB9, female, vertical mount NORCOMP 191-009-213-L-571

Mating Cable

2m female-to-female cable DIGI-KEY AE1020-ND

Part Description Manufacturer Part Number

3.5 mm dual stereo jack SWITCHCRAFT 35RAPC7JS

Mating Cable (shipped with EZ-Board)

3.5 mm male/male 6’ cable RANDOM 10A3-01106

Connectors

2-32 ADSP-BF526 EZ-Board Evaluation System Manual

Ethernet Connector (J5)

Battery Holder (J6)

JTAG Connector (P1)

The JTAG header is the connecting point for the JTAG interface to the

ADSP-BF526 processor. The standalone debug agent requires both con-

nectors P1 and ZP1.

Pin 3 is missing to provide keying. Pin 3 in the mating connector should

have a plug.

When using an emulator with the EZ-Board, the standalone debug agent

must be removed. Follow the installation instructions provided in “CCES

Install and Session Startup” on page 1-5 or “VisualDSP++ Install and Ses-

sion Startup” on page 1-9, using P1 as the JTAG connection point.

Part Description Manufacturer Part Number

RJ-45 Ethernet jack STEWART SS-6488-NF

Mating Cable (shipped with EZ-Board)

Cat 5E patch cable RANDOM PC10/100T-007

Part Description Manufacturer Part Number

16 mm battery holder MEMORY PROTECTION BH600

Mating Battery (shipped with EZ-Board)

3V 125MAH 16 mm LI-COIN PANASONIC CR1632

ADSP-BF526 EZ-Board Evaluation System Manual 2-33

ADSP-BF526 EZ-Board Hardware Reference

Expansion Interface II Connectors (P2 and P4)

P2 and P4 are board-to-board connectors providing signals for the SPI,

TWI, UART, SPORT interfaces and GPIO signals of the processor. The

connectors are located on the upper and lower edges of the board. For

more information, see “Expansion Interface II” on page 1-29. For avail-

ability and pricing of the connectors, contact Samtec.

Expansion Interface II Connector (P3)

P3 is a board-to-board connector providing signals for the PPI, TWI, and

GPIO signals of the processor. The connector is located on the upper edge

of the board. For more information, see “Expansion Interface II” on

page 1-29. For availability and pricing of the connector, contact Samtec.

DMAX Land Grid Array Connectors (P5–7)

The land grid array areas (P5—7) are intended for the probing of the pro-

cessor signals. The pads are exposed and designed to attach a Tektronix

logic analyzer to the connectors listed in Table 2-14. P5 and P6 require the

primary retention connectors, while P7 can connect to either the primary

Part Description Manufacturer Part Number

50-position 0.1”, SMT header SAMTEC TSSH-125-01-L-DV-A

Mating Connector

50-position 0.1”, SMT socket SAMTEC SSW-125-22-F-D-VS

Part Description Manufacturer Part Number

70-position 0.1”, SMT header SAMTEC TSSH-135-01-L-DV-A

Mating Connector

70-position 0.1”, SMT socket SAMTEC SSW-135-22-F-D-VS

Connectors

2-34 ADSP-BF526 EZ-Board Evaluation System Manual

or alternate retention connectors. For more information about the land

grid array, consult the Tektronix Web site.

USB OTG Connector (P8)

The pinout of the P8 connector can be found in “ADSP-BF526 EZ-Board

Schematic” on page B-1.

Host Interface Connector (P9)

The pinout of the P9 connector can be found in “ADSP-BF526 EZ-Board

Schematic” on page B-1.

Table 2-14. DMAX Land Grid Array Connectors (P5–7)

Part Description Manufacturer Part Number

Primary retention TEKTRONIX 020290800

Alternate retention TEKTRONIX 020291000

Part Description Manufacturer Part Number

USB 5-pin mini AB MOLEX 56579-0576

Mating Cable (shipped with EZ-Board)

3M mini USB 2.0 cable ASSMANN AK672M/2-3

Part Description Manufacturer Part Number

IDC header SAMTEC TSW-116-26-T-D

Mating Connector

IDC socket SAMTEC TSW-116-01-T-D

ADSP-BF526 EZ-Board Evaluation System Manual 2-35

ADSP-BF526 EZ-Board Hardware Reference

Power Connector (P14)

The power connector (J6) provides all of the power necessary to operate

the EZ-Board.

Battery Connector (P24)

P24 is a connection point of a single 3.3V lithium ion battery. Ensure that

the positive lead of the battery is inserted to the side labeled “+”, and the

negative terminal is inserted to the side labeled “–”. To remove the battery

leads, press the white plastic button in and slide out the lead. The battery

is not connected until the SW22 switch is ON.

Standalone Debug Agent Connector (ZP1)

ZP1 connects the standalone debug agent to the EZ-Board. The standalone

debug agent requires both the ZP1 and P1 connectors. For more informa-

tion, see “CCES Install and Session Startup” on page 1-5 or

“VisualDSP++ Install and Session Startup” on page 1-9.

Part Description Manufacturer Part Number

0.65 mm power jack CUI 045-0883R

Mating Power Supply (shipped with EZ-Board)

5.0VDC@2.5A power supply CUI STACK DMS050260-P12P-SZ

Part Description Manufacturer Part Number

Wire to board, push-in, 16–28 AWG WEIDMULLER 281-2020-ND

Mating Battery (shipped with EZ-Board)

3.7V lithium ion battery, 950 mAh MOUSER 5169-UBP563450

Connectors

2-36 ADSP-BF526 EZ-Board Evaluation System Manual

ADSP-BF526 EZ-Board Evaluation System Manual A-1

A ADSP-BF526 EZ-BOARD BILL

OF MATERIALS

The bill of materials corresponds to “ADSP-BF526 EZ-Board Schematic”

on page B-1.

Ref. Qty. Description Reference Designator Manufacturer Part Number

1174LVC14A

SOIC14

U5 TI 74LVC14AD

2 1 MMBT3904

SOT23

Q5 MOUSER 512-MMBT3904

3 1 32.768KHZ

OSC008

U12 EPSON MC-156-32.7680KA-

A0:ROHS

4 4 SN74LVC1G08

SOT23-5

U24-27 TI SN74LVC1G08DBVR

5 1 HX1188 ICS007 U28 DIGI-KEY 553-1340-ND

6 1 LAN8700 QFN3 U29 SMSC LAN8700C-AEZG

7 1 NJT4030P

SOT-223

VR8 ON SEMI NJT4030PT1G

8 1 50MHZ OSC012 U20 ECS INC ECS-3518-500-B-TR

9 1 SN74AUC1G00

SOT23-5

U9 TI SN74AUC1G00DBVR

10 1 BF526

M58WR032KB

“U16”

U16 NUMONYX M58WR032KB70ZB6E

11 1 BF526 BQ27500

“U33” OBS

U38 DIGI-KEY 296-22633-2-ND

12 1 BF526 SST25WF

040 “U6”

U6 SST SST25WF040-40-5I-

SAF

A-2 ADSP-BF526 EZ-Board Evaluation System Manual

13 1 25MHz OSC013 Y1 DIGI-KEY 535-9140-1-ND

14 1 24MHz OSC013 Y2 DIGI-KEY 535-9138-2-ND

15 1 12MHz OSC014 Y3 DIGI-KEY 535-9100-1-ND

16 1 SI1012R SC-75A Q1 VISHAY SI1012R-T1-E3

17 4 SI2333DS

SOT23D

Q2-4,Q6 VISHAY SI2333DS-T1-E3

18 1 GTL2002DC

VSSOP8

U39 DIGI-KEY 568-1869-1-ND

19 4 FXL2T245

MAC010A

U4,U32,U40-41 FAIRCHILD

SEMI

FXL2T245L10X

20 1 FXL4T245

MLP014A

U3 FAIRCHILD

SEMI

FXL4T245BQX

21 1 MIC2025-2

SOIC8

U2 MICREL MIC2025-2YM

22 1 NAND02

TFBGA63_80_95

X120

U15 NUMONYX NAND02GR3B2CZ

A6E

23 1 MT48H32M16

VFBGA54_80x90

U14 DIGI-KEY 557-1390-1-ND

24 1 ADSP-BF526

BGA208

U1 ANALOG

DEVICES

ADSP-BF526BBCZ-

4AX

25 1 ADP1715

MSOP8

VR5 ANALOG

DEVICES

ADP1715ARMZ-R7

26 1 ADP1710 TSOT5 VR10 ANALOG

DEVICES

ADP1710AUJZ-R7

27 1 ADR550B

SOT23-3

U35 ANALOG

DEVICES

ADR550BRTZ-REEL7

28 1 ADP2291

MSOP8

U37 ANALOG

DEVICES

ADP2291ARMZ-R7

29 1 ADP2105-1.8V

LFCSP16

VR3 ANALOG

DEVICES

ADP2105ACPZ-1.8-R7

Ref. Qty. Description Reference Designator Manufacturer Part Number

ADSP-BF526 EZ-Board Evaluation System Manual A-3

ADSP-BF526 EZ-Board Bill Of Materials

30 1 ADP2105-3.3V

LFCSP16

VR2 ANALOG

DEVICES

ADP2105ACPZ-3.3-

31 1 ADM13305-4

SOIC8

U22 ANALOG

DEVICES

ADM13305-4ARZ

32 1 AD5258

MSOP10

U34 ANALOG

DEVICES

AD5258BRMZ10

33 1 ADM1385ARSZ

SSOP20

U21 ANALOG

DEVICES

ADM1385ARSZ

34 1 AD8619ARUZ

TSSOP14

U36 ANALOG

DEVICES

AD8619ARUZ

35 2 ADP1610

MSOP8

VR7,VR9 ANALOG

DEVICES

ADP1610ARMZ-R7

36 1 SSM2603 ICS009 U31 ANALOG

DEVICES

SSM2603CPZ-R2

37 1 ADP120-AUJZ18

R7 TSOT5

VR1 ANALOG

DEVICES

ADP120-AUJZ18R7

38 1 DIP8 SWT016 SW21 C&K TDA08H0SB1

39 1 DIP6 SWT017 SW20 CTS 218-6LPST

40 10 DIP4 SWT018 SW2,SW4,SW6-7,

SW9-14

ITT TDA04HOSB1

41 1 DB9 9PIN

CON038

J2 NORCOMP 191-009-213-L-571

42 10 IDC 2X1

IDC2X1

P10-13,P15,P19,P21-

23,P25

FCI 90726-402HLF

43 5 IDC 2X1

IDC2X1

JP2,JP7,JP9,JP14,JP16 FCI 90726-402HLF

44 6 IDC 3X1

IDC3X1

JP3,JP5-6,JP10-11,JP17 FCI 90726-403HLF

45 20 IDC

2PIN_JUMPER_

SHORT

SJ1-9,SJ11-14,SJ16,

SJ21-22,SJ26-29

DIGI-KEY S9001-ND

Ref. Qty. Description Reference Designator Manufacturer Part Number

A-4 ADSP-BF526 EZ-Board Evaluation System Manual

46 1 IDC 3X2

IDC3X2

JP15 BURG 54102-T08-03LF

47 1 PWR .65MM

CON045

P14 DIG CP1-023-ND

48 1 IDC 4X2

IDC4X2

JP8 SULLINS GEC04DAAN

49 1 5A RESETABLE

FUS005

F1 MOUSER 650-RGEF500

50 1 ROTARY

SWT023

SW1 DIGI-KEY 563-1047-ND

51 2 3.5MM

DUAL_STEREO

CON050

J3-4 SWITCH-

CRAFT

35RAPC7JS

52 1 USB_MINI-AB

5PIN CON052

P8 MOLEX 56579-0576

53 1 RJ45 8PIN

CON_RJ45_12P

J5 DIGI-KEY 380-1022-ND

54 5 MOMENTARY

SWT024

SW15-19 PANASONIC EVQ-Q2K03W

55 1 ROTARY_ENC_

EDGE SWT025

SW5 PANASONIC EVQ-WKA001

56 1 QMS 52x2

QMS52x2_SMT

J1 SAMTEC QMS-052-06.75-L-

D-A

57 1 IDC 16x2

IDC16x2_SMT

P9 SAMTEC TSM-116-01-T-DV

58 2 IDC 25x2

IDC25x2_SMTA

P2,P4 SAMTEC TSSH-125-01-L-DV-A

59 1 IDC 35x2

IDC35x2_SMTA

P3 SAMTEC TSSH-135-01-L-DV-A

60 1 IDC 7x2

IDC7x2_SMTA

P1 SAMTEC TSM-107-01-T-DV-A

Ref. Qty. Description Reference Designator Manufacturer Part Number

ADSP-BF526 EZ-Board Evaluation System Manual A-5

ADSP-BF526 EZ-Board Bill Of Materials

61 1 BATT_HOLDER

16MM

BATT_COI

J6 MEMORY

PROTECTI

BH600

62 1 POWER 2X1

CON064

P24 WEID-

MULLER

1824420000

63 1 SPDTSWT026 SW22 NKK

SWITCHES

CS12ANW03

64 3 10 1/8W 5%

1206

R154-155,R310 KOA RK73B2BTTD100J

65 5 YELLOW

LED001

LED2-5,LED9 DIGI-KEY P512TR-ND

66 1 600 100MHZ

200MA 0603

FER13 DIGI-KEY 490-1014-2-ND

67 3 600 100MHZ

500MA 1206

FER1,FER17-18 STEWARD HZ1206B601R-10

68 1 1UF 16V 10%

0805

C97 KEMET C0805C105K4RAC TU

69 1 10 1/10W 5%

0805

R92 VISHAY CRCW080510R0

FKEA

70 2 10UF 16V 20%

CAP002

CT1-2 PANASONIC EEE1CA100SR

71 1 0 1/10W 5%

0805

R65 VISHAY CRCW08050000

Z0EA

72 1 190 100MHZ 5A

FER002

FER19 MURATA DLW5BSN191SQ2

73 1 YELLOW

LED009

LED10 PANASONIC LNJ416Q8YRA

74 10 10UF 6.3V 10%

0805

C8,C12,C18,C23,C34,

C104,C108,C120,

C122,C200

AVX 08056D106KAT2A

Ref. Qty. Description Reference Designator Manufacturer Part Number

A-6 ADSP-BF526 EZ-Board Evaluation System Manual

75 25 0.1UF 10V 10%

0402

C5-7,C17,C19-22,C48,

C79-80,C87,C93,

C105,C109,C119,

C121,C144,C147-150,

C205,C216,C237

AVX 0402ZD104KAT2A

76 62 0.01UF 16V 10%

0402

C9,C35-42,C51-52,

C54-59,C73,C77-78,

C81-86,C88-92,C96,

C98,C133,C135,C138-

141,C146,C151-152,

C156-158,C160,C199,

C201-204,C212,C214-

215,C236,C262-268

AVX 0402YC103KAT2A

77 16 10K 1/16W 5%

0402

R36,R72,R99-102,

R121,R124,R173,

R185,R190,R204,

R208,R245-246,R249

VISHAY CRCW040210K0

FKED

78 10 4.7K 1/16W 5%

0402

R26,R35,R66-68,R73,

R83-85,R95

VISHAY CRCW04024K70

JNED

79 16 0 1/16W 5%

0402

R12,R14,R18,R98,

R111,R168,R192-199,

R244,R308

PANASONIC ERJ-2GE0R00X

80 7 33 1/16W 5%

0402

R6,R10-11,R13,R82,

R203,R309

VISHAY CRCW040233R0

JNEA

81 1 150UF 10V

10% D

CT5 AVX TPSD157K010R0050

82 5 1A SK12

DO-214AA

D13,D19-22 DIODES

INC

B120B-13-F

83 8 0.1UF 16V

10%0603

C76,C184,C194,C245,

C251,C254-255,C257

AVX 0603YC104KAT2A

84 1 10UF 10V

+80/-20% 0805

C256 PANASONIC ECJ-2FF1A106Z

85 7 1UF 16V 10%

0603

C11,C13,C112-114,

C259,C269

KEMET C0603C105K4PACTU

Ref. Qty. Description Reference Designator Manufacturer Part Number

ADSP-BF526 EZ-Board Evaluation System Manual A-7

ADSP-BF526 EZ-Board Bill Of Materials

86 4 4.7UF 25V 20%

0805

C178-179,C188-189 AVX 0805ZD475KAT2A

87 1 68PF 50V 5%

0603

C195 AVX 06035A680JAT2A

88 5 4.7UF 6.3V 20%

0603

C143,C181,C234-235,

C238

PANASONIC ECJ-1VB0J475M

89 3 470PF 50V 5%

0603

C252,C258,C261 AVX 06033A471JAT2A

90 1 .022UF 16V 10%

0603

C145 AVX 06033C223KAT2A

91 2 220UF 6.3V 20%

D2E

CT3-4 SANYO 10TPE220ML

92 1 10M 1/10W 5%

0603

R2 VISHAY CRCW060310M0

FNEA

93 10 100K 1/10W 5%

0603

R175,R265,R268,

R277,R279,R282,

R286,R289-290,R293

VISHAY CRCW0603100KJNEA

94 4 1M 1/10W 5%

0603

R40,R278,R283,R291 VISHAY CRCW06031M00

FNEA

95 5 0 1/10W 5%

0603

R54-55,R136,R248,

R261

PHYCOMP 232270296001L

96 10 49.9 1/16W 1%

0603

R74-76,R79-81,R88-91 VISHAY CRCW060349R9

FNEA

97 4 10 1/10W 5%

0603

R115,R127,R130,R135 VISHAY CRCW060310R0

JNEA

98 1 75.0K 1/16W 1%

0603

R164 VISHAY CRCW060375K0FKEA

99 1 1K 1/10W 5%

0603

R276 DIGI-KEY 311-1.0KGRTR-ND

100 4 0.1 1/10W 1%

0603

R156-158,R188 PANASONIC ERJ-3RSFR10V

Ref. Qty. Description Reference Designator Manufacturer Part Number

A-8 ADSP-BF526 EZ-Board Evaluation System Manual

101 1 10.0K 1/10W 1%

0603

R259 DIGI-KEY 311-10.0KHRTR-ND

102 1 120PF 50V 5%

0603

C185 AVX 06035A121JAT2A

103 9 100PF 50V 5%

0603

C100-103,C115-118,

C209

PANASONIC ECJ-1VC1H101J

104 2 1000PF 50V 5%

0603

C183,C193 PANASONIC ECJ-1VC1H102J

105 1 12.4K 1/10W 1%

0603

R93 DIGI-KEY 311-12.4KHRTR-ND

106 1 2200PF 50V 5%

0603

C250 PANASONIC ECJ-1VB1H222K

107 2 75.0 1/10W 1%

0603

R77-78 DALE CRCW060375R0FKEA

108 6 100 1/16W 5%

0402

R51,R56,R116,R119,

R129,R133

DIGI-KEY 311-100JRTR-ND

109 1 2.05K 1/16W 1%

0402

R306 VISHAY CRCW04022K05FKED

110 1 4.99K 1/16W 1%

0603

R71 VISHAY CRCW06034K99FKEA

111 3 10UF 10V 10%

0805

C94,C99,C142 PANASONIC ECJ-2FB1A106K

112 1 2.0K 1/16W 1%

0603

R252 PANASONIC ERJ-3EKF2001V

113 9 10UF 16V 10%

1210

C10,C191,C206-207,

C243-244,C247,C249,

C273

AVX 1210YD106KAT2A

114 2 GREEN LED001 LED1,LED8 PANASONIC LN1361CTR

115 1 RED LED001 LED7 PANASONIC LN1261CTR

116 2 1000PF 50V 5%

1206

C180,C182 AVX 12065A102JAT2A

Ref. Qty. Description Reference Designator Manufacturer Part Number

ADSP-BF526 EZ-Board Evaluation System Manual A-9

ADSP-BF526 EZ-Board Bill Of Materials

117 2 18K 1/16W 5%

0402

R177,R270 DIGI-KEY 311-18KJRCT-ND

118 6 430 1/16W 1%

0402

R109-110,R114,R120,

R262-263

DIGI-KEY 311-430LRCT-ND

119 2 22000PF 25V

10% 0402

C208,C241 DIGI-KEY 490-3252-1-ND

120 2 5A

MBRS540T3G

SMC

D7,D18 ON SEMI MBRS540T3G

121 3 15KV

PGB1010603

0603

D8-10 LITTLEFUSE PGB1010603MR

122 1 VARISTOR

V5.5MLA 30A

0603

R1 LITTLEFUSE V5.5MLA0603

123 1 THERM 0.5A 0.4

1206

R167 LITTLEFUSE 1206L050-C

124 1 20MA

MA3X717E

DIO005

D1 PANASONIC MA3X717E

125 2 330.0 1/16W 1%

0402

R94,R97 DIGI-KEY 541-330LCT-ND

126 1 33.0K 1/16W 1%

0402

R9 ROHM MCR01MZPF3302

127 8 47.0K 1/16W 1%

0402

R39,R47-48,R50,R52-

53,R57,R61

ROHM MCR01MZPF4702

128 2 3.01K 1/16W 1%

0402

R301-302 ROHM MCR01MZPF3011

129 1 5.6K 1/16W 5%

0402

R307 PANASONIC ERJ-2GEJ562X

130 4 1.0K 1/16W 1%

0402

R105-107,R237 PANASONIC ERJ-2RKF1001X

Ref. Qty. Description Reference Designator Manufacturer Part Number

A-10 ADSP-BF526 EZ-Board Evaluation System Manual

131 2 1000PF 2000V

10% 1206

C131-132 AVX 1206GC102KAT1A

132 4 1UF 50V 10%

0603

C153-155,C159 DIGI-KEY 587-1257-2-ND

133 1 154.0K 1/16W

1% 0402

R165 DIGI-KEY 541-154KLCT-ND

134 10 10.0K 1/16W 1%

0402

R27-29,R58,R69-70,

R86-87,R169,R172

DIGI-KEY 541-10.0KLCT-ND

135 4 5.6K 1/16W

0.5% 0402

R41,R44-46 SUSUMU RR0510P-562-D

136 2 680 1/16W 1%

0402

R43,R273 BC COMPO-

NENTS

2312 275 16801

137 1 90.9K 1/16W 5%

0402

R42 DIGI-KEY 541-90.9KLCT-ND

138 1 40.2K 1/16W 5%

0402

R49 DIGI-KEY 541-40.2KLCT-ND

139 34 100K 1/16W 5%

0402

R4-5,R8,R17,R20-25,

R30-34,R59,R62-64,

R96,R103-104,R117-

118,R122-123,R125-

126,R128,R131,R134,

R171,R207,R305

DIGI-KEY 541-100KJTR-ND

140 1 3.3UF 16V 10%

0805

C125 DIGI-KEY 490-3337-2-ND

141 3 2.2UF 25V 10%

0805

C240,C246,C253 DIGI-KEY 490-3331-1-ND

142 3 22UF 16V 10%

1210

C177,C187,C190 YAIYO

YUDEN

EMK325BJ226KM-T

143 6 1.00K 1/10W

0.1% 0603

R264,R266,R280-281,

R288,R296

DIGI-KEY RG16P1.0KBCT-ND

144 1 21.5K 1/10W 1%

0603

R260 DIGI-KEY 311-21.5KHRCT-ND

Ref. Qty. Description Reference Designator Manufacturer Part Number

ADSP-BF526 EZ-Board Evaluation System Manual A-11

ADSP-BF526 EZ-Board Bill Of Materials

145 5 1A

MBR130LSFT1G

SOD-123FL

D12,D14-17 ON SEMI MBR130LSFT1G

146 1 22UH 20%

IND018

L7 COILCRAFT MSS4020-223MLB

147 1 1UH 20%

IND019

L6 COILCRAFT ME3220-102MLB

148 1 0.2 1/4W 1%

0805

R285 SUSUMU RL1220S-R20-F

149 1 40K 1/16W 0.1%

0402

R274 STACKPOLE RNC 10 T9 40K

0.1% R

150 1 30.9K 1/16W 1%

0402

R174 DIGI-KEY 541-30.9KLCT-ND

151 1 1.8M 1/16W 1%

0402

R271 DIGI-KEY 541-1.80MLCT-ND

152 1 10K 1/100W 1%

THERMAT-2

R300 SEMITEC 103AT-2

153 2 2.7UH 10.5%

IND022

L3-4 COILCRAFT 1812PS-272JLB

154 1 76.8K 1/16W 1%

0402

R178 DIGI-KEY 541-76.8KLCT-ND

155 8 18PF 50V 5%

0402

C2-3,C219-224 AVX 04025A180JAT2A

156 12 33 1/16W 5%

RNS003

RN2-13 PANASONIC EXB-2HV330JV

157 1 33 1/32W 5%

RNS005

RN14 PANASONIC EXB-28V330JX

158 1 1.2K 1/16W 1%

0402

R234 VISHAY CRCW04021K20FKED

159 2 4.3 1/4W 5%

1206

R233,R236 PANASONIC ERJ-8GEYJ4R3V

Ref. Qty. Description Reference Designator Manufacturer Part Number

A-12 ADSP-BF526 EZ-Board Evaluation System Manual

160 1 2.67K 1/16W 1%

0402

R235 PANASONIC ERJ-2RKF2671X

161 3 1.0M 1/16W 1%

0402

R312-314 VISHAY CRCW04021M00

FKED

162 1 169.0K 1/16W

1% 0402

R275 VISHAY CRCW0402169

KFKED

163 1 0.02 1/2W 1%

1206

R272 OHMITE LVK12R020FER

164 1 200.0K 1/16W

1% 0402

R304 ROHM MCR01MZPF2003

165 2 15K 1/16W 5%

0402

R160,R269 PANASONIC ERJ-2GEJ153X

166 1 3.3uH 20%

IND023

L5 COILCRAFT LPS4018-332MLC

167 3 330 100MHZ

1.5A 0805

FER10-11,FER20 MURATA BLM21PG331SN1D

168 1 24.0K 1/10W 1%

0603

R256 PANASONIC ERJ-3EKF2402V

169 1 140.0K 1/10W

1% 0603

R257 PANASONIC ERJ-3EKF1403V

170 1 1.91K 1/10W

.1% 0603

R253 SUSUMU RG1608P-1911-B-T5

171 1 3.01K 1/10W

.1% 0603

R254 SUSUMU RG1608P-3011-B-T1

172 3 30A GSOT05

SOT23-3

D6,D24-25 VISHAY GSOT05-GS08

173 1 30A GSOT03

SOT23-3

D11 VISHAY GSOT03-GS08

174 4 40A ESD5Z2.5

T1 SOD-523

D3-5,D23 ON SEMI ESD5Z2.5T1G

Ref. Qty. Description Reference Designator Manufacturer Part Number

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

A0212-2007

ADSP-526 EZ-BOARD

Rev

1.1

SCHEMATIC

ADSP-BF526 EZ-BOARD

TITLE

5-12-2009_16:42 1 15

1.8V

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

A0212-2007

ADSP-526 EZ-BOARD

Rev

1.1

1.8V

NC1 NC2

TERM1 TERM2

9ABCDEF

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

ABE0#/SDQM0

ABE1#/SDQM1

ARDY

CLKBUF

CLKOUT

D10

D11

D12

D13

D14

D15

EXT_WAKE1

SA10

SCKE

SS/PG

VROUT/EXT_WAKE0

VRSEL

AMS0

AMS1

AMS2

AMS3

AOE

ARE

AWE

NMI

RESET

SCAS

SMS

SRAS

SWE

BGA208

BMODE0

BMODE1

BMODE2

BMODE3

CLKIN

PF0/PPID0/DR0PRI/ND_D0A

PF1/PPID1/RFS0/ND_D1A

PF10/PPID10/RFS1/SPISEL7#

PF11/PPID11/TFS1/CZM

PF12/PPID12/DT1PRI/SPISEL2#/CDG

PF13/PPID13/TSCLK1/SPISEL3#/CUD

PF14/PPID14/DT1SEC/UART1TX

PF15/PPID15/DR1SEC/UART1RX/TACI3

PF2/PPID2/RSCLK0/ND_D2A

PF3/PPID3/DT0PRI/ND_D3A

PF4/PPID4/TFS0/ND_D4A/TACLK0

PF5/PPID5/TSCLK0/ND_D5A/TACLK1

PF6/PPID6/DT0SEC/ND_D6A/TACI0

PF7/PPID7/DR0SEC/ND_D7A/TACI1

PF8/PPID8/DR1PRI

PF9/PPID9/RSCLK1/SPISEL6#

PG0/HWAIT

PG1/SPISS#/SPISEL1#

PG10/TMR6/TSCLK0A/TACI6

PG11/TMR7/HOST_WR#

PG12/DMAR1/UART1TXA/HOST_ACK

PG13/DMAR0/UART1RXA/HOST_ADDR/TACI2

PG14/TSCLK0A1/MDC/HOST_RD#

PG15/TFS0A/MIIPHYINT#/RMIIMDINT#/HOST_CE#

PG2/SPISCK

PG3/SPIMISO/DR0SECA

PG4/SPIMOSI/DT0SECA

PG5/TMR1/PPIFS2

PG6/DT0PRIA/TMR2/PPIFS3

PG7/TMR3/DR0PRIA/UART0TX

PG8/TMR4/RFS0A/UART0RX/TACI4

PG9/TMR5/RSCLK0A/TACI5

PH0/ND_D0/MIICRS/RMIICRSDV/HOST_D0

PH1/ND_D1/ERXER/HOST_D1

PH10/ND_CE#/ERXD2/HOST_D10

PH11/ND_WE/ETXD3/HOST_D11

PH12/ND_RE/ERXD3/HOST_D12

PH13/ND_BUSY/ERXCLK/HOST_D13

PH14/ND_CLE/ERXDV/HOST_D14

PH15/ND_ALE/COL/HOST_D15

PH2/ND_D2/MDIO/HOST_D2

PH3/ND_D3/ETXEN/HOST_D3

PH4/ND_D4/MIITXCLK/RMIIREF_CLK/HOST_D4

PH5/ND_D5/ETXD0/HOST_D5

PH6/ND_D6/ERXD0/HOST_D6

PH7/ND_D7/ETXD1/HOST_D7

PH8/SPISEL4#/ERXD1/HOST_D8/TACLK2

PH9/SPISEL5#/ETXD2/HOST_D9/TACLK3

PJ0/PPIFS1/TMR0

PJ1/PPICLK/TMRCLK

PJ2/SCL

PJ3/SDA

RTXI

RTXO

TCK

TDI

TDO

TMS

XTALO

EMU

TRST

BGA208

"BOOT MODE"

Reserved

BOOT MODEPOSITION

Reserved

Boot from serial SPI memory

Reserved

Boot from 8-Bit Host DMA

Boot from 16-Bit Host DMA

Boot from SDRAM

Boot from UART1Host

Boot from UART0 host

Boot from TWI host

Boot from serial TWI memory

Boot from SPI host device

Boot from 16-bit asynchronous FIFO

Reserved

Boot from 8 or 16-bit external flash memory

SW1: Boot Mode Select Switch

"RTC ""DSP CLK"

Default

A15

A14

B12

A12

B11

B10

B17

B16

B15

B14

B13

A13

W10

A11

Y10

A10

M20

L20

M19

K19

J19

W11

Y12

W12

Y13

W13

Y14

W14

Y15

W15

Y18

W18

Y16

Y17

W17

Y19

W19

W20

W16 W5

N19

P19

N20

Y11

T19

U20

U19

T20

P20

K20

R19

B18 C19

B19

F19

H20

V19

V20

G19

J20

R18 0

0402

R23

100K

0402

R22

100K

0402

R21

100K

0402

R20

100K

0402

100K

0402

DNP

100K

0402

100K

0402

R17

100K

0402 0402

430

R16

0402

430

R15

SCL

R13 33

0402

R12 0

0402

R14 0

0402

ROTARY

SWT023

SW1

R11 33

0402

R10 33

0402 CLKOUT

R7 0

0402 DNP

TP1 VREFFLT

RESET_3V

AWE_Z

ARE_Z

AOE_Z

AMS0_Z

AMS1_Z

AMS2_Z

AMS3_Z

ABE0#/SDQM0_Z

ABE1#/SDQM1_Z

SRAS_Z

SMS_Z

SCAS_Z

SA10_Z

SWE_Z

SCKE_Z

R6 33

0402

C219

18PF

0402

0603

10M

25MHZ

OSC013

U12

OSC008

32.768KHZ

R200

1.0M

0402

DNP

DSP_USBXI

DSP_XTALO

C220

18PF

0402

DSP_CLKIN

18PF

0402

18PF

0402

33.0K

0402

100K

0402

DSP EBIU + CONTROL

155-12-2009_16:42 2

220PF

0402

DNP

VREFFLT

DSP_RTXI DSP_RTXO

D2_Z

D1_Z

D[0:15]_Z

D4_Z

D5_Z

D6_Z

D8_Z

D11_Z

D12_Z

D13_Z

D15_Z

D10_Z

D0_Z

D3_Z

D7_Z

D9_Z

D14_Z

A2_Z

A4_Z

A5_Z

A6_Z

A7_Z

A8_Z

A9_Z

A10_Z

A11_Z

A12_Z

A13_Z

A14_Z

A15_Z

A16_Z

A17_Z

A18_Z

A19_Z

A[1:19]_Z

A1_Z

A3_Z

ARDY

R19 0

0402 DNP

WAKEUP_OUT SPISCK

MDC_HOSTRD#

EMU

TDO

ARDY

R309 33

0402

PPICLK

DSP_XTALO

DSP_CLKIN

DSP_RTXI

DSP_RTXO

TDI

TCK

TMS

TRST

PPIFS1_Z

SCL_Z

SDA_Z

NDD0_RMIICRSDV_HOSTD0_Z

NDD1_ERXER_HOSTD1_Z

NDD2_MDIO_HOSTD2_Z

NDD3_ETXEN_HOSTD3_Z

NDD4_RMIIREFCLK_HOSTD4_Z

NDD5_ETXD0_HOSTD5_Z

NDD6_ERXD0_HOSTD6_Z

NDD7_ETXD1_HOSTD7_Z

ERXD1_HOSTD8_Z

HOSTD9_Z

NDCE#_HOSTD10_Z

NDWR#_HOSTD11_Z

NDRE#_HOSTD12_Z

NDBUSY#_HOSTD13_Z

NDCLE_HOSTD14_Z

NDALE_HOSTD15_Z

TFS0A_RMIIMDINT#_HOSTCE#_Z

PUSHBUTTON2_HOSTADDR_Z

LED2_HOSTACK_Z

LED1_HOSTWR#_Z

TSCLK0A_Z

RSCLK0A_Z

RFS0A_Z

DR0PRIA_Z

DT0PRIA_Z

PPIFS2_Z

SPIMOSI_Z

SPIMISO_Z

SPISEL1_Z

PUSHBUTTON1_HWAIT_Z

UART1RX_Z

UART1TX_Z

CUD_Z

CDG_Z

CZM_Z

UART1RTS_Z

PPID9_Z

LED0_Z

PPID7_Z

PPID6_Z

PPID5_Z

PPID4_Z

PPID3_Z

PPID2_Z

PPID1_Z

PPID0_Z

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

A0212-2007

ADSP-526 EZ-BOARD

Rev

1.1

R1A

1R1B16

R2A

2R2B15

R3A

3R3B14

R4A

4R4B13

R5A

5R5B12

R6A

6R6B11

R7A

7R7B10

R8A

8R8B9

R1A

1R1B16

R2A

2R2B15

R3A

3R3B14

R4A

4R4B13

R5A

5R5B12

R6A

6R6B11

R7A

7R7B10

R8A

8R8B9

R1A

1R1B16

R2A

2R2B15

R3A

3R3B14

R4A

4R4B13

R5A

5R5B12

R6A

6R6B11

R7A

7R7B10

R8A

8R8B9

R1A

1R1B16

R2A

2R2B15

R3A

3R3B14

R4A

4R4B13

R5A

5R5B12

R6A

6R6B11

R7A

7R7B10

R8A

8R8B9

R1A

1R1B16

R2A

2R2B15

R3A

3R3B14

R4A

4R4B13

R5A

5R5B12

R6A

6R6B11

R7A

7R7B10

R8A

8R8B9

R1A

1R1B16

R2A

2R2B15

R3A

3R3B14

R4A

4R4B13

R5A

5R5B12

R6A

6R6B11

R7A

7R7B10

R8A

8R8B9

R1A

1R1B16

R2A

2R2B15

R3A

3R3B14

R4A

4R4B13

R5A

5R5B12

R6A

6R6B11

R7A

7R7B10

R8A

8R8B9

R1A R1B

R2A R2B

R3A R3B

R4A R4B

R5A R5B

R6A R6B

R7A R7B

R8A R8B

R1A R1B

R2A R2B

R3A R3B

R4A R4B

R5A R5B

R6A R6B

R7A R7B

R8A R8B

R4B

R3B

R2B

R1BR1A

R2A

R4A

R3A

R1A

1R1B16

R2A

2R2B15

R3A

3R3B14

R4A

4R4B13

R5A

5R5B12

R6A

6R6B11

R7A

7R7B10

R8A

8R8B9

R1A

1R1B16

R2A

2R2B15

R3A

3R3B14

R4A

4R4B13

R5A

5R5B12

R6A

6R6B11

R7A

7R7B10

R8A

8R8B9

R1A

1R1B16

R2A

2R2B15

R3A

3R3B14

R4A

4R4B13

R5A

5R5B12

R6A

6R6B11

R7A

7R7B10

R8A

8R8B9

RN3

RNS003 NDD4_RMIIREFCLK_HOSTD4

NDD6_ERXD0_HOSTD6

NDD7_ETXD1_HOSTD7

RN10

RNS003

RN9

RNS003

RN14

RNS005

RN8

RNS003

RN5

RNS003

RN6

RNS003

RN12

RNS003

RN13

RNS003

RN4

RNS003

RN2

RNS003

RN11

RNS003

RN7

RNS003

NDBUSY#_HOSTD13_ZNDBUSY#_HOSTD13

SDA

AWE_ZAWE

SERIES TERMINATORS

1535-12-2009_16:42

D[0:15]_Z

D0_Z

D2_Z

D3_Z

D1_Z

D4_Z

D5_Z

D6_Z

D7_Z

D8_Z

D9_Z

D10_Z

D11_Z

D12_Z

D13_Z

D14_Z

D15_Z

D[0:15]

D10

D11

D12

D13

D14

D15

AOE_Z

AMS1_Z

AMS3_Z

AOE

AMS3

AMS1

SCAS

SMS

SRAS

SA10

SWE

SCKE

SRAS_Z

SMS_Z

SCAS_Z

SA10_Z

SWE_Z

SCKE_Z

ABE1#/SDQM1_ZABE1#/SDQM1

ABE0#/SDQM0_ZABE0#/SDQM0

PPID7

PPID5

PPID4

PPID3

PPID2

PPID1

PPID0

PPID7_Z

PPID5_Z

PPID4_Z

PPID3_Z

PPID2_Z

PPID1_Z

PPID0_Z

PPID6_ZPPID6

LED0

UART1RTS

CZM

UART1TX

UART1RX

CUD

PPID9

UART1TX_Z

CUD_Z

CZM_Z

UART1RTS_Z

PPID9_Z

LED0_Z

UART1RX_Z

CDG_ZCDG

RFS0A

PUSHBUTTON2_HOSTADDR

TFS0A_RMIIMDINT#_HOSTCE#_ZTFS0A_RMIIMDINT#_HOSTCE#

PUSHBUTTON2_HOSTADDR_Z

RFS0A_Z

SDA_Z

PPIFS2_ZPPIFS2

SPIMOSI

DR0PRIA

DT0PRIA

SPIMISO

SPISEL1 SPISEL1_Z

SPIMOSI_Z

PUSHBUTTON1_HWAIT_ZPUSHBUTTON1_HWAIT

SPIMISO_Z

DR0PRIA_Z

DT0PRIA_Z

PPIFS1_ZPPIFS1

NDCE#_HOSTD10_Z

NDWR#_HOSTD11_Z

NDRE#_HOSTD12_Z

NDCLE_HOSTD14_Z

NDALE_HOSTD15_Z

HOSTD9

ERXD1_HOSTD8 ERXD1_HOSTD8_Z

HOSTD9_Z

NDCE#_HOSTD10

NDWR#_HOSTD11

NDRE#_HOSTD12

NDCLE_HOSTD14

NDALE_HOSTD15

A19_Z

A18_Z

A16_Z

A15_Z

A14_Z

A13_Z

A12_Z

A11_Z

A10_Z

A9_Z

A2_Z

A3_Z

A4_Z

A5_Z

A6_Z

A7_Z

A8_Z

A1_Z

A[1:19]_Z

A17_Z

A19

A18

A16

A15

A14

A13

A12

A11

A10

A[1:19]

A17

LED2_HOSTACK

LED1_HOSTWR#_ZLED1_HOSTWR#

LED2_HOSTACK_Z

TSCLK0A TSCLK0A_Z

RSCLK0A_ZRSCLK0A

ARE_Z

AMS2_Z

ARE

AMS2

AMS0_ZAMS0

NDD7_ETXD1_HOSTD7_Z

NDD6_ERXD0_HOSTD6_Z

NDD4_RMIIREFCLK_HOSTD4_Z

NDD5_ETXD0_HOSTD5_Z

NDD2_MDIO_HOSTD2_Z

NDD3_ETXEN_HOSTD3_Z

NDD0_RMIICRSDV_HOSTD0_Z

NDD1_ERXER_HOSTD1_ZNDD1_ERXER_HOSTD1

NDD0_RMIICRSDV_HOSTD0

NDD3_ETXEN_HOSTD3

NDD2_MDIO_HOSTD2

NDD5_ETXD0_HOSTD5

3.3V

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

A0212-2007

ADSP-526 EZ-BOARD

Rev

1.1

BATTHOLDER

V_SELECT

GND1

GND10

GND11

GND12

GND13

GND14

GND15

GND16

GND17

GND18

GND19

GND2

GND20

GND21

GND22

GND23

GND24

GND25

GND26

GND27

GND28

GND29

GND3

GND30

GND31

GND32

GND33

GND34

GND35

GND36

GND4

GND5

GND6

GND7

GND8

GND9

VDDEXT1

VDDEXT10

VDDEXT11

VDDEXT12

VDDEXT2

VDDEXT3

VDDEXT4

VDDEXT5

VDDEXT6

VDDEXT7

VDDEXT8

VDDEXT9

VDDINT1

VDDINT10

VDDINT11

VDDINT12

VDDINT2

VDDINT3

VDDINT4

VDDINT5

VDDINT6

VDDINT7

VDDINT8

VDDINT9

VDDMEM1

VDDMEM10

VDDMEM2

VDDMEM3

VDDMEM4

VDDMEM5

VDDMEM6

VDDMEM7

VDDMEM8

VDDMEM9

VDDOTP

VDDRTC

VPPOTP

BGA208

"RTC BATTERY"

G11

G14

G12

N14

M14

K14

J14

H14

P13

P12

G10

P11

P10

H13

H12

H11

H10

B20

Y20

N13

N12

N11

N10

A20

M13

M12

M10

L13

L12

L11

L10

A17

K13

K12

K11

K10

J13

J12

J11

J10

G13

L14

M11

P14

R20

A16

L19

VDDMEM

C77

0.01UF

0402

C76

0.1UF

0603

0402

0.01UF

C73

VDDOTP

BATT_COIN16MM

0.1UF

0402

VDDINT

20MA

MA3X717E

DIO005

0805

10UF

C34

0805

10UF

C18

VDDEXT

0402

0.01UF

C54

DSP POWER, BYPASS CAPS

1545-12-2009_16:42

C59

0.01UF

04020402

0.01UF

C58

0402

0.01UF

C57 C56

0.01UF

0402 0402

0.01UF

C55

0402

0.01UF

C52 C51

0.01UF

0402

C48

0.1UF

0402

C42

0.01UF

04020402

0.01UF

C41C40

0.01UF

0402 0402

0.01UF

C39

0402

0.01UF

C38

0402

0.01UF

C37 C36

0.01UF

0402 0402

0.01UF

C35

0805

10UF

C23 C22

0.1UF

0402

C21

0.1UF

0402

C20

0.1UF

0402

C19

0.1UF

0402

C17

0.1UF

0402

0.01UF

0805

10UF

C8 C7

0.1UF

0402

0.1UF

0402

VDDINT

0402

0.01UF

C199

0805

10UF

C200 C201

0.01UF

0402

VDDEXT

VDDMEM

C216

0.1UF

0402

1.8V

1 2 3 4

1.8V

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

A0212-2007

ADSP-526 EZ-BOARD

Rev

1.1

1.8V

VCC1

VCC2

R/~B

GND

SCK

SI SO

VCC

RST/HOLD

JUMPER

SHORTING

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

CLK

D10

D11

D12

D13

D14

D15

VPP

WAIT

RESET

A10

A11

A12

BA0

BA1

CKE

CLK

DQ0

DQ1

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQMH

DQML

CAS

RAS

DSP (U1) FLASH (U16)

FLASH (U16)

4 MB FLASH

FROM DEFAULT ALTERNATE FUNCTION / OFF MODEPOS.

(2M x 16)

0x2020 0000 - 0x202F FFFF

0x2010 0000 - 0x201F FFFF

0x2000 0000 - 0x200F FFFF

0x2030 0000 - 0x203F FFFF

0x0000 0000 - 0x03FF FFFF

ADDRESS RANGE

MEMORY MAP

2Gb NAND FLASH

(Expansion Interface)

FLASH

ASYNC BANK 3

ASYNC BANK 2

ASYNC BANK 1

ASYNC BANK 0

NONE SDRAM

SELECT LINE TYPE

FLASH

64MB SDRAM (32M x 16)

U9,U24,U25,U26

U16

SW6: FLASH Enable

U14

U15

4 Mb SPI FLASH

FLASH (U16)

FLASH (U16)DSP (U1)

DSP (U1)

"FLASH ENABLE"

"CFG WP"

DSP (U1)SW6.1

SW6.2

SW6.3

SW6.4

R58

10.0K

0402

U14

MT48H32M16

VFBGA54_80X90

R29

10.0K

0402

R34

100K

0402

VFBGA56_77X90

M58WR032KB

U16

R27

10.0K

0402

R28

10.0K

0402

R169

10.0K

0402

R24

100K

0402

R26

4.7K

0402

R25

100K

0402

R33

100K

0402

R30

100K

0402

R32

100K

0402

R31

100K

0402

D[0:15]

D10

D15

D14

D13

D12

D11

JP7

IDC2X1 DEFAULT=INSTALLED

SJ3

SST25WF040

SOIC8

NAND02

TFBGA63_80_95X120

U15

U24

SOT23-5

SN74LVC1G08

SOT23-5

U25

SN74LVC1G08

SN74AUC1G00

SOT23-5

U26

SOT23-5

SN74LVC1G08

0402

10K

R36

SPIMOSI

R168

0402

SPISCK

RESET_1P8V

0402

0.01UF

C203

0402

0.01UF

C202

0402

0.01UF

C86

R35

4.7K

0402

AWE

ARE

MEMORY

5 155-12-2009_16:42

C85

0.01UF

0402

C84

0.01UF

0402

C83

0.01UF

0402

C82

0.01UF

0402

C81

0.01UF

0402

C80

0.1UF

0402

C79

0.1UF

0402

C78

0.01UF

0402

C92

0.01UF

0402 0402

0.01UF

C91 C90

0.01UF

0402 0402

0.01UF

C89

4 5

SW6

DIP4

SWT018

C88

0.01UF

0402

C87

0.1UF

0402

SPIMISO

NDBUSY#_HOSTD13

NDCLE_HOSTD14

NDALE_HOSTD15

NDWR#_HOSTD11

NDRE#_HOSTD12

NDCE#

NDD7_ETXD1_HOSTD7

NDD6_ERXD0_HOSTD6

NDD5_ETXD0_HOSTD5

NDD4_RMIIREFCLK_HOSTD4

NDD3_ETXEN_HOSTD3

NDD2_MDIO_HOSTD2

NDD1_ERXER_HOSTD1

NDD0_RMIICRSDV_HOSTD0

A18

A19

A[1:19] A1

A10

A11

A12

A13

A14

A15

A16

A17

AMS3

AMS2

AMS1

AMS0

SPI_FLASH_CS

0402

0.01UF

C204

1_8V_SDRAM

ABE1#/SDQM1

ABE0#/SDQM0

SRAS

SCAS

SWE

SA10

A19

A13

A12

A[1:19]

A10

A18

D[0:15]

D11

D12

D13

D14

D15

D10

SMS

SCKE

CLKOUT

3.3V

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

A0212-2007

ADSP-526 EZ-BOARD

Rev

1.1

3D+

D-

GND

4ID

6SHELL

VBUS

USBDM

USBDP

USBID

USBRSET

USBVBUS

USBVDD1

USBVDD2

USBVREF

USBXI

USBXO

BGA208 "USB OTG"

"USB CLK"

C99

10UF

0805

D19

H19

E19

C20

E20

F20

G20

A19

A18

D20

DSP_USBXI

24MHZ

OSC013

R201

1.0M

0402

DNP DSP_USBXO

CON052

USB_OTG_DM

USB_OTG_DP

1206

R167

THERM

DSP USB OTG

6 155-14-2009_17:34

VARISTOR

V5.5MLA

0603

R40

0603

FER1

600

1206

PGB1010603

D10

0603

C98

0.01UF

0402

R38

0402

DNP

C97

1UF

0805

C96

0.01UF

04020402

10K

R37

DNP

0805

10UF

C94

0402

0.1UF

C93

PGB1010603

0603

PGB1010603

0603

5V_USB

C222

18PF

0402

C221

18PF

0402

AGND

1 2 3 4

AGND

AGND AGND

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

A0212-2007

ADSP-526 EZ-BOARD

Rev

1.1

JUMPER

SHORTING

AGND

ADCDAT

ADCLRC

AGND

AVDD

BCLK

CLKOUTCSB

DACDAT

DACLRC

DBVDD

DCVDD

DGND

HPGND

HPVDD

LHPOUT

LLINEIN

LOUT

MICBIAS

MICIN

MUTE

RHPOUT

RLINEIN

ROUT

SCLK

SDIN

VMID

XTI/MCLK

XTO

1234

1 2 3 4

1234

4 NC

2 1 (0dB)

5 (14dB)1

POS. GAIN

"0A"

"ENBL"

"MIC GAIN"

for test purposes, to the Left and Right headphone.

DO NOT switch positions 1 & 2 ON at the same time.

SW10 allows the MICIN signal to be looped back,

0.5 (-6dB)

Ensure that JP6 is on 2&3 or OFF when using SW10.

LINE OUT

HP OUT MIC IN

J3 J4

"MIC SELECT"

"MIC"

"LINE IN"

"HEAD PHONE"

"LINE OUT"

"SPORT"

"AUDIO CLK"

DEFAULT

column is ON, all others OFF.

switch position in left

Table shows the gain if

SW9: MIC GAIN

LINE IN

"AUDIO LPBK"

Positions 3 and 4 allow the disconnect

of LINE IN to LINE OUT

"SPORT 0A ENBL"

SW7 AND SW2 (POSITIONS 1 AND 2) DISCONNECT DSP SPORT 0A FROM CODEC

"I2C ENBL"

SW2 POSITIONS 3 AND 4 ALLOW I2C TO BE DISCONNECTED FROM CODEC

DEFAULT CODEC I2C ADDRESS 0011011

CAN BE CHANGED TO 0011010 IF

R63 REMOVED AND PLACED ON R60

4 5

SW2

DIP4

SWT018

RIGHT_OUT_LPBK

LEFT_OUT_LPBK

RIGHT_IN_LPBK

LEFT_IN_LPBK

RIGHT_IN_LPBK

LEFT_IN_LPBK

RIGHT_OUT_LPBK

LEFT_OUT_LPBK

MUTE

1P8V_CODEC1P8V_CODEC

R59

100K

0402

CSB

MUTE

4 5

SW10

DIP4

SWT018

4 5

SW7

DIP4

SWT018

626

U31

SSM2603

ICS009

ROUT_RDIV

1P8V_CODEC1P8V_CODEC

LLINEIN_RDIV

MICIN_RDIV

R314

1.0M

0402

RLINEIN_RDIV

R312

1.0M

0402

R313

1.0M

0402

RLINEIN_RDIV

LLINEIN_RDIV

MICIN_RDIV FER11

330

0805

FER10

330

0805

FER20

330

0805

R60

100K

0402

DNP

R63

100K

0402

R56

100

0402

R51

100

0402

LOUT_RDIV

RHPOUT_RDIV

LHPOUT_RDIV

MICIN

MICBIAS

LLINEIN

RLINEIN

OSC014

12MHZ

AUDIO_XTOAUDIO_XTI

R202

1.0M

0402

DNP

VMID

SJ1

DEFAULT=2&3

0.1UF

0402

C119

AUDIO CODEC

75-15-2009_10:58 15

2J3

CON050

R57

47.0K

0402 C118

100PF

0603

C117

100PF

0603

C116

100PF

0603

C115

100PF

0603

R55

0603

R54

0603

R53

47.0K

0402

R52

47.0K

0402

CT4

220UF

D2E

CT3

220UF

D2E

R50

47.0K

0402

4 5

SW9

DIP4

SWT018

C114

1UF

0603

C113

1UF

0603

C112

1UF

0603

C111

1000PF

0805

DNP

C110

1000PF

0805

DNP

0.1UF

0402

C109C108

0805

10UF

R49

40.2K

0402

R48

47.0K

0402

C107

220PF

0402

DNP

R46

5.6K

0402

R45

5.6K

0402

R44

5.6K

0402

JP6

IDC3X1

R43

680

0402

0.1UF

0402

C105C104

0805

10UF

CT2

10UF

CAP002

C103

100PF

0603

C102

100PF

0603

C101

100PF

0603

C100

100PF

0603

R42

90.9K

0402

R41

5.6K

0402

CT1

10UF

CAP002

C123

220PF

0402

DNP

C122

10UF

0805

CON050

C121

0.1UF

0402

C120

0805

10UF

RHPOUT_RDIV

LHPOUT_RDIVMICIN

TFS0A_RMIIMDINT#_HOSTCE#

BCLK

DT0PRIA

DR0PRIA

RFS0A

CODEC_DACLRC

CODEC_DACDAT

CODEC_ADCDAT

CODEC_ADCLRC

SCLK

SDIN

MICBIAS_Z

VMID

AVDD

HPVDD

LHPOUT

RHPOUT

LOUT

ROUT

CSB

CODEC_DACLRC

CODEC_DACDAT

CODEC_ADCDAT

CODEC_ADCLRC

0.1UF

0402

C205

C224

18PF

0402

C223

18PF

0402

BCLK

SDIN

SCLKSCL

SDA

RSCLK0A

TSCLK0A

JUMPER

SHORTING

1234

SHGND2

1234

NC1

NC2

NC3

NC4

RCT

RD+

RD-

RX+

RX-

TCM

TCM_

TCT

TD+

TD-

TX+

TX-

1CT:1CT

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

A0212-2007

ADSP-526 EZ-BOARD

Rev

1.1

CON_RJ45_12P

GND

OE OUT

VDD

3.3V

MDIO

MDC

RXD3/NINTSEL

RXD2/MODE2

RXD1/MODE1

RXD0/MODE0

RX_DV

RX_CLK/REGOFF

RX_ER/RXD4

TX_CLK

TX_EN

TXD0

TXD1

TXD2

TXD3

COL/RMII/CRS_DV

CRS/PHYAD4

NRST

CLKIN/XTAL1

XTAL2

EXRES1

VSS/FLAG VDD33A1

VDD33A2

VDD33A3

RXP

RXN

TXN

TXP

VDD_CORE

NINT/TX_ER/TX4

FDUPLEX/PHYAD3

ACTIVITY/PHYAD2

LINK/PHYAD1

SPEED100/PHYAD0

VDDIO

VDD33

JUMPER

SHORTING

1.8V

SHGND2

T/~R

VCCA VCCB

000

001

010

011

100

101

110

111

MODE[2:0]

Power Down Mode

MODE DEFINITIONS

PHY ADDRESS 0x01

10Base-T Half Duplex

10Base-T Full Duplex

100Base-TX Half Duplex

100Base-TX Full Duplex

100Base-TX Half duplex Advertised, Auto Negotiaion

Repeater Mode, Auto Negotiation

All Capable, Auto Negotiation DEFAULT

"ETH MODE"

"FLASH CS"

OFF

"ETHERNET"

"RMII CLK"

OFF

SW1.1

SW1.2

SW1.3

SW1.4

GND

POS. FROM TO DEFAULT FUNCTIONS

ON (RMII CLK disabled), OFF (RMII CLK enabled)

ON (PHY not held in reset), OFF (PHY held in reset)

SW12: ETH Enable

"ETH ENABLE"

SW11: Ethernet Mode Select (SW9.1, SW9.2, SW9.3)

SW11.4 disconnects SPISEL1, for expansion interface (P1.26, P2.21)

"ETH PWR" Use P21,P22 to disconnect power to PHY

PHY (U29)RESET IC (U22)

RMII CLK (U20)

PHY (U29)DSP (U1, PG14)

DSP (U1, PH2) PHY (U29) ON (MDIO PHY U29), OFF (NAND U15, HOST connector P9.27)

ON (MDC PHY U29), OFF ( HOST connector P9.2)

"LINK" "ACTIVITY"

U20

U40

LAN8700 has internal mode pull-up pins. Setting of OFF = 1.

1 10

U40

MAC010A

FXL2T245

R305

100K

0402

3V_PHY

1P8V_PHY

0402

0.01UF

C141 C135

0.01UF

0402

R87

10.0K

0402

R68

4.7K

0402

LINKLED_1P8V

ACTIVITYLED_1P8V

R83

4.7K

0402

1P8V_PHY

3V_PHY

1P8V_PHY

ACTIVITYLED_1P8V

LINKLED_1P8V

1 2

IDC2X1

P22

1P8V_PHY

DEFAULT=INSTALLED

SJ26

R66

4.7K

0402

ERXD0_MODE0

ERXD1_MODE1

ERXD0_MODE0

NDD0_RMIICRSDV_HOSTD0

R67

4.7K

0402

R95

4.7K

0402

C145

.022UF

0603

C132

1000PF

1206

LED2

YELLOW

LED001

3V_PHY

1P8V_PHY3V_PHY

1P8V_PHY

LAN8700

QFN36

U29

1 2

IDC2X1

P21

VDDA33

TXP

R88

49.9

0603

R86

10.0K

0402

RMII_CLKIN

RXP

RXN

C226

15PF

0402

DNP

0603

49.9

R89

C227

15PF

0402

DNP

C225

15PF

0402

DNP

C228

15PF

0402

DNP

1 3

4U20

50MHZ

OSC012

R70

10.0K

0402

R69

10.0K

0402

R84

4.7K

0402

R85

4.7K

0402

MODE2

MDC

RMII_CLKIN

R203

0402

R82

0402

C143

4.7UF

0603

R71

4.99K

0603

TFS0A_RMIIMDINT#_HOSTCE#

C144

0.1UF

0402

NDD1_ERXER_HOSTD1

R193

0402

NDD6_ERXD0_HOSTD6

0402

10K

R72

R192

0402 MODE2

MDIO

R73

4.7K

0402

RMII PHY

8 155-12-2009_16:42

HX1188

ICS007

U28

4 5

SW12

DIP4

SWT018

C133

0.01UF

0402

0603

49.9

R81R80

49.9

0603

R79

49.9

0603

R78

75.0

0603 0603

75.0

R77

0603

49.9

R76

R75

49.9

0603 0603

49.9

R74

1206

1000PF

C131

0603

600

FER13

R65

0805

LED1

GREEN

LED001

4 5

SW11

DIP4

SWT018

C125

3.3UF

0805

0402

330.0

R97R94

330.0

0402

R93

12.4K

0603

R92

0805

R91

49.9

06030603

49.9

R90

C142

10UF

0805

C140

0.01UF

0402 0402

0.01UF

C139 C138

0.01UF

0402

NDD4_RMIIREFCLK_HOSTD4

MDIO

MDC

RESET_1P8V

MDC_HOSTRD#

NDD2_MDIO_HOSTD2

PHY_RESET

SPI_FLASH_CSSPISEL1

PHY_RESET

NDD7_ETXD1_HOSTD7

NDD5_ETXD0_HOSTD5

NDD3_ETXEN_HOSTD3

ERXD1_HOSTD8

R194

0402

VDDA33

TXN

DEFAULT=INSTALLED

SJ27

C264

0.01UF

04020402

0.01UF

C265

1P8V_PHY 3V_PHY

3.3V

1.8V

1.8V5V

1.8V

1 2 3 4

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

A0212-2007

ADSP-526 EZ-BOARD

Rev

1.1

1.8V

1234

1.8V

JUMPER

SHORTING

JUMPER

SHORTING

C1+

C1-

C2+

C2-

R1INR1OUT

R2INR2OUT

T1IN T1OUT

T2IN T2OUT

V+

V-

T/~R

VCCA VCCB

JUMPER

SHORTING

T/~R

VCCA VCCB

JUMPER

SHORTING

JUMPER

SHORTING

COMMON

SW1

SW2

DA_STANDALONE

DA_PWR

GND

VDD_EXT_DSP

DA_SOFT_RESET

RESET

SERIAL PORT

(UART 1)

UART 1 Loop Jumper

"UART LPBK"

http://www.analog.com

Engineer to Engineer Note EE-68 which can be found at

When designing your JTAG interface please refer to the

All USB interface circuitry is considered proprietary and has

been omitted from this schematic.

"NAND"

"ROTARY"

"ENABLE" "JTAG"

"ENCODER"

"UART 1"

"HOST"

"UART SETUP"

"UART SD"

"UART PWR"

"UART ENABLE"

U21, U32, U41

Use P21,P22 to disconnect power to UART

SW5

ROTARY_ENC_EDGE

SWT025

DEFAULT=INSTALLED

SJ29

DEFAULT=INSTALLED

SJ28

1 10

U32

MAC010A

FXL2T245

R104

100K

0402

R107

1.0K

0402

R106

1.0K

0402

R105

1.0K

0402

1P8V_UART

3V_UART

1P8V_UART

DEFAULT=1&2

SJ4

1P8V_UART

3V_UART

PUSHBUTTON1_HWAIT

UART1TX

1 10

U41

MAC010A

FXL2T245

R245

10K

0402

IDC2X1

JP14

3V_UART

1P8V_UART

0402

0.01UF

C146

0402

0.01UF

C151

1615

912

13 8

201

U21

SSOP20

ADM1385ARSZ

3V_UART

R103

100K

0402

DEFAULT=NOT INSTALLED

SJ18

DNP

DEFAULT=NOT INSTALLED

SJ2

P2_P9_ERXD1_HOSTD8

IDC2X1

JP2

R204

10K

0402

JP3

IDC3X1

CON038

0402

0.1UF

C149

R101

10K

0402 0402

10K

R102

0402

0.1UF

C148

IDC7X2_SMTA

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

21P9

IDC16X2_SMT

R99

10K

0402

R185

10K

0402

R100

10K

0402

4 5

SW14

DIP4

SWT018

ROTARY ENCODER, JTAG, RS232, HOST

95-12-2009_16:42 15

4 5

SW13

DIP4

SWT018

C150

0.1UF

0402

0.1UF

C147

0402

0.01UF

C152

NDRE#_HOSTD12

NDWR#_HOSTD11

NDD2_MDIO_HOSTD2

NDCE#_HOSTD10

NDD0_RMIICRSDV_HOSTD0

NDD1_ERXER_HOSTD1

NDD3_ETXEN_HOSTD3

NDD4_RMIIREFCLK_HOSTD4

NDD5_ETXD0_HOSTD5

NDD6_ERXD0_HOSTD6

NDD7_ETXD1_HOSTD7

NDBUSY#_HOSTD13

NDCLE_HOSTD14

NDALE_HOSTD15

RESET_1P8V

PUSHBUTTON2_HOSTADDR

TFS0A_RMIIMDINT#_HOSTCE#

LED2_HOSTACK

MDC_HOSTRD#

LED1_HOSTWR#

PUSHBUTTON1_HWAIT

HOSTD9

0402

10K

R190

WAKEUP_OUT

1 2

IDC2X1

P15

1 2

IDC2X1

P10

3V_UART

DA_SOFT_RESET

RESET_3V

EMU

TMS

TCK

TDI

TDO

TRST

CDG

NDCE#NDCE#_HOSTD10

CZM

CUD

UART1RTS

UART1RX

0402

0.01UF

C267

0402

0.01UF

C266

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

A0212-2007

ADSP-526 EZ-BOARD

Rev

1.1

CLK1+

CLK1-

CLK2+

CLK2-

D10

D11 D12

D13

D14

D15 D16

D17

D18

D19

D20

D21

D22

D23

D24

D25 D26

D27

D28

D29

D30

D31

D5 D6

GND0

GND1

GND10

GND11

GND12

GND13

GND14

GND15

GND16

GND17

GND2

GND3

GND4

GND5

GND6

GND7

GND8

GND9

CLK1+

CLK1-

CLK2+

CLK2-

D10

D11 D12

D13

D14

D15 D16

D17

D18

D19

D20

D21

D22

D23

D24

D25 D26

D27

D28

D29

D30

D31

D5 D6

GND0

GND1

GND10

GND11

GND12

GND13

GND14

GND15

GND16

GND17

GND2

GND3

GND4

GND5

GND6

GND7

GND8

GND9

CLK1+

CLK1-

CLK2+

CLK2-

D10

D11 D12

D13

D14

D15 D16

D17

D18

D19

D20

D21

D22

D23

D24

D25 D26

D27

D28

D29

D30

D31

D5 D6

GND0

GND1

GND10

GND11

GND12

GND13

GND14

GND15

GND16

GND17

GND2

GND3

GND4

GND5

GND6

GND7

GND8

GND9

LOGIC ANALYZER COMPRESSION LAND GRID ARRAY

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B27

B26

B25

B24

B23

DMAX

DNP

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B27

B26

B25

B24

B23

DMAX

DNP

A19

A18

A17

A11

A12

A14

A15

A16

A13

A10

A[1:19]

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B27

B26

B25

B24

B23

DMAX

DNP

PUSHBUTTON1_HWAIT

SPISEL1

SPIMOSI

SPIMISO

PPIFS1

DT0PRIA

PPIFS2

RFS0A

DR0PRIA

TSCLK0A

RSCLK0A

SPISCK

LED2_HOSTACK

LED1_HOSTWR#

PUSHBUTTON2_HOSTADDR

TFS0A_RMIIMDINT#_HOSTCE#

MDC_HOSTRD#

UART1TX

UART1RTS

CZM

CDG

CUD

PPICLK

HOSTD9

NDCE#_HOSTD10

NDWR#_HOSTD11

NDBUSY#_HOSTD13

NDRE#_HOSTD12

NDCLE_HOSTD14

NDALE_HOSTD15

ERXD1_HOSTD8

RESET_1P8V

NDD7_ETXD1_HOSTD7

NDD6_ERXD0_HOSTD6

NDD4_RMIIREFCLK_HOSTD4

NDD5_ETXD0_HOSTD5

NDD2_MDIO_HOSTD2

NDD3_ETXEN_HOSTD3

NDD1_ERXER_HOSTD1

NDD0_RMIICRSDV_HOSTD0

AMS0

AMS1

AMS3

ARE

AMS2

AOE

SCAS

SCKE

ARDY

SMS

SWE

SRAS

AWE

SA10

CLKOUT ARE

D[0:15] D0

D10

D11

D12

D13

D14

D15

PPID0

PPID1

PPID2

PPID3

PPID4

PPID5

PPID6

PPID7

LED0

PPID9

UART1RX

LOGIC ANALYZER CONN

10 155-13-2009_14:01

1.8V

3.3V

1.8V

1.8V3.3V

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

A0212-2007

ADSP-526 EZ-BOARD

Rev

1.1

1.8V

3.3V

1.8V

JUMPER

SHORTING

3.3V

1 2 4 5 6

1.8V

JUMPER

SHORTING

3.3V

T/~R

VCCA VCCB

T/~R

VCCA VCCB

RESET

SENSE1

SENSE2

VDD

WDI

MR RESET

JUMPER

SHORTING

DSP

(SW16)

pushbutton

DSP

(U1, PG0)

DSPPushbutton 1

(SW19)

U27

"RESET"

"WAKE"

"PWR DOWN"

"PB2"

"PB1"

"GPIO ENABLE"

U22

U4 U4 U3 U3

"RESET"

"SENSE2 SELECT"

"LED2" "LED1"

set point 3.16V

"LED0"

2 (ON) (SW15) (U1, PG13)

ON (PB2), OFF (host connector P9.8, OTP flag for writes

SW20.8, OTG voltage select SW13.7, expansion interface

P2.40, P4.40, J1.53)

SW20 Position FROM TO FUNCTION

1 (ON)

(Default)

(SW16)

Power down

pushbutton

Pushbutton 2

(U1, PG12)

(U1, PG15)

Wake

3 (OFF)

4 (OFF)

5 (OFF) _1P8V (U3)

OTP_FLAG

(U1, PG13)

ON (PB1), OFF (UART 1 CTS U21, HOST connector

P9.12, expansion interface P2.37, P4.37, J1.52)

OFF (LED2 not driven by power down push-

button). ON (SW16 drives PG12).

ON (connects wake pushbutton SW17 to PG15).

NOTE requires SW20.2 OFF, SW20.6 OFF and

JP16 installed.)

6 (OFF) USB_VRSEL

(U23) (U1, PG13) power. NOTE requires SW20.2 OFF, SW20.5 OFF.

ON (PG13 controls USB_VRSEL PG13 for OTG host

ON (PG13 controls OTP flag for OTP writes.

"RST LED"

"LED ENABLE"

DEFAULT=2&3

SJ5

BAT_P

8U22

ADM13305-4

SOIC8

R122

100K

0402

R112

100K

0402

DNP

R113

100K

0402

DNP

R132

100K

0402

DNP

R64

100K

0402

R62

100K

0402

R96

100K

0402

R246

10K

0402

1 14

MLP014A

FXL4T245

1 10

MAC010A

FXL2T245

MOMENTARY

SWT024

SW16

C154

1UF

0603

C153

1UF

0603

C155

1UF

0603

C159

1UF

0603

R119

100

0402

R116

100

0402

R133

100

0402

R129

100

0402

R131

100K

0402

R123

100K

0402

R171

100K

0402

R126

100K

0402

R118

100K

0402

R117

100K

0402

R134

100K

0402

R128

100K

0402

TP22

R308

0402

R207

100K

0402

DEFAULT=1&2

SJ16

RESET_1P8V

JP11

IDC3X1

U27

SN74LVC1G08

SOT23-5

6 7

SW20

DIP6

SWT017

R124

0402

10K R120

430

0402

LED001

RED

LED7

DEFAULT=2&3

SJ6

SWT024

MOMENTARY

SW19

R125

100K

0402

WAKEUP_OUT

LED1_HOSTWR#

WAKEUP_OUT

OTP_FLAG

JP5

IDC3X1

WAKEUP_OUT

11 10

74LVC14A

SOIC14

R110

430

0402

JP10

IDC3X1

R114

430

0402

R109

430

0402

5 6

74LVC14A

SOIC14

R178

76.8K

0402

9 8

74LVC14A

SOIC14

LED001

YELLOW

LED4

R177

18K

0402

YELLOW

LED001

LED3

1 2

74LVC14A

SOIC14

3 4

74LVC14A

SOIC14

13 12

74LVC14A

SOIC14

0603

R127

0603

R115

0402

0.01UF

C156C158

0.01UF

0402

R121

0402

10K

SWT024

MOMENTARY

SW18

YELLOW

LED001

LED5

R130

0603

R135

MOMENTARY

SWT024

SW15

RESET, LEDS

11 155-15-2009_16:56

0402

0.01UF

C160

0402

0.01UF

C157

LED0

MOMENTARY

SWT024

SW17

0402

0.01UF

C212

0402

0.01UF

C215

0402

0.01UF

C214

DA_SOFT_RESET

RESET_3V

PUSHBUTTON2_HOSTADDR

USB_VRSEL

TFS0A_RMIIMDINT#_HOSTCE#

PUSHBUTTON2_HOSTADDR

OTP_FLAG_1P8V

PUSHBUTTON1_HWAIT

LED2_HOSTACK

PUSHBUTTON2_HOSTADDR

WAKEUP_OUT

RESET_3V

R208

10K

0402

OTP_FLAG_1P8V

LED2_HOSTACK

1.8V3.3V

1.8V 3.3V

3.3V

1.8V 3.3V

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

A0212-2007

ADSP-526 EZ-BOARD

Rev

1.1

JUMPER

SHORTING

JUMPER

SHORTING

RSVD2RSVD1

3.3V1

GND3

GND1

PWR_IN2

GND4VDDIO2

VDDIO1

3.3V2

RSVD5

RSVD7

RSVD3

PWR_IN1

RSVD4

RSVD6

RSVD8

GND2

DATA24

DATA20

DATA18

DATA16

DATA23

DATA17

DATA21

DATA19

DATA30

DATA27

DATA29 DATA28

DATA25

DATA22

DATA26

DATA31

DATA15

DATA10

DATA6

DATA9

DATA12DATA13

DATA11

DATA14

ADDR10

AREARDY

ADDR0

ADDR2

ADDR4

ADDR6

ADDR3

ADDR5

ADDR17

ADDR15

ADDR16

ADDR27 ADDR26

ADDR29 ADDR28

ADDR31 ADDR30

AWE AOE

ADDR19 ADDR18

ADDR21 ADDR20

ADDR23 ADDR22

ADDR25 ADDR24

ADDR12ADDR13

ADDR14

ABE1

GPIO3

DATA3

DATA5

GPIO1

AMS1

AMS3

ABE3

BGH

CLKOUT

DATA1

AMS2

ABE0

ABE2

NMI

GPIO2

AMS0

ADDR1

ADDR8ADDR9

ADDR11

ADDR7

DATA7

RESET

DATA0

GPIO4

DATA2

DATA4

DATA8

3.3V1

3.3V2

DRPRI

DRSEC

GND1

GND2

GND3

GND4

GND5

GND6

GPIO2

GPIO4

RFS

RSCLK

RSVD1

RSVD3

RSVD5

RSVD7

SDA

SPISEL1

SPISEL3

SPISS

TFS

TIMER

UARTCTS

UARTRX

PWR_IN1

PWR_IN2

VDDIO1

VDDIO2

RSVD9RSVD8

SPISEL2

SPICLK

DTPRI

TSCLK

DTSEC

SPIMOSI

SPIMISO

SCL

UARTTX

UARTRTS

RESET

GPIO1

GPIO3

WAKE

RSVD2

RSVD4

RSVD6

1.8V

3.3V1

3.3V2

DRPRI

DRSEC

GND1

GND2

GND3

GND4

GND5

GND6

GPIO2

GPIO4

RFS

RSCLK

RSVD1

RSVD3

RSVD5

RSVD7

SDA

SPISEL1

SPISEL3

SPISS

TFS

TIMER

UARTCTS

UARTRX

PWR_IN1

PWR_IN2

VDDIO1

VDDIO2

RSVD9RSVD8

SPISEL2

SPICLK

DTPRI

TSCLK

DTSEC

SPIMOSI

SPIMISO

SCL

UARTTX

UARTRTS

RESET

GPIO1

GPIO3

WAKE

RSVD2

RSVD4

RSVD6

RSVD7

RSVD2

SDA

RSVD1

RSVD4 RSVD5

RSVD3

RSVD6

GND6

TIMER2/GPIO TIMER1/GPIO

GND1

GND2

GND3

GND4

PWR_IN2

VDDIO1

PPI0D0

PPI0CLK

PPI0D1

PPI0D10PPI0D11

PPI0D12PPI0D13

PPI0D14PPI0D15

PPI0D16PPI0D17

PPI0D2PPI0D3

PPI0D4PPI0D5

PPI0D6PPI0D7

PPI0D8PPI0D9

PPI0FS1 PPI0FS2

PPI0FS3

PPI1CLK

PPI1D10

PPI1D14

PPI1D16

PPI1D8

TIMER3/GPIO

PPI1FS2

PP1D0/PPI0D18

PPI1D2/PPI0D20

PPI1D4/PPI0D22

PPI1D6

PPI1D12

PPI1FS1

PPI1FS3

PPI1D1/PPI0D19

PPI1D3/PPI0D21

PPI1D5/PPI0D23

PPI1D9

RESET

PWR_IN1

GND5 3.3V1

3.3V2

VDDIO2

PPI1D7

PPI1D13

PPI1D11

PPI1D15

PPI1D17

SCL

812 4567

JP8 SELECTS 5V SOURCE FOR EXPANSION CONNECTORS

EITHER WALL POWER(1&2, 3&4) OR VR7(5&6, 7&8)

"EXP. 5V SELECT"

"SPORT 1 ENABLE"

SW21

DIP8

SWT016

R195

0402

R98

0402 P4_HOSTD9

SPISCK P4_SPISCK

R196

0402

SDA

SCL

67 68

35 36

2827

3029

3231

3433

2019

2221

2423

2625

13 14

9 10

IDC35X2_SMTA

5049

IDC25X2_SMTA

R199

0402

R198

0402

R197

0402 P4_SPIMISO

P4_SPIMOSI

P4_ERXD1_HOSTD9

P2_P9_ERXD1_HOSTD8ERXD1_HOSTD8

SPIMISO

SPIMOSI

P4_UART1TX

P4_UART1RX

P4_CUD

P4_CZM

P4_PPID9

P4_LED0

P4_UART1RTS

P4_CDG

UART1RX

UART1TX

CDG

UART1RTS

LED0

PPID9

CZM

CUD

NGEI_PWR_IN

5V_EXPANSION

P4_SPISCKP4_HOSTD9

P4_ERXD1_HOSTD9

P2_P9_ERXD1_HOSTD8

P4_UART1RX

P4_UART1TX

P4_CZM

P4_CUD

P4_CDG

P4_UART1RTS

P4_LED0

5049

IDC25X2_SMTA

DT0PRIA PPICLK

PPIFS2PPIFS1

PPID9

CZM

SCL

RSCLK0A

SPIMISO

DR0PRIADT0PRIA

SPIMOSI

TSCLK0A

TFS0A_RMIIMDINT#_HOSTCE#

SPISEL1

HOSTD9

SPIMOSI

DR0PRIA

SDA

RFS0A

PUSHBUTTON2_HOSTADDR

LED1_HOSTWR#

RESET_1P8V

PUSHBUTTON1_HWAIT

LED2_HOSTACK

DR0PRIA

RSCLK0ARESET_1P8V

RFS0A

LED0

UART1RTS

CDG

UART1TX

PPID7

CUD

UART1RX

8788

104

101102

100

103

84 83

6768

3536

28 27

30 29

32 31

34 33

20 19

22 21

24 23

26 25

1314

910

QMS52X2_SMT

DEFAULT=1&2

SJ7

DEFAULT=3&4

SJ8

5V_EXPANSION

EXPANSION INTERFACE

12 155-15-2009_16:56

PPID6

PPID2

RESET_1P8V

SPISEL1

LED1_HOSTWR#

SDA

SPISEL1

PPID1

PPID3

PPID5

LED1_HOSTWR#

PUSHBUTTON2_HOSTADDR

PUSHBUTTON1_HWAIT

LED2_HOSTACK

SPIMISO

RFS0A

SPISCK

SPISEL1

LED1_HOSTWR#

PPID0

PPID4

D[0:15]

D11

D13

D15

D1 D0

D10

D12

D14

AMS2

AMS0

ARDY

A[1:19]

A13

A15

A19

A17

A11

A10

A12

A14

A16

A18

CLKOUT

ABE1#/SDQM1

AWE

ARE

AOE

ABE0#/SDQM0

AMS3

AMS1

RESET_1P8V

PUSHBUTTON1_HWAIT

PUSHBUTTON2_HOSTADDR

LED1_HOSTWR#

LED2_HOSTACK

1 2

3 4

5 6

7 8

JP8

IDC4X2

P4_PPID9

P4_SPIMOSI

P4_SPIMISO

WAKEUP_OUT

SCL

HOSTD9

JUMPER

SHORTING

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

A0212-2007

ADSP-526 EZ-BOARD

Rev

1.1

3.3V

JUMPER

SHORTING

AGND2

COPPER

V_SELECT

3.3V

V+V-

TRIM

FLG

GND

IN1 OUT1

OUT2

COMP

GND

SW1

COMP

GND

SW1

GND

OUT

ADJ

DECOUPLING AT USB CONNECTOR

OTP POWER

"OTP FLAG ENABLE"

datasheet for exact details

5V @ 500mA "5V USB"

"VR7 ENABLE"

REMOVE JP9 IF USING VR7 FOR

EXPANSION CONNECTOR 5V POWER

BATTERY BOOST TO 5V @ 500MA STEP UP REGUALTOR

Warning: Only install jumper JP16

when programming OTP. See BF526

R47

47.0K

0402 D25

GSOT05

SOT23-3

C10

10UF

1210

5V_USB

R160

15K

0402

C197

1UF

0805

DNP

2.2UF

0805

C246

R255

0603

10K

DNP

D23

ESD5Z2.5T1

SOD-523

D13

SK12

DO-214AA

CT5

150UF

D14

SOD-123FL

MBR130LSFT1G

C248

0603

1UF

DNP

R258

0603

10K

DNP

R259

0603

10.0K

R260

21.5K

0603

ADP1710

TSOT5

VR10

C240

0805

2.2UF

VR7

ADP1610

MSOP8

VR9

ADP1610

MSOP8

D12

SOD-123FL

MBR130LSFT1G

7 6

MIC2025-2

SOIC8

JP16

IDC2X1

2 3

SI2333DS

SOT23D

D16

SOD-123FL

MBR130LSFT1G

BAT_P

C11

1UF

0603

NGEI_PWR_IN

100PF

0603

DNP

R310

1206

10K

0402

R173

C206

10UF

1210

3.3UH

IND023

D17

SOD-123FL

MBR130LSFT1G

3ADR550B

SOT23-3

U35

1UH

IND019

D15

SOD-123FL

MBR130LSFT1G

C247

1210

10UF

R253

0603

1.91K

R257

140.0K

0603

C244

10UF

1210

0603

1UF

C269

C245

0603

0.1UF

R252

0603

2.0K

R254

0603

3.01K1.00K

0603

R311

DNP

C241

0402

22000PF

C249

10UF

1210

C270

1UF

0603

DNP

C250

0603

2200PF

R256

0603

24.0K

IND018

22UH

R249

0402

10K C243

10UF

1210

R261

0603

R248

0603

TP18

R172

0402

10.0K

C208

0402

22000PF

MMBT3904

SOT23

R39

47.0K

0402

C207

10UF

1210

DEFAULT=INSTALLED

SJ9

1 2

JP9

IDC2X1

R174

0402

30.9K

C209

100PF

0603

R175

100K

0603

TP10

USB_VRSEL

OTP POWER, 5V_USB FET

13 155-13-2009_9:43

DEFAULT=NOT INSTALLED

SJ19

DNP

FUEL_GAUGE_VCC

VDDOTP

OTP_ENABLE

OTP_FLAG

R187

0402

10K

DNP

R61

47.0K

0402

JUMPER

SHORTING

3.3V

1.8V

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

A0212-2007

ADSP-526 EZ-BOARD

Rev

1.1

BAT

BAT_LOWBI/TOUT

SCL

SDA

SRN

SRP

VCC

VSS

BAT_GD

JUMPER

SHORTING

JUMPER

SHORTING

JUMPER

SHORTING

ADJ

BAT

CS DRV

GND

TIMER

CHG

1234

YES

"CHARGING"

"BAT GOOD" "BAT LOW"

FUEL GAUGE ADDRESS 0xAA

"BATTERY"

"OFF"

"ON"

"CHG GPIO"

"CHG CNTRL"

"R274 JMP"

U36

Low

Medium

Selectable

Control

Shutdown

Full Charge

WALL

USB

YES

OFF

1&2

JP17

X X

P23

OFF

OFF 32K

169K

32/169K

0/169K

Resistance Charge

Rate

OPEN 750 mA

375 mA

NONE

0/375 mA

MODE

Charge rate selection

Any jumper setting has no affect

Rate is selectable by the processor's flag, use JP15 to chose the flag pin.

Setting the flag high selects 83 mA and setting the flag low selects 375 mA charge rates.

3JP15 needs to be set to positions 1&2 (PG0), 3&4 (PG11), or 5&6 (PG12),

selecting the processor port pin to control the selection.

100 mAOFF

2&3

100/375 mA

BATTERY CHARGER

FUEL GAUGE

"BATT INSTALLED"

"GAUGE SIGNALS"

"-"

"+"

GSOT05

SOT23-3

BRD_POWER

C273

10UF

1210

D18

MBRS540T3G

SMC

USB_WALL

FUS005

4 5

SW4

DIP4

SWT018

U36

AD8619ARUZ

TSSOP14

VR8

NJT4030P

SOT-223

4 1

MSOP8

ADP2291

U37

1P24

CON064

R269

15K

0402

C257

0.1UF

0603

R293

100K

0603

BAT_LOW

BAT_GD

SDA

SCL

SI2333DS

SOT23D

R289

100K

0603

R265

100K

0603

R268

100K

0603

R282

100K

0603

R286

100K

0603

R266

1.00K

0603

R296

1.00K

0603

R280

1.00K

0603

R291

0603

R278

0603

R283

0603 R284

1.0M

0603

DNP

R298

1.0M

0603

DNP

R267

1.0M

0603

DNP

DEFAULT=UNINSTALLED

SJ20

DNP

DEFAULT=INSTALLED

SJ22DEFAULT=1&2

SJ21

BQ27500

U38

SON12

SI2333DS

SOT23D

5V_USB

1 2

IDC2X1

P25

1Q1

SI1012R

SC-75A

JP17

IDC3X1

C258

470PF

0603

U36

AD8619ARUZ

TSSOP14

U36

AD8619ARUZ

TSSOP14

U36

AD8619ARUZ

TSSOP14

R272

0.02

1206

R275

169.0K

0402

SW22

SPDT

SWT026

POWER, INPUT OR'ING, CHARGE, FUEL GAUGE

155-12-2009_16:42 14

SI2333DS

SOT23D

C261

470PF

0603

R290

100K

0603

R288

1.00K

0603

TP21

R285

0.2

0805

R281

1.00K

0603

R279

100K

0603

C259

1UF

0603

R277

100K

0603

C256

10UF

0805

R276

0603

1 2

IDC2X1

P23

R274

40K

0402

R273

680

0402

10K

R300

THERMAT-2

C255

0.1UF

0603

R271

1.8M

0402

R270

18K

0402

C254

0.1UF

0603

TP20

C253

2.2UF

0805

LED10

YELLOW

LED009

TP19

C252

470PF

0603

R264

1.00K

0603

C251

0.1UF

0603

YELLOW

LED001

LED9

R263

430

0402

LED8

LED001

GREEN

0402

430

R262

5 6

1JP15

IDC3X2

BAT_P

CHARGE_OFF

BRD_POWER

WALL_SENSE

BAT_P

BAT_INSTALLED

FUEL_GAUGE_VCC

BAT_INSTALLED

BAT_GD

BAT_LOW

CHARGE_OFF

LED2_HOSTACK

PUSHBUTTON1_HWAIT

LED1_HOSTWR#

DEFAULT=UNINSTALLED

SJ10

DNP

BAT_P

SHGND

COPPER

AGND4

AGND3

3.3V

AGND4

A B C

20 Cotton Road

Nashua, NH 03063

A B C D

PH: 1-800-ANALOGD

Title

Size Board No.

Date Sheet of

DEVICES

ANALOG

A0212-2007

ADSP-526 EZ-BOARD

Rev

1.1

1.8V 3.3V

AGND3

3.3V

SHGND

COPPER

1.8V

3.3V

JUMPER

SHORTING

3.3V

DREF

GREF

SREF

GND3

GND4

OUT

ADJ

GND1

GND2

1.8V

AGND

COMP

GND1

GND2

GND3

GND4

IN LX1

LX2

OUT_SENSE

PGND

PWIN1

PWIN2

LFCSP16

3.3V

JUMPER

SHORTING

JUMPER

SHORTING

AGND

COMP

GND1

GND2

GND3

GND4

IN LX1

LX2

OUT_SENSE

PGND

PWIN1

PWIN2

JUMPER

SHORTING

AD0

AD1

GND

SCL

SDA

VCC

VLOGIC

EN GND

INPUT OUTPUT

"VDDINT"

"VDDMEM"

"5.0V"

"VDDEXT"

1.8V @1A

DIGIPOT ADDRESS 0x30

3.3V @1A

U39

"SDRAM"

1.1 to 1.4V @ 500mA

1.8V @ 20mA

15155-14-2009_17:34

1 5

VR1

ADP120-AUJZ18R7

TSOT5

MH1

4 7

AD5258

MSOP10

U34

D19

SK12

DO-214AA

ESD5Z2.5T1

SOD-523

ESD5Z2.5T1

SOD-523

D21

SK12

DO-214AA

D22

SK12

DO-214AA

DEFAULT=INSTALLED

SJ11

D11

GSOT03

SOT23-3

MBRS540T3G

SMC

1P8V_CODEC

ESD5Z2.5T1

SOD-523

D20

SK12

DO-214AA

2.7UH

IND022

1 16

14 10

ADP2105-3.3V

VR2

LFCSP16

TP17

DEFAULT=INSTALLED

SJ13

DEFAULT=INSTALLED

SJ12

R307

5.6K

0402

C194

0.1UF

0603

1 16

14 10

ADP2105-1.8V

VR3

R306

2.05K

0402

C190

22UF

1210

2.7UH

IND022

P14

CON045

0402

1.2K

R234

VR5

ADP1715

MSOP8

U39

GTL2002DC

VSSOP8

1 2

IDC2X1

P12

R157

0.1

0603

R136

0603

R137

0603

DNP

BRD_POWER

C13

1UF

0603

R111

0402

C12

10UF

0805

R108

0402 DNP

WAKEUP_OUT

R244

0402

C237

0.1UF

0402

C234

4.7UF

0603

DEFAULT=INSTALLED

SJ14

C268

0.01UF

0402

C263

0.01UF

0402

R304

200.0K

0402

SDA_3V

SCL_3V

FER17

1206

600

R155

1206

C193

1000PF

0603

R302

680

0402

R301

680

0402

10K

0402

R162

DNP

R156

0.1

0603

R165

154.0K

0402

SCL

SDA

R161

0402

10K

DNP

C235

4.7UF

0603

R158

0.1

0603

1 2

IDC2X1

P13

0603

4.7UF

C238

C236

0.01UF

0402

1 2

IDC2X1

P11

R188

0.1

0603 1_8V_SDRAM

VDDINT

POWER, VDDINT, VDDEXT, 3.3V

MH3 MH4

MH2

R235

2.67K

0402

1206

4.3

R233

FER19

FER002

190

C184

0.1UF

0603

C183

1000PF

0603

C185

120PF

0603

R164

75.0K

0603

C177

22UF

1210

C181

4.7UF

0603

C195

68PF

0603

TP9

TP6

C187

22UF

1210

C180

1206

1000PF

C191

10UF

1210

R154

1206

TP4 W2

C179

4.7UF

0805

C178

4.7UF

0805

C189

4.7UF

0805

C188

4.7UF

0805

C182

1206

1000PF

TP5

TP12

1 2

IDC2X1

P19

R237

1.0K

0402

R236

4.3

1206 TP7TP8

600

FER18

1206

WALL_SENSE

BRD_POWER

VDDMEM

C262

0.01UF

0402

VDDEXT

BRD_POWER

WAKEUP_OUT

D24

GSOT05

SOT23-3

ADSP-BF526 EZ-Board Evaluation System Manual I-1

IINDEX

ADM1385 line driver/receiver (U21), 1-24

ADP1715 linear regulator (VR5), 1-30

ADP2105 converter (VR2), 1-31

AMS0-3 select lines, 1-17

analog audio interface, See audio

architecture, of this EZ-Board, 2-2

ASYNC (asynchronous memory control)

external memory banks 0-3, 1-16

audio

interface, 1-22

codec SPORT connect (SW2, SW7), 1-22,

2-11

codec (U31), 1-19, 1-28

dual connectors (J3-4), 1-23, 2-31

battery

ADP2291 battery charger, 1-32, 2-18, 2-24,

2-26

charge LED (LED10), 2-29

charge rate selection, 1-33

connector (P24), 2-35

GD LED (LED8), 2-28

holder connector (J6), 2-32, 2-35

installed jumper (P25), 2-18, 2-26, 2-29

low LED (LED9), 2-29

switch (SW22), 2-18

bill of materials, A-1

board design database, 1-37

board schematic (ADSP-BF526), B-1

boot

modes, 2-10

mode select switch (SW1), 1-18, 1-20

burst flash memory, xiii

CFG WP jumper (JP7), 2-21

CHG control jumper (JP17), 2-24

CHG GPIO jumper (JP15), 2-23

audio codec, See audio

code security, 1-13

configuration, of this EZ-Board, 1-3

connectors

diagram of locations, 2-30

J1 (expansion interface II), 1-29, 2-31

J2 (RS-232), 2-31

J3-4 (dual audio), 1-23, 2-31

J5 (Ethernet), 1-22, 2-32

J6 (battery holder), 2-32, 2-35

P14 (power), 1-9, 1-10, 2-29, 2-35

P1 (JTAG), 1-9, 1-28, 2-32

P24 (battery), 2-35

P2 (expansion interface II), 1-25, 1-29, 2-33

P3 (PPI, expansion interface II), 1-20, 1-29,

2-33

P4 (expansion interface II), 1-29, 2-33

P5-7 (land grid array), 1-29, 2-33

P8 (USB OTG), 1-10, 1-24, 2-29, 2-34

P9 (host interface), 1-18, 2-34

ZP1 (debug agent), 2-35

contents, of this EZ-Board package, 1-3

Index

I-2 ADSP-BF526 EZ-Board Evaluation System Manual

core voltage, 2-2

CTS signal, 1-25

CUD (up) signal, 1-20

Das U-Boot, universal boot loader, 1-19

debug agent connector (ZP1), 2-35

default configuration, of this EZ-Board, 1-3

DIP switch, See SW20

down signal (CDG), 1-20

Ethernet

interface, xiv, 1-21

connector (J5), 1-22, 2-32

enable switch (SW12), 1-18, 1-21, 2-14

LEDs (LED1-2), 1-35, 2-28

mode switch (SW11), 1-21, 2-13

PHY IC (U29), 1-18

PWR jumpers (P21-22), 1-35, 2-25

evaluation license

CCES, 1-12

example programs, 1-37

EXP 5V select jumper (JP8), 2-21

expansion interface II

connections, 1-18, 1-19

J1 connector, 1-29, 2-31

P2 connector, 1-25, 1-29, 2-33

P3 connector, 1-20, 1-29, 2-33

P4 connector, 1-29, 2-33

UART0 (P2), 1-25

UART1 (P4), 1-25

external memory, 1-14, 1-16

EXT_WAKE signal, 1-35

features, of this EZ-Board, xiii

FET switch (U23), 1-24

flag pins, See programmable flags by name (PFx,

PGs, PHx, PJx)

flash memory enable switch (SW6), 2-12

fuel gauge (U38), 1-32, 2-28

general-purpose IO pins (GPIO), 1-26, 2-14,

2-15, 2-16, 2-28

GPIO enable switch, See SW20

HOSTACK signal, 1-27

HOSTADDR signal, 1-24, 1-27

HOSTD10 signal, 1-18

host interface connector (P9), 1-18, 2-34

HOSTWR signals, 1-27

HWAIT port, 1-25

I2C voltage translator, 1-30

installation, of this EZ-Board, 1-9

CCES, 1-5

IO voltage, 2-2

JTAG

interface, 1-28

connector (P1), 1-9, 1-28, 2-32

ADSP-BF526 EZ-Board Evaluation System Manual I-3

Index

jumpers

diagram of locations, 2-19

JP10 (SENSE2 select), 2-22

JP11 (RST/ETH LED), 1-35, 2-22

JP14 (UART SD), 1-35, 2-23

JP15 (CHG GPIO), 2-23

JP16 (OTP flag enable), 2-23

JP17 (CHG control), 2-24

JP2 (UART1 loopback), 2-20

JP3 (UART1 enable), 1-20, 1-25, 1-35, 2-20

JP5 (LED enable), 1-35, 2-20

JP6 (mic select), 1-23, 2-21

JP7 (CFG WP), 2-21

JP8 (EXP 5V select), 2-21

JP9 (VR7 enable), 2-21

P11 (VDDEXT power), 1-36, 2-25

P12 (VDDMEM power), 1-36, 2-25

P13 (VDDINT power), 1-36, 2-25

P19 (SRAM power), 1-36

P21-22 (ETH PWR), 1-35, 2-25

P23 (R274 JMP), 2-26

P25 (BATT installed), 2-18, 2-26, 2-29

land grid array connectors (P5-7), 1-29, 2-33

LED2_HOSTACK signal, 1-28

LED enable jumper (JP5), 1-35, 2-20

LEDs

diagram of locations, 2-27

LED10 (battery charge), 2-29

LED1-2 (Ethernet), 1-35, 2-28

LED3-5 (PF8, PG11-12), 1-26, 2-28

LED4 (USB monitor), 1-10

LED7 (reset), 2-28

LED8 (batt GD), 2-28

LED9 (battery low), 2-29

license restrictions, 1-13

Lockbox secure technology, 1-13

MAC address, 1-21

media independent interface (MII), 1-21

Media Instruction Set Computing (MISC), xi

memory map, of this EZ-Board, 1-14

microphone

gain switch (SW9), 1-22, 2-12

headphone select (SW10), 1-23, 2-13

select jumper (JP6), 1-23, 2-21

Micro Signal Architecture (MSA), xi

NAND

flash memory interface, 1-18

enable switch (SW3), 1-18

NDCE#_HOSTD10 signal, 1-18

notation conventions, xxi

oscilloscope, 1-36

OTP_FLAG signal, 1-27

OTP memory

flag enable jumper (JP16), 2-23

writes, 1-31, 2-24

package contents, 1-3

parallel flash memory, 1-17