78M6610+PSU/C09T - Maxim Integrated

78M6610+PSU

Energy Measurement Processor

for Single-P h ase P ower-

Supply Units

DATA SHEET

19-6396; Rev 3; 8/14

DESCRIPTION

The 78M6610+PSU is a single-core energy measurement

processor for single-phase power supplies. It is designed

specifically for real-time monitoring at the input of AC/DC

power converters used in data centers and IT server rooms.

It is available in either a 24-pin QFN or 16-pin TSSOP

package for optimal space savings.

The 78M6610+PSU provides four analog in puts (two

differential and two single ended) for interfacing to voltage,

current, and two optional temperature sensors. Scaled

voltages from the sensors are fed to the single converter

front-end utilizing a high-resolution delta-sigma converter.

An embedded 24-bit energy measurement processor (EMP)

and firmware performs all the necessary computation,

compensation, and data formatting for accurate, real-time

reporting to the host. With integrated flash memory, the

78M6610+PSU is a completely autonomous solution

capable of storing nonvolatile data such as calibration

coefficients and input configuration settings.

The 78M6610+PSU is designed to interface to the host

processor via the UART interface. Alternatively, SPI or I2C

may also be used. Supported current sensors include

Current Transformers (CT) and Resistive Shunts.

FEATURES

• Delta-sigma ADC with precis ion vo ltag e

reference

• Internal or external oscillator timing reference

• SPI, I2C, or UART interface opt ions with

configurable I/O pins for alarm signaling,

address pins, or user control

• 24-bit energy measurement processor (EMP)

with integrated firmware and flash memory

provides the us er with:

o True RMS calculations for current,

voltage, line frequency, real power,

reactive power, apparent p o wer, and

power factor

o Compensation for ambient temperature,

sensor tolerances, offsets, and EMI filter

components

o Real-time data accumulation based on an

integer number of AC cycles

o Quick calibration routines for

manufacturability

o Up to two voltage inputs for optional

connection to thermal sensors

Measurement

Processor

RAM

FLASH

UART

SPI

I2C

Digital

I/O

Single Converter

Front End

MUX ADC

78M6610+PSU

Voltage

Sensor

Current

Sensor

Thermistor

Host

Controller

Rev 3 1

78M6610+PSU Data Sheet

Table of Contents

1 On-Chip Resources Overview ........................................................................................................... 5

1.1 Clock Management ...................................................................................................................... 6

1.2 Power-On Reset, WD Timer, and Reset Circuitry ....................................................................... 7

1.3 Analog Front-End and Conversion .............................................................................................. 8

1.4 24-Bit Energy Measurement Processor (EMP)............................................................................ 8

1.5 Flash and RAM ............................................................................................................................ 8

1.6 Com munication Peri phera l s ......................................................................................................... 8

1.7 Multi-Purpose Digital I/O Pins ...................................................................................................... 9

1.8 Alarm Pins (ACFAULT, ACCRIT) ................................................................................................ 9

2 Functional Descriptio n and Operation ........................................................................................... 10

2.1 Voltage and Current Inputs Conditioning ................................................................................... 10

2.1.1 High Pass Filters (HPF) and Offset Correction .............................................................. 10

2.1.2 Phase Compensat ion .................................................................................................... 10

2.2 Current and Voltage RMS Calculations ..................................................................................... 11

2.3 Power Calculations and Power Factor ....................................................................................... 12

2.3.1 Active Power Calculation ............................................................................................... 12

2.3.2 Appar ent Po wer ............................................................................................................. 12

2.3.3 Power Factor.................................................................................................................. 12

2.3.4 Reac tive Po wer .............................................................................................................. 12

2.4 Fundamental and Harmonics Calculations ................................................................................ 13

2.5 Accumulation Inter va l ................................................................................................................. 13

2.6 Zero-Crossing Detection ............................................................................................................ 14

2.7 Alarms ........................................................................................................................................ 14

2.8 Voltage and Current Min/Max and Peak Tracking ..................................................................... 15

2.8.1 Voltage and Current Min/Max Tracking ......................................................................... 15

2.8.2 Voltage and Current Peak Tracking .............................................................................. 15

2.9 X+Y Capacitor Current and I/R Voltage Drop Compensation ................................................... 15

2.9.1 X+Y Capacitor Compensation ....................................................................................... 15

2.9.2 I/R Voltage Drop Compensation .................................................................................... 16

2.10 External Temperature Monitor ................................................................................................... 16

2.11 Voltage Sag and Surge Detection ............................................................................................. 17

2.12 Relay Control ............................................................................................................................. 18

2.12.1 Autonomous Mode ......................................................................................................... 18

2.12.2 Slave Mode .................................................................................................................... 18

2.12.3 Activation De lay ............................................................................................................. 18

2.13 On-Chip Calibration Routines .................................................................................................... 20

2.13.1 Voltage and Current Gain Calibration ............................................................................ 20

2.13.2 Offset Calibration ........................................................................................................... 20

2.13.3 X+Y Capacitor and R Compensation Coefficient Calibration ........................................ 20

2.13.4 On-Chip Temperature Calibration.................................................................................. 21

2.13.5 External Temperature Calibration .................................................................................. 21

3 Data Access and Configurability ..................................................................................................... 22

3.1 Register Descriptions ................................................................................................................. 22

3.2 Scaling Registers (Iscale, Vscale, Pscale, Tscale, Fscale) ....................................................... 24

3.3 Output R eg ister s ........................................................................................................................ 25

3.4 Input Registers (Setup and Calibration) ..................................................................................... 27

3.5 Relay Configuration ................................................................................................................... 29

3.6 DIOState Register ...................................................................................................................... 30

3.7 Alarms and Alarms Configuration Registers .............................................................................. 31

3.7.1 Alarms Status Register (address 0x30) ......................................................................... 31

3.7.2 AlarmSticky Register (address 0x54) ............................................................................ 32

3.7.3 AlarmMask1 (address 0x09) and AlarmMask2 (address 0x51) .................................... 33

3.7.4 AlarmSet Register (address 0x0C) ................................................................................ 34

3.7.5 AlarmReset Register (address 0x0F) ............................................................................ 35

3.7.6 Alarms Configuration Registers (Thresholds and Hold-Off Time) ................................. 36

2 Rev 3

78M6610+PSU Data Sheet

3.7.7 Alarm Counter Registers ............................................................................................... 37

3.8 Command Register .................................................................................................................... 38

3.8.1 General Settings ............................................................................................................ 38

3.8.2 No Action (0x00xxxx) ..................................................................................................... 38

3.8.3 Save to Flash Command (0xACC2xx) ........................................................................... 39

3.8.4 Clear Flash Storage 0 Command (0xACC0xx) .............................................................. 39

3.8.5 Clear Flash Storage 1 Command (0xACC1xx) .............................................................. 39

3.8.6 Calibration Command (0xCAxxxx)................................................................................. 40

4 Serial Interfaces ................................................................................................................................ 41

4.1 UART Interface .......................................................................................................................... 43

4.1.1 Command-Response Protocol Description ................................................................... 44

4.1.2 Auto-Reported Data ....................................................................................................... 47

4.2 SPI Interf ac e .............................................................................................................................. 48

4.3 I2C Interface ............................................................................................................................... 51

5 Electrical Specifications ................................................................................................................... 55

5.1 Absolute Maximum Ratings ....................................................................................................... 55

5.2 Recommended External Components ....................................................................................... 55

5.3 Recommended Operat ing Cond itions ........................................................................................ 55

5.4 Performance Specifications ....................................................................................................... 56

5.4.1 Input Logic Levels .......................................................................................................... 56

5.4.2 Output Logic Levels ....................................................................................................... 56

5.4.3 Supply Current ............................................................................................................... 56

5.4.4 Crystal Oscillator ............................................................................................................ 56

5.4.5 Internal RC Oscillator ..................................................................................................... 56

5.4.6 ADC Converter, V3P3 Referenced .................................................................................. 57

5.5 Timing Specifications ................................................................................................................. 58

5.5.1 RESET ........................................................................................................................... 58

5.5.2 SPI S la ve Por t ................................................................................................................ 58

5.5.3 I2C Slave Port ................................................................................................................ 59

6 Packaging .......................................................................................................................................... 60

6.1 24-Pin QFN Pinout ..................................................................................................................... 60

6.2 16-Pin TSSOP Pinout ................................................................................................................ 61

6.3 Package Outline ......................................................................................................................... 62

7 Ordering Information ........................................................................................................................ 64

8 Contact Information .......................................................................................................................... 64

Revision History ........................................................................................................................................ 65

List of Figures

Figure 1-1: IC Functional Block Diagram ......................................................................................... 5

Figure 1-2: XTAL Connection .......................................................................................................... 6

Figure 1-3: RESET Pin Connections ............................................................................................... 7

Figure 2-1: Analog Input Signal Conditioning ................................................................................ 10

Figure 2-2: HPF .............................................................................................................................. 10

Figure 2-3: RMS Calculations ........................................................................................................ 11

Figure 2-4: Power (Active, Reactive, and Apparent) and Power Factor Calculation ..................... 12

Figure 2-5: Voltage and Current Fundamental and Harmonic Calculations .................................. 13

Figure 2-6: Typical Measurement Location in Power Supplies...................................................... 15

Figure 2-7: External Temperature Monitor ..................................................................................... 16

Figure 2-8: Typical Sag Event ........................................................................................................ 17

Figure 2-9: Relay Control for In-rush Current Limitation Circuitry.................................................. 18

Figure 2-10: Relay Control ............................................................................................................. 19

Figure 2-11: Typical Calibration Setup ........................................................................................... 21

Figure 4-1: UART Connections on a RS-485 Bus ......................................................................... 43

Rev 3 3

78M6610+PSU Data Sheet

Figure 4-2: Signal Timing on the SPI Bus ...................................................................................... 48

Figure 4-3: Single Word Read Access Timing ............................................................................... 49

Figure 4-4: Single Word W rite Access T iming ............................................................................... 50

Figure 4-5: I2C Bus Connection in Standard (A) and Isolated (B) Configuration ........................... 51

Figure 4-6: I2C Bus 3-byte Data Write ........................................................................................... 53

Figure 4-7: I2C Bus Multiple Sequential Register Write ................................................................. 53

Figure 5-1: SPI Slave Port T im ing ................................................................................................. 58

Figure 5-2: I2C (Slave) Port Timing ................................................................................................ 59

List of Tables

Table 1-1: Alarm Pins Functional Description .................................................................................. 9

Table 2-1: Rel a y Confi gurat ion Reg is ter and Seq uence Dela y Regis ter ....................................... 19

Table 3-1: Data Type Description .................................................................................................. 23

Table 3-2: Reg ist ers with Scalab le Va lues .................................................................................... 24

Table 3-3: Output Registers ........................................................................................................... 25

Table 3-4: H ig h-Rate Result Registers .......................................................................................... 26

Table 3-5: Input Registers .............................................................................................................. 27

Table 3-6: Rel a y Confi gurat ion Reg is ter s ...................................................................................... 29

Table 3-7: DIOSt ate Register ......................................................................................................... 30

Table 3-8: Alarms Register and Corresponding Configuration Registers ...................................... 31

Table 3-9: AlarmSticky Register Bits Assignment ......................................................................... 32

Table 3-10: AlarmMask1 and AlarmMask2 Registers Bits Assignment ........................................ 33

Table 3-11: AlarmSet Register Bit Assignments ............................................................................ 34

Table 3-12: AlarmReset Registers Bit Assignments ...................................................................... 35

Table 3-13: Alarms Threshold Registers ....................................................................................... 36

Table 3-14: Alarms Hold-Off Timers Registers .............................................................................. 37

Table 3-15: Alarms Counter Registers ........................................................................................... 37

Table 3-16: General Settings Command Bits ................................................................................ 38

Table 3-17. No Action Command Bits ............................................................................................ 38

Table 3-18. Save to Flash Command Bits ..................................................................................... 39

Table 3-19. Clear Flash Storage 0 Command Bits ........................................................................ 39

Table 3-20. Clear Flash Storage 1 Command Bits ........................................................................ 39

Table 3-21. Calibration Command Bits .......................................................................................... 40

Table 4-1: Host Commands ........................................................................................................... 46

Table 4-2: Slave Reply Codes ....................................................................................................... 46

Table 4-3: Default Measurements .................................................................................................. 47

Table 4-4. Single Word SPI Read Command (SDI) ....................................................................... 49

Table 4-5. Single Word SPI Read Response (SDO) ..................................................................... 49

Table 4-6. Single Word SPI Write Command and Data (SDI) ....................................................... 50

Table 5-1: I2C Slave Port Timing2 .................................................................................................. 59

4 Rev 3

78M6610+PSU Data Sheet

1 On-Chip Resources Overview

The 78M6610+PSU integrates all the functional hardware blocks required to embed solid-state AC power

and energy measurement. Included on the device are:

• Accurate oscillator and clock management logic

• Power-on reset, watchdog timer, and reset circuitry

• High-accuracy analog front-end (AFE) with trimmed voltage reference and temperature sensor

• 24-bit energy measurement processor (EMP)

• RAM and flash memory

• Communication inter f aces

• Multipurpose Digital I/O

Figure 1-1 shows a block diagram of the device. A detailed description of various functional blocks

follows.

XTAL

OSC

MUX

AIN

ATEMP2

AVN

AIP

XIN

XOUT

3P3D

VREF

VBIAS

GEN

IBIAS

GEN

MUX

CONTROL

INFO.

BLOCK

FLASH

4Kx16

PROGRAM

MEMORY

EMP

Energy Measurement

Processor

CLOCK

GEN

GNDD

UART

TEMP

SENSE

SDI/RX/SDAi

SDO/TX/SDAo

ACFAULT

SSB/DIR/SCL

ADDR1

SPCK/ADDR0

CE DATA

RAM

512x24

RESET

ADC

CK20M

SPI

OSC

SEL

24b data bus

RELAYCTRL

TIMERS

WATCH DOG

program bus

MUX

TRIM

BITS

3P3A

2.5v

REG.

2.5v V

3P3

DIV

MPY

TEMP

LOG.

IFCONFIG

MP0

ACCRIT

GNDA

MP1

AVP

ATEMP1

FIR

Figure 1-1: IC Functional Block Diagram

Rev 3 5

78M6610+PSU Data Sheet

1.1 Clock Management

The 78M6610+PSU can be clocked by either the trimmed internal RC oscillator or b y oscillator circuitry

that relies on an external crystal. The 78M6610+PSU hardware automatically handles the clock sources

logic and distributes the clock to the rest of the device.

Upon reset or power-on, the 78M6610 +P SU wil l automatically select the external clock, if available, after

1024 clock cycles of the internal oscillator, allowing the external crystal adequate time to start up. After

power-on or during run-time, the 78M6610+PSU will automatically switch to the internal oscillator in the

event of a failure with the external oscillator (or crystal not mounted). This condition is also monitored by

the processor and available to the user in the ALARMS register.

The internal RC oscillator is trimmed and temperature compensated. It provides an accurate clock

source, however for applications requiring highest line frequency accuracy, the use of an external crystal

is recommended (only available in the 24-pin QFN package).

The 78M6610+PSU external clock circuitry requires a 20.000MHz crystal. The circuitry includes two 18pF

ceramic capacitors. Figure 1-2 shows the typical connection of the external crystal. This oscillator is self-

biasing and therefore an external resistor should NOT be connected across the crystal.

XIN

XOUT

18pF

20.000MHz

78M6610+PSU/B

Figure 1-2: XTAL Co nn ection

Alternat ively, an external clock signal can be utilized instead of the crystal. In this case, the external clock

should be connected to the XOUT pin while the XIN pin should be connected to GNDD.

If the external crystal is not utilized (not mounted), the XOUT pin should be connected to GNDD and the

XIN pin left unconnected.

6 Rev 3

78M6610+PSU Data Sheet

1.2 Power-On Reset, WD Timer, and Reset Circuitry

Power-On Reset (POR)

An on-chip Power-On Reset (POR) block monitors the suppl y voltag e (V3P3D) and initializes the internal

digital circuitry at power-on. Once V3P3D is above the minimum operating threshold, the POR circuit

triggers and initiates a reset sequence. It will als o issue a reset to the digital circuitry if the supply voltage

falls below the minimum operating level.

Watchdog Timer (WDT)

A Watchdog Timer (WDT) block detects any soft ware pr oces s ing err ors . The embedded software

periodically refreshes the free-running watchdog timer to prevent it from timing out. If the WDT times out,

it is an indication that software is no longer being executed in the intended sequence; thus, a system

reset is initiated.

External Reset Pin (RESET Pin)

The 24-pin QFN package provides a dedicated reset (RESET) pin. In addition to the internal sources, a

reset can be forced by applying a low level to the RESET pin.

If the RESET pin is pulled low, all di git a l ac ti vities in the device stop, except the clock management

circuitry and oscillators, which continue to run. The external reset input is filtered to prevent spurious reset

events in noisy environments. The reset does not occur until RESET has been held low for at least 1 µs.

Once initiated, the reset mode persists until the RESET is set high and the reset timer times out (4096

clock cycles). At the completion of the reset sequence, the internal reset is released and the processor

(EMP) begins executing from address 0.

If not used, the RESET pin can be connected either directly or through a pull-up resistor to V3P3D supply.

A simple connection diagram is shown in Fi gur e 1-3.

GNDD

3P3D

RESET

1nF

10KΩ

3P3

GND

Manual

Reset Switch

GNDD

3P3D

RESET

3P3

GND

78M6610+PSU/B 78M6610+PSU/B

a) RESET External Connection Example b) Unused RESET Connection Example

Figure 1-3: RESET Pin Connections

Rev 3 7

78M6610+PSU Data Sheet

1.3 Analog Front-End and Conversion

The Analog Front-End (AFE) of the 78M6610+PSU includes an input multiplexer, delta-sigma A/D

converter, bias current references, voltage references, temperature sensor, and several voltage fault

comparators.

Delta-Sigma A/ D Con ver ter

A second-order delta-sigma converter digitizes the analog inputs. The converted data is then processed

through an FIR filter.

Voltage Reference

The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero

techniques as well as production trims to minimize errors caused by component mismatch and drift. The

voltage reference is digitally compensated over temperature.

Die Temperature Measurement

The device includes an on-chip die temperature sensor used for digital compensation of the voltage

reference. It is also used to report temperature information to the user.

Voltage and Current Inputs

The external voltage and current sensors are connected to differential voltage input pins. The full-scale

signal level that can be applied to the voltage input pi n s is V3P3A ±250 mV. Considering a sinusoidal

waveform, the maximum RMS voltage is:

VrmsMAX =250

2=176.78mV

Although the voltage input is differential, a common-mode voltage of less than ±25 mV is recommended

in order to utilize the available dynamic range.

Temperature Inputs

ATEMP1 and ATEM P2 ar e single-ended inputs that allow temperature measurement through an external

sensing element (NTC, RTD etc.). The temperature measurement is generally used to monitor heat-sink

or exhaust air operating conditions. TEMP2 is only available with the 24-pin pack age opt ion.

1.4 24-Bit Energy Measurement Processor (EMP)

The 78M6610+PSU integrates a dedicated 24-bit signal processor that performs all the digital signal

processing necessary for energy measurement, alarm generation, calibration, compensation, etc. See

Section 2 for a description of functionality and operations.

1.5 Flash and RAM

The 78M6610+PSU includes 8KB of on-chip flash memory. The flash memory primarily contains program

code, but also stores coefficients, calibration data, and configuration settings. The 78M6610+PSU

includes 1.5KB of on-c hip RAM which contains the values of input and output registers and is utilized by

the FW for its operations.

1.6 Communication Peripherals

The 78M6610+PSU includes three communication interface options: UART, SPI, and I2C.

Since the I/O pins are shared, only one mode is supported at a time. Two pins are sampled at power-on

or reset to determine which interface will be active.

8 Rev 3

78M6610+PSU Data Sheet

1.7 Multi-Purpose Digital I/O Pins

The MP0 and MP1 input/output pins ar e not currently used. The pins have an inter nal pull-up and can be

left floating.

1.8 Alarm Pins (ACFAULT, ACCRIT)

Alarm pins are available to signal an alarm condition has been reached. Table 1-1 shows the available

alarm pins and the intended usage. The alarm thresholds and conditions are programmable through

dedicated registers. The status of each individual alarm is accessible through a status register.

Table 1-1: Alarm Pins Functional Description

ACFAULT Non crit ic al warni ng upd ate d onc e per accumulation int er val.

ACCRIT Critical condition detected; AC Dropout, or SAG (see Section 2.5).

The alarm pins are open drain and active low (0=alarm). These pins need to be pulled up and can be

wired-OR.

Rev 3 9

78M6610+PSU Data Sheet

2 Functiona l Description and Oper ation

This section describes the 78M6610+PSU functionality. It includes measurements and relevant

calculations, alarms, auxiliary functions such as cal ibra tions , zero-crossing, relay control, etc.

A set of input (write), output (read) and read/write registers are provided to allow access to calculated

data and alarms and to configure the device. The input (write) registers values can be saved into flash

memory through a specific command. The values saved into flas h m em ory will be loaded in these

registers at reset or power-on as defaults.

2.1 Voltage and Current Inputs Conditioning

The sensor input voltages are digitized using a single integrated second-order delta-sigma A/D converter.

The analog front-end includes a temperature sensor whose output is digitized and used for temperature

(gain) compensation.

SINC

DECIMATOR

AIP

CROSS

POINT

∆Σ

MODULATOR

PRECISION

REFERENCE

IA_ RAW

VA_ RAW

ADC

DELAY

COMP

+250mv

ADC

X X i

AIN

CT PHASE

COMP

ON-CHIP

TEMPERATURE

SENSOR

Temperature

Compensation

AVP

DIE_TEMP

GAIN CORRECTION

SIGNAL

CONDITIONING

AVN

ATEMP 2

Igain

Vgain

PhaseComp

Tgain Toffs

HPFcoeffI

HPF

HPFcoefV

Figure 2-1: A nalog Input Signal Conditioning

2.1.1 High Pass Filters (HPF) and Offs et Correction

The high-pass filters (HPF) in Figure 2-1 and Figure 2-2 can remove any DC from the signal paths and

consequently from power and RMS calculated values. The HPFs work by subtracting the value of the

offset register (Voffs, Ioffs) from the corresponding voltage or current input. The offset registers can be set

by the user, by an automatic calibration routine or adjusted dynamically by the FW.

HPF

HPFcoef

X∑

N-1

n=0

offs N

Figure 2-2: HPF

2.1.2 Phase Compensation

A phase compensation register is provided to compensate phase errors introduced by current

transformers (CT) or external filters. The amount of phase shift is set by the PhaseComp register as a

fractional number of ADC samples with a total range of +/- 4 ADC samples (roughly +/- 20 degrees for a

60Hz line frequency).

10 Rev 3

78M6610+PSU Data Sheet

2.2 Current and Voltage RMS Calculations

The 78M6610+PSU provides true RMS measurements for both current and voltage inputs. The RMS is

obtained by performing the square sum of the instantaneous samples of voltage and current over a time

interval (commonly referred as accumulation time) and then performing a square root of the result after

dividing by the number of samples in the time interval.

=Vn







=In







Irms

∑

N-1

n=0

Vrms

∑

N-1

n=0

IrOff

VrOff

Figure 2-3: RMS Calculations

Rev 3 11

78M6610+PSU Data Sheet

2.3 Power Calculations and Powe r Factor

The 78M6610+PSU computes the active, reactive, and apparent power. In addition, the 78M6610+PSU

computes the fundamental power, determined only by the fundamental components of the voltage and

current and the harmonic power, determined by the harmonic components of the voltage and current.

2.3.1 Activ e Power Calculation

Active power is calculated as the product of the voltage and current waveforms. The resulting waveform

is the instantaneous power signal, and it is equal to the rate of energy flow at every instant of time. The

unit of power is the watt or joules/sec. The instantaneous power is then averaged over N samples

(accumulation time) for the computation of the active power available at register WATT.

=  





2.3.2 Apparent Power

The apparent power (S) is the product of RMS voltage (VRMS) and current (IRMS). The apparent power

results, also referred as Volt-Amps, are available at the register VA.

S = IRMS * VRMS

2.3.3 Power Factor

The power factor (PF) is calculated as active power (WATT) divided by the apparent power (S). The sign

of the power factor is determined by the active power sign.

=WATT

2.3.4 Reacti v e Power

The reactive power is calculated as multiplication of instantaneous samples of current (i) and the

instantaneous quadrature voltage (Vq). The quadrature voltage is obtained through a 90° phase shift

(quadrature delay) of the voltage samples. The samples are then averaged over the accumulation time

interval and updated in the VAR register.

=  



 ×

Figure 2-4: Power (Active, Reactive, and Apparent) and Power Factor Calculation

WATT

÷N

WATT

Irms

Vrms

Quadrature

Delay

VAR

N=0

N-1

÷N

N=0

N-1

POff

12 Rev 3

78M6610+PSU Data Sheet

2.4 Fundamental and Harmonics Ca lcul ations

Fundamental and Harmonics

The 78M6610+PSU provides measurements on fundamental and total harmonic of voltage, current, and

power (active, reactive, and apparent).

SINE(t)

COSINE(t)

SINE(t)

COSINE(t)

VSINE

VCOS

ISINE

ICOS

Vfund

Ifund

Vrms Vharm

Iharm

∑

N-1

n=0

∑

N-1

n=0

∑

N-1

n=0

∑

N-1

n=0

+ Y

- YI

Irms

Figure 2-5: Voltage and Curre n t Fu nd amental and Harmonic Calculations

Fundamental and Harmonic Selection

The 78M6610+PSU allows extraction and calculation of a single selected harmonic. By default, the

fundamental (first harmonic) is selected for voltage, current, active, reactive real and apparent power

calculations. The HARM register is used to select the single harmonic to extract.

By setting the value in the HARM register to a higher harmonic, the fundamental result registers will

contain amplitudes of the selected harmonic. In this case the harmonic result register will contain the

balance of the voltage, current, or power.

2.5 Accumulation Interval

The accumulation interval mode is configurable by the user through the Accum and AccumCyc registers

and the status of the line lock bit.

The ACCUM register contains an unsigned integer values representing the accumulation interval (time)

expressed in number of high-rate samples.

The accumulation interval can also be locked to the incoming line voltage cycles. The LINELOCK bit

in the command register allows the accumulation interval to be determined by the ACCUM register or

to be locked to the line cycle.

Once locked to the line cycle the accumulation interval will end after the first low-to-high zero

crossing of the Reference AC Voltage (see Zero-Crossing Detection) input occurs once the Minimum

Accumulation time has elapsed. The Actual Accumulation Interval will span an integer number of line

cycles. When LINELOCK is not set, the Accumulation Interval will equal the value set by the ACCUM

The effective sample rate for each input of the 78M6610+PSU is 4KS/s. The DIVISOR register

reports the actual number of samples within any g iv en ac c um ulation int er va l.

Rev 3 13

78M6610+PSU Data Sheet

It is also possible to set the accumulation interval based on a number of AC Voltage line cycles. If the

Line Lock (LL) Command register bit is set and AccumCyc register is non-zero then the device will

calculate, on e very frequen cy update, a ne w Accum value bas ed upon the line fr equency. T he formula is

as follows: =SampleRate

Line Frequency  18

The computed A ccum value locks the accumulation interval to the number of AC line voltage

cycles, specified by the AccumCyc line cycles regardless of the system frequency.

2.6 Zero-Crossing Detection

The 78M6610+PSU includes a zero-crossing detection feature on both AC input channels. The zero-

crossing detection allows measurements to be synchronized to the frequency of the incoming waveforms.

The time delay of the zero-crossing output versus the effective zero crossing is approximately 500 µs.

2.7 Alarms

The 78M6610+PSU includes a set of user-configurable alarms. Most alarms have a corresponding

“min” limits) an alarm condition is generated. Such a condition does not necessarily cause an alarm. The

condition must exist for the duration of the associated hol d-off time.

If the alarm condition exceeds the hold-off time, an alarm event is generated and reported in the

corres pondi ng bit of the alarm register . The corresponding event counter is also incremented.

The alarm bit will continue to be set as long as the alarm condition persists, even if the user clears it by

accessing the AlarmReset register. However, event counters will only record one event until the next new

assertion of the alarm.

The registers AlarmMask1 and AlarmMask2 allow the user to select which alarm will be used to drive the

corresponding alarm pins (AlarmMask1 controls ACFAULT pin while AlarmMask 2 controls ACCRIT pin).

For example, to select OverCurrent and Vsurge to drive the ACFAULT pin, AlarmMask1 should be set to

0x000440.

The AlarmSet register allows forcing a particular alarm in the alarm register. This function is mainly

intended for relay control and system test purposes.

The AlarmReset register allows clearing a particular alarm in the alarm register.

The AlarmSticky register allows the user to select which bits in the alarm register should remain set even

after the alarm condition no longer exists. These bits will remain set until reset by the host/user. All other

Alarms will be reset at the end of the accumulation interval unless the alarm condition remains.

Exceptions: Relay_On, Zero_Cross, and Data_Ready are not influenced by the value of the AlarmSticky

14 Rev 3

78M6610+PSU Data Sheet

2.8 Voltage and Current Min/Max and Peak Tracking

2.8.1 Voltage and Current Min/Max Tracking

The 78M6610+PSU allows recording the lowest and highest voltage and current rms values. These

values are stored in the registers Vhi, Vlo, Ihi, and Ilo. To reset these values it is nec ess ary to write to

these registers. For example, a value of 0x000000 should be written in the Vhi or Ihi register in order to

reset them. Similarly, a value of 0x7FFFFF should be written to the Vlo and Ilo registers in order to reset

them.

2.8.2 Voltage and Current Peak Tracking

The 78M6610+PSU allows recording the highest voltage and current measured during an accumulation

interval. These values are updated at each accumulation interval and available on the output registers

Vpeak and Ipeak, for voltage and current, respectively.

2.9 X+Y Capacitor Current and I/R Voltage Drop Compensation

The 78M6610+PSU location in the power supply AC input stage can be different from design to design. In

order to achieve high accuracy, the components preceding the measurement point should be accounted

for. For example, current flowing in filter capacitors or the voltage drop across PCB traces (I, Vdrop)

should be considered in the measurement as shown in Figure 2-6.

AC INLET TO PFC

78M6610+PSU

SHUNT

I I

Current (Measured)

Vdrop

Figure 2-6: Typical Measurement Locatio n in Power Supplies

2.9.1 X+Y Capacitor Compensation

The 78M6610+PSU, and therefore the measurement point, is usually located between the inlet and the

diode bridge. This stage is where the EMI filters are usually located as shown in Figure 2-6.

In this case the current flowing through the filter (X+Y) capacitors preceding the measurement cannot be

measured and is compensated for by the 78M6610+PSU. The current in flowing into these capacitors is

at 90° phase respect to the voltage; therefore it has no effect on the power measurement. The effect is

prominent in the current reading, in particular at light loads. Compensation is required in order to achieve

higher accuracy.

A fixed coefficient value can be set for compensation, however due to the tolerance of the filter capacitors

(in the +/-20% range) a calibration routine is included in the firmware. Calibration of the X+Y capacitor

coefficient facilitates higher accuracy in the measurement of the current

Rev 3 15

78M6610+PSU Data Sheet

2.9.2 I/R Voltage Drop Compensation

The PCB traces have a certain resistance that at high loads causes a voltage drop from the inlet to the

measurement point. The voltage drop causes an error in the voltage and power measurements. The

correction is proportional to the current measured. A coefficient proportional to the input stage resistance

is available and tunable by the user. Usually this coefficient is set by the user for a specific hardware and

does not require calibration.

2.10 External Temperature Monitor

The ATEMP1 and ATEMP2 inputs are dedicated to the acquisition of an external temperature. These

inputs are single ended with a range of +/-250 mV referenced to the 3.3VDC supply (V3P3A). The

converted value is multiplied by a user programmable gain and the results are reported in the EXTEMP

registers as a voltage drop from V3P3.

ATEMP1 EXTTEMP1

TEMP1GAIN

TEMP1THRES

ExtOvTemp1

ATEMP2 EXTTEMP2

TEMP2GAIN

TEMP2THRES

ExtOvTemp2

Figure 2-7: External Temperature Monitor

The output of the multiplier block is also compared w ith the value conta in ed in a user-programmable

16 Rev 3

78M6610+PSU Data Sheet

2.11 Voltage Sag and Surge Detection

The 78M6610+PSU implements a voltage sag detection function, which can generate an alarm when the

line voltage drops below a programmable threshold.

The firmware calculates on a sample-by-sample basis the trailing mean square of the input voltage:

 = 

2 ×  × 



 ( 

× )

At each sample interval the VMS value is compared to a programmable threshold contained in the Vsag

enabled in the AlarmMask2 register, the ACCRIT pin will also be asserted low. If the Vsag bit is set in the

AlarmsSticky register, then Alarms.Vsag will remain set and ACCRIT will remain low until the Vsag alarm

is cleared via the AlarmReset register or the 78M6610+PSU is reset. If AlarmsSticky.Vsag is cleared,

then Alarms.Vsag will be cleared and ACCRIT set high as soon as the VMS monitor is greater than the

programmable threshold.

The sample count for sag detection is automatically adjusted by the firmware to maintain coverage over

half of the AC cycle. Sag detection is disabled by default and can be enabled by writing a non-zero value

to the VSAG register. If the VSAG register is set to 0, the sag feature is disabled.

The sag detection can be used to monitor or record the quality of the power line or utilize the sag alarm

pin to notify external devices (for example a host microprocessor) of a pending power-down. The external

device can then enter a power-down mode (for example saving data or recording the event) before a

Power outage. Figure 2-8 shows a typical sag event.

SAG_THRESHOLD

Figure 2-8: Typical Sag E v ent

Rev 3 17

78M6610+PSU Data Sheet

2.12 Relay Control

The firmware includes relay control logic and provides a digital output RELAYCTRL for controlling a relay.

The relay control may operate in either an autonomous mode or in a slave mode. The operating mode is

selected by the setting of the AUTORELAY bit in the COMMAND register. A bit in the ALARMS register

reports the state of the RELAYCTRL output.

2.12.1 Autonomous Mode

When autonomous relay control mode is enabled, the 78M6610+PSU firmware controls the state of

RELAYCTRL output, based upon the input line voltage.

At power on, RELAYCTRL output is inactive. When the RMS voltage is within specified upper and lower

turn-on thresholds (RelayOnMin, RelayOnMax) for a specified time (RelayOnTime), RELAYCTRL output

will be activated. Should the RMS voltage exceed the specified turn-off thresholds (RelayOffMin,

RelayOffMax) for a specified time (RelayOffTime), RELAYCTRL output will be deactivated. The turn-on

and turn-off thresholds are specified separately, as are delay times, to provide hysteresis to prevent

unwanted switching of the relay due to short-term fluctuations in voltage.

The autonomous mode can be used to automatically control the in-rush current relay as shown in Figure

2-9.

AC INLET

TO PFC

78M6610+PSU

SHUNT

+Vcc

Figure 2-9: Relay Control for In-rush Current Limitation Circuitry

2.12.2 Slave Mode

When slave mode relay control is selected, the RELAYCTRL output is manually controlled by setting or

clearing the RELAY_ON bit in the AlarmSet and AlarmReset registers.

2.12.3 Activation Delay

The relay control logic allows setting a delay time for energizing and de-energizing the relay. The delay

time for energizing and de-energizing the relay is relative to the zero crossing of the Voltage as shown in

Figure 2-10.

The time specified in the registers is expressed in the number of high-rate samples.

The default timings are:

Energized delay time (RelayOnDelay) = 0x000000 sample counts

De-Energized delay time (RelayOffDelay) = 0x000000 sample counts

18 Rev 3

78M6610+PSU Data Sheet

Relay

Command

Line

Voltage

ON_DELAY

De-Energized Energized De-Energized

OFF_DELAY

Figure 2-10: Relay Control

Table 2-1: Relay Configuration Regi ster and Sequence Delay Register

Function Register Default

Value Comments

Name Address

TON_Delay RelayOnDelay 0x6b 0 Line Relay Activation Time

Delay

TOFF_Delay RelayOffDelay 0x6c 0 Line Relay De-Activation Time

Delay

Rev 3 19

78M6610+PSU Data Sheet

2.13 On-Chip Calibration Routines

The 78M6610+PSU includes current and voltage and temperature calibration routines. These routines

modify gain and offset coefficients. The device also includes routines for the calibration of the X+Y

capacitor and R resistance compensation coefficients.

The user can set and start a calibration routine through the Command register. When the calibration

process completes, command register bits 23:16 (set to 0xCA to issue a calibration command) are

cleared along with bits associated with channels that calibrated successfully. Any channels that failed will

have their corresponding bit left set. After completion of the calibration, the new coefficients can be saved

into flash memory as defaults by issuing the Save to Flash Command (0xACC2xx).

2.13.1 Voltage and Current Gain Calibration

In order to calibrate the voltage and current channels, a stable AC supply must be applied to the channel

to be calibrated. The value corresponding to the applied AC supply (usually measured using a power

meter) must be entered in the relevant target register (VTarget, ITarget). Figure 2-11 shows a typical

calibration setup.

To start the calibration, the calibration command must be written to the Command register.

Initially, the value of the gain is set to unity for the selected channels. RMS values are then calculated on

all inputs and averaged over the number of measurement cycles set by the register CalCyc. The new gain

is calculated by dividing the appropriate Target register value by the averaged measured value. The new

gain is then written to the select Gain registers unless an error occurred.

On completion, the command bits are cleared in the Command register, leaving only the system setup

bits. In case of a failed calibration, the corresponding bit in the command register is left set.

During calibration, the line-lock mode should be set. Once completed, the calibration routines will store

the ne w gain co ef ficients in the releva nt regis ters. In o rder to s ave t he n ew coef ficients into flash mem or y

as defaults, it is necessary to issue the Save to Flash Command (0xACC2xx).

2.13.2 Offset Calibrati o n

The FW provide build in routines for calibration of the offset registers (Ioffs, Voffs).

To calibrate offset, all DC signals should be removed from all inputs although it is possible to do the

calibration in the presence of AC signals. In the command, the user also specifies which channel(s) to

calibrate. Target registers are not used for Offset calibration.

During the calibration process, each input is accumulated over the entire calibration interval as specified

by the CalCycs register. The result is divided by the total number of samples and written to the

appropriate offset register if selected in the calibrat io n command. Using the Offset Calibration command

will set the HPF coefficients (HPFcoefV, HPFcoefI) to zero thereby fixing the offset registers (Ioffs, Voffs)

to their calibrated values. In order to save the new coefficients into flash memory as defaults, it is

necessary to issue the Save to Flash Command (0xACC2xx).

2.13.3 X+Y Capacitor and R Compensation Coefficient Calibration

Most applications use a line input filter to minimize the EM emissions as shown in Figure 2-11. The

current in th e f ilter ca pac it o r s ( Ic ap) pr ec edi ng t he 78M 6610 + PSU c ann ot b e measur ed. In order t o o btain

high accuracy of the current measurement it should be compounded in the total current (Irms) calculation.

Fixed com pensation coefficient values can the used, k nowing the filter capac itors value. However due to

the tolerance of the filter capacitors (often ±20%), in order to obtain higher accuracy in the current

measurement, it could required to utilize a specific coefficient for each system. The 78M6610+PSU

provides a calibration routine for the X+Y capacitor compensation coefficient.

20 Rev 3

78M6610+PSU Data Sheet

The routine X-Y compensation coefficient calibration, utilizes both measured voltage and frequency and

the target current measured using an external power meter as in Figure 2-11.

To start the c omm and, the user writes the c alibrati on command, s etting bits XYR and I, and ot her nee ded

options such as line-lock. On completion, the XYcomp parameter will be written with an estimate for the

bulk capacitance. Once completed, the calibration routines will store the new gain coefficients in the

relevant registers. During the calibration process, each input is accumulated over the entire calibration

interval as specified by the CalCycs register.

This routine is not recursive; the user may need to re-issue the calibration command until the current

reading matches the target current.

After completion of the calibration, in order to save the new coefficients into flash memory as defaults, it is

necessary to issue the Save to Flash Command (0xACC2xx).

AC INLET

78M6610+PSU

SHUNT

ICap

Vdrop

SOURCE

ICap

ICap ICap

POWER

METER POWER SUPPLY

Figure 2-11: Typical Calibration Setup

2.13.4 On-Chip Temperature Calibration

To calibrate the on-chip temperature sensor, the user must first write only the “T” command bit to a “1” (all

other bits 0). This command prevents the firmware from overwriting TempC register. Next the user must

write the known chip temperature to TempC. Finally the user writes the Calibration Command to

0xCA0400 (Calibrate Temperature). This will cause the Toffs parameter to be updated with a new offset

based on the known temperature supplied by the user. In order to save the new coefficients into flash

memory as defaults, it is necessary to issue the Save to Flash Command (0xACC2xx).

2.13.5 External Temperature Calibration

To calibrate External Temperature, the user must first write only the “X” command bit to a “1” (all other

bits 0). This prevents the firmware from overwriting ExtTemp. Next the user must write the known external

temperature reading to ExtTemp. Finally the user writes the Calibration Command to 0xCA0100

(Calibrate External Temperature). This will cause the Xgain parameter to be updated with a new gain

based on the known external temperature value supplied by the user. In order to save the new

coefficients into flash memory as defaults, it is necessary to issue the Save to Flash Command

(0xACC2xx).

Rev 3 21

78M6610+PSU Data Sheet

3 Data Access and Configurability

The 78M6610+PSU has several user accessible registers that are used for configuring the device and to

access results data. These registers are read (output), write (input), or read/write type, such as the

Command register. These registers are accessible through the serial interfaces available on-chip (UART,

SPI, and I2C).

Warning

Writing to reserved registers or to unspecified memory locations could result in

malfunctions or unexpec ted r esults.

Note

The documented address locations apply to the UART interface. For SPI or I2C addressing,

one must divide th e address by 3.

3.1 Register Descriptions

Data Types

The input and output registers have different data types, depending on their assignment and functions.

Table 3-1 shows the different data types.

The notation used indicates whether the number is signed, unsigned, or bit-mapped and the location of

the binary point.

U Indicates an unsigned value.

S Indicates a signed value.

. If present, indicates a fixed point number

nn If to the right of the decimal, indicates the number of bits to the right of the binary point.

If no decimal is present, indicates the total bits in the number.

Example: S.21

Bit Pos ition

…

S(-22)

2-1

2-2

2-3

2-4

…

2-19

2-20

2-21

22 Rev 3

78M6610+PSU Data Sheet

Table 3-1: Data Type Description

Data Type

Description

UINT24 A 24-bit unsigned integer having a range of 0 to 16777215.

Typically used for counters

INT24

A 24-bit signed integer with a range of -8388608 to +8388607.

USI24 A 24-bit unsigned scaled integer (scaled by the user).

SSI24 A 24-bit signed scaled integer (sc aled b y the user).

U.24 A 24-bit uns igne d fixed-po i nt value with the bi nary point to the left

of bit 23 with a range of 0 to 1-2-24.

U.23 A 24-bit unsigned fixed-point number with the binary point to the

left of bit 22 and with a range of 0 to 1-2-23.

U.22 A 24-bit unsigned fixed-point number with the binary point to the

left of bit 21 and with a range of 0 to 2-2-22.

U.21 A 24-bit unsigned fixed point number with the binary point to the

left of bit 20 and with a range of 0 to 4-221.

S.23 A 24-bit signed fixed point number with the binary point to the left

of bit 22 an d with a range of -1.0 to 1-2-23.

S.21 A 24-bit signed fixed-point number with a binary point to the left of

bit 20 and with a range of -4.0 to 4-2-21.

S.16 A 2 4-bit sign ed fixed-point num ber with a binary point to the left of

bit 16 and with a range of -128 to +128

Boolean (B24)

A variable containing 24 independent single-bit values.

Rev 3 23

78M6610+PSU Data Sheet

3.2 Scaling Registers (Iscale, Vscale, Pscale, Tscale, Fscale)

The scaling registers can be used to set the full-scale values and choosing the resolution of related

parameters and results.

For voltage and current inputs, full scale is defined as +/-250 mV (DC or Peak). The voltage input is usually

scaled down from the AC inlet using a sensing element: resis tor divider , volt age tr ans f ormer, etc.

The current input is connected to current sensing element, generally a low value resistive shunt or current

transformer (CT).

The Iscale and Vscale parameters need to be set in order to match the full scale range of the current and

voltage inputs with the full scale range of the sensor.

Examples

Voltage: A voltage divider produces an output of 250 mV (peak) with 230 V (peak) applied at its input. A

resolution of 1 mV is needed. In this case, the value of VSCALE register should be:

VSCALE = 230 * 1000 = 230000

Current: A current shunt produces a voltage drop of 250 mV (peak) at 30 A (peak). A resolution of 1 mA is

needed. In this case the value of ISCALE register should be:

ISCALE = 30 * 1000 = 30000

Power: To set the power scaling register PSCALE it is necessary to multiply the full-scale volt age b y the

full-scale current and by the desired resolution. For 1 mW resolution:

PSCAL E: 2 30 vo lts x 30 amps x 1000 = 6900000 mw. The value of Pscale register should be set to 6900000.

The scaling registers for Line Frequency, Power Factor, and Temperature do not set full scale values.

They only set resolution. For example, setting Tscale to 1000 the value of the temperature is represented

in 1/1000 of Degree Celsius. For example, by setting the Tscale register to 1000, a temperature of 27°C

is reported as 27000 in the Temperature register.

Note

All 78M6610 +PSU reg i sters are 24 bits and most are signed. The largest signe d integer is

+/- 83886 08. In case of larger numbers, a lower resolution must be chosen. For example,

10 mW versus 1 mW is case of PSCALE register.

Table 3-2: Registers with Scalable Values

Scaling Register

Registers Affected by Scaling

Iscale Irms Ifund Iharm Ihi Ilo Ipeak Imax Itarget

Vscale Vrms Vfund Vharm Vhi Vlo Vpeak Vsurge Vsag Vdrop Vmin Vmax Vtarget

RelayOnMin RelayOnMax RelayOffMin RelayOffMax

Pscale Power VA VAR Paverage Pfund Pharm Qfund Qharm Pmax

PFscale PF

Tscale Temperature Tmin Tmax Xtemperature Xmin Xmax

Fscale Frequency Fmin Fmax

24 Rev 3

78M6610+PSU Data Sheet

3.3 Output Registers

The output registers provide access to the measurement results. Unless otherwise specified, these

registers are read-only. Divide the address by 3 for I2C or SPI access.

Table 3-3: Output Registers

Address

(Hex)

Variable

Name

Data

Type

Description

0x00 Command B24 Command Register (see Command Register Section)

0x03 FW version UINT24 Firmware release date in hex format (0x00YMDD)

0x12 Temperature S.16 Chip Temperature (-128°C to +128°C, binary point to left of bit 16)

0x15 VA SSI24 Apparent Power (LSB weight determined by Pscale)

0x18 VAR SSI24 Reactive Power (LSB weight determined by Pscale)

0x1B Vrms USI24 RMS Vo ltage (L SB weight deter mined by Vscale)

0x1E Irms USI24 RMS Current (LSB weight determined by Iscale)

0x21 Watt SSI24 Ac ti ve Power (LSB weig ht deter mined by Pscale)

0x24 PAverage SSI24 Active Power Averaged over 30s Window (LSB determined by

Pscale)

0x27 PF SSI24 Power Factor (LSB weight determined by PFscale)

0x2A Frequency USI24 Line Frequency (LSB weight determined by Fscale)

0x30 Alarms B24 Alarm Status Registers

0x33 Vfund USI24 RMS Vo lta ge (Fu ndamenta l) (LSB we ight d etermined by Vscale)

0x36 Ifund USI24 RMS Current (Fundamental) (LSB weight determined by Iscale)

0x39 Pfund SSI24 Acti ve Pow er (Fund amental) (LS B weight determined by Pscale)

0x3C Qfund SSI24 Reactive Power (Fundamental) (LSB weight determined by

Pscale)

0x3F VAfund SSI24 Apparent Power (Fundamental) (LSB weight determined by

Pscale)

0x42 Vharm USI24 RMS Voltage (Harmonic) (LSB weight determined by Vscale)

0x45 Iharm USI24 RMS Current (Harmonic) (LSB weight determined by Iscale)

0x48 Pharm SSI24 Active Power (Harmonic) (LSB weight determined by Pscale)

0x4B Qharm SSI24 Reactive Power (Harmonic) (LSB weight determined by Pscale)

0x4E VAharm SSI24 Appar ent Po wer (Harmonic) (LSB weight det er mined by Pscale)

0x57 ILow USI24 Lowest RMS Current Recorded Since Reset (LSB determined by

Iscale)

0x5A IHigh USI24 Highest RMS Current Recorded Since Reset (LSB determined by

Iscale)

0x5D Ipeak USI24 Highest Current in Las t Acc umulation Interval (LSB determined

by Iscale)

0x60 VLow USI24 Lowest RMS Voltage Recorded Since Reset (LSB determined by

Vscale)

0x63 VHigh USI24 Highest RMS Voltage Recorded Since Reset (LSB weight

determined by Vscale)

0x66 Vpeak USI24 Highest Voltage in Last Ac c umulation Interval (LSB weight

determined by Vscale)

0xA8:C9 – UINT24 Event Counters for Alarms

Rev 3 25

78M6610+PSU Data Sheet

Address

(Hex)

Variable

Name

Data

Type

Description

0xD5 ExtTemp1 USI24 External Temperature 1 (ATEMP1 Input)

0xD8

ExtTemp2

USI24

External Temperature 2 (ATEMP2 Input)

0x10E Divisor UINT24 Actual Accumulation Interval for Low Rate Results

0x147 DIOState B24 State of DIO Outputs

0x156 Irms1 UINT24 Unscaled RMS Current

0x159 Vrms1 UINT24 Unscaled RMS Voltage

0x15C Power1 INT24 Unscaled Active Power

0x15F

Var1

INT24

Unscaled Reactive Power

0x162 VA1 INT24 Unscaled Apparent Power

0x165 PF1 INT24 Unscaled Power Factor

0x168

Freq1

UINT24

Unscaled Frequency

High-Rate Result (Output Registers)

These output registers contain the instantaneous values of voltage, current, power and quadrature power.

The high-rate registers are upda ted at the ADC Sampling Frequency (4.0 kHz). These register, given the

relatively high update rate, should be acc ess ed with a high speed interface such as SPI.

Table 3-4: High-Rate Result Registers

Address

(Hex) Vari able Nam e Data

Type Description

0x16B V

(1)

INT24 High-Rate Vo lta ge

0x16E I

(1)

INT24 High-Rate Cur rent

0x171 Vq

(1)

INT24 High-Rate Quadrature Voltage

0x174 P

(1)

INT24 High-Rate Po wer

0x177 PQ

(1)

INT24 High-Rate Quadrature Power

0x17A Cycle

(1)

UINT24 High-Rate Samples

0x17D Scycle

(1)

UINT24 High-Rate Sa g/S urge Cycles

Note:

1) The high rate registers are updated at the ADC converter sample rate. In order to access real

time data it is preferable to utilize the SPI interface.

26 Rev 3

78M6610+PSU Data Sheet

3.4 Input Registers (Setup and Ca l ibration)

Input Registers are used to configure the device, issue commands etc. The input registers content can be

saved to flash memory the values restored as defaults upon power-on or reset.

Table 3-5: Input Registers

Address

(Hex)

Variable

Name

Data

Type

Flash

Saved

Description Default

(Decimal)

0x00 Command B24 Y Command Register (see Command Register

Section)

0x06 PhaseComp S.21 Y Phase Compensation (High-Rate Sam ples) 0

0x09 Alarm_Mask1 B24 Y Alarm Mask Bits for ACFAULT Pin

0x0C Alarm_Set B24 Y Sets Corresponding Alarm Bits

0x0F Alarm_Reset B24 Y Clears Corresponding Alarm Bits

0x2D DevAddr UINT24

Y UART (MultiPoint) and I

C Address 0

0x51 Alarm_Mask2 B24 Y Alarm Mask Bits for ACCRIT Pin

0x54 Sticky B24 Y Alarm Bits to Con tr ol Aut o-Reset of Alarm Status

0x69:8D – – Y Alarm Limit Registers (See Section 3.6)

0x90:A2 – – Y Alarm Hold-Off Time Registers (See Section 3.6)

0xA5 IrOff U.23 Y RMS Current Offset Adjust

0xA8 VrOff U.23 Y RMS Voltage Offset Adjust

0xAB POff U.23 Y Power Offset Adjust

0xCC AccumCyc UINT24

Y Number of Line Cycles for Low Rate

0xCF Ptarget UINT24

Y Current Gain Calibration, Power Target 0

0xD2 Baud UINT24

Y UART Baud Rate 38,400

0xDB Temp1Gain UINT24

Y External Temperature Gain 0

0xDE Temp2Gain UINT24

Y External Temperature Gain 0

0xE1 HPFCoeffI U.23 Y Current Offset Removal Settling Time 1

0xE4 HPFCoeffV U.23 Y Voltage Offset Removal Settling Time 1

0xE7 Itarget UINT24

Y Current Gain Calibration, Current Target 128,000

0xEA Vtarget UINT24

Y Voltage Gain Calibration, Voltage Target 120,000

0xED CalCyc UINT24

Y Number of Calibration Cycles to Average 5

0xF0 Igain U.21 Y Current Gain Setting (Updated After Calibration)

Range 0 to 4 1

0xF3 Vgain U.21 Y V oltage Gain Setting (Updated After Calibration) 1

0xF6 Ioff S.23 Y Current Offset (Updated After Calibration) N/A

0xF9 Voff S.23 Y Voltage Offset (Updated After Calibration) N/A

0xFC Tgain U.24 Y Die Temperature Gain Setting (Updated After

Calibration) 701,233

0xFF Toffs U.24 Y Die Temperature Offset (Updated After

Calibration) 287,831

0x102 SysGain S.23 N Temperature Compensated System Gain

(Updated After Calibration) N/A

0x105 Harm UINT24

N Harmonic Selector 1

Rev 3 27

78M6610+PSU Data Sheet

Address

(Hex)

Variable

Name

Data

Type

Flash

Saved

Description Default

(Decimal)

0x108 Saccum UINT24

N Accumulation Interval for Sag and Surge 40

0x10B

Accum

UINT24

Accumulation Interval for Calculation (RMS, etc.)

400

0x111 Frame UINT48

N Low Rate Frame Number Counter N/A

0x117 XYcomp UINT24

Y Line Filters Capacitive Compensation 0

0x11A Rcomp UINT24

Y Resistive I/R Drop Compensation 0

0x11D Iscale UINT24

Y Current Scaling Register 30,000

0x120 Vscale UINT24

Y Voltage Scaling Register 30,000

0x123

Pscale

UINT24

Power Scaling Register

6,900,000

0x126 PFscale UINT24

Y Power Factor Scaling Register 1000

0x129 Fscale UINT24

Y Frequency Scaling Register 1000

0x12C

Tscale

UINT24

Temperature Scaling Register

1000

0x12F:144

– UINT24

Y Relay Configuration Registers (See Section 3.5)

0x14A TC1 UINT24

Y Temperature Compensation 0

0x14D TC2 UINT24

Y Temperature Compensation 0

0x147 RESERVED B24 N Read-Only Register N/A

28 Rev 3

78M6610+PSU Data Sheet

3.5 Relay Configuration

The registers in Table 3-6 are used to configure the relay operations.

Table 3-6: Relay Con figuration Regi sters

Address

Saved

Description Default

(Decimal)

0x12F RelayOnMin UINT24

Y Minimum Voltage to Keep Relay ON (LSB

weight determined by Vscal e) 85,000

0x132

RelayOnMax

UINT24

Y Maximum Voltage to Keep Relay ON (LSB

weight determined by Vscal e) 255,000

0x135

RelayOnTime

UINT24

Y Hold ON Time (Samples) If Min/Max Not Met 4

0x138 RelayOffMin UINT24

Y Minimum Voltage to Keep Relay OFF (LSB

weight determined by Vscal e) 90,000

0x13B RelayOffMax

UINT24

Y Maximum Voltage to Keep Relay OFF (LSB

weight determined by Vscal e) 250,000

0x13E RelayOffTime

UINT24

Y Hold OFF Time (Samples) If Min/Max Met 4

0x141

RelayOnD el a y

UINT24

Y Relay Closure Time (ms) 0

0x144 RelayOffDelay

UINT24

Y Relay Opening Time (ms) 0

Rev 3 29

78M6610+PSU Data Sheet

3.6 DIOState Register

The DIOState register reports the state of the digital input/output pins. Unconnected or floating pins are

reported as set as one. Table 3-7 lists the bit ass ignments.

Table 3-7: DIOState Register

Bit Pin Status Function

23-11 N/A N/A

10 MP1 Multi-Purpose Digital I/O

9 MP0 Multi-Purpose Digital I/O

8 IFCONFIG UART/I

C/SPI Selecti on

7 ACFAULT

ACFAULT Alarm

6 ADDR1 I

C/Multi-Point UART Address

5 SSB/DIR/SCL Slave Select (SPI) / RS485 TX-RX/I

C Serial Clock

4 ACCRIT

AC Input Voltage Alarm (Critical)

3 SDO/TX/SDAo SPI DATA OUT/UART TX/I

C Data Out

2 SDI/RX/SDAi SPI DATA IN/UART RX/I

C Data In

1 SCK/ADDR0 SPI CLOCK IN/I

C/Multi-Point UART Address

0 RELAYCTRL Relay Control Output

30 Rev 3

78M6610+PSU Data Sheet

3.7 Alarms and Alarms Configuration Registers

3.7.1 Alarms Status Register (address 0x30)

The Alarms Status register is an output register (read-only) that contains the status of the alarms and

other conditions. Table 3-8 reports the Alarms register bit assignment and the corresponding limit

registers (thresholds) and Hold-Off time registers.

Table 3-8: Alarms Register and Corresponding Configuration Registers

Bit Alarms

(Bit)

Limit

(1)

Hold-Off

(1) Function

23 DataReady – – Low-rate results have been updated

22 OverTemp Tmax TminHold Die temperature is over limit

21 UnderTemp Tmin TminHold Die temperature is under limit

20 Not Used N/A N/A Not used

19 ExtOvTemp1 XMax1 – External temperature 1 is over limit

18 ExtOvTemp2 XMax2 – External temperature 2 is over limit

17-12 Not Used N/A N/A Not used

11 Vsag Vsag VsagHold Voltage sag ged be lo w lim it

10 Vsurge Vsurge VsagHold Voltage surged above limit

9 VdropOut Vdrop – Voltage dropped below limit

8 OverVolt Vmax VminHold RMS voltage went above upper limit

7 UnderVolt Vmin VminHold RMS voltage fell below lower limit

6 OverCurrent Imax ImaxHold RMS curre nt went abo ve limit

5 OverPower Pmax PmaxHold Power went above limit

4 OverFreq Fmax Fminhold Line frequency went above upper limit

3 UnderFreq Fmin Fminhold Line frequency fell below lower limit

2 Relay_On – – Relay is ON

1 Zero_Cross – – Voltage low-to-high zero-crossing detected

(auto-clears)

0 Not Used – – Not used

Note:

1) These are input registers and their value can be saved in flash memory as defaults through the

ACC Command.

Rev 3 31

78M6610+PSU Data Sheet

3.7.2 AlarmSticky Register (address 0x54)

The AlarmSticky register is an input register that allows configuring individual bits into the Alarms register

to hold the alarm status (“sticky”) until an AlarmReset command is issued. Each alarm can otherwise be

set to auto-reset at the completion of each accumulation interval.

The AlarmSticky register can be saved into flash memory.

Table 3-9: AlarmSticky Register Bits Assignment

Bit Alarm Function

23 N/A N/A

22 OverTemp 1 = Alarm bit is set until AlarmReset command is issued.