ADA4806-1RJ-EBZ - ANALOG DEVICES

0.2 µV/°C Offset Drift, 105 MHz, Low Power,

Multimode, Rail-to-Rail Amplifier

Data Sheet

ADA4806-1

Rev. A Document Feedback

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FEATURES

Ultralow supply current

Full power mode: 500 µA

Sleep mode: 74 µA

Shutdown mode: 2.9 µA

Dynamic power scaling

Turn-on time from shutdown mode: 1.5 µs

Turn-on time from sleep mode: 0.45 µs

High speed performance with dc precision

Input offset voltage: 125 µV maximum

Input offset voltage drift: 1.5 µV/°C maximum

−3 dB bandwidth: 105 MHz

Slew rate: 160 V/ µs

Low noise and distortion

5.9 nV/√Hz input voltage noise with 8 Hz 1/f corner

−102 dBc/−126 dBc HD2/HD3 at 100 kHz

Wide supply range: 2.7 V to 10 V

Small package: 8-lead SOT-23

APPLICATIONS

Portable and battery-powered instruments and systems

High channel density data acquisition systems

Precision analog-to-digital converter (ADC) drivers

Voltage reference buffers

Portable point of sales terminals

Active RFID readers

GENERAL DESCRIPTION

The ADA4806-1 is a high speed, voltage feedback, rail-to-rail

output, single operational amplifier with three power modes:

full power mode, sleep mode, and shutdown mode. In full

power mode, this amplifier provides a wide bandwidth of 105 MHz

at a gain of +1, a fast slew rate 160 V/μs, and excellent dc precision

with a low input offset voltage of 125 μV (maximum) and an input

offset voltage drift of 1.5 μV/°C (maximum), while consuming

only 500 μA of quiescent current. Despite being a low power

amplifier, the ADA4806-1 provides excellent overall

performance, making it ideal for low power, high resolution

data conversion systems.

For data conversion applications where minimizing power

dissipation is paramount, the ADA4806-1 offers a method to

reduce power by dynamically scaling the quiescent power of the

ADC driver with the sampling rate of the system by switching the

amplifier to a lower power mode between samples.

TYPICAL APPLICATIONS CIRCUIT

13391-001

2.5V RE F

10µF

2.7nF

IN+ REF

GND

VDD

IN–

0.1µF C4

100nF

ADA4806-1

0V TO V

REF

ADA4806-1

AD7980

20Ω

Figure 1. Driving the AD7980 with the ADA4806-1

Sleep mode reduces the amplifier quiescent current to 74 µA

and provides a fast turn-on time of only 0.45 µs, enabling the

use of dynamic power scaling for sample rates approaching

2 MSPS. For additional power savings at lower samples rates,

the shutdown mode further reduces the quiescent current to

only 2.9 µA.

The ADA4806-1 operates over a wide range of supply voltages

and is fully specified at supplies of 3 V, 5 V and ±5 V. This

amplifier is available in a compact, 8-lead SOT-23 package and

is rated to operate over the industrial temperature range of

−40°C to +125°C.

13391-611

POWER CONSUMP TION (mW )

ADC SAMP LE RAT E ( ksps)

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0110 100 1000

SLEEP MODE

SHUT DO WN MODE

Figure 2. Quiescent Power Dissipation vs. ADC Sample Rate,

Using Dynamic Power Scaling for the Two Low Power Modes

Table 1. Complementary ADCs to the ADA4806-1

Product ADC Power (mW)

Throughput

(MSPS)

Resolution

(Bits)

SNR

(dB)

AD7980 4.0 1 16 90.51

AD7982 7.0 1 18 98

AD7984

10.5

1.33

98.5

1 This SNR value is for the A Grade version of the AD7980.

ADA4806-1 Data Sheet

Rev. A | Page 2 of 24

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Typical Applications Circuit ............................................................ 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

±5 V Supply ................................................................................... 3

5 V Supply ...................................................................................... 4

3 V Supply ...................................................................................... 6

Absolute Maximum Ratings ............................................................ 8

Thermal Resistance ...................................................................... 8

Maximum Power Dissipation ..................................................... 8

ESD Caution .................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Typical Performance Characteristics ........................................... 10

Test Circuits ..................................................................................... 17

Theory of Operation ...................................................................... 18

Amplifier Description ................................................................ 18

Input Protection ......................................................................... 18

Shutdown/Sleep Mode Operation ............................................ 18

Noise Considerations ................................................................. 19

Applications Information .............................................................. 20

Slew Enhancement ..................................................................... 20

Effect of Feedback Resistor on Frequency Response ............ 20

Compensating Peaking in Large Signal Frequency Response ... 20

Driving Low Power, High Resolution Successive

Approximation Register (SAR) ADCs..................................... 20

Dynamic Power Scaling ............................................................. 21

Single-Ended to Differential Conversion ................................... 23

Layout Considerations ............................................................... 23

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

5/2017—Rev. 0 to Rev. A

Changes to Figure 1 ........................................................................... 1 9/2015—Revision 0: Initial Version

Data Sheet ADA4806-1

Rev. A | Page 3 of 24

SPECIFICATIONS

±5 V SUPPLY

VS = ±5 V at TA = 25°C; RF = 0 Ω for G = +1; otherwise, RF = 1 kΩ; RL = 2 kΩ to ground; unless otherwise noted.

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, VOUT = 0.02 V p-p 120 MHz

G = +1, VOUT = 2 V p-p 40 MHz

Bandwidth for 0.1 dB Flatness G = +1, VOUT = 0.02 V p-p 18 MHz

Slew Rate G = +1, VOUT = 2 V step 190 V/µs

G = +2, VOUT = 4 V step 250 V/µs

Settling Time to 0.1% G = +1, VOUT = 2 V step 35 ns

G = +2, VOUT = 4 V step 78 ns

NOISE/DISTORTION PERFORMANCE

Harmonic Distortion, HD2/HD31 fC = 20 kHz, VOUT = 2 V p-p −114/−140 dBc

fC = 100 kHz, VOUT = 2 V p-p −102/−128 dBc

= 20 kHz, V

OUT

= 4 V p-p, G = +1

−109/−143

dBc

fC = 100 kHz, VOUT = 4 V p-p, G = +1 −93/−130 dBc

fC = 20 kHz, VOUT = 4 V p-p, G = +2 −113/−142 dBc

fC = 100 kHz, VOUT = 4 V p-p, G = +2 −96/−130 dBc

Input Voltage Noise f = 100 kHz 5.2 nV/√Hz

Input Voltage Noise 1/f Corner Frequency 8 Hz

0.1 Hz to 10 Hz Voltage Noise 44 nV rms

Input Current Noise f = 100 kHz 0.7 pA/√Hz

DC PERFORMANCE

Input Offset Voltage Full power mode 13 125 µV

Low power mode, SLEEP = −VS 800 µV

Input Offset Voltage Drift2 TMIN to TMAX, 4 σ 0.2 1.5 µV/°C

Input Bias Current (IB) Full power mode 550 800 nA

Low power mode, SLEEP = −VS 3 nA

Input Offset Current 2.1 25 nA

Open-Loop Gain VOUT = −4.0 V to +4.0 V 107 111 dB

INPUT CHARACTERISTICS

Input Resistance

Common Mode 50 MΩ

Differential Mode 260 kΩ

Input Capacitance 1 pF

Input Common-Mode Voltage Range −5.1 +4 V

Common-Mode Rejection Ratio (CMRR)

IN, CM

= −4.0 V to +4.0 V

103

130

SHUTDOWN PIN

SHUTDOWN Voltage

Low Powered down <−1.3 V

High Enabled >−0.9 V

SHUTDOWN Current

Low Powered down −1.0 +0.2 µA

High Enabled 0.02 1.0 µA

Turn-Off Time 50% of SHUTDOWN to <10% of enabled

quiescent current

1.25 2.75 µs

Turn-On Time 50% of SHUTDOWN to >99% of final VOUT 1 3 µs

ADA4806-1 Data Sheet

Rev. A | Page 4 of 24

Parameter Test Conditions/Comments Min Typ Max Unit

SLEEP PIN

SLEEP Voltage

Low Powered down <−1.3 V

High Enabled >−0.9 V

SLEEP

Current

Low Low Power Mode, SLEEP = −VS −1.0 +0.2 µA

High Enabled 0.02 1.0 µA

Turn-Off Time (Full Power Mode to Sleep Mode) 50% of SLEEP to 30% of enabled quiescent

current

180 240 ns

Turn-On Time (Sleep Mode to Full Power Mode) 50% of SLEEP to >99% of final VOUT 450 600 ns

OUTPUT CHARACTERISTICS

Output Overdrive Recovery Time

(Rising/Falling Edge)

VIN = +6 V to −6 V, G = +2 95/100 ns

Output Voltage Swing RL = 2 kΩ −4.98 +4.98 V

Short-Circuit Current Sourcing/sinking; full power mode 85/73 mA

Sourcing/sinking; low power mode, SLEEP = −VS 1.4/1.8 mA

Linear Output Current <1% total harmonic distortion (THD) at 100 kHz,

VOUT = 2 V p-p

±58 mA

Off Isolation VIN = 0.5 V p-p, f = 1 MHz, SHUTDOWN = −VS 41 dB

Capacitive Load Drive 30% overshoot 15 pF

POWER SUPPLY

Operating Range

2.7

Quiescent Current per Amplifier Full power mode 570 625 µA

Low power mode, SLEEP = −VS 85 µA

SHUTDOWN = −VS 7.4 12 µA

Power Supply Rejection Ratio (PSRR)

Positive +VS = +3 V to +5 V, −VS = −5 V 100 119 dB

Negative +VS = +5 V, −VS = −3 V to −5 V 100 122 dB

1 fC is the fundamental frequency.

2 Guaranteed, but not tested.

5 V SUPPLY

VS = 5 V at TA = 25°C; RF = 0 Ω for G = +1; otherwise, RF = 1 kΩ; RL = 2 kΩ to midsupply; unless otherwise noted.

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, VOUT = 0.02 V p-p 105 MHz

G = +1, VOUT = 2 V p-p 35 MHz

Bandwidth for 0.1 dB Flatness G = +1, VOUT = 0.02 V p-p 20 MHz

Slew Rate G = +1, VOUT = 2 V step 160 V/µs

G = +2, VOUT = 4 V step 220 V/µs

Settling Time to 0.1% G = +1, VOUT = 2 V step 35 ns

G = +2, VOUT = 4 V step 82 ns

Data Sheet ADA4806-1

Rev. A | Page 5 of 24

Parameter Test Conditions/Comments Min Typ Max Unit

NOISE/DISTORTION PERFORMANCE

Harmonic Distortion, HD2/HD31 fC = 20 kHz, VOUT = 2 V p-p −114/−135 dBc

fC = 100 kHz, VOUT = 2 V p-p −102/−126 dBc

fC = 20 kHz, G = +2, VOUT = 4 V p-p −107/−143 dBc

= 100 kHz, G = +2, V

OUT

= 4 V p-p

−90/−130

dBc

Input Voltage Noise f = 100 kHz 5.9 nV/√Hz

Input Voltage Noise 1/f Corner 8 Hz

0.1 Hz to 10 Hz Voltage Noise 54 nV rms

Input Current Noise f = 100 kHz 0.6 pA/√Hz

DC PERFORMANCE

Input Offset Voltage Full power mode 10 125 µV

Low power mode, SLEEP = −VS 500 µV

Input Offset Voltage Drift2 TMIN to TMAX, 4 σ 0.2 1.5 µV/°C

Input Bias Current Full power mode 470 720 nA

Low power mode, SLEEP = −VS 3 nA

Input Offset Current 0.4 nA

Open-Loop Gain VOUT = 1.25 V to 3.75 V 105 109 dB

INPUT CHARACTERISTICS

Input Resistance

Common Mode 50 MΩ

Differential Mode

260

kΩ

Input Capacitance

Input Common-Mode Voltage Range −0.1 +4 V

Common-Mode Rejection Ratio VIN, CM = 1.25 V to 3.75 V 103 133 dB

SHUTDOWN PIN

SHUTDOWN Voltage

Low Powered down <1.5 V

High Enabled >1.9 V

SHUTDOWN Current

Low Powered down −1.0 +0.1 µA

High Enabled 0.01 1.0 µA

Turn-Off Time 50% of SHUTDOWN to <10% of enabled

quiescent current

0.9 1.25 µs

Turn-On Time 50% of SHUTDOWN to >99% of final VOUT 1.5 4 µs

SLEEP PIN

SLEEP Voltage

Low Powered down <1.5 V

High Enabled >1.9 V

SLEEP Current

Low Low power mode, SLEEP = −VS −1.0 +0.1 µA

High Enabled 0.01 1.0 µA

Turn-Off Time (Full Power Mode to

Sleep Mode)

50% of SLEEP to 30% of enabled quiescent

current

150 185 ns

Turn-On Time (Sleep Mode to Full

Power Mode)

50% of SLEEP to >99% of final VOUT 450 600 ns

ADA4806-1 Data Sheet

Rev. A | Page 6 of 24

Parameter Test Conditions/Comments Min Typ Max Unit

OUTPUT CHARACTERISTICS

Overdrive Recovery Time (Rising/Falling

Edge)

VIN = −1 V to +6 V, G = +2 130/145 ns

Output Voltage Swing RL = 2 kΩ 0.02 4.98 V

Short-Circuit Current Sourcing/sinking; full power mode 73/63 mA

Sourcing/sinking; low power mode, SLEEP = −VS 1.0/1.3 mA

Linear Output Current <1% THD at 100 kHz, VOUT = 2 V p-p ±47 mA

Off Isolation VIN = 0.5 V p-p, f = 1 MHz, SHUTDOWN = −VS 41 dB

Capacitive Load Drive 30% overshoot 15 pF

POWER SUPPLY

Operating Range 2.7 10 V

Quiescent Current per Amplifier Full power mode 500 520 µA

Low power mode, SLEEP = −VS 74 µA

SHUTDOWN = −VS 2.9 4 µA

Power Supply Rejection Ratio

Positive +VS = 1.5 V to 3.5 V, −VS = −2.5 V 100 120 dB

Negative +VS = 2.5 V, −VS = −1.5 V to −3.5 V 100 126 dB

1 fC is the fundamental frequency.

2 Guaranteed, but not tested.

3 V SUPPLY

VS = 3 V at TA = 25°C; RF = 0 Ω for G = +1; otherwise, RF = 1 kΩ; RL = 2 kΩ to midsupply; unless otherwise noted.

Table 4.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, VOUT = 0.02 V p-p 95 MHz

G = +1, VOUT = 1 V p-p, +VS = 2 V, −VS = −1 V 30 MHz

Bandwidth for 0.1 dB Flatness G = +1, VOUT = 0.02 V p-p 35 MHz

Slew Rate G = +1, VOUT = 1 V step, +VS = 2 V, −VS = −1 V 85 V/µs

Settling Time to 0.1%

G = +1, V

OUT

= 1 V step

NOISE/DISTORTION PERFORMANCE

Harmonic Distortion, HD2/HD3

= 20 kHz, V

OUT

= 1 V p-p, +V

= 2 V, −V

= −1 V

−123/−143

dBc

= 100 kHz, V

OUT

= 1 V p-p, +V

= 2 V, −V

= −1 V

−107/−133

dBc

Input Voltage Noise f = 100 kHz 6.3 nV/√Hz

Input Voltage Noise 1/f Corner 8 Hz

0.1 Hz to 10 Hz Voltage Noise 55 nV rms

Input Current Noise f = 100 kHz 0.8 pA/√Hz

DC PERFORMANCE

Input Offset Voltage Full power mode 7 125 µV

Low power mode, SLEEP = −VS 300 µV

Input Offset Voltage Drift

MIN

to T

MAX

, 4 σ

0.2

1.5

µV/°C

Input Bias Current Full power mode 440 690 nA

Low power mode, SLEEP = −VS 3 nA

Input Offset Current 0.5 nA

Open-Loop Gain VOUT = 1.1 V to 1.9 V 100 107 dB

Data Sheet ADA4806-1

Rev. A | Page 7 of 24

Parameter Test Conditions/Comments Min Typ Max Unit

INPUT CHARACTERISTICS

Input Resistance

Common Mode 50 MΩ

Differential Mode 260 kΩ

Input Capacitance

Input Common-Mode Voltage Range −0.1 +2 V

Common-Mode Rejection Ratio VIN, CM = 0.5 V to 2 V 89 117 dB

SHUTDOWN PIN

SHUTDOWN Voltage

Low Powered down <0.7 V

High Enabled >1.1 V

SHUTDOWN Current

Low Powered down −1.0 +0.1 µA

High

Enabled

0.01

1.0

µA

Turn-Off Time 50% of SHUTDOWN to <10% of enabled

quiescent current

0.9 1.25 µs

Turn-On Time 50% of SHUTDOWN to >99% of final VOUT 2.5 8 µs

SLEEP PIN

SLEEP Voltage

Low Powered down <0.7 V

High

Enabled

>1.1

SLEEP Current

Low Low Power Mode, SLEEP = −VS −1.0 +0.1 µA

High Enabled 0.01 1.0 µA

Turn-Off Time (Full Power Mode to Sleep Mode) 50% of SLEEP to 30% of enabled quiescent current 155 210 ns

Turn-On Time (Sleep Mode to Full Power Mode) 50% of SLEEP to >99% of final VOUT 450 600 ns

OUTPUT CHARACTERISTICS

Output Overdrive Recovery Time

(Rising/Falling Edge)

VIN = −1 V to +4 V, G = +2 135/175 ns

Output Voltage Swing RL = 2 kΩ 0.02 2.98 V

Short-Circuit Current Sourcing/sinking; full power mode 65/47 mA

Sourcing/sinking; low power mode, SLEEP = −VS 1.0/1.3 mA

Linear Output Current <1% THD at 100 kHz, VOUT = 1 V p-p ±40 mA

Off Isolation VIN = 0.5 V p-p, f = 1 MHz, SHUTDOWN = −VS 41 dB

Capacitive Load Drive 30% overshoot 15 pF

POWER SUPPLY

Operating Range 2.7 10 V

Quiescent Current per Amplifier Full power mode 470 495 µA

Low power mode,

SLEEP

= −V

µA

SHUTDOWN = −VS 1.3 3 µA

Power Supply Rejection Ratio

Positive +VS = 1.5 V to 3.5 V, −VS = −1.5 V 96 119 dB

Negative +VS = 1.5 V, −VS = −1.5 V to −3.5 V 96 125 dB

1 fC is the fundamental frequency.

2 Guaranteed, but not tested.

ADA4806-1 Data Sheet

Rev. A | Page 8 of 24

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Supply Voltage 11 V

Power Dissipation

See Figure 3

Common-Mode Input Voltage −VS − 0.7 V to +VS + 0.7 V

Differential Input Voltage ±1 V

Storage Temperature Range −65°C to +125°C

Operating Temperature Range −40°C to +125°C

Lead Temperature (Soldering, 10 sec) 300°C

Junction Temperature 150°C

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL RESISTANCE

θJA is specified for the worst case conditions, that is, θJA is specified

for a device soldered in a circuit board for surface-mount packages.

Table 6 lists the θJA for the ADA4806-1.

Table 6. Thermal Resistance

Package Type θJA Unit

8-Lead SOT-23 209.1 °C/W

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation for the ADA4806-1 is

limited by the associated rise in junction temperature (TJ) on

the die. At approximately 150°C, which is the glass transition

temperature, the properties of the plastic change. Even temporarily

exceeding this temperature limit may change the stresses that the

package exerts on the die, permanently shifting the parametric

performance of the ADA4806-1. Exceeding a junction temperature

of 175°C for an extended period of time can result in changes in

silicon devices, potentially causing degradation or loss of

functionality.

The power dissipated in the package (PD) is the sum of the

quiescent power dissipation and the power dissipated in the die

due to the ADA4806-1 output load drive.

The quiescent power dissipation is the voltage between the supply

pins (VS) multiplied by the quiescent current (IS).

PD = Quiescent Power + (Total Drive Power − Load Power)

( )

OUT

OUTS

IVP

2−











×+×=

RMS output voltages must be considered. If RL is referenced

to −VS, as in single-supply operation, the total drive power is

VS × IOUT. If the rms signal levels are indeterminate, consider the

worst case, when VOUT = VS/4 for RL to midsupply.

( ) ( )

SSD

IVP

+×=

In single-supply operation with RL referenced to −VS, the worst

case is VOUT = VS/2.

Airflow increases heat dissipation, effectively reducing θJA.

Additionally, more metal directly in contact with the package

leads and exposed pad from metal traces, through holes,

ground, and power planes reduces θJA.

Figure 3 shows the maximum safe power dissipation in the

package vs. the ambient temperature on a JEDEC standard,

4-layer board. θJA values are approximations.

13391-600

MAXIMUM POWER DISSIPATIO N (W)

AMBI E NT TE M P E RATURE (°C)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

–50 –30 –10 10 30 50 70 90 110 130

= 150° C

Figure 3. Maximum Power Dissipation vs. Ambient Temperature for a

4-Layer Board

ESD CAUTION

Data Sheet ADA4806-1

Rev. A | Page 9 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VOUT 1

NC 2

–VS3

+VS

SHUTDOWN

NOTES

1. NC = NO CO NNE CTION. DO NOT CONNE CT TO THIS PIN.

+IN 4–IN

13391-002

SLEEP

ADA4806-1

Figure 4. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 VOUT Output.

2 NC No Connection. Do not connect to this pin.

3 −VS Negative Supply.

4 +IN Noninverting Input.

5 −IN Inverting Input.

6 SLEEP Low Power Mode.

7 SHUTDOWN Power-Down Mode.

8 +VS Positive Supply.

ADA4806-1 Data Sheet

Rev. A | Page 10 of 24

TYPICAL PERFORMANCE CHARACTERISTICS

RL = 2 kΩ, unless otherwise noted. When G = +1, RF = 0 Ω.

–12

–9

–6

–3

0.1 110 100 1000

NORMALIZED CLOSED-LOOP GAI N ( dB)

FREQUENCY (MHz)

G = +1

G = +10

= ±2. 5V

OUT

= 20mV p - p

= 2kΩ

= 1kΩ

G = +5

G = +2

13391-206

Figure 5. Small Signal Frequency Response for Various Gains

–12

–9

–6

–3

0.1 110 100 1000

CLOSED-LOOP G AIN (d B)

FREQUENCY (MHz)

= ±2. 5V

G = +1

OUT

= 20mV p - p

= 2kΩ

–40°C

+25°C

+125°C

13391-208

Figure 6. Small Signal Frequency Response for Various Temperatures

–12

–9

–6

–3

0.1 110 100 1000

CLOSED-LOOP G AIN (d B)

FREQUENCY (MHz)

G = +1

VOUT = 20mV p-p

RL = 2kΩ

= ±1. 5V

= ±2. 5V

= ±5V

13391-207

Figure 7. Small Signal Frequency Response for Various Supply Voltages

–12

–9

–6

–3

0.1 110 100

NORMALIZED CLOSED-LOOP GAI N ( dB)

FREQUENCY (MHz)

= ±2. 5V

OUT

= 2V p-p

= 1kΩ

= 2kΩ

G = +2

G = +5

G = +10

G = +1

13391-015

Figure 8. Large Signal Frequency Response for Various Gains

–9

–6

–3

0.1 110 100

CLOSED-LOOP G AIN (d B)

FREQUENCY (MHz)

VS = ±2. 5V

G = +1

VOUT = 2V p-p

RL = 2kΩ

+25°C

+125°C

–40°C

13391-016

Figure 9. Large Signal Frequency Response for Various Temperatures

FREQUENCY (MHz)

–6

–3

0.1 110 100 1000

CLOSED-LOOP G AIN (d B)

= ±2. 5V

G = +1

= 2kΩ

OUT

= 20mV p - p

OUT

= 0.5V p-p

OUT

= 2V p-p

OUT

= 100mV p - p

13391-211

Figure 10. Frequency Response for Various Output Voltages

Data Sheet ADA4806-1

Rev. A | Page 11 of 24

–12

–9

–6

–3

110 100

CLOSED-LOOP GAIN ( dB)

FREQUENCY (MHz)

= ±2. 5V

G = +1

= 2kΩ

OUT

= 20mV p - p

13391-309

= 15pF

= 10pF

= 5pF

= 0pF

= 15pF

= 226Ω

Figure 11. Small Signal Frequency Response for Various Capacitive Loads

(See Figure 47)

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

–50

110 100 1000

DISTORTION (dBc)

FREQUENCY (kHz)

HD2, G = + 1

VS = ±5V, VOUT = 4V p-p

HD2, G = + 2

HD3, G = + 1

HD3, G = + 2

13391-514

Figure 12. Distortion vs. Frequency for Various Gains

–140

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

TOTAL HARMONI C DISTORTION (dB)

OUTPUT VOLTAGE (V peak)

INPUT CO M M ON-MODE

VOLTAGE UPPER LIMIT

(+V

– 1V)

= ±2. 5V

IN, CM

= 0V

G = +1

= 2kΩ

= 1MHz

= 100kHz

= 10kHz

13391-316

Figure 13. Total Harmonic Distortion vs. Output Voltage For Various

Frequencies

–0.6

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0.5

0.6

110 100

CLOSED-LOOP GAIN ( dB)

FREQUENCY (MHz)

= ±2. 5V

G = +1

= 2kΩ

OUT

= 20mV p - p

13391-110

Figure 14. Small Signal 0.1 dB Bandwidth

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

–50

110 100 1000

DISTORTION (dBc)

FREQUENCY (kHz)

HD3 V

= +2V/–1V

HD3 V

= ±5V

HD3 V

= ±2. 5V

HD2 V

= +2V/–1V

HD2 V

= ±5V

HD2 V

= ±2. 5V

= ±5V, V

OUT

= 2V p-p

= ±2. 5V, V

OUT

= 2V p-p

= +2V/–1V, V

OUT

= 1V p-p

13391-517

Figure 15. Distortion vs. Frequency for Various Supplies, G = +1

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

–50

110 100 1000

DISTORTION (dBc)

FREQUENCY (kHz)

HD2 V

= ±2. 5V

HD2 V

= +2V/–1V

HD3 V

= +2V/–1V

HD3 V

= ±2. 5V

HD2 V

= ±5V

HD3 V

= ±5V

= ±5V, V

OUT

= 4V p-p

= ±2. 5V, V

OUT

= 4V p-p

= +2V/–1V, V

OUT

= 1V p-p

13391-518

Figure 16. Distortion vs. Frequency, G = +2

ADA4806-1 Data Sheet

Rev. A | Page 12 of 24

0.1 110 100 1k 10k 100k 1M 10M 100M

VOLTAGE NOISE (nV/√Hz)

FREQUENCY (Hz)

= ±2. 5V

G = +1

13391-219

Figure 17. Voltage Noise vs. Frequency

–300

–250

–200

–150

–100

–50

100

150

200

250

300

012345678910

AMPLITUDE (nV)

TIME (Seconds)

= ±2. 5V

AVE RAGE NO ISE = 54nV rms

13391-318

Figure 18. 0.1 Hz to 10 Hz Voltage Noise

–140

–120

–100

–80

–60

–40

–20

10 100 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

–PSRR

+PSRR

CMRR

CMRR, P SRR (dB)

= ±2. 5V

ΔV

,ΔV

= 100mV p - p

13391-232

Figure 19. CMRR, PSRR vs. Frequency

110 100 1k 100k10k

CURRENT NOISE (pA/√Hz)

FREQUENCY (Hz)

10M1M

VS = ±2. 5V

G = +1

13391-018

Figure 20. Current Noise vs. Frequency (See Figure 48)

13391-601

ISOLATION (dB)

FREQUENCY (MHz)

–90

–80

–70

–60

–50

–40

–30

–20

–10

0.01 0.1 110 100

= ±2. 5V

G = +1

= 2kΩ

= 0.5 V p-p

SHUT DO WN = –V

SLEEP = –V

Figure 21. Forward Isolation vs. Frequency

= +5V

G = +1

OUT

= 2V STEP

= 2kΩ

SETTLING (%)

–0.3

–0.2

–0.1

0.1

0.2

0.3

020 40 60 80 100

TIME (n s)

120 140 160 180

13391-030

Figure 22. Settling Time to 0.1%

Data Sheet ADA4806-1

Rev. A | Page 13 of 24

13391-613

NUMBER OF UNITS

INPUT OFFSET VOLTAGE (µV)

–120 –90 –60 –30 030 60 90 120

500

1000

1500

2000

2500

3000

3500

4000

4500

VS = ±2. 5V

= 9.8µV

σ = 19.5µV

Figure 23. Input Offset Voltage Distribution

–100

–80

–60

–40

–20

100

–

3.0

–

2.5

–

2.0

–

1.5

–1

–

0.5 00.5 1.0 1.5 2.0

INPUT OFFSET VOLTAGE (µV)

INPUT COMMON-MODE VOLTAG E (V)

VS = ±2. 5V

10 UNITS

13391-327

Figure 24. Input Offset Voltage vs. Input Common-Mode Voltage

–40 –25 –10 520 35 50 65 80 95 110 125

INPUT BI AS CURRE NT ( nA)

TEMPERAT URE ( °C)

= ±2. 5V

= ±1. 5V

= ±5V

390

410

430

450

470

490

510

530

550

570

590

610

630

650

13391-257

Figure 25. Input Bias Current vs. Temperature for Various Supplies

(See Figure 49)

–1.6 –1.2 –0.8 –0.4 00.4 0.8 1.2 1.6

UNITS (%)

INPUT OFFSET VOLTAGE DRIFT (µV/°C)

= ±2. 5V

T = –40°C TO +125°C

= –0.19µV/ °C

σ = 0.28µV/°C

13391-323

Figure 26. Input Offset Voltage Drift Distribution

–150

–100

–50

100

150

–40 –25 –10 520 35 50 65 80 95 110 125

INPUT OFFSET VOLTAGE (µV)

TEMPERAT URE ( °C)

= ±2. 5V

30 UNITS

13391-013

Figure 27. Input Offset Voltage vs. Temperature

–

–800

–750

–700

–650

–600

–550

–500

–450

–400

–

0.4 00.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0

INPUT O FFS E T CURRENT ( nA)

INPUT BI AS CURRE NT (n A)

INPUT COMMON-MODE VOLTAG E (V)

INPUT O FFS E T CURRENT

B+

B–

13391-135

Figure 28. Input Bias Current and Input Offset Current vs.

Input Common-Mode Voltage

ADA4806-1 Data Sheet

Rev. A | Page 14 of 24

–15

–10

–5

050 100 150 200 250 300

OUTPUT VOLTAGE (mV)

TIME (ns)

G = +1

OUT

= 20mV p - p

= ±5V

= ±1. 5V

= ±2. 5V

13391-024

Figure 29. Small Signal Transient Response for Various Supplies

0100200300400500

TIME (ns)6007008009001000

–3

–4

–2

–1

INPUT AND OUTPUT VOLTAGE (V)

=±2.5V

G = +1

OUT

13391-128

Figure 30. Input Overdrive Recovery Time

13391-602

OUTPUT VOLTAGE (V)

TIME (µs)

–0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0–0.5 0.5 1.51.0 2.0

= ±2. 5V

G = +1

= 2kΩ

+125°C

+25°C

–40°C

Figure 31. Turn-On Response Time from Shutdown for Various Temperatures

(See Figure 50)

–1.5

–1.0

–0.5

0.5

1.0

1.5

050 100 150 200 250 350300

OUTPUT VOLTAGE (V)

TIME (ns)

= ±1. 5V, V

IN, CM

= –0.5V, V

OUT

= 1V p-p

= ±2. 5V, V

IN, CM

= 0V, V

OUT

= 2V p-p

= ±5V, V

IN, CM

= 0V, V

OUT

= 2V p-p G = +1

13391-025

Figure 32. Large Signal Transient Response for Various Supplies

–5

–4

–3

–2

–1

INPUT AND OUT P UT VOLTAGE (V)

= ±2.5V

G = +2

2×V

OUT

0100 200 300 400 500

TIME (n s)600 700 800 900 1000

13391-129

Figure 33. Output Overdrive Recovery Time

13391-605

OUTPUT VOLTAGE (V)

TIME (µs)

–0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

–0.25 00.25 0.50 0.75

+125°C

+25°C

–40°C

VS = ±2. 5V

G = +1

RL = 2kΩ

Figure 34. Turn-On Response Time from Sleep for Various Temperatures

(See Figure 50)

Data Sheet ADA4806-1

Rev. A | Page 15 of 24

100

200

300

400

500

600

700

800

0 1–1 2 3 4 5 6

SUPPLY CURRENT (µA)

TIME (µs)

+125°C

+25°C

–

40°C

= ±2. 5V

G = +1

= 2kΩ

13391-258

Figure 35. Turn-Off Response Time to Shutdown for Various Temperatures

(See Figure 51)

13391-603

OUTPUT VOLTAGE (V)

TIME (µs)

–0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

–1 0123

G = +1

= 2kΩ

= +2/ –1V

= ±2. 5V

= ±5V

Figure 36. Turn-On Response Time from Shutdown for Various Supplies

100

200

300

400

500

600

800

700

0 1–1 2 3 4 5 6

SUPPLY CURRENT (µA)

TIME (µs)

= ±1. 5V

= ±5V

= ±2. 5V

G = +1

= 2kΩ

13391-242

Figure 37. Turn-Off Response Time to Shutdown for Various Supplies

13391-607

SUPPLY CURRE NT (µA)

TIME (µs)

100

200

300

400

500

600

700

800

–1 0123456

= ±2. 5V

G = +1

= 2kΩ

+125°C

+25°C

–40°C

Figure 38. Turn-Off Response Time to Sleep for Various Temperatures

(See Figure 51)

13391-608

OUTPUT VOLTAGE (V)

TIME (µs)

–0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

00.5–0.25 0.25 0.75

G = +1

= 2kΩ

= ±5V

= +2V/–1V

= ±2. 5V

Figure 39. Turn-On Response Time from Sleep for Various Supplies

13391-609

SUPPLY CURRE NT (µA)

TIME (µs)

100

200

300

400

500

600

700

800

–1 0123456

G = +1

= 2kΩ

= ±5V

= ±2. 5V

= ±1. 5V

Figure 40. Turn-Off Response Time to Sleep for Various Supplies

ADA4806-1 Data Sheet

Rev. A | Page 16 of 24

300

350

400

450

500

550

600

650

700

750

800

–40 –25 –10 520 35 50 65 80 95 110 125

QUIESCENT SUPPLY CURRENT ( µA)

TEMPERAT URE ( °C)

= ±2. 5V

= ±1. 5V

= ±5V

13391-256

Figure 41. Quiescent Supply Current vs. Temperature

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0

SHUTDOWN AND SLE EP THRES HOLD ( V )

SUPPLY VOLTAGE FROM GRO UND ( V )

+125°C

+25°C

–40°C

13391-236

Figure 42. SHUTDOWN and SLEEP Threshold vs. Supply Voltage from Ground

for Various Temperatures

21.5

22.0

22.5

23.0

23.5

24.0

24.5

25.0

25.5

–5

–4

–3

–2

–1

0200 400 600 800 1000 1200 1400

TEMPERAT URE ( °C)

CHANGE IN INPUT OFFSET VOLTAGE (µV)

TIME (Hours)

OIL BATH

TEMPERATURE

= ±2. 5V

6 UNIT S , SO LDERE D TO PCB

13391-542

Figure 43. Long-Term VOS Drift

13391-606

QUI E S CE NT SUPP LY CURRE NT (µA)

TEMPERATURE (°C)

110

100

120

130

140

–40 –25 –10 520 35 50 65 80 95 110 125

= ±2. 5V

= ±1. 5V

= ±5. 0V

Figure 44. Sleep Mode Quiescent Supply Current vs. Temperature

13391-604

OUTPUT CURRE NT (mA)

TEMPERATURE (°C)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

–40 –25 –10 520 35 50 65 80 95 110 125

= ±2. 5V

= ±1. 5V

= ±5. 0V

Figure 45. Sleep Mode Output Current vs. Temperature

–180

–160

–140

–120

–100

–80

–60

–40

–20

100

120

10 100 1k 10k 100k 1M 10M 100M

OPEN-LOOP PHASE (Degrees)

OPEN-LOOP GAIN ( dB)

FREQUENCY (Hz)

GAIN

PHASE

13391-026

Figure 46. Open-Loop Gain and Phase Margin

Data Sheet ADA4806-1

Rev. A | Page 17 of 24

TEST CIRCUITS

50Ω

+2.5V

–2.5V

OUT

2kΩC

20mV p-

13391-401

Figure 47. Output Capacitive Load Behavior Test Circuit (See Figure 11)

75kΩ

+2.5V

–2.5V

VOUT

13391-402

Figure 48. Current Noise Test Circuit (See Figure 20)

IB+

IB–

13391-403

Figure 49. Input Bias Current Temperature Test Circuit (See Figure 25)

–2.5V

–

–2.5V

SHUTDOWN OR SLEEP

+2.5

OUT

2kΩ

13391-404

Figure 50. Turn-On Response Test Circuit (See Figure 31 and Figure 34)

–2.5V

+2.5

OUT

2kΩ

–

13391-405

SHUTDOWN OR SLEE

Figure 51. Turn-Off Response Test Circuit (See Figure 35 and Figure 38)

ADA4806-1 Data Sheet

Rev. A | Page 18 of 24

THEORY OF OPERATION

AMPLIFIER DESCRIPTION

The ADA4806-1 has a bandwidth of 105 MHz and a slew rate of

160 V/µs. It has an input referred voltage noise of only 5.9 nV/√Hz.

The ADA4806-1 operates over a supply voltage range of 2.7 V to

10 V and consumes only 500 µA of supply current at VS = 5 V. The

low end of the supply range allows −10% variation of a 3 V supply.

The amplifier is unity-gain stable, and the input structure results in

an extremely low input 1/f noise. The ADA4806-1 uses a slew

enhancement architecture, as shown in Figure 52. The slew

enhancement circuit detects the absolute difference between the

two inputs. It then modulates the tail current, ITAIL, of the input

stage to boost the slew rate. The architecture allows a higher

slew rate and fast settling time with low quiescent current while

maintaining low noise.

+IN

VIN+ VIN–

+VS

INPUT

STAGE

TO DET E CT

ABSOLUTE

VALUE

SLE W ENHANCE M E NT CIRCUIT

ITAIL

–IN

13391-255

Figure 52. Slew Enhancement Circuit

INPUT PROTECTION

The ADA4806-1 is fully protected from ESD events,

withstanding human body model ESD events of ±3.5 kV and

charged device model events of ±1.25 kV with no measured

performance degradation. The precision input is protected with

an ESD network between the power supplies and diode clamps

across the input device pair, as shown in Figure 53.

+IN

ESD

–V

BIAS

TO THE REST OF THE AMPLIFIER

–IN

ESD

13391-005

Figure 53. Input Stage and Protection Diodes

For differential voltages above approximately 1.2 V at room

temperature, and 0.8 V at 125°C, the diode clamps begin to

conduct. If large differential voltages must be sustained across

the input terminals, the current through the input clamps must

be limited to less than 10 mA. Series input resistors that are sized

appropriately for the expected differential overvoltage provide

the needed protection.

The ESD clamps begin to conduct for input voltages that are

more than 0.7 V above the positive supply and input voltages

more than 0.7 V below the negative supply. If an overvoltage

condition is expected, the input current must be limited to less

than 10 mA.

SHUTDOWN/SLEEP MODE OPERATION

Figure 54 shows the ADA4806-1 shutdown circuitry. To

maintain very low supply current in shutdown mode, no internal

pull-up resistor is supplied; therefore, the SHUTDOWN pin must

be driven high or low externally and must not be left floating.

Pulling the SHUTDOWN pin to ≥1 V below midsupply turns the

device off, reducing the supply current to 2.9 µA for a 5 V supply.

When the amplifier is powered down, its output enters a high

impedance state. The output impedance decreases as frequency

increases. In shutdown mode, a forward isolation of −62 dB can

be achieved at 100 kHz (see Figure 21).

A second circuit similar to Figure 54 is used for sleep mode

operation. Pulling the SLEEP pin low places the amplifier in a low

power state, drawing only 74 µA from a 5 V supply. Leaving the

amplifier biased on at a very low level greatly reduces the turn-

on time from sleep to full power mode, thus enabling dynamic

power scaling of the ADA4806-1 at higher sample rates.

The ADA4806-1 is not characterized for operation in sleep mode.

–V

SHUTDOWN

ESD

2.2R

1.8R

1.1V

TO ENABL E

AMPLIFIER

13391-006

Figure 54. Shutdown/Sleep Equivalent Circuit

The SHUTDOWN pin and the SLEEP pin are protected by ESD

clamps, as shown in Figure 54. Voltages beyond the power supplies

cause these diodes to conduct. To protect the SHUTDOWN and

SLEEP pins, ensure that the voltage to these pins does not

exceed 0.7 V above the positive supply or 0.7 V below the

negative supply. If an overvoltage condition is expected, the

input current must be limited to less than 10 mA with a series

resistor.

Data Sheet ADA4806-1

Rev. A | Page 19 of 24

Table 8 summarizes the threshold voltages for the

SHUTDOWN and SLEEP pins for various supplies. Table 9

shows the truth table for the SHUTDOWN and SLEEP pins.

Table 8. Threshold Voltages for Enabled Mode and

Shutdown/Sleep Modes

Mode +3 V +5 V ±5 V +7 V/−2 V

Enabled >+1.1 V >+1.9 V >−0.9 V >+1.6 V

Shutdown/Sleep

Mode

<+0.7 V <+1.5 V <−1.3 V <+1.2 V

Table 9. Truth Table for the SHUTDOWN and SLEEP Pins

SHUTDOWN SLEEP Operating State

Low Low Powered down

Low

High

Powered down

High Low Low power mode

High High Full power mode

NOISE CONSIDERATIONS

Figure 55 shows the primary noise contributors for the typical

gain configurations. The total output noise (vn_OUT) is the root

sum square of all the noise contributions.

n–

4kTR

n_RS

4kTR

n_RG

n_RF

+ V

n_OUT

4kTR

13391-034

Figure 55. Noise Sources in Typical Connection

The output noise spectral density is calculated by

[ ]

222

4414

OUTn

RikTR

vRikTRs

kTR

−+













+++











++

where:

k is Boltzmann’s constant.

T is the absolute temperature in degrees Kelvin.

RF and RG are the feedback network resistances, as shown in

Figure 55.

RS is the source resistance, as shown in Figure 55.

in+ and in− represent the amplifier input current noise spectral

density in pA/√Hz.

vn is the amplifier input voltage noise spectral density in

nV/√Hz.

Source resistance noise, amplifier input voltage noise (vn), and

the voltage noise from the amplifier input current noise

(in+ × RS) are all subject to the noise gain term (1 + RF/RG).

Figure 56 shows the total referred to input (RTI) noise due to

the amplifier vs. the source resistance. Note that with a

5.9 nV/√Hz input voltage noise and 0.6 pA/√Hz input current

noise, the noise contributions of the amplifier are relatively

small for source resistances from approximately 2.6 kΩ to

47 kΩ.

The Analog Devices, Inc., silicon germanium (SiGe) bipolar

process makes it possible to achieve a low noise of 5.9 nV/√Hz

for the ADA4806-1. This noise is much improved compared to

similar low power amplifiers with a supply current in the range

of hundreds of microamperes.

100

1000

100 1k 10k 100k 1M

RTI NOISE (nV/√Hz)

SOURCE RE S IS TANCE (Ω)

TOTAL NOISE

SOURCE RE S IS TANCE NOISE

AMPLIFIER NOISE

SOURCE RE S IS TANCE = 2.6kΩ

SOURCE RE S IS TANCE = 47kΩ

13391-051

Figure 56. RTI Noise vs. Source Resistance

ADA4806-1 Data Sheet

Rev. A | Page 20 of 24

APPLICATIONS INFORMATION

SLEW ENHANCEMENT

The ADA4806-1 has an internal slew enhancement circuit that

increases the slew rate as the feedback error voltage increases.

This circuit allows the amplifier to settle a large step response

faster, as shown in Figure 57. This is useful in ADC applications

where multiple input signals are multiplexed. The impact of the

slew enhancement can also be seen in the large signal frequency

response, where larger input signals cause a slight increase in

peaking, as shown in Figure 58.

TIME (ns)

OUTPUT VOLTAGE (V)

5040302010010090807060

VOUT

=500mV p-p

–0.5

–1.0

–1.5

0.5

1.0

1.5

VOUT = 2V p-p

VOUT = 1V p-p

VS = ±2. 5V

G = +1

RL = 2kΩ

13391-254

Figure 57. Step Response with Selected Output Steps

–6

–5

–4

–3

–2

–1

NORM ALIZED G AIN (d B)

FREQUENCY (Hz)

VS = ±2. 5V

G = +1

RL = 2kΩ

VIN = 400mV p-p

VIN = 100mV p-p

VIN = 200mV p-p

100k 1M 10M 100M

VIN = 632mV p-p

VIN = 2V p -p

13391-105

Figure 58. Peaking in Frequency Responses as Signal Level Changes, G = +1

EFFECT OF FEEDBACK RESISTOR ON FREQUENCY

RESPONSE

The amplifier input capacitance and feedback resistor form a

pole that, for larger value feedback resistors, can reduce phase

margin and contribute to peaking in the frequency response.

Figure 59 shows the peaking for selected feedback resistors (RF)

when the amplifier is configured in a gain of +2. Figure 59 also

shows how peaking can be mitigated with the addition of a

small value capacitor placed across the feedback resistor of the

amplifier.

–6

–5

–4

–3

–2

–1

NORM ALIZED G AIN (d B)

FREQUENCY (Hz)

100k 1M 10M 100M

= 1kΩ

= 2.6kΩ

= 2.6kΩ, C

= 1pF

= 4.99kΩ

= 4.99kΩ, C

= 1pF

= ±2. 5V

G = +2

= 2 kΩ

= 20mV p - p

13391-106

Figure 59. Peaking in Frequency Response at Selected RF Values

COMPENSATING PEAKING IN LARGE SIGNAL

FREQUENCY RESPONSE

At high frequency, the slew enhancement circuit can contribute to

peaking in the large signal frequency response. Figure 59 shows the

effect of a feedback capacitor on the small signal response, whereas

Figure 60 shows that the same technique is effective for reducing

peaking in the large signal response.

–15

–12

–9

–6

–3

NORM ALIZED G AIN (d B)

FREQUENCY (Hz)

= ±2. 5V

G = +2

= 2 kΩ

= 632mV p - p

= 2.6kΩ, C

= 0pF

= 1kΩ, C

= 0pF

= 2.6kΩ, C

= 2.7pF

= 1 kΩ, C

= 2 pF

100k 1M 10M 100M

13391-107

Figure 60. Peaking Mitigation in Large Signal Frequency Response

DRIVING LOW POWER, HIGH RESOLUTION

SUCCESSIVE APPROXIMATION REGISTER (SAR)

ADCs

The ADA4806-1 is ideal for driving low power, high resolution

SAR ADCs. The 5.9 nV/√Hz input voltage noise and rail-to-rail

output stage of the ADA4806-1 help minimize distortion at

large output levels. With its low power of 500 µA, the amplifier

consumes power that is compatible with low power SAR ADCs,

which are usually in the microwatt (µW) to low milliwatt (mW)

range. Furthermore, the ADA4806-1 supports a single-supply

configuration; the input common-mode range extends to 0.1 V

below the negative supply, and 1 V below the positive supply.

Data Sheet ADA4806-1

Rev. A | Page 21 of 24

Figure 61 shows a typical 16-bit, single-supply application. The

ADA4806-1 drives the AD7980, a 16-bit, 1 MSPS, SAR ADC in

a low power configuration. The AD7980 operates on a 2.5 V

supply and supports an input from 0 V to VREF. In this case, the

ADR435 provides a 5 V reference. The ADA4806-1 is used both

as a driver for the AD7980 and as a reference buffer for the

ADR435.

The low-pass filter formed by R3 and C1 reduces the noise to

the input of the ADC (see Figure 61). In lower frequency

applications, the designer can reduce the corner frequency of

the filter to remove additional noise.

AD7980

10µF

IN+

IN– GND

VDDREF

0.1µF C4

100nF

VDD

2.7nF

20Ω

+7.5V

ADA4806-1

ADR435

5V REF

0V TO

REF

13391-310

Figure 61. Driving the AD7980 with the ADA4806-1

In this configuration, the ADA4806-1 consume 7.2 mW of

quiescent power. The measured signal-to-noise ratio (SNR),

THD, and signal-to-noise-and-distortion ratio (SINAD) of the

whole system for a 10 kHz signal are 89.4 dB, 104 dBc, and

89.3 dB, respectively. This translates to an effective number of

bits (ENOB) of 14.5 at 10 kHz, which is compatible with the

AD7980 performance. Table 10 shows the performance of this

setup at selected input frequencies.

DYNAMIC POWER SCALING

One of the merits of a SAR ADC, like the AD7980, is that its

power scales with the sampling rate. This power scaling makes

SAR ADCs very power efficient, especially when running at a

low sampling frequency. However, the ADC driver used with

the SAR ADC traditionally consumes constant power regardless

of the sampling frequency.

Figure 62 illustrates a method by which the quiescent power of

the ADC driver can be dynamically scaled with the sampling

rate of the system. By providing properly timed signals to the

convert input (CNV) pin of the ADC and the SHUTDOWN

and SLEEP pins of the ADA4806-1, both devices can be run at

optimum efficiency.

+5V

2.7nF

20Ω

TIMING

GENERATOR

VIN

AD7980

ADA4806-1

REF VDD

GND

+6V +2.5V

0.1µF

CNV

13391-330

Figure 62. ADA4806-1/AD7980 Power Management Circuitry

Figure 63 illustrates the relative signal timing for power scaling

the ADA4806-1 and the AD7980. To prevent any degradation in

the performance of the ADC, the ADA4806-1 must have a fully

settled output into the ADC before the activation of the

CNV pin. The amplifier on-time (tAMP, ON) is the time the amplifier

is enabled prior to the rising edge of the CNV signal; this time

depends on whether the SHUTDOWN pin or SLEEP pin is being

driven. In the example shown in Figure 64, tAMP, ON is 3 µs for the

SHUTDOWN pin and 0.5 µs for the SLEEP pin. After a

conversion, the SHUTDOWN pin and/or the SLEEP pin of the

ADA4806-1 are pulled low when the ADC input is inactive in

between samples. While in shutdown mode, the ADA4806-1

output impedance is high.

Table 10. System Performance at Selected Input Frequencies for Driving the AD7980 Single-Ended

ADC Driver Reference Buffer Results

Input Frequency (kHz) Supply (V) Gain Supply (V) Gain SNR (dB) THD (dBc) SINAD (dB) ENOB

1 7.5 1 7.5 1 89.8 103 89.6 14.6

10 7.5 1 7.5 1 89.4 104 89.3 14.5

20 7.5 1 7.5 1 89.9 103 89.7 14.6

50 7.5 1 7.5 1 88.5 99 88.1 14.3

100

7.5

86.3

93.7

85.6

13.9

ADA4806-1 Data Sheet

Rev. A | Page 22 of 24

SAMPLING PERIOD,

ACQUISITION ACQUISITION ACQUISITION

POWERED

Q, ON

tAMP, OFF tAMP, OFF tAMP, OFF

tAMP, ON tAMP, ON tAMP, ON

ADC

CNV

ADA4806-1

SHUTDOWN/

SLEEP SHUTDOWN/SLEEPSHUTDOWN/SLEEPSHUTDOWN/SLEEP

CONVERSION CONVERSION CONVERSION

ADA4806-1

QUIESCENT

CURRENT

13391-329

Figure 63. Timing Waveforms

Figure 64 shows the quiescent power of the ADA4806-1,

operating from a single +6 V supply, without power scaling and

while power scaling via the SHUTDOWN pin and the SLEEP pin.

Without power scaling, the ADA4806-1 consumes constant

power regardless of the sampling frequency, as shown in

Equation 1.

PQ = IQ × VS (1)

With power scaling, the quiescent power becomes proportional

to the ratio between the amplifier on time, tAMP, O N , and the

sampling time, tS:











−

××+











××=

ONAMPS

SoffQ

ONAMP

SonQQ

VIP

(2)

Thus, by dynamically switching the ADA4806-1 between

shutdown/sleep and full power modes between consecutive

samples, the quiescent power of the driver scales with the

sampling rate.

Note that tA MP, O N in Figure 64 is 3 µs for the SHUTDOWN pin and

0.5 µs for the SLEEP pin.

13391-612

QUI E S CE NT POWE R CONSUMP TION (mW )

ADC SAMP LE RAT E ( ksps)

0.01

0.1

1.0

0.1 110 100 1000

CONTINUOUSLY ON

SLEEP MODE

SHUT DO WN MODE

AD7980 ADC

Figure 64. Quiescent Power Consumption of the ADA4806-1 vs.

ADC Sample Rate, Using Dynamic Power Scaling

Data Sheet ADA4806-1

Rev. A | Page 23 of 24

SINGLE-ENDED TO DIFFERENTIAL CONVERSION

Most high resolution ADCs have differential inputs to reduce

common-mode noise and harmonic distortion. Therefore, it is

necessary to use an amplifier to convert a single-ended signal

into a differential signal to drive the ADCs.

There are two common ways the user can convert a single-ended

signal into a differential signal: either use a differential

amplifier, or configure two amplifiers as shown in Figure 65.

The use of a differential amplifier yields better performance,

whereas the 2-op-amp solution results in lower system cost. The

ADA4806-1 solves this dilemma of choosing between the two

methods by combining the advantages of both. Its low harmonic

distortion, low offset voltage, and low bias current mean that it can

produce a differential output that is well matched with the

performance of the high resolution ADCs.

Figure 65 shows how the ADA4806-1 converts a single-ended

signal into a differential output. The first amplifier is configured

in a gain of +1 with its output then inverted to produce the

complementary signal. The differential output then drives the

AD7982, an 18-bit, 1 MSPS SAR ADC. To further reduce noise,

the user can reduce the values of R1 and R2. However, note that

this increases the power consumption. The low-pass filter of the

ADC driver limits the noise to the ADC.

The measured SNR, THD, and SINAD of the whole system for a

10 kHz signal are 93 dB, 113 dBc, and 93 dB, respectively. This

translates to an ENOB of 15.1 at 10 kHz, which is compatible

with the performance of the AD7982. Table 11 shows the

performance of this setup at selected input frequencies.

Table 11. System Performance at Selected Input Frequencies

for Driving the AD7982 Differentially

Results

Input Frequency (kHz)

SNR

(dB)

THD

(dBc)

SINAD

(dB) ENOB

1 93 104 93 15.1

10 93 113 93 15.1

20 93 110 93 15.1

50 92 102 91 14.8

100 89 96 88 14.3

LAYOUT CONSIDERATIONS

To ensure optimal performance, careful and deliberate attention

must be paid to the board layout, signal routing, power supply

bypassing, and grounding.

Ground Plane

It is important to avoid ground in the areas under and around the

input and output of the ADA4806-1. Stray capacitance between

the ground plane and the input and output pads of a device is

detrimental to high speed amplifier performance. Stray

capacitance at the inverting input, together with the amplifier

input capacitance, lowers the phase margin and can cause

instability. Stray capacitance at the output creates a pole in the

feedback loop, which can reduce phase margin and cause the

circuit to become unstable.

Power Supply Bypassing

Power supply bypassing is a critical aspect in the performance

of the ADA4806-1. A parallel connection of capacitors from

each power supply pin to ground works best. Smaller value

ceramic capacitors offer better high frequency response,

whereas larger value ceramic capacitors offer better low

frequency performance.

Paralleling different values and sizes of capacitors helps to ensure

that the power supply pins are provided with a low ac impedance

across a wide band of frequencies. This is important for minimizing

the coupling of noise into the amplifier—especially when the

amplifier PSRR begins to roll off—because the bypass capacitors

can help lessen the degradation in PSRR performance.

Place the smallest value capacitor on the same side of the board

as the amplifier and as close as possible to the amplifier power

supply pins. Connect the ground end of the capacitor directly to

the ground plane.

It is recommended that a 0.1 µF ceramic capacitor with a

0508 case size be used. The 0508 case size offers low series

inductance and excellent high frequency performance. Place a

10 µF electrolytic capacitor in parallel with the 0.1 µF capacitor.

Depending on the circuit parameters, some enhancement to

performance can be realized by adding additional capacitors.

Each circuit is different and must be analyzed individually for

optimal performance.

ADA4806-1

+7.5V

+2.5V +2.5V

VDD

1kΩ

1kΩ C2

2.7nF

0.1µF

2.7nF

0.1µF

22Ω

AD7982

IN+

IN–

REF

+5V

VDD

13391-053

Figure 65. Driving the AD7982 with the ADA4806-1

ADA4806-1 Data Sheet

Rev. A | Page 24 of 24

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-178-BA

8°

4°

0°

SEATING

PLANE

1.95

BSC

0.65 BSC

0.60

BSC

7 6

1 2 3 4

3.00

2.90

2.80

3.00

2.80

2.60

1.70

1.60

1.50

1.30

1.15

0.90

0.15 MAX

0.05 MIN

1.45 MAX

0.95 MIN

0.22 MAX

0.08 MIN

0.38 MAX

0.22 MIN

0.60

0.45

0.30

PIN 1

INDICATOR

12-16-2008-A

Figure 66. 8-Lead Small Outline Transistor Package [SOT-23]

(RJ-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADA4806-1ARJZ-R2 −40°C to +125°C 8-Lead Small Outline Transistor Package [SOT-23] RJ-8

ADA4806-1ARJZ-R7 −40°C to +125°C 8-Lead Small Outline Transistor Package [SOT-23] RJ-8

ADA4806-1RJ-EBZ Evaluation Board for 8-Lead SOT-23

1 Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D13391-0-5/17(A)