Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1995
1996 Integrated Device Technology, Inc. 9.2 DSC-2920/5
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
IDT49FCT805BT/CT
IDT49FCT806BT/CT
IDT49FCT805T IDT49FCT806T
FEATURES:
• 0.5 MICRON CMOS Technology
• Guaranteed low skew < 500ps (max.)
• Very low duty cycle distortion < 600ps (max.)
• Low CMOS power levels
• TTL compatible inputs and outputs
• TTL level output voltage swings
• High drive: -32mA IOH, 48mA IOL
• Two independent output banks with 3-state control
• 1:5 fanout per bank
• ‘Heartbeat’ monitor output
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in DIP, SOIC, SSOP, QSOP, Cerpack and
LCC packages
OE
A
5
5
IN
A
IN
B
OE
B
OA
1
-OA
5
OB
1
-OB
5
MON
2920 drw 01
FAST CMOS
BUFFER/CLOCK DRIVER
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT49FCT805BT/CT and IDT49FCT806BT/CT are
clock drivers built using advanced dual metal CMOS technol-
ogy. The IDT49FCT805BT/CT is a non-inverting clock driver
and the IDT49FCT806BT/CT is an inverting clock driver. Each
device consists of two banks of drivers. Each bank drives five
output buffers from a standard TTL compatible input. The
805BT/CT and 806BT/CT have extremely low output skew,
pulse skew, and package skew. The devices has a "heart-
beat" monitor for diagnostics and PLL driving. The MON
output is identical to all other outputs and complies with the
output specifications in this document. The 805BT/CT and
806BT/CT offer low capacitance inputs with hysteresis.
FUNCTIONAL BLOCK DIAGRAMS
OEA
5
5
INA
INB
OEB
OA1-OA5
OB1-OB5
2920 drw 02
MON
IDT49FCT805BT/CT, 806BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.2 2
PIN CONFIGURATIONS
IDT49FCT805T
IDT49FCT806T
INDEX
LCC
TOP VIEW
3 2 20 19
1
4
5
6
7
8
18
17
16
15
14
910111213
L20-2
OA
3
GND
OA
4
OA
5
GND
OB
2
OB
3
GND
OB
4
OB
5
2920 drw 04
OE
A
IN
A
IN
B
OE
B
MON
OA
2
OA
1
V
CC
V
CC
OB
1
PIN DESCRIPTION
2920 tbl 01
FUNCTION TABLE(1)
OB1
OA1
OA3
GND
OA4
OA5
OA2
OEA
INA
OB2
OB3
GND
OB4
MON
INB
OB5
OEB
VCC
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
E20-1
VCC
2920 drw 03
GND
OB1
GND
GND
INA
OB2
OB3
GND
OB4
MON
INB
OB5
OEB
VCC
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
E20-1
VCC
2920 drw 05
OA1
OA3
OA2
OA4
OA5
OEA
OB
2
OB
3
GND
OB
4
OB
5
INDEX
LCC
TOP VIEW
3 2 20 19
1
4
5
6
7
8
18
17
16
15
14
9 10111213
L20-2
GND
GND
2920 drw 06
OA
3
OA
4
OA
5
OE
A
IN
A
IN
B
OE
B
MON
OA
2
OA
1
V
CC
V
CC
OB
1
Pin Names Description
OE
A,
OE
B3-State Output Enable Inputs (Active LOW)
INA, INBClock Inputs
OAn, OBnClock Outputs (FCT805T)
OA
n,
OB
nClock Outputs (FCT806T)
MON Monitor Output (FCT805T)
MON
Monitor Output (FCT806T)
Outputs
Inputs 49FCT805T 49FCT806T
OE
OE
A,
OE
OE
BINA, INBOAn, OBnMON
OA
OA
n,
OB
OB
n
MON
MON
LLLLHH
LHHHLL
HLZLZH
HHZHZL
NOTE: 2920 tbl 02
1. H = HIGH, L = LOW, Z = High Impedance
IDT49FCT805BT/CT, 806BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.2 3
ABSOLUTE MAXIMUM RATINGS(1) CAPACITANCE (TA = +25°C, f = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested. 2920 lnk 04
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input
Capacitance VIN = 0V 4.5 6.0 pF
COUT Output
Capacitance VOUT = 0V 5.5 8.0 pF
Symbol Rating Commercial Military Unit
VTERM(2) Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0 V
VTERM(3) Terminal Voltage
with Respect to
GND
–0.5 to VCC
+0.5 –0.5 to VCC
+0.5 V
TAOperating
Temperature 0 to +70 –55 to +125 °C
TBIAS Temperature
Under Bias –55 to +125 –65 to +135 °C
TSTG Storage
Temperature –55 to +125 –65 to +150 °C
IOUT DC Output
Current –60 to +120 –60 to +120 mA
2920 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specifica-
tion is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals.
3. Output and I/O terminals.
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
2920 lnk 05
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
V
IH
Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
V
IL
Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
I
I H
Input HIGH Current
(5)
V
CC
= Max. V
I
= 2.7V — —
±
1
µ
A
I
I L
Input LOW Current
(5)
V
CC
= Max. V
I
= 0.5V — —
±
1
µ
A
I
OZH
High Impedance Output Current V
CC
= Max. V
O
= 2.7V — —
±
1
µ
A
I
OZL
(3-State Output pins)
(5)
V
O
= 0.5V — —
±
1
µ
A
I
I
Input HIGH Current
(5)
V
CC
= Max., V
I
= V
CC
(Max.) — —
±
1
µ
A
V
IK
Clamp Diode Voltage V
CC
= Min., I
IN
= –18mA — –0.7 –1.2 V
I
OS
Short Circuit Current V
CC
= Max.
(3)
, V
O
= GND –60 –120 –225 mA
V
OH
Output HIGH Voltage V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L. 2.4 3.3 — V
I
OH
= –24mA MIL.
I
OH
= –32mA COM'L.
(4)
2.0 3.0 —
V
OL
Output LOW Voltage V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 32mA MIL.
I
OL
= 48mA COM'L. — 0.3 0.55 V
I
OFF
Input/Output Power Off Leakage
(5)
V
CC
= 0V, V
IN
or V
O
≤
4.5V — —
±
1
µ
A
V
H
Input Hysteresis for all inputs — — 150 — mV
I
CCL
I
CCH
I
CCZ
Quiescent Power Supply Current V
CC
= Max., V
IN
= GND or V
CC
— 5 500
µ
A
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
IDT49FCT805BT/CT, 806BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.2 4
POWER SUPPLY CHARACTERISTICS
2920 tbl 06
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fONO)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fO= Output Frequency
NO= Number of Outputs at fO
All currents are in milliamps and all frequencies are in megahertz.
Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
∆I
CC
Quiescent Power Supply Current
TTL Inputs HIGH V
CC
= Max.
V
IN
= 3.4V
(3)
— 0.5 2.0 mA
I
CCD
Dynamic Power Supply Current
(4)
V
CC
= Max.
Outputs Open
OE
A
=
OE
B
= GND
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND — 60 100
µ
A/
MHz/bit
I
C
Total Power Supply Current
(6)
V
CC
= Max.
Outputs Open
fo = 25MHz
V
IN
= V
CC
V
IN
= GND — 1.5 3.0 mA
50% Duty Cycle
OE
A
=
OE
B
=V
CC
Mon. Output Toggling
V
IN
= 3.4V
V
IN
= GND — 1.8 4.0
V
CC
= Max.
Outputs Open
fo = 50MHz
V
IN
= V
CC
V
IN
= GND — 33 55.5
(5)
50% Duty Cycle
OE
A
=
OE
B
= GND
Eleven Outputs
Toggling
V
IN
= 3.4V
V
IN
= GND — 33.5 57.5
(5)
IDT49FCT805BT/CT, 806BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.2 5
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay
limits do not imply skew.
2920 tbl 07
IDT49FCT805BT/806BT IDT49FCT805CT/806CT
Com'l. Mil. Com'l. Mil.
Symbol Parameter Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
tPLH
tPHL Propagation Delay
INA to OAn, INB to OBnCL = 50pF
RL = 500Ω1.5 5.0 1.5 5.7 1.5 4.5 1.5 5.2 ns
tROutput Rise Time — 1.5 — 2.0 — 1.5 — 2.0 ns
tFOutput Fall Time — 1.5 — 1.5 — 1.5 — 1.5 ns
tSK(o) Output skew: skew between outputs of all
banks of same package (inputs tied together) — 0.7 — 0.9 — 0.5 — 0.7 ns
tSK(p) Pulse skew: skew between opposite
transitions of same output (|tPHL–tPLH|) — 0.7 — 0.9 — 0.6 — 0.8 ns
tSK(t) Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
— 1.2 — 1.5 — 1.0 — 1.2 ns
tPZL
tPZH Output Enable Time
OE
A to OAn,
OE
B to OBn1.5 6.0 1.5 6.5 1.5 5.0 1.5 6.0 ns
tPLZ
tPHZ Output Disable Time
OE
A to OAn,
OE
B to OBn1.5 6.0 1.5 6.5 1.5 5.0 1.5 6.0 ns
IDT49FCT805BT/CT, 806BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.2 6
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUIT FOR ALL OUTPUTS ENABLE AND DISABLE TIME
SWITCH POSITION
Test Switch
Disable LOW
Enable LOW Closed
Disable HIGH
Enable HIGH Open
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT =Termination resistance: should be equal to ZOUT of the Pulse
Generator.
2920 lnk 08
Pulse
Generator
RT
D.U.T.
VCC
VIN
CL
VOUT
50pF 500Ω
500Ω
7.0V
2920 drw 07
tPLH1
OUTPUT 1
OUTPUT 2
tSK(o)
tPLH2
3V
0V
VOH
1.5V
1.5V
VOL
VOH
1.5V
VOL
INPUT tPHL1
tPHL2
tSK(o)
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
3V
1.5V
0V
3.5V
0V
SWITCH
CLOSED
SWITCH
OPEN
VOL
VOH
0.3V
0.3V
tPLZtPZL
tPZH tPHZ
3.5V
0V
1.5V
1.5V
ENABLE DISABLE
3V
0V
VOH
tPLH tPHL
VOL
1.5V
1.5V
tRtF
2.0V
0.8V
INPUT
OUTPUT
INPUT tPLH1
PACKAGE 1 OUTPUT
PACKAGE 2 OUTPUT
tSK(t)
tPLH2
3V
0V
VOH
1.5V
1.5V
VOL
VOH
1.5V
VOL
tPHL1
tPHL2
tSK(t)
tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
tPLH tPHL
3V
0V
VOH
1.5V
1.5V
VOL
tSK(p) = |tPHL - tPLH|
INPUT
OUTPUT
PULSE SKEW - tSK(p) PACKAGE SKEW - tSK(t)
PACKAGE DELAY OUTPUT SKEW- tSK(o)
Package 1 and Package 2 are same device type and speed grade
ENABLE AND DISABLE TIMES
2920 drw 08
2920 drw 10
2920 drw 09
2920 drw 11
2920 drw 12
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
IDT49FCT805BT/CT, 806BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.2 7
ORDERING INFORMATION
XXX
Device Type XX
Package X
Process/
Blank
B
P
D
E
L
SO
PY
Q
805BT
806BT
805CT
806CT
Commercial (0
°
C to +70
°
C)
MIL-STD-883, Class B (–55
°
C to +125
°
C)
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline IC
Quarter-size Small Outline Package
Non-Inverting Buffer/Clock Driver
Inverting Buffer/Clock Driver
Temperature Range
2920 drw 13
IDT49FCT
