TMP106YZCRG4 - Burr-Brown / Texas Instruments

FEATURES

DTWO ADDRESSES

DDIGITAL OUTPUT: Two-Wire Serial Interface

DRESOLUTION: 9- to 12-Bits, User-Selectable

DACCURACY:

±2.0°C (max) from −25°C to +85°C

±3.0°C (max) from −40°C to +125°C

DLOW QUIESCENT CURRENT:

50µA, 0.1µA Standby

DNO POWER-UP SEQUENCE REQUIRED, I2C

PULLUPS CAN BE ENABLED PRIOR TO V+

APPLICATIONS

DNOTEBOOK COMPUTERS

DCOMPUTER PERIPHERAL THERMAL

PROTECTION

DCELL PHONES

DBATTERY MANAGEMENT

DTHERMOSTAT CONTROLS

DENVIRONMENTAL MONITORING AND HVAC

SDA

SCL

V+

GND

ALERT

YZC LEAD−FREE

2 X 3 ARRAY

(TOP VIEW)

Note: Pin A1 is marked with a for Pb−free (YZC)

1,65 mm

1,50 mm

1,15 mm

1,00 mm

(Bump Side Down)

‘’

DESCRIPTION

The TMP106 is a two-wire, serial output temperature

sensor available in a WCSP package. Requiring no

external components, the TMP106 is capable of reading

temperatures with a resolution of 0.0625°C.

The TMP106 features a Two-Wire interface that is

SMBus-compatible, with the TMP106 allowing up to two

devices on one bus. The TMP106 also features an SMBus

Alert function.

The TMP106 is ideal for extended temperature

measurement in a variety of communication, computer,

consumer, environmental, industrial, and instrumentation

applications.

The TMP106 is specified for operation over a temperature

range of −40°C to +125°C.

Diode

Temp.

Sensor

∆Σ

A/D

Converter

OSC

Control

Logic

Serial

Interface

Config.

and Temp.

TMP106

Temperature

V+

SDA A1

GND

SCL B1 B2 ALERT

TMP106

SLLS672A − OCTOBER 2005 − REVISED JANUAR Y 2006

Digital Temperature Sensor

with Two-Wire Interface

Chip-Scale

Package

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

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ABSOLUTE MAXIMUM RATINGS(1)

Power Supply, V+ 7.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Voltage(2) −0.5V to 7.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Current 10mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating Temperature Range −55 °C to +127°C. . . . . . . . . . . . . . .

Storage Temperature Range −60 °C to +130°C. . . . . . . . . . . . . . . . .

Junction Temperature (TJ max) +150°C. . . . . . . . . . . . . . . . . . . . . .

ESD Rating(3):

Human Body Model (HBM) 2000V. . . . . . . . . . . . . . . . . . . . . . .

Charged-Device Model (CDM) 500V. . . . . . . . . . . . . . . . . . . . . .

Machine Model (MM) 200V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(1) Stresses above these ratings may cause permanent damage.

Exposure t o absolute maximum conditions for extended periods

may degrade device reliability. These are stress ratings only, an d

functional operation of the device at these or any other conditions

beyond those specified is not supported.

(2) Input voltage rating applies to all TMP106 input voltages.

(3) ESD testing has been tested to TI specifications JEDEC

J−Std 020.

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be

handled with appropriate precautions. Failure to observe

proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

ORDERING INFORMATION(1)

PACKAGE P ART NUMBER SYMBOL

W afer chip-scale package (YZC) TMP106YZC F7

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website

at www.ti.com.

PIN ASSIGNMENTS

SDA

SCL

V+

GND

ALERT

WCSP−6 PACKAGE

(TOP VIEW)

Note: Pin 1 is determined by orienting the package marking as indicated in the diagram.

(Bump Side Down)

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ELECTRICAL CHARACTERISTICS

At TA = −40°C to +125°C, and V+ = 2.7V to 5.5V, unless otherwise noted.

PARAMETER

CONDITION

TMP106

UNITS

PARAMETER

CONDITION

MIN TYP MAX

UNITS

TEMPERATURE INPUT

Range −40 +125 °C

Accuracy (Temperature Error) −25°C to +85°C±0.5 ±2.0 °C

−40°C to +125°C±1.0 ±3.0 °C

vs Supply 0.2 ±0.5 °C/V

Resolution(1) Selectable 0.0625 °C

DIGITAL INPUT/OUTPUT

Input Capacitance 3 pF

Input Logic Levels:

VIH 2.1 6.0 V

VIL −0.5 0.8 V

Leakage Input Current, IIN 0V ≤ VIN ≤ 6V 1µA

Input Voltage Hysteresis SCL and SDA Pins 250 mV

Output Logic Levels:

VOL SDA IOL = 3mA 0 0.15 0.4 V

VOL ALERT IOL = 4mA 0 0.15 0.4 V

Resolution Selectable 9 to 12 Bits

Conversion Time 9-Bit 27.5 37.5 ms

10-Bit 55 75 ms

11-Bit 110 150 ms

12-Bit 220 300 ms

Timeout Time 25 54 74 ms

POWER SUPPLY

Operating Range 2.7 5.5 V

Quiescent Current IQSerial Bus Inactive 50 85 µA

Serial Bus Active, SCL Freq = 400kHz 100 µA

Serial Bus Active, SCL Freq = 3.4MHz 410 µA

Shutdown Current ISD Serial Bus Inactive 0.1 3 µA

Serial Bus Active, SCL Freq = 400kHz 60 µA

Serial Bus Active, SCL Freq = 3.4MHz 380 µA

TEMPERATURE RANGE

Specified Range −40 +125 °C

Operating Range −55 +127 °C

Thermal Resistance qJA 240 °C/W

(1) Specified for 12-bit resolution.

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TYPICAL CHARACTERISTICS

At TA = +25°C and V+ = 5.0V, unless otherwise noted.

QUIESCENT CURRENT vs TEMPERATURE

Temperature (_C)

−50 −25 0 25 50 75 100 125

IQ(µA)

V+ = 2.7V

Serial Bus Inactive

V+ = 5V

300

250

200

150

100

CONVERSION TIME vs TEMPERATURE

Temperature (_C)

Conversion Time (ms)

−50 −25 0 25 50 75 100 125

V+ = 2.7V

V+=5V

12−bit resolution.

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

−0.1

SHUTDOWN CURRENT vs TEMPERATURE

Temperature (_C)

ISD (µA)

−55 −35 −15 5 25 45 65 85 105 125

V+=2.8V

2.0

1.5

1.0

0.5

0.0

−0.5

−1.0

−1.5

−2.0

TEMPERATURE ACCURACY vs TEMPERATURE

Temperature Error (_C)

3 typical units 12−bit resolution.

Temperature (_C)

−55 −35 −15 5 25 45 65 85 105 125

500

450

400

350

300

250

200

150

100

QUIESCENT CURRENT WITH

BUS ACTIVITY vs TEMPERATURE

Frequency (Hz)

1k 10k 100k 1M 10M

IQ(µA)

125_C

25_C

−55_C

Hs MODE

FAST MODE

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APPLICATIONS INFORMATION

The TMP106 is a digital temperature sensor that is optimal

for thermal management and thermal protection

applications. The TMP106 is Two-Wire and SMBus

interface-compatible, and is specified over a temperature

range of −40°C to +125°C.

The TMP106 requires no external components for

operation except for pull-up resistors on SCL, SDA, and

ALERT, although a 0.1µF bypass capacitor is

recommended, as shown in Figure 1.

TMP106

0.1µF

V+

GND

ALERT

(Output)

SCL

SDA

Two−Wire

Controller

NOTE:SCL,SDA,andALERT

pins require pull−up resistors.

Figure 1. Typical Connections of the TMP106

The sensing device of the TMP106 is the chip itself.

Thermal paths run through the package leads. The lower

thermal resistance of metal causes the leads to provide the

primary thermal path.

To maintain accuracy in applications requiring air or

surface temperature measurement, care should be taken

to isolate the package and leads from ambient air

temperature.

POINTER REGISTER

Figure 2 shows the internal register structure of the

TMP106. The 8-bit Pointer Register of the device is used

to address a given data register. The Pointer Register uses

the two LSBs to identify which of the data registers should

respond to a read or write command. Table 1 identifies the

bits of the Pointer Register byte. Table 2 describes the

pointer address of the registers available in the TMP106.

Power-up reset value of P1/P0 is 00.

P7 P6 P5 P4 P3 P2 P1 P0

000000Register Bits

Table 1. Pointer Register Byte

I/O

Control

Interface

SCL

SDA

Temperature

Configuration

TLOW

THIGH

Pointer

Figure 2. Internal Register Structure of the

TMP106

P1 P0 REGISTER

0 0 Temperature Register (Read Only)

0 1 Configuration Register (Read/Write)

1 0 TLOW Register (Read/Write)

1 1 THIGH Register (Read/Write)

Table 2. Pointer Addresses of the TMP106

TEMPERATURE REGISTER

The Temperature Register of the TMP106 is a 12-bit,

read-only register that stores the output of the most recent

conversion. Two bytes must be read to obtain data, and are

described in Table 3 and Table 4. Note that byte 1 is the

most significant byte; byte 2 is the least significant byte.

The first 12 bits are used to indicate temperature, with all

remaining bits equal to zero. The least significant byte

does not have to be read if that information is not needed.

Data format for temperature is summarized in Table 5.

Following power-up or reset, the Temperature Register will

read 0°C until the first conversion is complete.

D7 D6 D5 D4 D3 D2 D1 D0

T11 T10 T9 T8 T7 T6 T5 T4

Table 3. Byte 1 of Temperature Register

D7 D6 D5 D4 D3 D2 D1 D0

T3 T2 T1 T0 0 0 0 0

Table 4. Byte 2 of Temperature Register

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TEMPERATURE

(°C) DIGITAL OUTPUT

(BINARY) HEX

128 0111 1111 1111 7FF

127.9375 0111 1111 1111 7FF

100 0110 0100 0000 640

80 0101 0000 0000 500

75 0100 1011 0000 4B0

50 0011 0010 0000 320

25 0001 1001 0000 190

0.25 0000 0000 0100 004

00000 0000 0000 000

−0.25 1111 1111 1100 FFC

−25 1110 0111 0000 E70

−55 1100 1001 0000 C90

Table 5. Temperature Data Format

The user can obtain 9, 10, 11, or 12 bits of resolution by

addressing the Configuration Register and setting the

resolution bits accordingly. For 9-, 10-, or 11-bit resolution,

the most significant bits in the Temperature Register are

used with the unused LSBs set to zero.

CONFIGURATION REGISTER

The Configuration Register is an 8-bit read/write register

used to store bits that control the operational modes of the

temperature sensor. Read/write operations are performed

MSB first. The format of the Configuration Register for the

TMP106 is shown in Table 6, followed by a breakdown of

the register bits. The power-up/reset value of the

Configuration Register is all bits equal to 0.

BYTE D7 D6 D5 D4 D3 D2 D1 D0

1 OS R1 R0 F1 F0 POL TM SD

Table 6. Configuration Register Format

SHUTDOWN MODE (SD)

The Shutdown Mode of the TMP106 allows the user to

save maximum power by shutting down all device circuitry

other than the serial interface, which reduces current

consumption to typically less than 0 .1µA. Shutdown Mode

is enabled when the SD bit is 1; the device will shut down

once the current conversion is completed. When SD is

equal to 0, the device will maintain a continuous

conversion state.

THERMOSTAT MODE (TM)

The Thermostat Mode bit of the TMP106 indicates to the

device whether to operate in Comparator Mode (TM = 0)

or Interrupt Mode (TM = 1). For more information on

comparator and interrupt modes, see the High and Low

Limit Registers section.

POLARITY (POL)

The Polarity Bit of the TMP106 allows the user to adjust the

polarity of the ALERT pin output. If POL = 0, the ALER T pin

will be active LOW, as shown in Figure 3. For POL = 1, the

ALERT pin will be active HIGH, and the state of the ALER T

pin is inverted.

Measured

Temperature

THIGH

TLOW

TMP106 ALERT PIN

(Comparator Mode)

POL = 0

TMP106 ALERT PIN

(Interrupt Mode)

POL = 0

TMP106 ALERT PIN

(Comparator Mode)

POL = 1

TMP106 ALERT PIN

(Interrupt Mode)

POL = 1

Read Read

Time Read

Figure 3. Output Transfer Function Diagrams

FAULT QUEUE (F1/F0)

A fault condition is defined as when the measured

temperature exceeds the user-defined limits set in the

THIGH and TLOW Registers. Additionally, the number of

fault conditions required to generate an alert may be

programmed using the fault queue. The fault queue is

provided to prevent a false alert as a result of

environmental noise. The fault queue requires

consecutive fault measurements in order to trigger the

alert function. Table 7 defines the number of measured

faults that may be programmed to trigger an alert condition

in the device. For THIGH and TLOW register format and byte

order, see the High and Low Limit Registers section.

F1 F0 CONSECUTIVE FAULTS

0 0 1

0 1 2

1 0 4

1 1 6

Table 7. Fault Settings of the TMP106

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CONVERTER RESOLUTION (R1/R0)

The Converter Resolution bits control the resolution of the

internal analog-to-digital (A/D) converter. This control

allows the user to maximize efficiency by programming for

higher resolution or faster conversion time. Table 8

identifies the resolution bits and the relationship between

resolution and conversion time.

R1 R0 RESOLUTION CONVERSION TIME

(typical)

0 0 9 Bits (0.5°C) 27.5ms

0 1 10 Bits (0.25°C) 55ms

1 0 11 Bits (0.125°C) 110ms

1 1 12 Bits (0.0625°C) 220ms

Table 8. Resolution of the TMP106

ONE-SHOT (OS)

The TMP106 features a One-Shot Temperature

Measurement Mode. When the device is in Shutdown

Mode, writing a ‘1’ to the OS bit starts a single temperature

conversion. The device will return to the shutdown state at

the completion of the single conversion. This option is

useful to reduce power consumption in the TMP106 when

continuous temperature monitoring is not required. When

the Configuration Register is read, the OS always reads

zero.

HIGH AND LOW LIMIT REGISTERS

In Comparator Mode (TM = 0), the ALERT pin of the

TMP106 becomes active when the temperature equals or

exceeds the value in THIGH and generates a consecutive

number of faults according to fault bits F1 and F0. The

ALERT pin remains active until the temperature falls below

the indicated TLOW value for the same number of faults.

In Interrupt Mode (TM = 1), the ALERT pin becomes active

when the temperature equals or exceeds THIGH for a

consecutive number of fault conditions. The ALERT pin

remains active until a read operation of any register

occurs, or until the device successfully responds to the

SMBus Alert Response address. The ALERT pin clears if

the device is placed in Shutdown Mode. Once the ALERT

pin is cleared, it will only become active again by the

temperature falling below TLOW. When the temperature

falls below TLOW, the ALERT pin becomes active and

remains active until cleared by a read operation of any

Response address. When the ALERT pin clears, the

above cycle will repeat, with the ALERT pin becoming

active when the temperature equals or exceeds THIGH.

The ALERT pin can also be cleared by resetting the device

with the General Call Reset command. This reset also

clears the state of the internal registers in the device,

returning the device to Comparator Mode (TM = 0).

Both operational modes are represented in Figure 3.

Table 9 and Table 10 describe the format for the THIGH and

TLOW Registers. Note that the most significant byte is sent

first, followed by the least significant byte. Power-up reset

values for THIGH and TLOW are:

THIGH = 80°C and TLOW = 75°C

The format of the data for THIGH and TLOW is the same as

for the Temperature Register.

BYTE D7 D6 D5 D4 D3 D2 D1 D0

1 H11 H10 H9 H8 H7 H6 H5 H4

BYTE D7 D6 D5 D4 D3 D2 D1 D0

2 H3 H2 H1 H0 0 0 0 0

Table 9. Bytes 1 and 2 of THIGH Register

BYTE D7 D6 D5 D4 D3 D2 D1 D0

1 L11 L10 L9 L8 L7 L6 L5 L4

BYTE D7 D6 D5 D4 D3 D2 D1 D0

2 L3 L2 L1 L0 0 0 0 0

Table 10. Bytes 1 and 2 of TLOW Register

All 12 bits for the Temperature, THIGH, and TLOW Registers

are used in the comparisons for the ALERT function for all

converter resolutions. The three LSBs in THIGH and TLOW

can affect the ALERT output even if the converter is

configured for 9-bit resolution.

SERIAL INTERFACE

The TMP106 operates only as a slave device on the

Two-Wire bus and SMBus. Connections to the bus are

made via the open-drain I/O lines SDA and SCL. The SDA

and SCL pins feature integrated spike suppression filters

and Schmitt triggers to minimize the effects o f input spikes

and bus noise. The TMP106 supports the transmission

protocol for fast (1kHz to 400kHz) and high-speed (1kHz

to 3.4MHz) modes. All data bytes are transmitted MSB

first.

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SERIAL BUS ADDRESS

To communicate with the TMP106, the master must first

address slave devices via a slave address byte. The slave

address byte consists of seven address bits, and a

direction bit indicating the intent of executing a read or

write operation.

The TMP106 features one address pin allowing up to two

devices to be connected per bus. Pin logic levels are

described in Table 11. The address pin of the TMP106 is

read after reset, at start of communication, or in response

to a Two-Wire address acquire request. Following the

reading of the pin state, the address is latched to minimize

power dissipation associated with detection.

A0 SLAVE ADDRESS

0 1001000

1 1001001

Table 11. Address Pin and Slave Addresses for

the TMP106

BUS OVERVIEW

The device that initiates the transfer is called a master, and

the devices controlled by the master are slaves. The bus

must be controlled by a master device that generates the

serial clock (SCL), controls the bus access, and generates

the START and STOP conditions.

To address a specific device, a START condition is

initiated, indicated by pulling the data-line (SDA) from a

HIGH to LOW logic level while SCL is HIGH. All slaves on

the bus shift in the slave address byte, with the last bit

indicating whether a read or write operation is intended.

During the ninth clock pulse, the slave being addressed

responds to the master by generating an Acknowledge

and pulling SDA LOW.

Data transfer is then initiated and sent over eight clock

pulses followed by an Acknowledge Bit. During data

transfer SDA must remain stable while SCL is HIGH, as

any change in SDA while SCL is HIGH will be interpreted

as a control signal.

Once all data has been transferred, the master generates

a ST OP condition, indicated by pulling SDA from LOW to

HIGH while SCL is HIGH.

WRITING/READING TO THE TMP106

Accessing a particular register on the TMP106 is

accomplished by writing the appropriate value to the

Pointer Register. The value for the Pointer Register is the

first byte transferred after the slave address byte with the

R/W bit LOW. Every write operation to the TMP106

requires a value for the Pointer Register. (Refer to

Figure 5.)

When reading from the TMP106, the last value stored in

the Pointer Register by a write operation is used to

determine which register is read by a read operation. To

change the register pointer for a read operation, a new

value must be written to the Pointer Register. This is

accomplished by issuing a slave address byte with the

R/W bit LOW, followed by the Pointer Register byte. No

additional data are required. The master can then

generate a START condition and send the slave address

byte with the R/W bit HIGH to initiate the read command.

See Figure 6 for details of this sequence. If repeated reads

from the same register are desired, it is not necessary to

continually send the Pointer Register byte, as the TMP106

remembers the Pointer Register value until it is changed

by the next write operation.

Note that register bytes are sent most-significant byte first,

followed by the least-significant byte.

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SLAVE MODE OPERATIONS

The TMP106 can operate as a slave receiver or slave

transmitter.

Slave Receiver Mode:

The first byte transmitted by the master is the slave

address, with the R/W bit LOW. The TMP106 then

acknowledges reception of a valid address. The next byte

transmitted by the master is the Pointer Register. The

TMP106 then acknowledges reception of the Pointer

acknowledges reception of each data byte. The master

may terminate data transfer by generating a START or

STOP condition.

Slave Transmitter Mode:

The first byte is transmitted by the master and is the slave

address, with the R/W bit HIGH. The slave acknowledges

reception of a valid slave address. The next byte is

transmitted by the slave and is the most significant byte of

the register indicated by the Pointer Register. The master

acknowledges reception of the data byte. The next byte

transmitted by the slave is the least significant byte. The

master acknowledges reception of the data byte. The

master may terminate data transfer by generating a

Not-Acknowledge on reception of any data byte, or

generating a START or STOP condition.

SMBus ALERT FUNCTION

The TMP106 supports the SMBus Alert function. When

the TMP106 is operating in Interrupt Mode (TM = 1), the

ALERT pin of the TMP106 may be connected as an

SMBus Alert signal. When a master senses that an ALER T

condition is present on the ALERT line, the master sends

an SMBus Alert command (00011001) on the bus. If the

ALERT pin of the TMP106 is active, the devices will

acknowledge the SMBus Alert command and respond by

returning its slave address on the SDA line. The eighth bit

(LSB) of the slave address byte will indicate if the

temperature exceeding THIGH or falling below TLOW

caused the ALERT condition. This bit will be HIGH if the

temperature is greater than or equal to T HIGH. This bit will

be LOW if the temperature is less than TLOW. Refer to

Figure 7 for details of this sequence.

If multiple devices on the bus respond to the SMBus Alert

command, arbitration during the slave address portion of

the SMBus Alert command will determine which device

will clear its ALERT status. If the TMP106 wins the

arbitration, its ALERT pin will become inactive at the

completion of the SMBus Alert command. If the TMP106

loses the arbitration, its ALERT pin will remain active.

GENERAL CALL

The TMP106 responds to a Two-Wire General Call

address (0000000) if the eighth bit is 0. The device will

acknowledge the General Call address and respond to

commands in the second byte. If the second byte is

00000100, the TMP106 will latch the status of the address

pin, but will not reset. If the second byte is 00000110, the

TMP106 will latch the status of the address pin and reset

the internal registers to their power-up values.

HIGH-SPEED MODE

In order for the Two-Wire bus to operate at frequencies

above 400kHz, the master device must issue an Hs-mode

master code (00001XXX) as the first byte after a START

condition to switch the bus to high-speed operation. The

TMP106 will not acknowledge this byte, but will switch its

input filters on S D A and S C L and it s outpu t f ilter s o n SDA

to operate in Hs-mode, allowing transfers at up to 3.4MHz.

After the Hs-mode master code has been issued, the

master will transmit a Two-Wire slave address to initiate a

data transfer operation. The bus will continue to operate in

Hs-mode until a STOP condition occurs on the bus. Upon

receiving the STOP condition, the TMP106 will switch the

input and output filters back to fast-mode operation.

TIMEOUT FUNCTION

The TMP106 will reset the serial interface if either SCL or

SDA are held LOW for 54ms (typ) between a START and

STOP condition. The TMP106 will release the bus if it is

pulled LOW and will wait for a START condition. To avoid

activating the timeout function, it is necessary to maintain

a communication speed of at least 1kHz for SCL operating

frequency.

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TIMING DIAGRAMS

The TMP106 is Two-Wire- and SMBus-compatible.

Figure 4 to Figure 7 describe the various operations on the

TMP106. Bus definitions are given below. Parameters for

Figure 4 are defined in Table 12.

Bus Idle: Both SDA and SCL lines remain HIGH.

Start Data Transfer: A change in the state of the SDA line,

from HIGH to LOW, while the SCL line is HIGH, defines a

START condition. Each data transfer is initiated with a

START condition.

Stop Da t a Transfer: A change in the state of the SDA line

from LOW to HIGH while the SCL line is HIGH defines a

STOP condition. Each data transfer is terminated with a

repeated START or STOP condition.

Data Transfer: The number of data bytes transferred

between a START and a STOP condition is not limited and

is determined by the master device. The receiver

acknowledges the transfer of data.

Acknowledge: Each receiving device, when addressed,

is obliged to generate an Acknowledge bit. A device that

acknowledges must pull down the SDA line during the

Acknowledge clock pulse in such a way that the SDA line

is stable LOW during the HIGH period of the Acknowledge

clock pulse. Setup and hold times must be taken into

account. On a master receive, the termination of the data

transfer can be signaled by the master generating a

Not-Acknowledge on the last byte that has been

transmitted by the slave.

PARAMETER

FAST MODE HIGH-SPEED MODE

UNITS

PARAMETER

MIN MAX MIN MAX

UNITS

SCL Operating Frequency f(SCL) 0.001 0.4 0.001 3.4 MHz

Bus Free Time Between STOP and START Condition t(BUF) 600 160 ns

Hold time after repeated START condition.

After this period, the first clock is generated. t(HDSTA) 100 100 ns

Repeated STAR T Condition Setup Time t(SUSTA) 100 100 ns

STOP Condition Setup Time t(SUSTO) 100 100 ns

Data Hold Time t(HDDAT) 0 0 ns

Data Setup Time t(SUDAT) 100 10 ns

SCL Clock LOW Period t(LOW) 1300 160 ns

SCL Clock HIGH Period t(HIGH) 600 60 ns

Clock/Data Fall Time tF300 160 ns

Clock/Data Rise Time

300 160 ns

for SCLK ≤ 100kHz

1000 ns

Table 12. Timing Diagram Definitions for the TMP106

TWO-WIRE TIMING DIAGRAMS

SCL

SDA

t(LOW) tRtFt(HDSTA)

t(HDSTA) t(HDDAT)

t(BUF)

t(SUDAT)

t(HIGH) t(SUSTA) t(SUSTO)

PS SP

Figure 4. Two-Wire Timing Diagram

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Frame1Two−WireSlaveAddressByte Frame 2 Pointer Register Byte

Frame4 Data Byte 2

Start By

Master ACKBy

TMP106 ACK By

TMP106

ACK By

TMP106 Stop By

Master

191

D7 D6 D5 D4 D3 D2 D1 D0

Frame3DataByte1

ACK By

TMP106

SDA

(Continued)

SCL

(Continued)

D6 D5 D4 D3 D2 D1 D0

SDA

SCL

0 0 1 0 0 A0 R/W 0 0 0 0 0 0 P1 P0 …

…

Figure 5. Two-Wire Timing Diagram for TMP106 Write Word Format

Frame 1 Two−Wire Slave Address Byte Frame 2 Pointer Register Byte

Start By

Master ACK By

TMP106 ACK By

TMP106

Frame3Two−WireSlaveAddressByte Frame4DataByte1ReadRegister

Start By

Master ACK By

TMP106 ACK By

Master

From

TMP106

1919

SDA

SCL

00 R/W 000000P1P0 …

…

SDA

(Continued)

SCL

(Continued)

SDA

(Continued)

SCL

(Continued)

1001

00A0

R/W D7 D6 D5 D4 D3 D2 D1 D0

Frame5DataByte2ReadRegister

Stop By

Master

ACK By

Master

From

TMP106

D7 D6 D5 D4 D3 D2 D1 D0

Figure 6. Two-Wire Timing Diagram for Read Word Format

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Frame 1 SMBus ALERT Response Address Byte Frame 2 Slave Address Byte

Start By

Master ACK By

TMP106 From

TMP106 NACK By

Master Stop By

Master

1919

SDA

SCL

ALERT

0001100R/W 100100A0

Status

Figure 7. Timing Diagram for SMBus ALERT

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

TMP106YZCR ACTIVE DSBGA YZC 6 3000 Green (RoHS &

no Sb/Br) Call TI Level-1-260C-UNLIM

TMP106YZCRG4 ACTIVE DSBGA YZC 6 TBD Call TI Call TI

TMP106YZCT ACTIVE DSBGA YZC 6 250 Green (RoHS &

no Sb/Br) Call TI Level-1-260C-UNLIM

TMP106YZCTG4 ACTIVE DSBGA YZC 6 TBD Call TI Call TI

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 31-Jul-2006

Addendum-Page 1

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