CY7C419/21/25/29/33
256/512/1K/2K/4K x 9 Asynchronous FIFO
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-06001 Rev. *D Revised June 03, 2009
Features
■Asynchronous First-In First-Out (FIFO) Buffer Memories
❐256 x 9 (CY7C419)
❐512 x 9 (CY7C421)
❐1K x 9 (CY7C425)
❐2K x 9 (CY7C429)
❐4K x 9 (CY7C433)
■Dual-Ported RAM Cell
■High Speed 50 MHz Read and Write Independent of Depth and
Width
■Low Operating Power: ICC = 35 mA
■Empty and Full Flags (Half Full Flag in Standalone)
■TTL Compatible
■Retransmit in Standalone
■Expandable in Width
■PLCC, 7x7 TQFP, SOJ, 300-mil, and 600-mil DIP
■Pb-free Packages Available
■Pin Compatible and Functionally Equivalent to IDT7200,
IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201,
AM7202, AM7203, and AM7204
Functional Description
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and
CY7C432/3 are first-in first-out (FIFO) memories offered in
600-mil wide and 300-mil wide packages. There are 256, 512,
1,024, 2,048, and 4,096 words respectively by 9 bits wide. Each
FIFO memory is organized such that the data is read in the same
sequential order that it was written. Full and empty flags are
provided to prevent overrun and underrun. Three additional pins
are also provided to facilitate unlimited expansion in width, depth,
or both. The depth expansion technique steers the control
signals from one device to another in parallel. This eliminates the
serial addition of propagation delays, so that throughput is not
reduced. Data is steered in a similar manner.
The read and write operations may be asynchronous; each can
occur at a rate of 50 MHz. The write operation occurs when the
write (W) signal is LOW. Read occurs when read (R) goes LOW.
The nine data outputs go to the high impedance state when R is
HIGH.
A Half Full (HF) output flag that is valid in the standalone and
width expansion configurations is provided. In the depth
expansion configuration, this pin provides the expansion out
(XO) information that is used to tell the next FIFO that it is
activated.
In the standalone and width expansion configurations, a LOW on
the retransmit (RT) input causes the FIFOs to retransmit the
data. Read enable (R) and write enable (W) must both be HIGH
during retransmit, and then R is used to access the data.
The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425,
CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated
using an advanced 0.65-micron P-well CMOS technology. Input
ESD protection is greater than 2000V and latch up is prevented
by careful layout and guard rings.
Table 1. Selection Guide
4K x 9 –10 –15 –20 –25 –30 –40 –65
Frequency (MHz) 50 40 33.3 28.5 25 20 12.5
Maximum Access Time (ns) 10 15 20 25 30 40 65
ICC1 (mA) 35 35 35 35 35 35 35
CY7C419/21/25/29/33256/512/1K/2K/4K x 9 Asynchronous FIFO
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CY7C419/21/25/29/33
Document #: 38-06001 Rev. *D Page 2 of 16
Logic Block Diagram
Pin Configurations
Figure 1. 32-Pin PLCC/LCC (Top View) Figure 2. 28-Pin DIP (Top View) Figure 3. 32-PIn TQFP (Top View)
RAM ARRAY
256x 9
512x 9
1024x 9
2048x 9
4096x 9
READ
CONTROL
WRITE
CONTROL
WRITE
POINTER
RESET
LOGIC
EXPANSION
LOGIC
DATA INPUTS
(D0–D 8
)
THREE-
STATE
BUFFERS
DATA OUTPUTS
(Q0–Q 8)
W
READ
POINTER
FLAG
LOGIC
R
XI
EF
FF
XO/HF
MR
FL/RT
4 3 2 1 323130
14 15 1617 181920
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
FL/RT
MR
EF
XO/HF
Q
7
D
6
Q
6
D
7
NC
D
2
D
1
D
0
XI
FF
Q
0
Q
1
NC
Q
2
D
D
W
NC
V
D
D
3
8
cc
4
5
Q
Q
GND
NC
R
Q
Q
3
8
4
5
7C419
7C421/5/9
7C433
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
7C420/1
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
GND
Vcc
D4
FL/RT
MR
EF
XO/HF
Q7
R
Q3
Q8
D5
D6
D7
Q6
Q5
Q4
7C424/5
7C428/9
7C432/3
7C419
26
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 101112131415
32 3130 29 28 27 25
Q1
XI
Q0
D1
D0
NC
NC
FF
D6
D5
D4
VCC
W
D8
D3
D2
D7
FL/RT
NC
NC
MR
EF
XO/HF
Q7
Q2
Q3
Q8
GND
R
Q4
Q5
Q6
16
7C419
7C421/5/9
7C433
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CY7C419/21/25/29/33
Document #: 38-06001 Rev. *D Page 3 of 16
Maximum Rating
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.[1]
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied.. –55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
Power Dissipation.......................................................... 1.0W
Output Current, into Outputs (LOW)............................ 20 mA
Static Discharge Voltage............................................ >2000V
(per MIL–STD–883, Method 3015)
Latch Up Current ..................................................... >200 mA
Operating Range
Range Ambient Temperature[2] VCC
Commercial 0°C to + 70°C 5V ± 10%
Industrial –40°C to +85°C5V ± 10%
Electrical Characteristics
Over the Operating Range[3]
Parameter Description Test Conditions All Speed Grades Unit
Min Max
VOH Output HIGH Voltage VCC = Min., IOH = –2.0 mA 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage Commercial 2.0 VCC V
Industrial 2.2 VCC
VIL Input LOW Voltage [4] 0.8 V
IIX Input Leakage Current GND < VI < VCC –10 +10 μA
IOZ Output Leakage Current R > VIH, GND < VO < VCC –10 +10 μA
IOS Output Short Circuit Current[5] VCC = Max., VOUT = GND –90 mA
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions –10 –15 –20 –25 Unit
Min Max Min Max Min Max Min Max
ICC Operating Current VCC = Max.,
IOUT = 0 mA
f = fMAX
Commercial 85 65 55 50 mA
Industrial 100 90 80
ICC1 Operating Current VCC = Max.,
IOUT = 0 mA
F = 20 MHz
Commercial 35 35 35 35 mA
ISB1 Standby Current All Inputs =
VIH Min.
Commercial 10 10 10 10 mA
Industrial 15 15 15
ISB2 Power Down Current All Inputs >
VCC –0.2V
Commercial 5 5 5 5 mA
Industrial 8 8 8
Notes
1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power up.
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. VIL (Min.) = –2.0V for pulse durations of less than 20 ns.
5. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
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CY7C419/21/25/29/33
Document #: 38-06001 Rev. *D Page 4 of 16
Electrical Characteristics
Over the Operating Range[3]
Parameter Description Test Conditions –30 –40 –65 Unit
Min Max Min Max Min Max
ICC Operating Current VCC = Max.,
IOUT = 0 mA
f = fMAX
Commercial 40 35 35 mA
Industrial 75 70 65
ICC1 Operating Current VCC = Max.,
IOUT = 0 mA
F = 20 MHz
Commercial 35 35 35 mA
ISB1 Standby Current All Inputs =
VIH Min.
Commercial 10 10 10 mA
Industrial 15 15 15
ISB2 Power Down Current All Inputs >
VCC –0.2V
Commercial 5 5 5 mA
Industrial 8 8 8
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 4.5V
6pF
COUT Output Capacitance 6pF
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CY7C419/21/25/29/33
Document #: 38-06001 Rev. *D Page 5 of 16
Switching Characteristics
Over the Operating Range[6, 7]
Parameter Description –10 –15 –20 –25 Unit
Min Max Min Max Min Max Min Max
tRC Read Cycle Time 20 25 30 35 ns
tAAccess Time 10 15 20 25 ns
tRR Read Recovery Time 10 10 10 10 ns
tPR Read Pulse Width 10 15 20 25 ns
tLZR[,8] Read LOW to Low Z 3 3 3 3 ns
tDVR[8,9] Data Valid After Read HIGH 5 5 5 5 ns
tHZR[,8,9] Read HIGH to High Z 15 15 15 18 ns
tWC Write Cycle Time 20 25 30 35 ns
tPW Write Pulse Width 10 15 20 25 ns
tHWZ[,8] Write HIGH to Low Z 5 5 5 5 ns
tWR Write Recovery Time 10 10 10 10 ns
tSD Data Setup Time 6 8 12 15 ns
tHD Data Hold Time 0 0 0 0 ns
tMRSC MR Cycle Time 20 25 30 35 ns
tPMR MR Pulse Width 10 15 20 25 ns
tRMR MR Recovery Time 10 10 10 10 ns
tRPW Read HIGH to MR HIGH 10 15 20 25 ns
tWPW Write HIGH to MR HIGH 10 15 20 25 ns
tRTC Retransmit Cycle Time 20 25 30 35 ns
tPRT Retransmit Pulse Width 10 15 20 25 ns
tRTR Retransmit Recovery Time 10 10 10 10 ns
tEFL MR to EF LOW 20 25 30 35 ns
tHFH MR to HF HIGH 20 25 30 35 ns
tFFH MR to FF HIGH 20 25 30 35 ns
tREF Read LOW to EF LOW 10 15 20 25 ns
tRFF Read HIGH to FF HIGH 10 15 20 25 ns
tWEF Write HIGH to EF HIGH 10 15 20 25 ns
tWFF Write LOW to FF LOW 10 15 20 25 ns
tWHF Write LOW to HF LOW 10 15 20 25 ns
tRHF Read HIGH to HF HIGH 10 15 20 25 ns
tRAE Effective Read from Write HIGH 10 15 20 25 ns
tRPE Effective Read Pulse Width After EF HIGH 10 15 20 25 ns
tWAF Effective Write from Read HIGH 10 15 20 25 ns
tWPF Effective Write Pulse Width After FF HIGH 10 15 20 25 ns
tXOL Expansion Out LOW Delay from Clock 10 15 20 25 ns
tXOH Expansion Out HIGH Delay from Clock 10 15 20 25 ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V and output loading of the specified IOL/IOH and 30 pF load capacitance,
as in part (a) of AC Test Load and Waveforms, unless otherwise specified.
7. See the last page of this specification for Group A subgroup testing information.
8. tHZR transition is measured at +200 mV from VOL and –200 mV from VOH. tDVR transition is measured at the 1.5V level. tHWZ and tLZR transition is measured at ±100
mV from the steady state.
9. tHZR and tDVR use capacitance loading as in part (b) of AC Test Load and Waveforms.
[+] Feedback [+] Feedback [+] Feedback
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *D Page 6 of 16
Switching Characteristics
Over the Operating Range[6, 7] (continued)
Parameter Description –30 –40 –65 Unit
Min Max Min Max Min Max
tRC Read Cycle Time 40 50 80 ns
tAAccess Time 30 40 65 ns
tRR Read Recovery Time 10 10 15 ns
tPR Read Pulse Width 30 40 65 ns
tLZR[,8] Read LOW to Low Z 333ns
tDVR[8,9] Data Valid After Read HIGH 555ns
tHZR[,8,9] Read HIGH to High Z 20 20 20 ns
tWC Write Cycle Time 40 50 80 ns
tPW Write Pulse Width 30 40 65 ns
tHWZ[,8] Write HIGH to Low Z 555ns
tWR Write Recovery Time 10 10 15 ns
tSD Data Setup Time 18 20 30 ns
tHD Data Hold Time 000ns
tMRSC MR Cycle Time 40 50 80 ns
tPMR MR Pulse Width 30 40 65 ns
tRMR MR Recovery Time 10 10 15 ns
tRPW Read HIGH to MR HIGH 30 40 65 ns
tWPW Write HIGH to MR HIGH 30 40 65 ns
tRTC Retransmit Cycle Time 40 50 80 ns
tPRT Retransmit Pulse Width 30 40 65 ns
tRTR Retransmit Recovery Time 10 10 15 ns
tEFL MR to EF LOW 40 50 80 ns
tHFH MR to HF HIGH 40 50 80 ns
tFFH MR to FF HIGH 40 50 80 ns
tREF Read LOW to EF LOW 30 35 60 ns
tRFF Read HIGH to FF HIGH 30 35 60 ns
tWEF Write HIGH to EF HIGH 30 35 60 ns
tWFF Write LOW to FF LOW 30 35 60 ns
tWHF Write LOW to HF LOW 30 35 60 ns
tRHF Read HIGH to HF HIGH 30 35 60 ns
tRAE Effective Read from Write HIGH 30 35 60 ns
tRPE Effective Read Pulse Width After EF HIGH 30 40 65 ns
tWAF Effective Write from Read HIGH 30 35 60 ns
tWPF Effective Write Pulse Width After FF HIGH 30 40 65 ns
tXOL Expansion Out LOW Delay from Clock 30 40 65 ns
tXOH Expansion Out HIGH Delay from Clock 30 40 65 ns
[+] Feedback [+] Feedback [+] Feedback
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *D Page 7 of 16
Switching Waveforms
Figure 4. Asynchronous Read and Write
Figure 5. Master Reset
Figure 6. Half-full Flag
DATA VALIDDATA VALID
DATA VALID DATA VALID
tSD tHD
tRC tPR
tAtRR tA
tLZR tDVR tHZR
tWC
tPW tWR
R
Q0–Q 8
W
D0–D 8
MR
R,W
HF
FF
EF
tMRSC
tPMR
tEFL
tHFH
tFFH
tRPW
tWPW tRMR
[10]
[11]
HALF FULL+1HALF FULL HALF FULL
W
R
HF
tWHF
tRHF
Notes
10. W and R ≥ VIH around the rising edge of MR
11. tMRSC = tPMR + tRMR.
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Document #: 38-06001 Rev. *D Page 8 of 16
Figure 7. Last Write to First Read Full Flag
Figure 8. Last Read to First Write Empty Flag
Figure 9. Retransmit[12]
Switching Waveforms (continued)
LAST WRITE FIRST READ
ADDITIONAL
READS FIRST WRITE
tWFF tRFF
R
W
FF
VALID
LAST READ FIRST WRITE
ADDITIONAL
WRITES FIRST READ
VALID
tREF tWEF
tA
W
R
EF
DATA OUT
tRTC
tPRT
tRTR
FL/RT
R,W
[13]
Notes
12. EF, HF and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags are valid at tRTC.
13. tRTC = tPRT + tRTR.
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Document #: 38-06001 Rev. *D Page 9 of 16
Figure 10. Empty Flag and Read Data Flow-through Mode
Figure 11. Full Flag and Write Data Flow-through Mode
Switching Waveforms (continued)
W
R
EF
DATA IN
DATA OUT DATA VALID
tRAE
tREF
tWEF
tHWZ
tA
tRPE
R
W
FF
DATA IN
DATA OUT
DATA VALID
DATA VALID
tWAF tWPF
tWFF
tRFF
tSD
tHD
tA
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CY7C419/21/25/29/33
Document #: 38-06001 Rev. *D Page 10 of 16
Figure 12. Expansion Timing Diagrams
Switching Waveforms (continued)
R
W
XO1(XI2)
D0–D 8DATA VALID
DATA DATA
VALID VALID
tXOL tXOH
tHD
tSD tSD
tHD
tXOL
tLZR
tA
tDVR
tXOH
tA
tDVR
tHZR
XO1(XI2)
Q0–Q 8
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
tWR
tRR
DATA VALID
[14]
[14]
Note
14. Expansion Out of device 1 (XO1) is connected to Expansion In of device 2 (XI2)
[+] Feedback [+] Feedback [+] Feedback
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *D Page 11 of 16
Architecture
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9,
CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048,
4096 words of 9 bits each (implemented by an array of dual-port
RAM cells), a read pointer, a write pointer, control signals (W, R,
XI, XO, FL, RT, MR), and Full, Half Full, and Empty flags.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory cell
used in the RAM. The cell itself enables the read and write opera-
tions to be independent of each other, which is necessary to
achieve truly asynchronous operation of the inputs and outputs.
A second benefit is that the time required to increment the read
and write pointers is much less than the time required for data
propagation through the memory, which is the case if memory is
implemented using the conventional register array architecture.
Resetting the FIFO
Upon power up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the Empty flag (EF) being LOW, and both the Half
Full (HF) and Full flags (FF) being HIGH. Read (R) and write (W)
must be HIGH tRPW/tWPW before and tRMR after the rising edge
of MR for a valid reset cycle. If reading from the FIFO after a reset
cycle is attempted, the outputs are in the high impedance state.
Writing Data to the FIFO
The availability of at least one empty location is indicated by a
HIGH FF. The falling edge of W initiates a write cycle. Data
appearing at the inputs (D0–D8) tSD before and tHD after the
rising edge of W are stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs tWEF after the first
LOW-to-HIGH transition of W for an empty FIFO. HF goes LOW
tWHF after the falling edge of W following the FIFO actually being
Half Full. Therefore, the HF is active after the FIFO is filled to half
its capacity plus one word. HF remains LOW while less than one
half of total memory is available for writing. The LOW-to-HIGH
transition of HF occurs tRHF after the rising edge of R when the
FIFO goes from half full +1 to half full. HF is available in
standalone and width expansion modes. FF goes LOW tWFF
after the falling edge of W, during the cycle in which the last
available location is filled. Internal logic prevents overrunning a
full FIFO. Writes to a full FIFO are ignored and the write pointer
is not incremented. FF goes HIGH tRFF after a read from a full
FIFO.
Reading Data from the FIFO
The falling edge of R initiates a read cycle if the EF is not LOW.
Data outputs (Q0 to Q8) are in a high impedance condition
between read operations (R HIGH), when the FIFO is empty, or
when the FIFO is not the active device in the depth expansion
mode.
When one word is in the FIFO, the falling edge of R initiates a
HIGH-to-LOW transition of EF. The rising edge of R causes the
data outputs to go to the high impedance state and remain such
until a write is performed. Reads to an empty FIFO are ignored
and do not increment the read pointer. From the empty condition,
the FIFO can be read tWEF after a valid write.
The retransmit feature is beneficial when transferring packets of
data. It enables the receiver to acknowledge receipt of data and
retransmit, if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last MR cycle. A LOW pulse on RT
resets the internal read pointer to the first physical location of the
FIFO. R and W must both be HIGH while and tRTR after
retransmit is LOW. With every read cycle after retransmit, previ-
ously accessed data and not previously accessed data is read
and the read pointer is incremented until it is equal to the write
pointer. Full, Half Full, and Empty flags are governed by the
relative locations of the read and write pointers and are updated
during a retransmit cycle. Data written to the FIFO after activation
of RT are also transmitted. FIFO, up to the full depth, can be
repeatedly retransmitted.
Standalone/Width Expansion Modes
Standalone and width expansion modes are set by grounding
Expansion In (XI) and tying First Load (FL) to VCC. FIFOs can be
expanded in width to provide word widths greater than nine in
increments of nine. During width expansion mode, all control line
inputs are common to all devices, and flag outputs from any
device can be monitored.
Depth Expansion Mode
Depth expansion mode (see Figure on page 12) is entered
when, during a MR cycle, Expansion Out (XO) of one device is
connected to Expansion In (XI) of the next device, with XO of the
last device connected to XI of the first device. In the depth
expansion mode the First Load (FL) input, when grounded,
indicates that this part is the first to be loaded. All other devices
must have this pin HIGH. To enable the correct FIFO, XO is
pulsed LOW when the last physical location of the previous FIFO
is written to and pulsed LOW again when the last physical
location is read. Only one FIFO is enabled for read and one for
write at any particular time. All other devices are in standby.
FIFOs can also be expanded simultaneously in depth and width.
Consequently, any depth or width FIFO can be created of word
widths in increments of 9. When expanding in depth, a composite
FF must be created by ORing the FFs together. Likewise, a
composite EF is created by ORing the EFs together. HF and RT
functions are not available in depth expansion mode.
[+] Feedback [+] Feedback [+] Feedback
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *D Page 12 of 16
Use of the Empty and Full Flags
To achieve maximum frequency, the flags must be valid at the
beginning of the next cycle. However, because they can be
updated by either edge of the read or write signal, they must be
valid by one-half of a cycle. Cypress FIFOs meet this
requirement; some competitors’ FIFOs do not.
The reason for why the flags should be valid by the next cycle is
complex. The “effective pulse width violation” phenomenon can
occur at the full and empty boundary conditions, if the flags are
not properly used. The empty flag must be used to prevent
reading from an empty FIFO and the full flag must be used to
prevent writing into a full FIFO.
For example, consider an empty FIFO that is receiving read
pulses. Because the FIFO is empty, the read pulses are ignored
by the FIFO, and nothing happens. Next, a single word is written
into the FIFO, with a signal that is asynchronous to the read
signal. The (internal) state machine in the FIFO goes from empty
to empty+1. However, it does this asynchronously with respect
to the read signal, so that the effective pulse width of the read
signal cannot be determined, because the state machine does
not look at the read signal until it goes to the empty+1 state.
Similarly, the minimum write pulse width may be violated by
trying to write into a full FIFO, and asynchronously performing a
read. The empty and full flags are used to avoid these effective
pulse width violations, but to do this and operate at the maximum
frequency, the flag must be valid at the beginning of the next
cycle.
Figure 13. Depth Expansion
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
W
MR
XI
FL
EF
XO
FF
XI
FL
EF
XO
XI
FL
EF
XO
FF
R
EMPTY
FULL
Q
9
9
9
9
FF
VCC
* FIRSTDEVICE
*
9CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
D
[+] Feedback [+] Feedback [+] Feedback
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *D Page 13 of 16
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type Operating
Range
10 CY7C421–10AC 51-85063 32-Pin Thin Plastic Quad Flatpack Commercial
CY7C421–10JC 51-85002 32-Pin Plastic Leaded Chip Carrier
CY7C421–10JXC 51-85002 32-Pin Plastic Leaded Chip Carriers (Pb-free)
CY7C421–10PC 51-85014 28-Pin (300-Mil) Molded DIP
CY7C421–10VC 51-85031 28-Pin (300-Mil) Molded SOJ
15 CY7C421–15AC 51-85063 32-Pin Thin Plastic Quad Flatpack Commercial
CY7C421–15AXC 51-85063 32-Pin Thin Plastic Quad Flatpack (Pb-free)
CY7C421–15JC 51-85002 32-Pin Plastic Leaded Chip Carrier
CY7C421–15JI 51-85002 32-Pin Plastic Leaded Chip Carrier Industrial
CY7C421–15VI 51-85031 28-Pin (300-Mil) Molded SOJ
20 CY7C421–20JC 51-85002 32-Pin Plastic Leaded Chip Carrier Commercial
CY7C421–20JXC 51-85002 32-Pin Plastic Leaded Chip Carriers (Pb-free)
CY7C421–20PC 51-85014 28-Pin (300-Mil) Molded DIP
CY7C421–20VC 51-85031 28-Pin (300-Mil) Molded SOJ
CY7C421–20VXC 51-85031 28-Pin (300-Mil) Molded SOJ (Pb-free)
CY7C421–20JI 51-85002 32-Pin Plastic Leaded Chip Carrier Industrial
CY7C421–20JXI 51-85002 32-Pin Plastic Leaded Chip Carrier (Pb-free)
25 CY7C421–25JC 51-85002 32-Pin Plastic Leaded Chip Carrier Commercial
CY7C421–25PC 51-85014 28-Pin (300-Mil) Molded DIP
CY7C421–25VC 51-85031 28-Pin (300-Mil) Molded SOJ
CY7C421–25JI 51-85002 32-Pin Plastic Leaded Chip Carrier Industrial
CY7C421–25PI 51-85014 28-Pin (300-Mil) Molded DIP
30 CY7C421–30JC 51-85002 32-Pin Plastic Leaded Chip Carrier Commercial
CY7C421–30PC 51-85014 28-Pin (300-Mil) Molded DIP
CY7C421–30JI 51-85002 32-Pin Plastic Leaded Chip Carrier Industrial
40 CY7C421–40JC 51-85002 32-Pin Plastic Leaded Chip Carrier Commercial
CY7C421–40PC 51-85014 28-Pin (300-Mil) Molded DIP
CY7C421–40VC 51-85031 28-Pin (300-Mil) Molded SOJ
CY7C421–40JI 51-85002 32-Pin Plastic Leaded Chip Carrier Industrial
65 CY7C421–65JC 51-85002 32-Pin Plastic Leaded Chip Carrier Commercial
CY7C421–65PC 51-85014 28-Pin (300-Mil) Molded DIP
CY7C421–65VC 51-85031 28-Pin (300-Mil) Molded SOJ
CY7C421–65JI 51-85002 32-Pin Plastic Leaded Chip Carrier Industrial
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CY7C419/21/25/29/33
Document #: 38-06001 Rev. *D Page 14 of 16
Package Diagrams
Figure 14. 32-Pin Thin Plastic Quad Flat Pack, 51-85063
Figure 15. 32-Pin Plastic Leaded Chip Carrier, 51-85002
51-85063-*B
51-85002-*B
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CY7C419/21/25/29/33
Document #: 38-06001 Rev. *D Page 15 of 16
Figure 16. 28-Pin (300-Mil) PDIP, 51-85014
Figure 17. 28-Pin (300-Mil) Molded SOJ, 51-85031
Package Diagrams
DIMENSIONS IN INCHES [MM] MIN.
MAX.
SEATING PLANE
0.260[6.60]
0.295[7.49]
0.090[2.28]
0.110[2.79]
0.055[1.39]
0.065[1.65]
0.015[0.38]
0.020[0.50]
0.015[0.38]
0.060[1.52]
0.120[3.05]
0.140[3.55]
0.009[0.23]
0.012[0.30]
0.310[7.87]
0.385[9.78]
0.290[7.36]
0.325[8.25]
0.030[0.76]
0.080[2.03]
0.115[2.92]
0.160[4.06]
0.140[3.55]
0.190[4.82]
1.345[34.16]
1.385[35.18]
3° MIN.
114
15 28
REFERENCE JEDEC MO-095
LEAD END OPTION
SEE LEAD END OPTION
SEE LEAD END OPTION
(LEAD #1, 14, 15 & 28)
PACKAGE WEIGHT: 2.15 gms
51-85014-*D
51-85031-*B
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Document #: 38-06001 Rev. *D Revised June 03, 2009 Page 16 of 16
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C419/21/25/29/33
© Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
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Use may be limited by and subject to the applicable Cypress software license agreement.
Document History Page
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Document Title: CY7C419/21/25/29/33, 256/512/1K/2K/4Kx9 Asynchronous FIFO
Document Number: 38-06001
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 106462 SZV 07/11/01 Change from Spec Number: 38-00079 to 38-06001
*A 122332 RBI 12/30/02 Added power up requirements to maximum ratings information.
*B 383597 PCX See ECN Added Pb-Free Logo
Added to Part-Ordering Information:
CY7C419–10JXC, CY7C419–15JXC, CY7C419-15VXC,
CY7C421–10JXC, CY7C421–15AXC, CY7C421–20JXC,
CY7C421–20VXC, CY7C425–10AXC, CY7C425–10JXC,
CY7C425–15JXC, CY7C425–20JXC, CY7C425–20VXC,
CY7C429–10AXC, CY7C429–15JXC, CY7C429–20JXC,
CY7C433–10AXC, CY7C433–10JXC, CY7C433–15JXC,
CY7C433–20AXC, CY7C433–20JXC
*C 2623658 VKN/PYRS 12/17/08 Added CY7C421-20JXI
Removed CY7C419/25/29/33 from the ordering information table
Removed 26-Lead CerDIP, 32-Lead RLCC, 28-Lead molded DIP
packages from the data sheet
Removed Military Information
*D 2714768 VKN/AESA 06/04/2009 Corrected defective Logic Block diagram, Pinouts, and Package diagrams
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