S6J328CKSPSE20000 - CYPRESS SEMICONDUCTOR

S6J3200 Series

32-bit Microcontroller

Traveo Family

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 002-05682 Rev. *K Revised April 4, 2019

The Traveo MCU S6J3200 family features 32-bit RISC microcontrollers with an Arm® Cortex®- R5 core and operates up to 240 MHz.

This microcontroller comes with highly-efficient 2D/3D graphic engines with advanced feature-sets for memory saving, safety, and

high image quality to help manufacturers take advantage of the lower overall system costs. It also meets the increasingly high levels

of performance and quality that industrial, consumer, and automotive applications demand. In addition, this microcontroller offers

support for the Cypress HyperBus™ memory interface, a breakthrough that dramatically improves read performance while reducing

the number of pins. This microcontroller comes with Ethernet AVB, CAN-FD, a high-speed communication protocol compatible with

the conventional CAN, and Secure Hardware Extension (SHE) as a security function.

Features

 System

 32-bit Arm Cortex-R5F CPU core at up to 240 MHz

 GPIO port: Up to 120

 12-bit A/D converter: Up to 50 channels

 External interrupt: Up to 16 channels

 Base timer: Up to 24 channels

 32-bit free-run timer: Up to 12 channels

 Built-in CR oscillators

 Real-time clock

 Input capture unit: Up to 24 channels

 Output compare unit: Up to 24 channels

 DMA controller: 16 channels

 Stepper motor controller (SMC): Six units

 JTAG debug interface

 Graphics and Display

 2D graphic engine

 3D graphic engine (optional)

 Timing generator - TCON

 TTL/RSDS

 FPD-Link – LVDS (optional)

 Video capture (optional)

 Communication: Ethernet AVB MAC (optional)

 CAN-FD: up to four channels

 Multi-function serial interface：up to 12 channels, selec

table protocol: UART, CSIO, LIN, and I2C

 MediaLB: up to one channel (optional)

 Memory

 Cypress HyperBus Memory interface

 Dual quad double data rate SPI Flash Interface

 Multimedia

 I2S input/output: Up to two units

 PCM to PWM output unit

 Sound mixer (optional): 1 unit x 10 inputs (optional)

 Stereo audio DAC (optional)

 Security and Safety

 Secure Hardware Extension

 Safety features, such as MPU, TPU, ECC, and others

 CRC generator: One channel

 Watchdog timer with window function

 Low-voltage detector

 Clock supervisor for all source clocks

Document Number: 002-05682 Rev. *K Page 2 of 222

S6J3200 Series

Table of Contents

Features ................................................................................................................................................................................... 1

1. Overview ............................................................................................................................................................................ 3

1.1 Document Definition ...................................................................................................................................................... 3

2. Function List ..................................................................................................................................................................... 4

2.1 Function List .................................................................................................................................................................. 4

2.2 Optional Function .......................................................................................................................................................... 7

3. Product Description ........................................................................................................................................................ 15

3.1 Overview ..................................................................................................................................................................... 15

3.2 Product Description ..................................................................................................................................................... 15

4. Package and Pin Assignment ........................................................................................................................................ 22

4.1 Pin Assignment ........................................................................................................................................................... 22

4.2 Package Dimensions ................................................................................................................................................... 39

5. I/O Circuit Type................................................................................................................................................................ 44

5.1 I/O Circuit Type ........................................................................................................................................................... 44

5.2 Note ............................................................................................................................................................................. 51

6. Port Description .............................................................................................................................................................. 52

6.1 Port Description List .................................................................................................................................................... 52

6.2 Remark ........................................................................................................................................................................ 70

7. Precautions and Handling Devices ............................................................................................................................... 70

7.1 Handling Precautions .................................................................................................................................................. 70

7.2 Handling Devices ........................................................................................................................................................ 73

8. Electric Characteristics .................................................................................................................................................. 75

8.1 Absolute Maximum Rating ........................................................................................................................................... 75

8.2 Operation Assurance Condition ................................................................................................................................... 79

8.3 DC Characteristics....................................................................................................................................................... 84

8.4 AC Characteristics ....................................................................................................................................................... 98

8.5 A/D Converter ............................................................................................................................................................ 174

8.6 Audio DAC ................................................................................................................................................................. 178

8.7 Flash Memory ............................................................................................................................................................ 181

9. Abbreviation .................................................................................................................................................................. 182

10. Ordering Information .................................................................................................................................................... 184

11. Errata .............................................................................................................................................................................. 186

12. Appendix ........................................................................................................................................................................ 189

12.1 Application 1: JTAG tool Connection ....................................................................................................................... 189

13. Major Changes .............................................................................................................................................................. 190

13.1 Supplementary Information ....................................................................................................................... 190

Document History ............................................................................................................................................................... 212

Sales, Solutions, and Legal Information ........................................................................................................................... 222

Document Number: 002-05682 Rev. *K Page 3 of 222

S6J3200 Series

1. Overview

1.1 Document Definition

Following are the related documents of S6J3200.

Table 1-1

Document Type

Definition

Primary User

Document Code

Datasheet

The function and its characteristics

are specified quantitatively.

Investigator and hardware

engineer

002-05682 Revision

(Previous: DS708-00003-Revision)

S6J3200 hardware

manual

The function and operation of the

S6J3200 series are described.

Software engineer

002-04852 Revision

TraveoTM Platform

hardware manual

The function and operation of the

CPU core platform are described.

Software engineer

002-04854 Revision

Application note

The reference software, sample

application, the reference board

design, and so on are explained.

Software and hardware

engineer

002-09861 Revision

002-09715 Revision

002-04455 Revision

002-04096 Revision

002-12061 Revision

002-04452 Revision

002-09716 Revision

002-11319 Revision

002-02495 Revision

Notes:

− Refer to all documents for the system development.

− "Primary user" is most likely the engineer for whom the document is the most useful.

− The description of the datasheet and the S6J3200 hardware manual should precede the duplicated description of Traveo

platform hardware manual.

− The Traveo platform hardware manual is expected to be used as a dictionary of platform specification.

− Document code usually includes its revision.

− Revised information from the previous revision can be seen the supplementary information.

Document Number: 002-05682 Rev. *K Page 4 of 222

S6J3200 Series

2. Function List

2.1 Function List

The table shows the functions which are implemented in S6J3200 series.

Table 2-1

Function

Description

Remark

CPU core

Arm Cortex R5F

FPU

Available

(Double precision and Single precision)

PPU

Available

MPU

Available

TPU

Available

Endian

Little endian

Core clock frequency

Option

See 2.2.1 and AC

specification on the

datasheet.

HPM bus frequency

Option

See AC specification on

the datasheet

Resource clock frequency

Option

See AC specification on

the datasheet

Embedded CR oscillation

Slow clock:100 kHz, Fast clock: 4 MHz (Center frequency)

See AC specification on

the datasheet

PLL

PLL0, 1, 2, 3

SSCG PLL

SSCG0, 1, 2, 3

Clock supervisor

Available

DMA

16 ch

Boot-ROM

16 Kbytes

JTAG

Available

Data cache

16 Kbytes

Instruction cache

16 Kbytes

Program FLASH

Option

See 2.2.1

Work FLASH

112 Kbytes

TC-RAM

Option

See 2.2.1

System-RAM

Option

See 2.2.1

Backup-RAM

16 Kbytes

Security (SHE)

Option

See 2.2.1

Low latency interrupt

Available

Power domain

5 domains

Power supply

5 V +/- 0.5 V, 3.3 V +/- 0.3 V, 1.2 V +/- 0.1 V

Embedded LDO power supply for

5.0 V

Available

Low-voltage detection of external

power supply

Available

Low-voltage detection of internal

LDO output

Available

Hardware watchdog timer

Available

Software watchdog timer

Available

Package

Option

See 2.2.1

AUTOSAR

AUTOSAR 4.0.3

General Purpose I/O

Option

See 2.2.3

Quad Position & Revolution

Counter

(Up/Down Counter)

2 ch

I/O timer

3 unit x 8 ch

32 bit Reload timer

14 ch

Real time clock

Available

Automatic calibration

Sound generator

4 ch

Sound waveform generator

Option

1 unit x 5 outputs

See 2.2.1

Document Number: 002-05682 Rev. *K Page 5 of 222

S6J3200 Series

Function

Description

Remark

Sound mixer

Option

1 unit x 10 inputs

See 2.2.1

Stereo audio DAC

Option

1 unit (L and R)

See 2.2.1

PCM-PWM

Option

1 unit (L and R)

See 2.2.1

Base timer

12 units (24 ch)

Free-run timer

12 ch

Input Capture Unit

12 unit (24channels of capture)

Output Compare Unit

12unit (24 channels of compare match)

Stepping motor controller (SMC)

For 6 gauges

12 bit-A/D converter

Option

1 unit x 50 input ports (Max)

See 2.2.3

CRC

4 unit

Programmable CRC

1 unit

Source clock timer

4 ch

NMI

Available

External interrupt

16 ch

Internal interrupt

512 vectors

I2S

2 ch

One only supports an

output as a function of

the sound system.

DDR HSSPI

2 ch

A type of Quad SPI

HyperBus (RPC2)

Option

See 2.2.1

See AC specification on

the datasheet.

Multi-function serial interface

12 ch

CAN-FD

4 ch

CAN-FD RAM (ECC supported)

16KB/ch

It equivalents to 128 message buffer per channel of CCAN

module

Ethernet AVB

Option

See 2.2.1

Media-LB (MOST25)

Option

See 2.2.1

LCD controller

Option

4 COM x 32 SEG (Max)

See 2.2.3

Indicator PWM

1 ch

MPU for AHB

1 unit

MPU for AXI

1 unit

Internal VRAM

Option

See 2.2.1

Graphic engine clock

Option

See 2.2.1

Graphic AXI clock

Option

See 2.2.1

Display clock

Option

80 MHz (ch.0), 50 MHz(ch.1)

See 2.2.1

Display clock source

Graphic display controller clock or external clock

Target frame rate

60 fps

Number of display outputs

Option

Maximum 2 outputs simultaneously

See 2.2.1

TTL output (RGB888)

Option

See 2.2.1

RSDS/TCON support

1 output

FPD-Link (LVDS)

Option

1 output, 350 Mbps (Max)

See 2.2.1

Video capture unit

Option

See 2.2.1

Video capture format

ITU656, YCbCr4:4:4, YCbCr4:2:2, RGB888, RGB666

2D Graphic engine

1 unit

2.5D support

Available

Vector drawing on 2D engine

Available

Warping

Available

Scale/Rotate/Blend

Available

2D Driver API

CYPRESS proprietary

Document Number: 002-05682 Rev. *K Page 6 of 222

S6J3200 Series

Function

Description

Remark

3D Graphic engine

Option

See 2.2.1

Vector drawing on 3D engine

Option

See 2.2.1

3D Driver API

Option

See 2.2.1

Notes:

− The options are described in 2.2.

− The described specifications in the table which are related the electric characteristics only show the typical values. They don’t

necessarily include the width of characteristics, errors, and so on. They should be seen in the datasheet in detailed.

− Target resolution of graphics is WVGA 800 x 480, WQVGA 480 x 272.

− Target capture resolution of graphics is WVGA 800 x 480.

Document Number: 002-05682 Rev. *K Page 7 of 222

S6J3200 Series

2.2 Optional Function

2.2.1 Basic Option

The following figure shows the optional function and the part number relations of the series.

2.2.1.1 S6J320C

Figure 2-1: Option and Part Number for S6J320C

*1 TEQFP-256 is a package option under planning.

*2 TCRAM: 128 KB + System-RAM: 128 KB

1) Please contact your Cypress sales representative to receive the customer information CI708-0001

2) Please contact your Cypress sales representative to receive the product errata notification PEN182201

S 6 J 3 2 0 0 H A A x x x x x x x x

Ordering options 7 digit

Revision: Revision version

Digit

F

Support MCAN 3.2. (ISO Certification), 1)

M

Support MCAN 3.2. (ISO Certification), Fixed FL0014, FL0017, FL0021, FL0023, FL0025, FL0027 1)

P

Support MCAN 3.2. (ISO Certification), Fixed PEN182201 2) for revision digit M

Option

Digit SHE

SON

UOFF

Pin count

Digit Pin count

K 208 pin

L 216 pin

M 256 pin*1

Memory size

Digit Program FLASH Work FLASH RAM VRAM

C 2112KB 112KB 256KB*2 2048KB

Function

See the function digit table.

Product series

Digit Product type

2 Graphic SoC

Identifier: Automotive MCU

Description

Document Number: 002-05682 Rev. *K Page 8 of 222

S6J3200 Series

Table 2-2: Function Digit Table

Part Number

S6J32X

(X = Function Digit)

Function Digit

3

4

5

6

7

8

9

CPU Clock Maximum

240 MHz

Graphics Clock

Maximum

200 MHz

Display Output

Support

ch.0, 1

Video Capture Support

1 unit

Graphic Engine Type

2D

2D, 3D

2D

2D, 3D

2D

HyperBus Interface

ch.0, 1

ch.0, 1, 2

Sound System

N/A

YES

N/A

YES

FPD-Link

N/A

YES

N/A

YES

Media System

YES

Chip Select Output of

MFS

YES

I2C

MFS ch.4,

10, 12, 16,

17

MFS ch.4,

10, 12, 16,

17

MFS ch.4,

10, 12, 16,

17

MFS ch.4,

10, 12, 16,

17

MFS ch.4,

10, 12, 16,

17

MFS ch.4,

10, 12, 16,

17

MFS ch.4,

10, 12, 16,

17

Notes:

− This table only shows the relation between the optional function and the part numbers. That is, all products are not

necessarily available for orders. See the order number on the datasheet, and confirm actual availabilities of products.

− The sound system is composed of the sound waveform generator, the sound mixer, the audio DAC, PCM-PWM, and I2S0.

− The media system means both Ethernet AVB and Media LB.

− The CLK_CPU is assigned for CPU clock. The CLK_CD3A0 is assigned for Graphic clock. They are defined at the chapter of

Clock Configuration.

− Display Output ch.0 is used for RSDS and FPD-LINK (LVDS) as well as DRGB (Digital RGB). The ch.0 of the product which

doesn’t support FPD-LINK is used for RSDS and DRGB.

− Display Output ch.1 is used for FPD-LINK (LVDS) and DRGB (Digital RGB). The ch.1 of the product which doesn't support

FPD-LINK is used for DRGB only.

− HyperBus Interface ch.0 for MCU and ch.1 for graphic subsystem cannot be used simultaneously.

Document Number: 002-05682 Rev. *K Page 9 of 222

S6J3200 Series

2.2.1.2 S6J320A

Figure 2-2: Option and Part Number for S6J320A

* TCRAM: 64 KB + System-RAM: 128 KB

S 6 J 3 2 0 0 H A A x x x x x x x x

Ordering options 7 digit

Revision: Revision version

Digit

E Support MCAN 3.0.1

Option

Digit SHE

SON

Pin count

Digit Pin count

K 208 pin

Memory size

Digit Program FLASH Work FLASH RAM VRAM

A 1088KB 112KB 192KB* 1024KB

Function

See the function digit table.

Product series

Digit Product type

2 Graphic SoC

Identifier: Automotive MCU

Description

Document Number: 002-05682 Rev. *K Page 10 of 222

S6J3200 Series

Table 2-3: Function Digit Table

Part Number

S6J32X

(X = Function Digit)

Function Digit

B

CPU Clock Maximum

160 MHz

Graphics Clock Maximum

160 MHz

Display Output Support

ch.0

Video Capture Support

N/A

Graphic Engine Type

2D

HyperBus Interface

ch.0, 1

Sound System

YES

FPD-Link

N/A

Media System

N/A

Chip Select Output of MFS

N/A

I2C

MFS ch.16, 17

Notes:

− This table only shows the relation between the optional function and the part numbers. That is, all products are not

necessarily available for orders. See the order number on the datasheet, and confirm actual availabilities of products.

− The sound system is composed of the sound waveform generator, the sound mixer, the audio DAC, PCM-PWM, and I2S0.

− The media system means both Ethernet AVB and Media LB.

− The CLK_CPU is assigned for CPU clock. The CLK_CD3A0 is assigned for Graphic clock. They are defined at the chapter of

Clock Configuration.

− Display Output ch.0 is used for RSDS and FPD-LINK (LVDS) as well as DRGB (Digital RGB). The ch.0 of the product which

doesn’t support FPD-LINK is used for RSDS and DRGB.

− HyperBus Interface ch.0 for MCU and ch.1 for graphic subsystem cannot be used simultaneously.

Document Number: 002-05682 Rev. *K Page 11 of 222

S6J3200 Series

2.2.1.3 S6J320E

Figure 2-3: Option and Part Number for S6J320E

*1 TEQFP-256 is a package option under planning.

*2 TCRAM: 128 KB + System-RAM: 384 KB

S 6 J 3 2 0 0 H A A x x x x x x x x

Ordering options 7 digit

Revision: Revision version

Digit

M First version

Option

Digit SHE

SON

Pin count

Digit Pin count

K 208 pin

L 216 pin

M 256 pin*1

Memory size

Digit Program FLASH Work FLASH RAM VRAM

E 4160KB 112KB 512KB*2 2048KB

Function

See the function digit table.

Product series

Digit Product type

2 Graphic SoC

Identifier: Automotive MCU

Description

Document Number: 002-05682 Rev. *K Page 12 of 222

S6J3200 Series

Table 2-4: Function Digit Table

Part Number

S6J32X

(X = Function Digit)

Function Digit

K

L

M

N

CPU Clock Maximum

240 MHz

Graphics Clock Maximum

200 MHz

Display Output Support

ch.0, 1

Video Capture Support

1 unit

Graphic Engine Type

2D, 3D

HyperBus Interface

ch.0, 1

ch.0, 1, 2

ch.0, 1

Sound System

N/A

YES

N/A

FPD-Link

YES

N/A

Media System

YES

Chip Select Output of

MFS

YES

I2C

MFS ch.4, 10,

12, 16, 17

MFS ch.4,

10, 12, 16, 17

MFS ch.4, 10,

12, 16, 17

MFS ch.4, 10,

12, 16, 17

Notes:

− This table only shows the relation between the optional function and the part numbers. That is, all products are not

necessarily available for orders. See the order number on the datasheet, and confirm actual availabilities of products.

− The sound system is composed of the sound waveform generator, the sound mixer, the audio DAC, PCM-PWM, and I2S0.

− The media system means both Ethernet AVB and Media LB.

− The CLK_CPU is assigned for CPU clock. The CLK_CD3A0 is assigned for Graphic clock. They are defined at the chapter of

Clock Configuration.

− Display Output ch.0 is used for RSDS and FPD-LINK (LVDS) as well as DRGB (Digital RGB). The ch.0 of the product which

doesn’t support FPD-LINK is used for RSDS and DRGB.

− Display Output ch.1 is used for FPD-LINK (LVDS) and DRGB (Digital RGB). The ch.1 of the product which doesn't support

FPD-LINK is used for DRGB only.

− HyperBus Interface ch.0 for MCU and ch.1 for graphic subsystem cannot be used simultaneously.

Document Number: 002-05682 Rev. *K Page 13 of 222

S6J3200 Series

2.2.2 ID

ID is specified for each function digit and revision, which is defined in Figure 2-1 through Figure 2-3. The Chip ID can be read from

SYSC0_SYSIDR and the Platform ID can be read from SYSC0_SYSPFIDR. For SYSC0_SYSIDR and SYSC0_SYSPFIDR, see

the Traveo™ Platform hardware manual.

The Graphic subsystem ID can be read from the IPIdentifier register on the graphic subsystem. See the chapter Graphic

Subsystem in S6J3200 hardware manual.

Function

Digit

Option

Revision

Chip ID

JTAG ID

Platform ID

Graphic

Subsystem

3, 4, 5, 6, 7,

8, 9

S and U

A

0x10100000

0x100085CF

0x00110200

N/A

B

-

C and D

0x10100100

0x1000C5CF

0x00110200

N/A

E and F

0x10100101

0x1000C5CF

0x00110200

0x23443420

H

0x10100102

0x1000C5CF

0x00110200

0x23443470

J

0x10100103

0x1000C5CF

0x00110200

0x23443480

M

0x10100104

0x1000C5CF

0x00110200

0x23443490

P

0x10100104

0x1000C5CF

0x00110200

0x23443490

B

S

A

-

B

0x10110000

0x100095CF

0x00110200

N/A

C and D

-

E

0x10110002

0x100095CF

0x00110200

0x23442450

K

S

M

0x10170000

0x002705CF

0x00110200

0x23443490

L

S

0x002715CF

M

S

0x002725CF

N

S

0x002735CF

2.2.3 Restriction

Some functions have restrictions which depend on package pin counts.

Table 2-5

Function

TEQFP256

TEQFP216

TEQFP208

Analog input port (12 bit-

ADC)

AN0 to AN49

(50 ports)

AN0 to AN49

(50 ports)

AN1 to AN3, AN5 to AN17,

AN20 to AN49

(46 ports)

SEG port of LCD controller

SEG0 to SEG31

(32 ports)

SEG0 to SEG31

(32 ports)

SEG0 to SEG29

(30 ports)

Document Number: 002-05682 Rev. *K Page 14 of 222

S6J3200 Series

Function

TEQFP256

TEQFP216

TEQFP208

General Purpose I/O

P0_00, P0_01, P0_02,

P0_03, P0_04, P0_05,

P0_06, P0_07, P0_08,

P0_09, P0_10, P0_11,

P0_12, P0_13, P0_14,

P0_15, P0_16, P0_17,

P0_18, P0_19, P0_26,

P0_27, P0_28, P0_30,

P0_31, P1_00, P1_01,

P1_02, P1_03, P1_04,

P1_05, P1_06, P1_07,

P1_08, P1_09, P2_16,

P2_17, P2_19, P2_22,

P2_24, P2_25, P2_26,

P2_27, P2_28, P2_29,

P2_30, P2_31, P3_00,

P3_01, P3_02, P3_03,

P3_04, P3_05, P3_06,

P3_07, P3_08, P3_09,

P3_10, P3_11, P3_12,

P3_13, P3_14, P3_15,

P3_16, P3_17, P3_18,

P3_19, P3_20, P3_21,

P3_22, P3_23, P3_24,

P3_25, P3_26, P3_27,

P3_28, P3_29, P3_30,

P3_31, P4_00, P4_01,

P4_02, P4_03, P4_04,

P4_05, P4_06, P4_07,

P4_08, P4_09, P4_10,

P4_11, P4_12, P4_25,

P4_26, P4_27, P4_28,

P4_29, P4_30, P4_31,

P5_00, P5_01, P5_02,

P5_03, P5_04, P5_05,

P5_06, P5_07, P5_08,

P5_09, P5_10, P5_11,

P5_12, P5_13, P5_14,

P5_15, P5_16, P5_17,

P5_18, P5_19, P5_20,

P5_21, P5_22, P5_27,

P5_28, P5_29, P5_30,

P5_31, P6_00, P6_01,

P6_02, P6_03, P6_04,

P6_05, P6_06, P6_07,

P6_08, P6_09, P6_10,

P6_11, P6_12, P6_13,

P6_14, P6_15, P6_16,

P6_17, P6_18, P6_19,

P6_20, P6_21, P6_22,

P6_23, P6_24, P6_25,

P6_26

(154 ports)

P0_00, P0_01, P0_02,

P0_03, P0_04, P0_05,

P0_06, P0_07, P0_08,

P0_09, P0_10, P0_11,

P0_12, P0_13, P0_14,

P0_15, P0_16, P0_17,

P0_18, P0_19, P0_26,

P0_27, P0_28, P0_30,

P0_31, P1_00, P1_01,

P1_02, P1_03, P1_04,

P1_05, P1_06, P1_07,

P1_08, P1_09, P2_16,

P2_17, P2_19, P2_22,

P2_24, P2_25, P2_26,

P2_27, P2_28, P2_29,

P2_30, P2_31, P3_00,

P3_01, P3_02, P3_03,

P3_04, P3_05, P3_06,

P3_07, P3_08, P3_09,

P3_10, P3_11, P3_12,

P3_13, P3_14, P3_15,

P3_16, P3_17, P3_18,

P3_19, P3_20, P3_21,

P3_22, P3_23, P3_24,

P3_25, P3_26, P3_27,

P3_28, P3_29, P3_30,

P3_31, P4_00, P4_01,

P4_02, P4_03, P4_04,

P4_05, P4_06, P4_07,

P4_08, P4_09, P4_10,

P4_11, P4_12, P4_25,

P4_26, P4_27, P4_28,

P4_29, P4_30, P4_31,

P5_00, P5_01, P5_02,

P5_03, P5_04, P5_05,

P5_06, P5_07, P5_08,

P5_09, P5_10, P5_11,

P5_12, P5_13, P5_14,

P5_15, P5_16, P5_17,

P5_18, P5_19, P5_20,

P5_21, P5_22, P5_27,

P5_28, P5_29, P5_30,

P5_31, P6_00

(128 ports)

P0_00, P0_01, P0_04,

P0_05, P0_06, P0_07,

P0_08, P0_09, P0_10,

P0_11, P0_12, P0_13,

P0_14, P0_15, P0_16,

P0_17, P0_18, P0_19,

P0_26, P0_27, P0_28,

P0_30, P0_31, P1_00,

P1_01, P1_02, P1_03,

P1_04, P1_05, P1_06,

P1_07, P1_08, P1_09,

P2_16, P2_17, P2_19,

P2_22, P2_25, P2_26,

P2_27, P2_29, P2_30,

P2_31, P3_00, P3_01,

P3_02, P3_03, P3_04,

P3_05, P3_06, P3_07,

P3_08, P3_09, P3_12,

P3_13, P3_14, P3_15,

P3_16, P3_17, P3_18,

P3_21, P3_22, P3_23,

P3_24, P3_25, P3_26,

P3_27, P3_28, P3_29,

P3_30, P3_31, P4_00,

P4_01, P4_02, P4_03,

P4_04, P4_05, P4_06,

P4_07, P4_08, P4_09,

P4_10, P4_11, P4_12,

P4_25, P4_26, P4_27,

P4_28, P4_29, P4_30,

P4_31, P5_00, P5_01,

P5_02, P5_03, P5_04,

P5_05, P5_06, P5_07,

P5_08, P5_09, P5_10,

P5_11, P5_12, P5_13,

P5_14, P5_15, P5_16,

P5_17, P5_18, P5_19,

P5_20, P5_21, P5_22,

P5_27, P5_28, P5_29,

P5_30, P5_31, P6_00

(120 ports)

PPG triggered input

PPG0/1/2/3/4/5_TIN1,

PPG6/7/8/9/10/11_TIN

PPG0/1/2/3/4/5_TIN1,

PPG6/7/8/9/10/11_TIN

Notes:

− See multiplexed functions on pin assignment sheet.

− The optional restriction will be added without notification.

− TEQFP-256 is a package option under planning

Document Number: 002-05682 Rev. *K Page 15 of 222

S6J3200 Series

3. Product Description

3.1 Overview

This section explains the product features of the S6J3200 series. The description of this section should precede the duplicated

description on platform manual.

3.2 Product Description

Table 3-1: Product Features

Feature

Description

Technology

55-nm CMOS technology with embedded flash

Fully automotive qualified according to ISO/TS 16949 and AEC-Q100

Functional Safety

The product series has some functional safety features suited for ASIL-B application.

Peripherals

See function list.

Power Domain (PD)

See the platform manual and the STATE TRANSITION chapter in detail.

The product series supports the power-off control of PD2 (including PD3 and 5), PD4_0, PD4_1,

and PD6.

The power domain resets of PD3 and PD5 included in PD2 are not supported in the product

series, and "0" is always read from the reset factor flags of them.

This series does not support partial wakeup for PD6.

Debug and Trace

See the platform manual in detail.

− Standard 5-pin JTAG interface

− 4k Word Embedded Trace Buffer

4-bit trace support for TEQFP package.

Full trace (dedicated 16-bit port) with special bond-out package is planned.

System Control

See the platform manual in detail.

Main and sub oscillator is available.

− A wide range of 3.6 - 16 MHz is available for main oscillator

− 32 KHz is available for sub oscillator

Sub clock is enable/disable by register settings

Clock

See the platform manual in detail.

CLK_CLKO (Clock Output Function) is not supported.

Main Oscillation Stabilization Wait Time (at 4 MHz):8.19 ms (Initial value)

Embedded CR oscillation

See the platform manual in detail.

Stabilization time is as followings.

− 0.35 ms to 0.8 ms for 4 MHz (Fast clock)

− 0.43 ms to 1.28 ms for 100 kHz (Slow clock)

Clock Supervisor

See the platform manual in detail.

This product series does not support the clock supervisor output port. (Related register and

internal circuit is implemented.)

Reset

See the platform manual in detail.

Following resets are not mounted on this device or not supported.

− INITX: INITX is issued by simultaneous assert of RSTX and MODE, but this product series does not support INITX.

− SRSTX (and nSRST pin)

The product series does not support EX5VRST and writing EX5VRSTCNT bits in

SYSC0_SPECFGR has no effect.

Hardware Watchdog

See the platform manual in detail.

Hardware watchdog function stops during PSS mode. In the related register of HWDG_CFG, the

bit ALLOWSTOPCLK is always read as 1 (HWDG_CFG.ALLOWSTOPCLK=1).

The product series does not support Watchdog Counter Monitor Output port. (Related register and

internal circuit is implemented.)

Document Number: 002-05682 Rev. *K Page 16 of 222

S6J3200 Series

Feature

Description

Software Watchdog

See the platform manual in detail.

The product series doesn’t support Watchdog Counter Monitor Output port. (Related register and

internal circuit is implemented.)

Standby Mode

See the platform manual in detail.

Standby mode with 5 V single power supply is available.

Turning off the 3.3-V supply and the external 1.2-V supply in standby mode is available.

The long term pulse of the indicator PWM can be outputted during RTC Standby mode.

PLL / SSCG PLL

See the platform manual in detail.

Use case assumption is following.

− PLL

➢ Sound system clock

➢ Sound frequency master clock

➢ Peripherals

➢ Display clock

➢ Trace clock

− SSCG

➢ CPU core

➢ GDC core

➢ HyperBus

➢ DDR-HSSPI

Product supports down spread and center spread modes with the conditions defined in chapter

"Internal Clock Timing" on the datasheet.

External Interrupts

See the platform manual in detail.

NMI

See the platform manual in detail.

1 NMI pin.

Memory Protection

MPU16 AHB: See the platform manual in detail.

MPU for AXI: ch.0 (Supervise Ethernet)

MPU for AHB: ch.1 (Supervise Media LB)

Additional MPU for Graphic sub system, MediaLB and Ethernet AVB. They are described on the

chapter of MPU for AHB and MPU for AXI.

To configure Lock or Unlock for both MPUXn_UNLOCK and MPUHn_UNLOCK,

− Lock: 0x112ABB56

− Unlock: 0xACCABB56

Peripheral Protection

See the platform manual in detail.

Protected peripherals are described in the base address map.

Internal Memories

System RAM

See the platform manual in detail.

1 wait cycle is necessary for RAM read at over 160 MHz.

No need to insert wait cycles for RAM write.

Internal Memories

TCRAM

See the platform manual in detail.

Internal Memories

Backup RAM

16 KB

Backup RAM can only be operated in RUN mode (normal operation mode). In other mode the

memory content should be retained, but it cannot be operated. SLEEP control for Backup RAM is

not supported and cannot be used.

Internal Memories

VRAM

ECC region is shared with user region.

Memory size available for user program become less when ECC is enabled.

User can define ECC enabled area and ECC disabled area.

Single error correction, double error detection (SECDED) ECC support per 32-bit word.

Document Number: 002-05682 Rev. *K Page 17 of 222

S6J3200 Series

Feature

Description

Embedded

Program/Work Flash

Memory

Embedded Program flash can be accessed with 0-wait-cycle if CPU frequency is 80 MHz or less.

0-wait-cycle: 80 MHz or less.

1-wait-cycle: 160 MHz or less.

2-wait-cycle: more than 160 MHz.

The maximum frequency should be referred in datasheet.

Erase suspend is supported. Reading and writing to the other sector are possible when Flash

Erase is suspended.

Serial Flash programing and Parallel Flash programing are supported.

Margin mode is not supported.

Security

Chip erase function is available for flash memory.

The function of "MK_CEER" is not supported. (MK_CEER = not selectable)

For details, see the platform manual and chapter "Security"

Internal Power Domain

PD1: Always ON

PD2: Cortex R5F platform/ GDC/ additional peripherals

PD4: Backup RAM in Always On domain

PD6: Peripherals in Always On domain

* The chapter of the block diagram explains in detail.

Power Supply

External 5 V, 3 V, 1.2 V is required.

Built in LDO provides internal 1.2 V for Always On region (PD1).

External 1.2-V power supply control pin is supported.

External 3.3-V power supply should be controlled by GPIO.

There are constraints of power on/off sequence.

Low-voltage Detection

LVD for external voltage is supported.

LVD for internal voltage is supported.

See the specification of the detected level on the datasheet.

Low-voltage Detection for

RAM Retention (RVD)

RVD for RAM retention is effective during the standby mode only. That is, it is only for the Backup

RAM of 16 KB that the function is available.

Resource inter-connect

The output signal of some resources can be inputted to the other resource.

I/O Ports

5-V GPIO

3-V GPIO

Multi input level and multi output drivability

Pull-up, pull-down function is available.

Resource input and output is multiplexed.

+B input is allowed many pins of 3.3 V, 5 V, and 3.3 V/5 V I/O domain.

A/D Converter

12-bit resolution, 1 unit

50 channels of analog input for TEQFP256 and TEQPF216

46 channels of analog input for TEQFP208

24 channels of them are shared with the SMC for TEQFP256/216/208

External trigger and timer trigger are available.

The description of the A/D converter function should be referred in the S6J3200 hardware manual.

Though the chapter of I/O port in Traveo PF V3 hardware manual describes another A/D converter

function, do not refer it.

CRC

See the platform manual in detail.

Programmable CRC

DMA support

Sound Generator

Produces sound/melody with varying frequency and amplitude for convenient duration

Square wave sound output

Automatic linear amplitude increment or decrement

Interrupt request generated when specified sound length has ended

Document Number: 002-05682 Rev. *K Page 18 of 222

S6J3200 Series

Feature

Description

Sound Waveform

Generator

Sine waveform, saw-tooth waveform and Square waveform are generated with easy configuration

of the parameters which specified sound sources.

Fade-in and Fade-out control for reverberation.

Sound Mixer

The input channels of 0-4 are reserved for waveform generator.

Mixing different sampling frequency sounds.

Mixing Internal sounds and External I2S input sounds.

Saturating addition function for keeping sound quality.

Cut a specific frequency data by digital filter.

LPF is support by FIR filter.

Fade-in and Fade-out control.

PCM-PWM

Conversion of PCM audio streaming to Pulse Width Modulated signals.

Supports 2 output channels for stereo and mono data

Up to 16-bit output sample resolution

Support for half and full H-bridges

Audio DAC

The sound source of the fixed 48 kHz sampling frequency can be outputted.

1unit, L/R channels support.

BTL connection is available.

I2S

2 ch.

− I2S0 can output sound sources which are processed by Sound System.

− I2S1 can input sound sources which are processed by Sound System.

See the "Sound System Configuration" of S6J3200 hardware manual in detail.

Base Timer

See the platform manual in detail.

A unit consists of a pair of 16 bit base timers. 12 units, that is, 24 channels of base timers are

available.

Reload Timer

See the platform manual in detail.

I/O Timer

See the platform manual in detail.

Quad Position &

Revolution Counter

(Up/Down Counter)

See the platform manual in detail.

Multi-functional Serial

(MFS)

See the platform manual in detail.

5 ports of MFS only support I2C.

Note

− Not all pins support I2C. Only pins which have the I2C I/O characteristics support it. See the datasheet in detail.

The I2C is not designed to be hot swappable.

The availability of chip select function can be seen at Function Digit Table.

Chip Select Input is not supported.

CTS/RTS is not mounted (hardware flow control is not supported for this series.)

WUCR function is not supported for this product.

CAN-FD

Flexible data rate is supported.

16 KB/ch of message RAM is available.

The clock output from CAN pre-scaler is supplied to every CAN. ECC error generation function of

the message RAM is not supported for this device. Therefore, CAN FD ECC Error Insertion

Control Register (FDFECR) is not writeable.

See the platform manual in detail

Real Time Clock (RTC)

with Auto-calibration

See the platform manual in detail.

Document Number: 002-05682 Rev. *K Page 19 of 222

S6J3200 Series

Feature

Description

DDR High Speed SPI

ch.0: HSSPI as a MCU peripheral

ch.1: HSSPI on graphic subsystem

See the platform manual in detail

HyperBus I/F

ch.0: HyperBus as a MCU peripheral

ch.1: HyperBus on graphic subsystem

ch.2: HyperBus on graphic subsystem

The following register is not supported and cannot be used.

− Controller Status Register (HYPERBUSIn_CSR)

− Interrupt Enable Register (HYPERBUSIn_IEN)

− Interrupt Status Register (HYPERBUSIn_ISR)

− Write Protection Register (HYPERBUSIn_WPR)

− Test Register (HYPERBUSIn_TEST)

GPO signal can only be used for "Internal Control example by GPO" in this product, that is, it can

select using HyperBus of PF or using HyperBus of Graphic Sub System.

See the "HyperBus Interface Port Configuration" of S6J3200 hardware manual in detail.

Stepper Motor Control

(SMC)

Each channel has four motor drivers with high output capability

External Interrupt Capture

Unit (EICU)

See the platform manual in detail.

Ethernet AVB

10/100 Mbps

MII-Interface

Supports Audio-Video Bridging (AVB)

ETHERNETn_revision_reg :

0x30070106 (Initial value) for after revision B

ETHERNETn_designcfg_debug6:

0x0302000E (Initial value)

See 0 in details.

MediaLB

MOST25 (512FS)

3 wires

Maximum 15 ch is available.

LCD Controller

TEQFP256: 4com x 32seg

TEQFP216: 4com x 32seg

TEQFP208: 4com x 30seg

LCDC pins are initialized with Reset. (Stop LCDC alternating current output).

Duty and Static of segment output is supported. (SEG23/ST0, SEG24/ST1, SEG25/ST2,

SEG26/ST3, SEG27/ST4, SEG28/ST5, SEG29/ST6, SEG30/ST7, SEG31/ST8)

SHE

See the platform manual in detail.

Source Clock Timer

See the platform manual in detail.

Graphics Subsystem

Variable setting about GDC clock. (Asynchronous with CPU clock)

Two drawing engines for “2D drawing” and “3D drawing”. Parallel processing support.

CPU can direct access to VRAM.

Programmable panel timing controller with RGB888 and RSDS support.

FPD-Link Converter

LFCTRL and FRANGE bit of CTRL1. See chapter FPD-Link Converter about function.

-These register bit are supported for revision M, P.

-These register bit are not supported for revision F and J. These bit are reserved bit(Access type is

R0,W0. Initial value is 0).

Document Number: 002-05682 Rev. *K Page 20 of 222

S6J3200 Series

Feature

Description

Power Supply Control

(PSC)

PSC (PSC_1) output is used for external 1.2-V power supply module control and automatically

switched with the following condition.

"High": Request to supply VCC12

- "Power ON Reset" is released

- CPU wakes up from PSS shutdown mode

"Low": Request to stop supplying VCC12

- CPU transfers from RUN mode to PSS shutdown mode.

For timing chart of output signals include PSC in detail, see the "S6J3200 hardware manual" and

chapter "State Transition"

Document Number: 002-05682 Rev. *K Page 21 of 222

S6J3200 Series

3.2.1 Ethernet

The following functions are not supported.

Functions

Remark

External FIFO Interface

Additional Low Latency TX FIFO Interface for DMA configurations

MAC Transmit Block

- half-duplex

- collision

- back_pressure

MAC Filtering Block

- external address match

- Wakeup On Lan

Energy Efficient Ethernet support

LPI Operation in Cadence IP

PHY Interface

- GMII

- SGMII

- TBI

10/100/1000 Operation

- 1000 M

SGMII Operation

Jumbo Frames

Physical Control Sub-Layer

Document Number: 002-05682 Rev. *K Page 22 of 222

S6J3200 Series

4. Package and Pin Assignment

4.1 Pin Assignment

The characters next to the pin number in the pin assignment drawing specify the I/O circuit type.

Figure 4-1: Pin Number and I/O Circuit Type

Function Digit

TEQFP-216

TEQFP-208

TEQFP-256

S6J328, S6J329, S6J32M

Figure 4-2

Figure 4-9

Figure 4-17

S6J327

Figure 4-3

Figure 4-10

-

S6J326, S6J32L

Figure 4-4

Figure 4-11

-

S6J325, S6J32N

Figure 4-5

Figure 4-12

-

S6J324

Figure 4-6

Figure 4-13

-

S6J323

Figure 4-7

Figure 4-14

-

S6J32K

Figure 4-8

Figure 4-15

-

B

-

Figure 4-16

-

0

VCC53

DSP1_CTRL0

-

Y

216

215

0 0 VSS - 1

0 0 AVSS - 2

0 0 DAC_R A 3

0 0 C_R A 4

0 0 AVSS - 5

0 0 AVCC3_DAC - 6

0 0 DAC_L A 7

0 0 C_L A 8

0 0 AVSS - 9

0 0 VSS -10

0 0 VCC12 - 11

0 0 AVSS_LVDS_PLL -12

0 0

AVCC3_LVDS_PLL

-13

0 0 VCC3_LVDS_Tx - 14

0 0 VSS_LVDS_Tx -15

0 0 TxDOUT3+ B 16

0 0 TxDOUT3- B 17

0 0 TxDOUT2+ B 18

○

Pin Number

I/O Circuit Type

Document Number: 002-05682 Rev. *K Page 23 of 222

S6J3200 Series

4.1.1 TEQFP-216 Pin Assignment

Figure 4-2: TEQFP-216 (S6J328CLxx, S6J329CLxx, S6J32MELxx)

Note:

− The pins highlighted in "red" font are not supported for products with revision A and C.

0

MFS10_SCL

MFS10_SDA

0

MFS12_SCL

MFS12_SDA

0

MFS8_CS2

MFS8_CS1

MFS8_CS3

0

MFS9_CS1

MFS9_CS0

MFS8_CS0

0

INDICATOR0_1

0

MFS8_CS2

MFS8_CS1

MFS8_CS3

MFS9_CS1

MFS9_CS0

MFS8_CS0

0

P4_28

P4_27

P4_26

P4_25

P5_20

P5_19

P5_18

P5_17

P5_16

P5_15

P5_14

P5_13

0

P5_12

P5_11

P5_10

P5_09

P5_08

P5_07

P5_06

P5_05

0

P5_04

P5_03

P5_02

P5_01

P5_00

P4_31

P4_30

P4_29

0

P2_16

P2_17

P3_17

P3_16

P3_15

P3_14

P3_13

P3_12

P3_11

P3_10

P3_09

P3_08

P3_07

P2_19

0

COM0

COM1

COM2

COM3

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

0

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

0

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

0

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

V0

V1

V2

V3

0

EINT12

EINT11

EINT10

EINT9

EINT4

EINT3

EINT2

EINT1

EINT0

EINT15

EINT14

EINT13

0

EINT12

EINT11

EINT10

EINT9

EINT8

EINT7

EINT6

EINT5

0

EINT4

EINT3

EINT2

EINT1

EINT0

EINT15

EINT14

EINT13

0

EINT0

EINT1

EINT0

EINT15

EINT14

EINT13

EINT12

EINT11

EINT10

EINT9

EINT8

EINT7

EINT3

0

PPG2_TOUT0

PPG1_TOUT2

PPG1_TOUT0

PPG0_TOUT2

PPG2_TOUT0

PPG1_TOUT2

PPG1_TOUT0

PPG0_TOUT2

PPG0_TOUT0

PPG11_TOUT2

PPG11_TOUT0

PPG10_TOUT2

0

PPG10_TOUT0

PPG9_TOUT2

PPG9_TOUT0

PPG8_TOUT2

PPG8_TOUT0

PPG7_TOUT2

PPG7_TOUT0

PPG6_TOUT2

0

PPG6_TOUT0

PPG5_TOUT2

PPG5_TOUT0

PPG4_TOUT2

PPG4_TOUT0

PPG3_TOUT2

PPG3_TOUT0

PPG2_TOUT2

0

PPG0_TOUT0

PPG0_TOUT2

PPG4_TOUT2

PPG4_TOUT0

PPG3_TOUT2

PPG3_TOUT0

PPG2_TOUT2

PPG2_TOUT0

PPG1_TOUT2

PPG1_TOUT0

PPG0_TOUT2

PPG0_TOUT0

PPG11_TOUT2

0

FRT4/5/6/7_TEXT

0

PPG6/7/8/9/10/11_TIN

FRT0/1/2/3_TEXT

TIN48

0

ICU2_IN0

ICU1_IN1

ICU1_IN0

ICU0_IN1

ICU2_IN0

ICU1_IN1

ICU1_IN0

ICU0_IN1

ICU0_IN0

ICU11_IN1

ICU11_IN0

ICU10_IN1

0

ICU10_IN0

ICU9_IN1

ICU9_IN0

ICU8_IN1

ICU8_IN0

ICU7_IN1

ICU7_IN0

ICU6_IN1

0

ICU6_IN0

ICU5_IN1

ICU5_IN0

ICU4_IN1

ICU4_IN0

ICU3_IN1

ICU3_IN0

ICU2_IN1

0

ICU0_IN0

ICU0_IN1

ICU4_IN1

ICU4_IN0

ICU3_IN1

ICU3_IN0

ICU2_IN1

ICU2_IN0

ICU1_IN1

ICU1_IN0

ICU0_IN1

ICU0_IN0

ICU11_IN1

ICU1_IN1

0

OCU2_OTD0

OCU1_OTD1

OCU1_OTD0

OCU0_OTD1

OCU2_OTD0

OCU1_OTD1

OCU1_OTD0

OCU0_OTD1

OCU0_OTD0

OCU11_OTD1

OCU11_OTD0

OCU10_OTD1

0

OCU10_OTD0

OCU9_OTD1

OCU9_OTD0

OCU8_OTD1

OCU8_OTD0

OCU7_OTD1

OCU7_OTD0

OCU6_OTD1

0

OCU6_OTD0

OCU5_OTD1

OCU5_OTD0

OCU4_OTD1

OCU4_OTD0

OCU3_OTD1

OCU3_OTD0

OCU2_OTD1

0

OCU0_OTD0

OCU0_OTD1

OCU4_OTD1

OCU4_OTD0

OCU3_OTD1

OCU3_OTD0

OCU2_OTD1

OCU2_OTD0

OCU1_OTD1

OCU1_OTD0

OCU0_OTD1

OCU0_OTD0

OCU11_OTD1

0

SGO1

SGA1

0

ZIN9

BIN9

0

AIN9

ZIN8

BIN8

AIN8

0

SGO3

SGA3

0

SGO2

SGA2

SGO1

SGA1

SGA0

SGO0

0

WOT

0

TIN34

TOT34

TIN33

TOT33

TIN32

TOT32

TIN19

TOT19

TIN18

TOT18

TOT17

0

SIN11

SCK11

SOT11

0

SIN12

SCK12

SOT12

0

SIN11

SCK11

SOT11

0

SIN10

SCK10

SOT10

0

SIN9

SCK9

SOT9

0

SIN8

SCK8

SOT8

0

SIN11

SCK11

SOT11

SIN10

SCK10

SOT10

0

SIN9

SCK9

SOT9

0

DSP0_CTRL11

DSP0_CTRL10

DSP0_CTRL9

DSP0_CTRL8

DSP0_CTRL7

DSP0_CTRL6

DSP0_CTRL5

DSP0_CTRL4

DSP0_CTRL3

DSP0_CTRL2

DSP0_CTRL1

DSP0_CTRL0

0

BN1(BL1)

BP1(BH1)

AN1(AL1)

AP1(AH1)

BN0(BL0)

BP0(BH0)

AN0(AL0)

AP0(AH0)

0

TX6

RX6

TX5

RX5

0

TX6

RX6

TX5

RX5

0

DSP1_CTRL1

DSP1_CTRL0

DSP1_CLK

DSP1_CTRL2

0

VCC53

DSP1_CTRL0

DSP1_CTRL1

DSP1_CTRL2

DSP1_CLK

DSP1_DATA0_0

DSP1_DATA1_0

DSP1_DATA0_1

DSP1_DATA1_1

DSP1_DATA0_2

DSP1_DATA1_2

DSP1_DATA0_3

DSP1_DATA1_3

VSS

VCC53

DSP1_DATA0_4

DSP1_DATA1_4

DSP1_DATA0_5

DSP1_DATA1_5

DSP1_DATA0_6

DSP1_DATA1_6

DSP1_DATA0_7

DSP1_DATA1_7

VCC53

VSS

VCC12

DSP1_DATA0_8

DSP1_DATA1_8

DSP1_DATA0_9

DSP1_DATA1_9

DSP1_DATA0_10

DSP1_DATA1_10

DSP1_DATA0_11

DSP1_DATA1_11

VCC53

VSS

VCC5

X0A

X1A

AN25

AN24

AN23

AN22

AN21

AN20

AN19

AN18

AN17

AN16

AN15

0

VSS

VCC5

-

Y

-

Y

-

Y

-

X

W

V

U

-

216

215

214

213

212

211

210

209

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 1 162 - DVCC 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVSS - 2 161 -DVSS 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC_R A 3 160 S AN49 SIN4 TX1 PWM2M5

OCU6_OTD0

ICU6_IN0

PPG6_TOUT0

EINT12 P4_12 MFS0_CS2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C_R A 4 159 S AN48 SCK4 RX1 PWM2P5

OCU5_OTD1

ICU5_IN1

PPG5_TOUT2

EINT11 P4_11 MFS0_CS1 MFS4_SCL

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVSS - 5 158 S AN47 SOT4 0PWM1M5

OCU5_OTD0

ICU5_IN0

PPG5_TOUT0

EINT10 P4_10 MFS0_CS3 MFS4_SDA

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVCC3_DAC - 6 157 S AN46 0 0 PWM1P5

OCU4_OTD1

ICU4_IN1

PPG4_TOUT2

EINT9 P4_09 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC_L A 7 156 S AN45 SIN3 0PWM2M4

OCU4_OTD0

ICU4_IN0

PPG4_TOUT0

EINT8 P4_08 MFS2_CS1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C_L A 8 155 S AN44 SCK3 0PWM2P4

OCU3_OTD1

ICU3_IN1

PPG3_TOUT2

EINT7 P4_07 MFS2_CS0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVSS - 9 154 S AN43 SOT3 0PWM1M4

OCU3_OTD0

ICU3_IN0

PPG3_TOUT0

EINT6 P4_06 MFS0_CS0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS -10 153 S AN42 0 0 PWM1P4

OCU2_OTD1

ICU2_IN1

PPG2_TOUT2

EINT5 P4_05 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 11 152 - DVCC 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVSS_LVDS_PLL -12 151 -DVSS 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVCC3_LVDS_PLL - 13 150 S AN41 SIN2 0PWM2M3

OCU2_OTD0

ICU2_IN0

PPG2_TOUT0

EINT4 P4_04 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3_LVDS_Tx - 14 149 S AN40 SCK2 0PWM2P3

OCU1_OTD1

ICU1_IN1

PPG1_TOUT2

EINT3 P4_03 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS_LVDS_Tx -15 148 S AN39 SOT2 0PWM1M3

OCU1_OTD0

ICU1_IN0

PPG1_TOUT0

EINT2 P4_02 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT3+ B 16 147 S AN38 0 0 PWM1P3

OCU0_OTD1

ICU0_IN1

PPG0_TOUT2

EINT1 P4_01 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT3- B 17 146 S AN37 0 0 PWM2M2

OCU0_OTD0

ICU0_IN0

PPG0_TOUT0

EINT0 P4_00 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT2+ B 18 145 S AN36 0 0 PWM2P2

OCU11_OTD1

ICU11_IN1

PPG11_TOUT2

EINT15 P3_31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT2- B 19 144 S AN35 0 0 PWM1M2

OCU11_OTD0

ICU11_IN0

PPG11_TOUT0

EINT14 P3_30 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxCLK+ B 20 143 S AN34 0 0 PWM1P2

OCU10_OTD1

ICU10_IN1

PPG10_TOUT2

EINT13 P3_29 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxCLK- B 21 142 - DVCC 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT1+ B 22 141 -DVSS 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT1- B 23 140 S AN33 0BN1(BL1) PWM2M1

OCU10_OTD0

ICU10_IN0

PPG10_TOUT0

EINT12 P3_28 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT0+ B 24 139 S AN32 0BP1(BH1) PWM2P1

OCU9_OTD1

ICU9_IN1

PPG9_TOUT2

EINT11 P3_27 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT0- B 25 138 S AN31 0AN1(AL1) PWM1M1

OCU9_OTD0

ICU9_IN0

PPG9_TOUT0

EINT10 P3_26 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS_LVDS_Tx -26 137 S AN30 0AP1(AH1) PWM1P1

OCU8_OTD1

ICU8_IN1

PPG8_TOUT2

EINT9 P3_25 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3_LVDS_Tx - 27 136 S AN29 0BN0(BL0) PWM2M0

OCU8_OTD0

ICU8_IN0

PPG8_TOUT0

EINT8 P3_24 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 28 135 S AN28 0BP0(BH0) PWM2P0

OCU7_OTD1

ICU7_IN1

PPG7_TOUT2

EINT7 P3_23 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS -29 134 S AN27 0AN0(AL0) PWM1M0

OCU7_OTD0

ICU7_IN0

PPG7_TOUT0

EINT6 P3_22 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 30 133 S AN26 0AP0(AH0) PWM1P0

OCU6_OTD1

ICU6_IN1

PPG6_TOUT2

EINT5 P3_21 0

DSP0_DATA1_10 00000 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0DSP0_DATA0_4 MDC CAP0_DATA0 0DSP0_CTRL1 C 31 132 - DVCC 0 0 0 0 0 0 0 0 0

DSP0_DATA0_11 00000 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK+ DSP0_CLK D 32 131 -DVSS 0 0 0 0 0 0 0 0 0

DSP0_DATA1_11 00000 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0DSP0_DATA1_4 0CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 130 -VSS 0 0 0 0 0 0 0 0 0

0 00000 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0TOT0 0CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 129 - VCC12 0 0 0 0 0 0 0 0 0

0 00000 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0TIN0 0CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 128 - VCC12 0 0 0 0 0 0 0 0 0

0 00000 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0TOT1 0CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 127 -AVSS 0 0 0 0 0 0 0 0 0

0 00000 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 126 - AVRH5 0 0 0 0 0 0 0 0 0

0 00000 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 125 - AVCC5 0 0 0 0 0 0 0 0 0

0 00000 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0TIN2 0CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 39 124 H0 0 0 0

OCU6_OTD0

ICU6_IN0

PPG6_TOUT0

EINT4 P3_20 0

0 00000 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0TOT3 0CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 123 H0 0 SGO3 TIN35

OCU5_OTD1

ICU5_IN1

PPG5_TOUT2

EINT3 P3_19 0

0 00000 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 122 H ADTRG 0SGA3 TOT35

OCU5_OTD0

ICU5_IN0

PPG5_TOUT0

EINT2 P3_18 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS -42 121 - C 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 120 -VSS 0 0 0 0 0 0 0 0 0

0 00000 P0_02 EINT3 PPG1_TOUT2 ICU1_IN1 OCU1_OTD1 0TOT16 COL CAP0_DATA11 DSP0_DATA_D4+ DSP0_DATA0_4 D 44 119 - VCC5 0 0 0 0 0 0 0 0 0

0 00000 P0_03 EINT4 PPG2_TOUT0 ICU2_IN0 OCU2_OTD0 0TIN16 CRS CAP0_DATA12 DSP0_DATA_D4- DSP0_DATA1_4 D 45 118 Q RSTX 0 0 0 0 0 0 0 0 0

CAP0_DATA11 G_CK_2 0000 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 46 117 P MODE 0 0 0 0 0 0 0 0 0

CAP0_DATA12 G_DQ3_2 0000 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 47 116 N2 JTAG_TMS 0 0 0 0 0 0 0 0 0

CAP0_DATA13 G_DQ2_2 0000 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 48 115 N2 JTAG_TCK 0 0 0 0 0 0 0 0 0

CAP0_DATA14 G_DQ1_2 0000 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 49 114 N2 JTAG_TDI 0 0 0 0 0 0 0 0 0

CAP0_DATA15 G_DQ0_2 0000 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 50 113 O JTAG_TDO 0 0 0 0 0 0 0 0 0

0G_CS#1_2 0000 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 51 112 N JTAG_NTRST 0 0 0 0 0 0 0 0 0

0G_RWDS_2 0000 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1

I2S0_ECLK

TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 52 111 MX0 0 0 0 0 0 0 0 0 0

0G_CS#2_2 0000 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0

I2S0_SD

TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 53 110 MX1 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS -54 109 -VSS 0 0 0 0 0 0 0 0 0

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

-

D

C

-

E

-

E

-

E

-

E

-

F

-

G

H

I

J

I

J

I

L

-

VCC3

DSP0_DATA0_9

DSP0_DATA1_9

DSP0_DATA0_10

DSP0_DATA1_10

DSP0_DATA0_11

DSP0_DATA1_11

DSP0_CTRL0

VCC12

VSS

M_SCLK0

VSS

VCC3

M_SDATA0_0

M_SDATA0_2

M_SDATA0_1

M_SSEL0

M_SDATA0_3

VSS

0

VSS

VCC3

M_SDATA1_0

M_SDATA1_2

M_SDATA1_1

M_SSEL1

M_SDATA1_3

VSS

VCC3

MLBDAT

MLBSIG

MLBCLK

VCC12

VSS

VCC5

PSC_1

0

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

AN12

AN13

AN14

NMIX

VCC5

0

DSP0_DATA_D9+

DSP0_DATA_D9-

DSP0_DATA_D10+

DSP0_DATA_D10-

DSP0_DATA_D11+

DSP0_DATA_D11-

DSP0_CTRL2

0

G_SDATA1_0

G_SDATA1_2

G_SDATA1_1

G_SSEL1

G_SDATA1_3

0

G_SCLK0

0

G_SDATA0_0

G_SDATA0_2

G_SDATA0_1

G_SSEL0

G_SDATA0_3

0

DSP0_CTRL2

DSP0_CTRL3

DSP0_CTRL4

0

SOT0

SCK0

SIN0

0

SOT1

SCK1

SIN1

SOT16

SCK16

SIN16

SOT8

SCK8

SIN8

0

CAP0_DATA21

CAP0_DATA22

CAP0_DATA23

CAP0_DATA32

CAP0_DATA33

CAP0_CLK

CAP0_DATA34

0

CAP0_DATA24

CAP0_DATA25

0

SOT17

SCK17

SIN17

0

CAP0_DATA32

CAP0_DATA35

0

MFS17_SDA

MFS17_SCL

0

MFS16_SDA

MFS16_SCL

0

TXCLK

RXCLK

RXER

RXDV

COL

0

TXER

0

CRS

0

RX0

TX0

RX1

TX1

0

TOT33

TIN33

TOT34

TIN34

TOT35

TIN35

0

TIN49

0

TIN0

TIN1

TIN2

TIN3

TOT0

TOT1

TOT2

TOT3

TIN16

TOT16

TIN17

0

I2S0_WS

I2S0_SCK

I2S1_ECLK

I2S1_SD

I2S1_WS

I2S1_SCK

0

SGO0

SGA0

SGA1

SGO1

SGA2

SGO2

SGA3

SGO3

SGO0

SGA0

SGA1

SGO1

SGA2

SGO2

0

SOT1

SCK1

SIN1

0

AIN8

BIN8

ZIN8

0

AIN9

BIN9

ZIN9

0

OCU6_OTD1

OCU7_OTD0

OCU7_OTD1

OCU8_OTD0

OCU8_OTD1

OCU9_OTD0

OCU10_OTD0

0

OCU11_OTD0

0

OCU9_OTD0

OCU10_OTD0

OCU9_OTD1

OCU8_OTD1

OCU10_OTD1

0

OCU5_OTD1

0

OCU6_OTD0

OCU7_OTD0

OCU6_OTD1

OCU8_OTD0

OCU7_OTD1

0

OCU4_OTD1

0

OCU3_OTD0

OCU4_OTD0

OCU4_OTD1

OCU5_OTD0

OCU5_OTD1

OCU6_OTD0

OCU6_OTD1

OCU7_OTD0

OCU7_OTD1

OCU8_OTD0

OCU8_OTD1

OCU9_OTD0

OCU9_OTD1

OCU10_OTD0

OCU10_OTD1

OCU11_OTD0

0

ICU6_IN1

ICU7_IN0

ICU7_IN1

ICU8_IN0

ICU8_IN1

ICU9_IN0

ICU10_IN0

0

ICU11_IN0

0

ICU9_IN0

ICU10_IN0

ICU9_IN1

ICU8_IN1

ICU10_IN1

0

ICU5_IN1

0

ICU6_IN0

ICU7_IN0

ICU6_IN1

ICU8_IN0

ICU7_IN1

0

ICU4_IN1

0

ICU3_IN0

ICU4_IN0

ICU4_IN1

ICU5_IN0

ICU5_IN1

ICU6_IN0

ICU6_IN1

ICU7_IN0

ICU7_IN1

ICU8_IN0

ICU8_IN1

ICU9_IN0

ICU9_IN1

ICU10_IN0

ICU10_IN1

ICU11_IN0

0

PPG0/1/2/3/4/5_TIN1

0

FRT8/9/10/11_TEXT

0

PPG6_TOUT2

PPG7_TOUT0

PPG7_TOUT2

PPG8_TOUT0

PPG8_TOUT2

PPG9_TOUT0

PPG10_TOUT0

0

PPG11_TOUT0

0

PPG9_TOUT0

PPG10_TOUT0

PPG9_TOUT2

PPG8_TOUT2

PPG10_TOUT2

0

PPG5_TOUT2

0

PPG6_TOUT0

PPG7_TOUT0

PPG6_TOUT2

PPG8_TOUT0

PPG7_TOUT2

0

PPG4_TOUT2

0

PPG3_TOUT0

PPG4_TOUT0

PPG4_TOUT2

PPG5_TOUT0

PPG5_TOUT2

PPG6_TOUT0

PPG6_TOUT2

PPG7_TOUT0

PPG7_TOUT2

PPG8_TOUT0

PPG8_TOUT2

PPG9_TOUT0

PPG9_TOUT2

PPG10_TOUT0

PPG10_TOUT2

PPG11_TOUT0

0

EINT13

EINT14

EINT15

EINT0

EINT1

EINT2

EINT4

0

EINT0

0

EINT12

EINT14

EINT13

EINT11

EINT15

0

EINT5

0

EINT6

EINT8

EINT7

EINT10

EINT9

0

EINT1

EINT2

EINT3

0

EINT6

EINT8

EINT9

EINT10

EINT11

EINT12

EINT13

EINT14

EINT15

EINT0

EINT1

EINT2

EINT3

EINT4

EINT5

EINT6

0

P0_12

P0_13

P0_14

P0_15

P0_16

P0_17

P5_22

0

P1_09

0

P1_05

P1_07

P1_06

P1_04

P1_08

0

P0_30

0

P0_31

P1_01

P1_00

P1_03

P1_02

0

P0_26

P0_27

P0_28

0

P2_22

P2_24

P2_25

P2_26

P2_27

P2_28

P2_29

P2_30

P2_31

P3_00

P3_01

P3_02

P3_03

P3_04

P3_05

P3_06

0

M_CK_0

0

M_DQ3_0

M_DQ2_0

M_DQ1_0

M_DQ0_0

M_CS#1_0

0

M_RWDS_0

0

M_CS#2_0

M_DQ4_0

M_DQ5_0

M_DQ6_0

M_DQ7_0

0

INDICATOR0_0

0

G_DQ4_2

G_DQ5_2

G_DQ6_2

G_DQ7_2

0

G_CK_1

0

G_DQ3_1

G_DQ2_1

G_DQ1_1

G_DQ0_1

G_CS#1_1

0

G_RWDS_1

0

G_CS#2_1

G_DQ4_1

G_DQ5_1

G_DQ6_1

G_DQ7_1

0

DSP0_CTRL2

DSP0_CLK

DSP0_CTRL0

DSP0_CTRL1

0

TRACE0

TRACE1

TRACE2

TRACE3

TRACE_CLK

TRACE_CTL

0

○

TOP VIEW

TEQFP-216

Document Number: 002-05682 Rev. *K Page 24 of 222

S6J3200 Series

Figure 4-3: TEQFP-216 (S6J327CLxx)

Notes:

− The pins highlighted in "red" font are not supported for products with revision A and C.

− Any function at the following pins is not supported.

Package Pin Number

Condition on PCB

12 to 27

Set to ground

0

MFS10_SCL

MFS10_SDA

0

MFS12_SCL

MFS12_SDA

0

MFS8_CS2

MFS8_CS1

MFS8_CS3

0

MFS9_CS1

MFS9_CS0

MFS8_CS0

0

INDICATOR0_1

0

MFS8_CS2

MFS8_CS1

MFS8_CS3

MFS9_CS1

MFS9_CS0

MFS8_CS0

0

P4_28

P4_27

P4_26

P4_25

P5_20

P5_19

P5_18

P5_17

P5_16

P5_15

P5_14

P5_13

0

P5_12

P5_11

P5_10

P5_09

P5_08

P5_07

P5_06

P5_05

0

P5_04

P5_03

P5_02

P5_01

P5_00

P4_31

P4_30

P4_29

0

P2_16

P2_17

P3_17

P3_16

P3_15

P3_14

P3_13

P3_12

P3_11

P3_10

P3_09

P3_08

P3_07

P2_19

0

COM0

COM1

COM2

COM3

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

0

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

0

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

0

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

V0

V1

V2

V3

0

EINT12

EINT11

EINT10

EINT9

EINT4

EINT3

EINT2

EINT1

EINT0

EINT15

EINT14

EINT13

0

EINT12

EINT11

EINT10

EINT9

EINT8

EINT7

EINT6

EINT5

0

EINT4

EINT3

EINT2

EINT1

EINT0

EINT15

EINT14

EINT13

0

EINT0

EINT1

EINT0

EINT15

EINT14

EINT13

EINT12

EINT11

EINT10

EINT9

EINT8

EINT7

EINT3

0

PPG2_TOUT0

PPG1_TOUT2

PPG1_TOUT0

PPG0_TOUT2

PPG2_TOUT0

PPG1_TOUT2

PPG1_TOUT0

PPG0_TOUT2

PPG0_TOUT0

PPG11_TOUT2

PPG11_TOUT0

PPG10_TOUT2

0

PPG10_TOUT0

PPG9_TOUT2

PPG9_TOUT0

PPG8_TOUT2

PPG8_TOUT0

PPG7_TOUT2

PPG7_TOUT0

PPG6_TOUT2

0

PPG6_TOUT0

PPG5_TOUT2

PPG5_TOUT0

PPG4_TOUT2

PPG4_TOUT0

PPG3_TOUT2

PPG3_TOUT0

PPG2_TOUT2

0

PPG0_TOUT0

PPG0_TOUT2

PPG4_TOUT2

PPG4_TOUT0

PPG3_TOUT2

PPG3_TOUT0

PPG2_TOUT2

PPG2_TOUT0

PPG1_TOUT2

PPG1_TOUT0

PPG0_TOUT2

PPG0_TOUT0

PPG11_TOUT2

0

FRT4/5/6/7_TEXT

0

PPG6/7/8/9/10/11_TIN

FRT0/1/2/3_TEXT

TIN48

0

ICU2_IN0

ICU1_IN1

ICU1_IN0

ICU0_IN1

ICU2_IN0

ICU1_IN1

ICU1_IN0

ICU0_IN1

ICU0_IN0

ICU11_IN1

ICU11_IN0

ICU10_IN1

0

ICU10_IN0

ICU9_IN1

ICU9_IN0

ICU8_IN1

ICU8_IN0

ICU7_IN1

ICU7_IN0

ICU6_IN1

0

ICU6_IN0

ICU5_IN1

ICU5_IN0

ICU4_IN1

ICU4_IN0

ICU3_IN1

ICU3_IN0

ICU2_IN1

0

ICU0_IN0

ICU0_IN1

ICU4_IN1

ICU4_IN0

ICU3_IN1

ICU3_IN0

ICU2_IN1

ICU2_IN0

ICU1_IN1

ICU1_IN0

ICU0_IN1

ICU0_IN0

ICU11_IN1

ICU1_IN1

0

OCU2_OTD0

OCU1_OTD1

OCU1_OTD0

OCU0_OTD1

OCU2_OTD0

OCU1_OTD1

OCU1_OTD0

OCU0_OTD1

OCU0_OTD0

OCU11_OTD1

OCU11_OTD0

OCU10_OTD1

0

OCU10_OTD0

OCU9_OTD1

OCU9_OTD0

OCU8_OTD1

OCU8_OTD0

OCU7_OTD1

OCU7_OTD0

OCU6_OTD1

0

OCU6_OTD0

OCU5_OTD1

OCU5_OTD0

OCU4_OTD1

OCU4_OTD0

OCU3_OTD1

OCU3_OTD0

OCU2_OTD1

0

OCU0_OTD0

OCU0_OTD1

OCU4_OTD1

OCU4_OTD0

OCU3_OTD1

OCU3_OTD0

OCU2_OTD1

OCU2_OTD0

OCU1_OTD1

OCU1_OTD0

OCU0_OTD1

OCU0_OTD0

OCU11_OTD1

0

SGO1

SGA1

0

ZIN9

BIN9

0

AIN9

ZIN8

BIN8

AIN8

0

SGO3

SGA3

0

SGO2

SGA2

SGO1

SGA1

SGA0

SGO0

0

WOT

0

TIN34

TOT34

TIN33

TOT33

TIN32

TOT32

TIN19

TOT19

TIN18

TOT18

TOT17

0

SIN11

SCK11

SOT11

0

SIN12

SCK12

SOT12

0

SIN11

SCK11

SOT11

0

SIN10

SCK10

SOT10

0

SIN9

SCK9

SOT9

0

SIN8

SCK8

SOT8

0

SIN11

SCK11

SOT11

SIN10

SCK10

SOT10

0

SIN9

SCK9

SOT9

0

DSP0_CTRL11

DSP0_CTRL10

DSP0_CTRL9

DSP0_CTRL8

DSP0_CTRL7

DSP0_CTRL6

DSP0_CTRL5

DSP0_CTRL4

DSP0_CTRL3

DSP0_CTRL2

DSP0_CTRL1

DSP0_CTRL0

0

BN1(BL1)

BP1(BH1)

AN1(AL1)

AP1(AH1)

BN0(BL0)

BP0(BH0)

AN0(AL0)

AP0(AH0)

0

TX6

RX6

TX5

RX5

0

TX6

RX6

TX5

RX5

0

DSP1_CTRL1

DSP1_CTRL0

DSP1_CLK

DSP1_CTRL2

0

VCC53

DSP1_CTRL0

DSP1_CTRL1

DSP1_CTRL2

DSP1_CLK

DSP1_DATA0_0

DSP1_DATA1_0

DSP1_DATA0_1

DSP1_DATA1_1

DSP1_DATA0_2

DSP1_DATA1_2

DSP1_DATA0_3

DSP1_DATA1_3

VSS

VCC53

DSP1_DATA0_4

DSP1_DATA1_4

DSP1_DATA0_5

DSP1_DATA1_5

DSP1_DATA0_6

DSP1_DATA1_6

DSP1_DATA0_7

DSP1_DATA1_7

VCC53

VSS

VCC12

DSP1_DATA0_8

DSP1_DATA1_8

DSP1_DATA0_9

DSP1_DATA1_9

DSP1_DATA0_10

DSP1_DATA1_10

DSP1_DATA0_11

DSP1_DATA1_11

VCC53

VSS

VCC5

X0A

X1A

AN25

AN24

AN23

AN22

AN21

AN20

AN19

AN18

AN17

AN16

AN15

0

VSS

VCC5

-

Y

-

Y

-

Y

-

X

W

V

U

-

216

215

214

213

212

211

210

209

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 1 162 - DVCC 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVSS - 2 161 -DVSS 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC_R A 3 160 S AN49 SIN4 TX1 PWM2M5

OCU6_OTD0

ICU6_IN0

PPG6_TOUT0

EINT12 P4_12 MFS0_CS2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C_R A 4 159 S AN48 SCK4 RX1 PWM2P5

OCU5_OTD1

ICU5_IN1

PPG5_TOUT2

EINT11 P4_11 MFS0_CS1 MFS4_SCL

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVSS - 5 158 S AN47 SOT4 0PWM1M5

OCU5_OTD0

ICU5_IN0

PPG5_TOUT0

EINT10 P4_10 MFS0_CS3 MFS4_SDA

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVCC3_DAC - 6 157 S AN46 0 0 PWM1P5

OCU4_OTD1

ICU4_IN1

PPG4_TOUT2

EINT9 P4_09 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC_L A 7 156 S AN45 SIN3 0PWM2M4

OCU4_OTD0

ICU4_IN0

PPG4_TOUT0

EINT8 P4_08 MFS2_CS1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C_L A 8 155 S AN44 SCK3 0PWM2P4

OCU3_OTD1

ICU3_IN1

PPG3_TOUT2

EINT7 P4_07 MFS2_CS0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVSS - 9 154 S AN43 SOT3 0PWM1M4

OCU3_OTD0

ICU3_IN0

PPG3_TOUT0

EINT6 P4_06 MFS0_CS0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS -10 153 S AN42 0 0 PWM1P4

OCU2_OTD1

ICU2_IN1

PPG2_TOUT2

EINT5 P4_05 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 11 152 - DVCC 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVSS_LVDS_PLL -12 151 -DVSS 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVCC3_LVDS_PLL -13 150 S AN41 SIN2 0PWM2M3

OCU2_OTD0

ICU2_IN0

PPG2_TOUT0

EINT4 P4_04 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3_LVDS_Tx -14 149 S AN40 SCK2 0PWM2P3

OCU1_OTD1

ICU1_IN1

PPG1_TOUT2

EINT3 P4_03 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS_LVDS_Tx -15 148 S AN39 SOT2 0PWM1M3

OCU1_OTD0

ICU1_IN0

PPG1_TOUT0

EINT2 P4_02 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT3+ B16 147 S AN38 0 0 PWM1P3

OCU0_OTD1

ICU0_IN1

PPG0_TOUT2

EINT1 P4_01 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT3- B17 146 S AN37 0 0 PWM2M2

OCU0_OTD0

ICU0_IN0

PPG0_TOUT0

EINT0 P4_00 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT2+ B18 145 S AN36 0 0 PWM2P2

OCU11_OTD1

ICU11_IN1

PPG11_TOUT2

EINT15 P3_31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT2- B19 144 S AN35 0 0 PWM1M2

OCU11_OTD0

ICU11_IN0

PPG11_TOUT0

EINT14 P3_30 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxCLK+ B20 143 S AN34 0 0 PWM1P2

OCU10_OTD1

ICU10_IN1

PPG10_TOUT2

EINT13 P3_29 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxCLK- B21 142 - DVCC 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT1+ B22 141 -DVSS 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT1- B23 140 S AN33 0BN1(BL1) PWM2M1

OCU10_OTD0

ICU10_IN0

PPG10_TOUT0

EINT12 P3_28 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT0+ B24 139 S AN32 0BP1(BH1) PWM2P1

OCU9_OTD1

ICU9_IN1

PPG9_TOUT2

EINT11 P3_27 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT0- B25 138 S AN31 0AN1(AL1) PWM1M1

OCU9_OTD0

ICU9_IN0

PPG9_TOUT0

EINT10 P3_26 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS_LVDS_Tx -26 137 S AN30 0AP1(AH1) PWM1P1

OCU8_OTD1

ICU8_IN1

PPG8_TOUT2

EINT9 P3_25 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3_LVDS_Tx -27 136 S AN29 0BN0(BL0) PWM2M0