S6J3200 Series 32-bit Microcontroller Traveo Family The Traveo MCU S6J3200 family features 32-bit RISC microcontrollers with an Arm(R) Cortex(R)- R5 core and operates up to 240 MHz. This microcontroller comes with highly-efficient 2D/3D graphic engines with advanced feature-sets for memory saving, safety, and high image quality to help manufacturers take advantage of the lower overall system costs. It also meets the increasingly high levels of performance and quality that industrial, consumer, and automotive applications demand. In addition, this microcontroller offers support for the Cypress HyperBusTM memory interface, a breakthrough that dramatically improves read performance while reducing the number of pins. This microcontroller comes with Ethernet AVB, CAN-FD, a high-speed communication protocol compatible with the conventional CAN, and Secure Hardware Extension (SHE) as a security function. Features System Memory 32-bit Arm Cortex-R5F CPU core at up to 240 MHz GPIO port: Up to 120 12-bit A/D converter: Up to 50 channels External interrupt: Up to 16 channels Base timer: Up to 24 channels 32-bit free-run timer: Up to 12 channels Built-in CR oscillators Real-time clock Input capture unit: Up to 24 channels Output compare unit: Up to 24 channels DMA controller: 16 channels Stepper motor controller (SMC): Six units JTAG debug interface Cypress Dual HyperBus Memory interface quad double data rate SPI Flash Interface Multimedia I2S input/output: Up to two units to PWM output unit Sound mixer (optional): 1 unit x 10 inputs (optional) Stereo audio DAC (optional) PCM Security and Safety Graphics and Display 2D graphic engine graphic engine (optional) Timing generator - TCON TTL/RSDS FPD-Link - LVDS (optional) Video capture (optional) Communication: Ethernet AVB MAC (optional) CAN-FD: up to four channels Multi-function serial interfaceup to 12 channels, selec table protocol: UART, CSIO, LIN, and I2C MediaLB: up to one channel (optional) Secure Hardware Extension features, such as MPU, TPU, ECC, and others CRC generator: One channel Watchdog timer with window function Low-voltage detector Clock supervisor for all source clocks Safety 3D Cypress Semiconductor Corporation Document Number: 002-05682 Rev. *K * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised April 4, 2019 S6J3200 Series Table of Contents Features................................................................................................................................................................................... 1 1. Overview ............................................................................................................................................................................ 3 1.1 Document Definition ...................................................................................................................................................... 3 2. Function List ..................................................................................................................................................................... 4 2.1 Function List .................................................................................................................................................................. 4 2.2 Optional Function .......................................................................................................................................................... 7 3. Product Description ........................................................................................................................................................ 15 3.1 Overview ..................................................................................................................................................................... 15 3.2 Product Description ..................................................................................................................................................... 15 4. Package and Pin Assignment ........................................................................................................................................ 22 4.1 Pin Assignment ........................................................................................................................................................... 22 4.2 Package Dimensions ................................................................................................................................................... 39 5. I/O Circuit Type................................................................................................................................................................ 44 5.1 I/O Circuit Type ........................................................................................................................................................... 44 5.2 Note ............................................................................................................................................................................. 51 6. Port Description .............................................................................................................................................................. 52 6.1 Port Description List .................................................................................................................................................... 52 6.2 Remark ........................................................................................................................................................................ 70 7. Precautions and Handling Devices ............................................................................................................................... 70 7.1 Handling Precautions .................................................................................................................................................. 70 7.2 Handling Devices ........................................................................................................................................................ 73 8. Electric Characteristics .................................................................................................................................................. 75 8.1 Absolute Maximum Rating ........................................................................................................................................... 75 8.2 Operation Assurance Condition ................................................................................................................................... 79 8.3 DC Characteristics....................................................................................................................................................... 84 8.4 AC Characteristics ....................................................................................................................................................... 98 8.5 A/D Converter ............................................................................................................................................................ 174 8.6 Audio DAC................................................................................................................................................................. 178 8.7 Flash Memory ............................................................................................................................................................ 181 9. Abbreviation .................................................................................................................................................................. 182 10. Ordering Information .................................................................................................................................................... 184 11. Errata.............................................................................................................................................................................. 186 12. Appendix ........................................................................................................................................................................ 189 12.1 Application 1: JTAG tool Connection ....................................................................................................................... 189 13. Major Changes .............................................................................................................................................................. 190 13.1 Supplementary Information ....................................................................................................................... 190 Document History ............................................................................................................................................................... 212 Sales, Solutions, and Legal Information ........................................................................................................................... 222 Document Number: 002-05682 Rev. *K Page 2 of 222 S6J3200 Series 1. Overview 1.1 Document Definition Following are the related documents of S6J3200. Table 1-1 Document Type Datasheet S6J3200 hardware manual TraveoTM Platform hardware manual Application note Definition The function and its characteristics are specified quantitatively. The function and operation of the S6J3200 series are described. The function and operation of the CPU core platform are described. The reference software, sample application, the reference board design, and so on are explained. Primary User Investigator and hardware engineer Document Code 002-05682 Revision (Previous: DS708-00003-Revision) Software engineer 002-04852 Revision Software engineer 002-04854 Revision Software and hardware engineer 002-09861 Revision 002-09715 Revision 002-04455 Revision 002-04096 Revision 002-12061 Revision 002-04452 Revision 002-09716 Revision 002-11319 Revision 002-02495 Revision Notes: - Refer to all documents for the system development. - - "Primary user" is most likely the engineer for whom the document is the most useful. - - - The Traveo platform hardware manual is expected to be used as a dictionary of platform specification. The description of the datasheet and the S6J3200 hardware manual should precede the duplicated description of Traveo platform hardware manual. Document code usually includes its revision. Revised information from the previous revision can be seen the supplementary information. Document Number: 002-05682 Rev. *K Page 3 of 222 S6J3200 Series 2. Function List 2.1 Function List The table shows the functions which are implemented in S6J3200 series. Table 2-1 Function CPU core PPU MPU TPU Endian Description Arm Cortex R5F Available (Double precision and Single precision) Available Available Available Little endian Core clock frequency Option HPM bus frequency Option Resource clock frequency Option Embedded CR oscillation Slow clock:100 kHz, Fast clock: 4 MHz (Center frequency) PLL SSCG PLL Clock supervisor DMA Boot-ROM JTAG Data cache Instruction cache Program FLASH Work FLASH TC-RAM System-RAM Backup-RAM Security (SHE) Low latency interrupt Power domain Power supply Embedded LDO power supply for 5.0 V Low-voltage detection of external power supply Low-voltage detection of internal LDO output Hardware watchdog timer Software watchdog timer Package AUTOSAR General Purpose I/O Quad Position & Revolution Counter (Up/Down Counter) I/O timer 32 bit Reload timer Real time clock Sound generator PLL0, 1, 2, 3 SSCG0, 1, 2, 3 Available 16 ch 16 Kbytes Available 16 Kbytes 16 Kbytes Option 112 Kbytes Option Option 16 Kbytes Option Available 5 domains 5 V +/- 0.5 V, 3.3 V +/- 0.3 V, 1.2 V +/- 0.1 V FPU Sound waveform generator Document Number: 002-05682 Rev. *K Remark See 2.2.1 and AC specification on the datasheet. See AC specification on the datasheet See AC specification on the datasheet See AC specification on the datasheet See 2.2.1 See 2.2.1 See 2.2.1 See 2.2.1 Available Available Available Available Available Option AUTOSAR 4.0.3 Option See 2.2.1 See 2.2.3 2 ch 3 unit x 8 ch 14 ch Available 4 ch Option 1 unit x 5 outputs Automatic calibration See 2.2.1 Page 4 of 222 S6J3200 Series Function CRC Programmable CRC Source clock timer NMI External interrupt Internal interrupt Description Option 1 unit x 10 inputs Option 1 unit (L and R) Option 1 unit (L and R) 12 units (24 ch) 12 ch 12 unit (24channels of capture) 12unit (24 channels of compare match) For 6 gauges Option 1 unit x 50 input ports (Max) 4 unit 1 unit 4 ch Available 16 ch 512 vectors I2S 2 ch DDR HSSPI 2 ch HyperBus (RPC2) Option Multi-function serial interface CAN-FD 12 ch 4 ch 16KB/ch It equivalents to 128 message buffer per channel of CCAN module Option Option Option 4 COM x 32 SEG (Max) 1 ch 1 unit 1 unit Option Option Option Option 80 MHz (ch.0), 50 MHz(ch.1) Graphic display controller clock or external clock 60 fps Option Maximum 2 outputs simultaneously Option 1 output Option 1 output, 350 Mbps (Max) Option ITU656, YCbCr4:4:4, YCbCr4:2:2, RGB888, RGB666 1 unit Available Available Available Available CYPRESS proprietary Sound mixer Stereo audio DAC PCM-PWM Base timer Free-run timer Input Capture Unit Output Compare Unit Stepping motor controller (SMC) 12 bit-A/D converter CAN-FD RAM (ECC supported) Ethernet AVB Media-LB (MOST25) LCD controller Indicator PWM MPU for AHB MPU for AXI Internal VRAM Graphic engine clock Graphic AXI clock Display clock Display clock source Target frame rate Number of display outputs TTL output (RGB888) RSDS/TCON support FPD-Link (LVDS) Video capture unit Video capture format 2D Graphic engine 2.5D support Vector drawing on 2D engine Warping Scale/Rotate/Blend 2D Driver API Document Number: 002-05682 Rev. *K Remark See 2.2.1 See 2.2.1 See 2.2.1 See 2.2.3 One only supports an output as a function of the sound system. A type of Quad SPI See 2.2.1 See AC specification on the datasheet. See 2.2.1 See 2.2.1 See 2.2.3 See 2.2.1 See 2.2.1 See 2.2.1 See 2.2.1 See 2.2.1 See 2.2.1 See 2.2.1 See 2.2.1 Page 5 of 222 S6J3200 Series Function 3D Graphic engine Vector drawing on 3D engine 3D Driver API Description Option Option Option Remark See 2.2.1 See 2.2.1 See 2.2.1 Notes: - The options are described in 2.2. - The described specifications in the table which are related the electric characteristics only show the typical values. They don't necessarily include the width of characteristics, errors, and so on. They should be seen in the datasheet in detailed. - - Target resolution of graphics is WVGA 800 x 480, WQVGA 480 x 272. Target capture resolution of graphics is WVGA 800 x 480. Document Number: 002-05682 Rev. *K Page 6 of 222 S6J3200 Series 2.2 Optional Function 2.2.1 Basic Option The following figure shows the optional function and the part number relations of the series. 2.2.1.1 S6J320C Figure 2-1: Option and Part Number for S6J320C S 6 J 3 2 0 0 H A A x x x x x x x x Ordering options 7 digit Revision: Revision version Description Digit Support MCAN 3.2. (ISO Certification), 1) F Support MCAN 3.2. (ISO Certification), Fixed FL0014, FL0017, FL0021, FL0023, FL0025, FL0027 1) M Support MCAN 3.2. (ISO Certification), Fixed PEN182201 2) for revision digit M P Option Digit S U Pin count Digit K L M SHE ON OFF Pin count 208 pin 216 pin 256 pin*1 Memory size Program FLASH Digit C 2112KB Work FLASH 112KB RAM 256KB*2 VRAM 2048KB Function See the function digit table. Product series Digit Product type 2 Graphic SoC Identifier: Automotive MCU *1 TEQFP-256 is a package option under planning. *2 TCRAM: 128 KB + System-RAM: 128 KB 1) Please contact your Cypress sales representative to receive the customer information CI708-0001 2) Please contact your Cypress sales representative to receive the product errata notification PEN182201 Document Number: 002-05682 Rev. *K Page 7 of 222 S6J3200 Series Table 2-2: Function Digit Table S6J32X (X = Function Digit) Part Number Function Digit CPU Clock Maximum Graphics Clock Maximum Display Output Support Video Capture Support Graphic Engine Type HyperBus Interface Sound System FPD-Link Media System Chip Select Output of MFS I2 C 3 240 MHz 4 240 MHz 5 240 MHz 6 240 MHz 7 240 MHz 8 240 MHz 9 240 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz ch.0, 1 ch.0, 1 ch.0, 1 ch.0, 1 ch.0, 1 ch.0, 1 ch.0, 1 1 unit 2D ch.0, 1 N/A N/A YES 1 unit 2D ch.0, 1 YES N/A YES 1 unit 2D, 3D ch.0, 1 N/A N/A YES 1 unit 2D, 3D ch.0, 1 YES YES YES 1 unit 2D ch.0, 1, 2 YES N/A YES 1 unit 2D, 3D ch.0, 1, 2 YES YES YES 1 unit 2D ch.0, 1, 2 YES YES YES YES YES YES YES YES YES YES MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 Notes: - This table only shows the relation between the optional function and the part numbers. That is, all products are not necessarily available for orders. See the order number on the datasheet, and confirm actual availabilities of products. - - - The sound system is composed of the sound waveform generator, the sound mixer, the audio DAC, PCM-PWM, and I2S0. - Display Output ch.0 is used for RSDS and FPD-LINK (LVDS) as well as DRGB (Digital RGB). The ch.0 of the product which doesn't support FPD-LINK is used for RSDS and DRGB. - Display Output ch.1 is used for FPD-LINK (LVDS) and DRGB (Digital RGB). The ch.1 of the product which doesn't support FPD-LINK is used for DRGB only. - HyperBus Interface ch.0 for MCU and ch.1 for graphic subsystem cannot be used simultaneously. The media system means both Ethernet AVB and Media LB. The CLK_CPU is assigned for CPU clock. The CLK_CD3A0 is assigned for Graphic clock. They are defined at the chapter of Clock Configuration. Document Number: 002-05682 Rev. *K Page 8 of 222 S6J3200 Series 2.2.1.2 S6J320A Figure 2-2: Option and Part Number for S6J320A S 6 J 3 2 0 0 H A A x x x x x x x x Ordering options 7 digit Revision: Revision version Digit E Support MCAN 3.0.1 Option Digit S SHE ON Pin count Digit K Pin count 208 pin Memory size Digit A Description Program FLASH Work FLASH 1088KB 112KB RAM 192KB* VRAM 1024KB Function See the function digit table. Product series Digit 2 Product type Graphic SoC Identifier: Automotive MCU * TCRAM: 64 KB + System-RAM: 128 KB Document Number: 002-05682 Rev. *K Page 9 of 222 S6J3200 Series Table 2-3: Function Digit Table Part Number S6J32X (X = Function Digit) Function Digit CPU Clock Maximum Graphics Clock Maximum Display Output Support Video Capture Support Graphic Engine Type HyperBus Interface Sound System FPD-Link Media System Chip Select Output of MFS I2 C B 160 MHz 160 MHz ch.0 N/A 2D ch.0, 1 YES N/A N/A N/A MFS ch.16, 17 Notes: - This table only shows the relation between the optional function and the part numbers. That is, all products are not necessarily available for orders. See the order number on the datasheet, and confirm actual availabilities of products. - - - The sound system is composed of the sound waveform generator, the sound mixer, the audio DAC, PCM-PWM, and I2S0. - Display Output ch.0 is used for RSDS and FPD-LINK (LVDS) as well as DRGB (Digital RGB). The ch.0 of the product which doesn't support FPD-LINK is used for RSDS and DRGB. - HyperBus Interface ch.0 for MCU and ch.1 for graphic subsystem cannot be used simultaneously. The media system means both Ethernet AVB and Media LB. The CLK_CPU is assigned for CPU clock. The CLK_CD3A0 is assigned for Graphic clock. They are defined at the chapter of Clock Configuration. Document Number: 002-05682 Rev. *K Page 10 of 222 S6J3200 Series 2.2.1.3 S6J320E Figure 2-3: Option and Part Number for S6J320E S 6 J 3 2 0 0 H A A x x x x x x x x Ordering options 7 digit Revision: Revision version Digit M First version Option Digit S SHE ON Pin count Digit K L M Pin count 208 pin 216 pin 256 pin*1 Memory size Digit E Description Program FLASH Work FLASH 4160KB 112KB RAM 512KB*2 VRAM 2048KB Function See the function digit table. Product series Digit 2 Product type Graphic SoC Identifier: Automotive MCU *1 TEQFP-256 is a package option under planning. *2 TCRAM: 128 KB + System-RAM: 384 KB Document Number: 002-05682 Rev. *K Page 11 of 222 S6J3200 Series Table 2-4: Function Digit Table S6J32X Part Number Function Digit CPU Clock Maximum Graphics Clock Maximum Display Output Support Video Capture Support Graphic Engine Type HyperBus Interface Sound System FPD-Link Media System Chip Select Output of MFS I2C (X = Function Digit) K 240 MHz 200 MHz ch.0, 1 1 unit 2D, 3D ch.0, 1 N/A YES YES L 240 MHz 200 MHz ch.0, 1 1 unit 2D, 3D ch.0, 1 YES YES YES M 240 MHz 200 MHz ch.0, 1 1 unit 2D, 3D ch.0, 1, 2 YES YES YES N 240 MHz 200 MHz ch.0, 1 1 unit 2D, 3D ch.0, 1 N/A N/A YES YES YES YES YES MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 MFS ch.4, 10, 12, 16, 17 Notes: - This table only shows the relation between the optional function and the part numbers. That is, all products are not necessarily available for orders. See the order number on the datasheet, and confirm actual availabilities of products. - - - The sound system is composed of the sound waveform generator, the sound mixer, the audio DAC, PCM-PWM, and I2S0. - Display Output ch.0 is used for RSDS and FPD-LINK (LVDS) as well as DRGB (Digital RGB). The ch.0 of the product which doesn't support FPD-LINK is used for RSDS and DRGB. - Display Output ch.1 is used for FPD-LINK (LVDS) and DRGB (Digital RGB). The ch.1 of the product which doesn't support FPD-LINK is used for DRGB only. - HyperBus Interface ch.0 for MCU and ch.1 for graphic subsystem cannot be used simultaneously. The media system means both Ethernet AVB and Media LB. The CLK_CPU is assigned for CPU clock. The CLK_CD3A0 is assigned for Graphic clock. They are defined at the chapter of Clock Configuration. Document Number: 002-05682 Rev. *K Page 12 of 222 S6J3200 Series 2.2.2 ID ID is specified for each function digit and revision, which is defined in Figure 2-1 through Figure 2-3. The Chip ID can be read from SYSC0_SYSIDR and the Platform ID can be read from SYSC0_SYSPFIDR. For SYSC0_SYSIDR and SYSC0_SYSPFIDR, see the TraveoTM Platform hardware manual. The Graphic subsystem ID can be read from the IPIdentifier register on the graphic subsystem. See the chapter Graphic Subsystem in S6J3200 hardware manual. Function Digit Option 3, 4, 5, 6, 7, 8, 9 S and U B S K L M N S S S S Revision Chip ID JTAG ID Platform ID A B C and D E and F H J M P A B C and D E 0x10100000 0x10100100 0x10100101 0x10100102 0x10100103 0x10100104 0x10100104 0x10110000 0x10110002 0x00110200 0x00110200 0x00110200 0x00110200 0x00110200 0x00110200 0x00110200 0x00110200 0x00110200 M 0x10170000 0x100085CF 0x1000C5CF 0x1000C5CF 0x1000C5CF 0x1000C5CF 0x1000C5CF 0x1000C5CF 0x100095CF 0x100095CF 0x002705CF 0x002715CF 0x002725CF 0x002735CF Graphic Subsystem N/A N/A 0x23443420 0x23443470 0x23443480 0x23443490 0x23443490 N/A 0x23442450 0x00110200 0x23443490 2.2.3 Restriction Some functions have restrictions which depend on package pin counts. Table 2-5 Function TEQFP256 TEQFP216 Analog input port (12 bitADC) AN0 to AN49 (50 ports) AN0 to AN49 (50 ports) SEG port of LCD controller SEG0 to SEG31 (32 ports) SEG0 to SEG31 (32 ports) Document Number: 002-05682 Rev. *K TEQFP208 AN1 to AN3, AN5 to AN17, AN20 to AN49 (46 ports) SEG0 to SEG29 (30 ports) Page 13 of 222 S6J3200 Series Function General Purpose I/O PPG triggered input TEQFP256 P0_00, P0_01, P0_02, P0_03, P0_04, P0_05, P0_06, P0_07, P0_08, P0_09, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_26, P0_27, P0_28, P0_30, P0_31, P1_00, P1_01, P1_02, P1_03, P1_04, P1_05, P1_06, P1_07, P1_08, P1_09, P2_16, P2_17, P2_19, P2_22, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31, P3_00, P3_01, P3_02, P3_03, P3_04, P3_05, P3_06, P3_07, P3_08, P3_09, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31, P4_00, P4_01, P4_02, P4_03, P4_04, P4_05, P4_06, P4_07, P4_08, P4_09, P4_10, P4_11, P4_12, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31, P5_00, P5_01, P5_02, P5_03, P5_04, P5_05, P5_06, P5_07, P5_08, P5_09, P5_10, P5_11, P5_12, P5_13, P5_14, P5_15, P5_16, P5_17, P5_18, P5_19, P5_20, P5_21, P5_22, P5_27, P5_28, P5_29, P5_30, P5_31, P6_00, P6_01, P6_02, P6_03, P6_04, P6_05, P6_06, P6_07, P6_08, P6_09, P6_10, P6_11, P6_12, P6_13, P6_14, P6_15, P6_16, P6_17, P6_18, P6_19, P6_20, P6_21, P6_22, P6_23, P6_24, P6_25, P6_26 (154 ports) PPG0/1/2/3/4/5_TIN1, PPG6/7/8/9/10/11_TIN TEQFP216 P0_00, P0_01, P0_02, P0_03, P0_04, P0_05, P0_06, P0_07, P0_08, P0_09, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_26, P0_27, P0_28, P0_30, P0_31, P1_00, P1_01, P1_02, P1_03, P1_04, P1_05, P1_06, P1_07, P1_08, P1_09, P2_16, P2_17, P2_19, P2_22, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31, P3_00, P3_01, P3_02, P3_03, P3_04, P3_05, P3_06, P3_07, P3_08, P3_09, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31, P4_00, P4_01, P4_02, P4_03, P4_04, P4_05, P4_06, P4_07, P4_08, P4_09, P4_10, P4_11, P4_12, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31, P5_00, P5_01, P5_02, P5_03, P5_04, P5_05, P5_06, P5_07, P5_08, P5_09, P5_10, P5_11, P5_12, P5_13, P5_14, P5_15, P5_16, P5_17, P5_18, P5_19, P5_20, P5_21, P5_22, P5_27, P5_28, P5_29, P5_30, P5_31, P6_00 (128 ports) PPG0/1/2/3/4/5_TIN1, PPG6/7/8/9/10/11_TIN TEQFP208 P0_00, P0_01, P0_04, P0_05, P0_06, P0_07, P0_08, P0_09, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_26, P0_27, P0_28, P0_30, P0_31, P1_00, P1_01, P1_02, P1_03, P1_04, P1_05, P1_06, P1_07, P1_08, P1_09, P2_16, P2_17, P2_19, P2_22, P2_25, P2_26, P2_27, P2_29, P2_30, P2_31, P3_00, P3_01, P3_02, P3_03, P3_04, P3_05, P3_06, P3_07, P3_08, P3_09, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31, P4_00, P4_01, P4_02, P4_03, P4_04, P4_05, P4_06, P4_07, P4_08, P4_09, P4_10, P4_11, P4_12, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31, P5_00, P5_01, P5_02, P5_03, P5_04, P5_05, P5_06, P5_07, P5_08, P5_09, P5_10, P5_11, P5_12, P5_13, P5_14, P5_15, P5_16, P5_17, P5_18, P5_19, P5_20, P5_21, P5_22, P5_27, P5_28, P5_29, P5_30, P5_31, P6_00 (120 ports) PPG6/7/8/9/10/11_TIN Notes: - See multiplexed functions on pin assignment sheet. - The optional restriction will be added without notification. - TEQFP-256 is a package option under planning Document Number: 002-05682 Rev. *K Page 14 of 222 S6J3200 Series 3. Product Description 3.1 Overview This section explains the product features of the S6J3200 series. The description of this section should precede the duplicated description on platform manual. 3.2 Product Description Table 3-1: Product Features Feature Technology Functional Safety Peripherals Power Domain (PD) Debug and Trace Description 55-nm CMOS technology with embedded flash Fully automotive qualified according to ISO/TS 16949 and AEC-Q100 The product series has some functional safety features suited for ASIL-B application. See function list. See the platform manual and the STATE TRANSITION chapter in detail. The product series supports the power-off control of PD2 (including PD3 and 5), PD4_0, PD4_1, and PD6. The power domain resets of PD3 and PD5 included in PD2 are not supported in the product series, and "0" is always read from the reset factor flags of them. This series does not support partial wakeup for PD6. See the platform manual in detail. - Standard 5-pin JTAG interface - 4k Word Embedded Trace Buffer 4-bit trace support for TEQFP package. Full trace (dedicated 16-bit port) with special bond-out package is planned. See the platform manual in detail. Main and sub oscillator is available. System Control Clock Embedded CR oscillation Clock Supervisor Reset Hardware Watchdog - A wide range of 3.6 - 16 MHz is available for main oscillator - 32 KHz is available for sub oscillator Sub clock is enable/disable by register settings See the platform manual in detail. CLK_CLKO (Clock Output Function) is not supported. Main Oscillation Stabilization Wait Time (at 4 MHz):8.19 ms (Initial value) See the platform manual in detail. Stabilization time is as followings. - 0.35 ms to 0.8 ms for 4 MHz (Fast clock) - 0.43 ms to 1.28 ms for 100 kHz (Slow clock) See the platform manual in detail. This product series does not support the clock supervisor output port. (Related register and internal circuit is implemented.) See the platform manual in detail. Following resets are not mounted on this device or not supported. - INITX: INITX is issued by simultaneous assert of RSTX and MODE, but this product series does not support INITX. - SRSTX (and nSRST pin) The product series does not support EX5VRST and writing EX5VRSTCNT bits in SYSC0_SPECFGR has no effect. See the platform manual in detail. Hardware watchdog function stops during PSS mode. In the related register of HWDG_CFG, the bit ALLOWSTOPCLK is always read as 1 (HWDG_CFG.ALLOWSTOPCLK=1). The product series does not support Watchdog Counter Monitor Output port. (Related register and internal circuit is implemented.) Document Number: 002-05682 Rev. *K Page 15 of 222 S6J3200 Series Feature Software Watchdog Standby Mode Description See the platform manual in detail. The product series doesn't support Watchdog Counter Monitor Output port. (Related register and internal circuit is implemented.) See the platform manual in detail. Standby mode with 5 V single power supply is available. Turning off the 3.3-V supply and the external 1.2-V supply in standby mode is available. The long term pulse of the indicator PWM can be outputted during RTC Standby mode. See the platform manual in detail. Use case assumption is following. - PLL Sound system clock Sound frequency master clock Peripherals Display clock Trace clock PLL / SSCG PLL - SSCG CPU core GDC core HyperBus DDR-HSSPI External Interrupts NMI Memory Protection Product supports down spread and center spread modes with the conditions defined in chapter "Internal Clock Timing" on the datasheet. See the platform manual in detail. See the platform manual in detail. 1 NMI pin. MPU16 AHB: See the platform manual in detail. MPU for AXI: ch.0 (Supervise Ethernet) MPU for AHB: ch.1 (Supervise Media LB) Additional MPU for Graphic sub system, MediaLB and Ethernet AVB. They are described on the chapter of MPU for AHB and MPU for AXI. To configure Lock or Unlock for both MPUXn_UNLOCK and MPUHn_UNLOCK, Peripheral Protection Internal Memories System RAM Internal Memories TCRAM Internal Memories Backup RAM Internal Memories VRAM - Lock: 0x112ABB56 - Unlock: 0xACCABB56 See the platform manual in detail. Protected peripherals are described in the base address map. See the platform manual in detail. 1 wait cycle is necessary for RAM read at over 160 MHz. No need to insert wait cycles for RAM write. See the platform manual in detail. 16 KB Backup RAM can only be operated in RUN mode (normal operation mode). In other mode the memory content should be retained, but it cannot be operated. SLEEP control for Backup RAM is not supported and cannot be used. ECC region is shared with user region. Memory size available for user program become less when ECC is enabled. User can define ECC enabled area and ECC disabled area. Single error correction, double error detection (SECDED) ECC support per 32-bit word. Document Number: 002-05682 Rev. *K Page 16 of 222 S6J3200 Series Feature Embedded Program/Work Flash Memory Security Internal Power Domain Power Supply Low-voltage Detection Low-voltage Detection for RAM Retention (RVD) Resource inter-connect I/O Ports A/D Converter CRC Programmable CRC Sound Generator Description Embedded Program flash can be accessed with 0-wait-cycle if CPU frequency is 80 MHz or less. 0-wait-cycle: 80 MHz or less. 1-wait-cycle: 160 MHz or less. 2-wait-cycle: more than 160 MHz. The maximum frequency should be referred in datasheet. Erase suspend is supported. Reading and writing to the other sector are possible when Flash Erase is suspended. Serial Flash programing and Parallel Flash programing are supported. Margin mode is not supported. Chip erase function is available for flash memory. The function of "MK_CEER" is not supported. (MK_CEER = not selectable) For details, see the platform manual and chapter "Security" PD1: Always ON PD2: Cortex R5F platform/ GDC/ additional peripherals PD4: Backup RAM in Always On domain PD6: Peripherals in Always On domain * The chapter of the block diagram explains in detail. External 5 V, 3 V, 1.2 V is required. Built in LDO provides internal 1.2 V for Always On region (PD1). External 1.2-V power supply control pin is supported. External 3.3-V power supply should be controlled by GPIO. There are constraints of power on/off sequence. LVD for external voltage is supported. LVD for internal voltage is supported. See the specification of the detected level on the datasheet. RVD for RAM retention is effective during the standby mode only. That is, it is only for the Backup RAM of 16 KB that the function is available. The output signal of some resources can be inputted to the other resource. 5-V GPIO 3-V GPIO Multi input level and multi output drivability Pull-up, pull-down function is available. Resource input and output is multiplexed. +B input is allowed many pins of 3.3 V, 5 V, and 3.3 V/5 V I/O domain. 12-bit resolution, 1 unit 50 channels of analog input for TEQFP256 and TEQPF216 46 channels of analog input for TEQFP208 24 channels of them are shared with the SMC for TEQFP256/216/208 External trigger and timer trigger are available. The description of the A/D converter function should be referred in the S6J3200 hardware manual. Though the chapter of I/O port in Traveo PF V3 hardware manual describes another A/D converter function, do not refer it. See the platform manual in detail. DMA support Produces sound/melody with varying frequency and amplitude for convenient duration Square wave sound output Automatic linear amplitude increment or decrement Interrupt request generated when specified sound length has ended Document Number: 002-05682 Rev. *K Page 17 of 222 S6J3200 Series Feature Sound Waveform Generator Sound Mixer PCM-PWM Audio DAC I2S Description Sine waveform, saw-tooth waveform and Square waveform are generated with easy configuration of the parameters which specified sound sources. Fade-in and Fade-out control for reverberation. The input channels of 0-4 are reserved for waveform generator. Mixing different sampling frequency sounds. Mixing Internal sounds and External I2S input sounds. Saturating addition function for keeping sound quality. Cut a specific frequency data by digital filter. LPF is support by FIR filter. Fade-in and Fade-out control. Conversion of PCM audio streaming to Pulse Width Modulated signals. Supports 2 output channels for stereo and mono data Up to 16-bit output sample resolution Support for half and full H-bridges The sound source of the fixed 48 kHz sampling frequency can be outputted. 1unit, L/R channels support. BTL connection is available. 2 ch. - I2S0 can output sound sources which are processed by Sound System. - I2S1 can input sound sources which are processed by Sound System. See the "Sound System Configuration" of S6J3200 hardware manual in detail. See the platform manual in detail. Base Timer Reload Timer I/O Timer Quad Position & Revolution Counter (Up/Down Counter) A unit consists of a pair of 16 bit base timers. 12 units, that is, 24 channels of base timers are available. See the platform manual in detail. See the platform manual in detail. See the platform manual in detail. See the platform manual in detail. 5 ports of MFS only support I2C. Note - Multi-functional Serial (MFS) The Not all pins support I2C. Only pins which have the I2C I/O characteristics support it. See the datasheet in detail. I 2C is not designed to be hot swappable. The availability of chip select function can be seen at Function Digit Table. Chip Select Input is not supported. CTS/RTS is not mounted (hardware flow control is not supported for this series.) CAN-FD Real Time Clock (RTC) with Auto-calibration WUCR function is not supported for this product. Flexible data rate is supported. 16 KB/ch of message RAM is available. The clock output from CAN pre-scaler is supplied to every CAN. ECC error generation function of the message RAM is not supported for this device. Therefore, CAN FD ECC Error Insertion Control Register (FDFECR) is not writeable. See the platform manual in detail See the platform manual in detail. Document Number: 002-05682 Rev. *K Page 18 of 222 S6J3200 Series Feature DDR High Speed SPI HyperBus I/F Description ch.0: HSSPI as a MCU peripheral ch.1: HSSPI on graphic subsystem See the platform manual in detail ch.0: HyperBus as a MCU peripheral ch.1: HyperBus on graphic subsystem ch.2: HyperBus on graphic subsystem The following register is not supported and cannot be used. - Controller Status Register (HYPERBUSIn_CSR) - Interrupt Enable Register (HYPERBUSIn_IEN) - Interrupt Status Register (HYPERBUSIn_ISR) - Write Protection Register (HYPERBUSIn_WPR) - Test Register (HYPERBUSIn_TEST) GPO signal can only be used for "Internal Control example by GPO" in this product, that is, it can select using HyperBus of PF or using HyperBus of Graphic Sub System. See the "HyperBus Interface Port Configuration" of S6J3200 hardware manual in detail. Stepper Motor Control (SMC) External Interrupt Capture Unit (EICU) Ethernet AVB Each channel has four motor drivers with high output capability See the platform manual in detail. 10/100 Mbps MII-Interface Supports Audio-Video Bridging (AVB) ETHERNETn_revision_reg : 0x30070106 (Initial value) for after revision B ETHERNETn_designcfg_debug6: 0x0302000E (Initial value) MediaLB LCD Controller SHE Source Clock Timer Graphics Subsystem FPD-Link Converter See 0 in details. MOST25 (512FS) 3 wires Maximum 15 ch is available. TEQFP256: 4com x 32seg TEQFP216: 4com x 32seg TEQFP208: 4com x 30seg LCDC pins are initialized with Reset. (Stop LCDC alternating current output). Duty and Static of segment output is supported. (SEG23/ST0, SEG24/ST1, SEG25/ST2, SEG26/ST3, SEG27/ST4, SEG28/ST5, SEG29/ST6, SEG30/ST7, SEG31/ST8) See the platform manual in detail. See the platform manual in detail. Variable setting about GDC clock. (Asynchronous with CPU clock) Two drawing engines for "2D drawing" and "3D drawing". Parallel processing support. CPU can direct access to VRAM. Programmable panel timing controller with RGB888 and RSDS support. LFCTRL and FRANGE bit of CTRL1. See chapter FPD-Link Converter about function. -These register bit are supported for revision M, P. -These register bit are not supported for revision F and J. These bit are reserved bit(Access type is R0,W0. Initial value is 0). Document Number: 002-05682 Rev. *K Page 19 of 222 S6J3200 Series Feature Power Supply Control (PSC) Description PSC (PSC_1) output is used for external 1.2-V power supply module control and automatically switched with the following condition. "High": Request to supply VCC12 - "Power ON Reset" is released - CPU wakes up from PSS shutdown mode "Low": Request to stop supplying VCC12 - CPU transfers from RUN mode to PSS shutdown mode. For timing chart of output signals include PSC in detail, see the "S6J3200 hardware manual" and chapter "State Transition" Document Number: 002-05682 Rev. *K Page 20 of 222 S6J3200 Series 3.2.1 Ethernet The following functions are not supported. Functions Remark External FIFO Interface Additional Low Latency TX FIFO Interface for DMA configurations MAC Transmit Block - half-duplex - collision - back_pressure MAC Filtering Block - external address match - Wakeup On Lan Energy Efficient Ethernet support LPI Operation in Cadence IP PHY Interface - GMII - SGMII - TBI 10/100/1000 Operation - 1000 M SGMII Operation Jumbo Frames Physical Control Sub-Layer Document Number: 002-05682 Rev. *K Page 21 of 222 S6J3200 Series 4. Package and Pin Assignment 4.1 Pin Assignment The characters next to the pin number in the pin assignment drawing specify the I/O circuit type. Figure 4-1: Pin Number and I/O Circuit Type 0 DAC_R A 3 0 0 C_R A 4 0 0 AVSS - 5 0 0 AVCC3_DAC - 6 0 0 DAC_L A 7 0 0 C_L A 8 0 0 AVSS - 9 0 0 VSS - 10 0 0 VCC12 - 11 0 0 AVSS_LVDS_PLL - 12 0 0 AVCC3_LVDS_PLL - 13 0 0 VCC3_LVDS_Tx - 14 0 0 VSS_LVDS_Tx - 15 0 0 TxDOUT3+ B 16 0 0 TxDOUT3- B 17 0 0 TxDOUT2+ B 18 TEQFP-216 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 4-7 Figure 4-8 - TEQFP-208 Figure 4-9 Figure 4-10 Figure 4-11 Figure 4-12 Figure 4-13 Figure 4-14 Figure 4-15 Figure 4-16 215 2 0 216 1 - - - AVSS Y VSS 0 VCC53 Document Number: 002-05682 Rev. *K 0 0 DSP1_CTRL0 Function Digit S6J328, S6J329, S6J32M S6J327 S6J326, S6J32L S6J325, S6J32N S6J324 S6J323 S6J32K B 0 0 I/O Circuit Type 0 Pin Number TEQFP-256 Figure 4-17 - Page 22 of 222 S6J3200 Series TEQFP-216 Pin Assignment 4.1.1 Figure 4-2: TEQFP-216 (S6J328CLxx, S6J329CLxx, S6J32MELxx) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDICATOR0_1 0 0 0 MFS8_CS2 0 MFS8_CS1 0 MFS8_CS3 0 MFS9_CS1 0 MFS9_CS0 0 MFS8_CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_10 P5_09 P5_08 P5_07 P5_06 P5_05 0 0 0 0 P5_04 P5_03 P5_02 P5_01 P5_00 P4_31 P4_30 P4_29 0 0 0 P2_16 P2_17 P3_17 P3_16 P3_15 P3_14 P3_13 P3_12 P3_11 P3_10 P3_09 P3_08 P3_07 P2_19 0 0 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 0 0 0 0 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 0 0 0 0 0 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 V0 V1 V2 V3 0 0 EINT10 EINT9 EINT8 EINT7 EINT6 EINT5 0 0 0 0 EINT4 EINT3 EINT2 EINT1 EINT0 EINT15 EINT14 EINT13 0 0 0 EINT0 EINT1 EINT1 EINT0 EINT15 EINT14 EINT13 EINT12 EINT11 EINT10 EINT9 EINT8 0 0 PPG8_TOUT2 PPG8_TOUT0 PPG7_TOUT2 PPG7_TOUT0 PPG6_TOUT2 0 0 0 0 PPG6_TOUT0 PPG5_TOUT2 PPG5_TOUT0 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 0 0 0 PPG0_TOUT0 PPG0_TOUT2 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 PPG2_TOUT0 PPG1_TOUT2 PPG1_TOUT0 PPG0_TOUT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN48 0 0 ICU9_IN0 ICU8_IN1 ICU8_IN0 ICU7_IN1 ICU7_IN0 ICU6_IN1 0 0 0 0 ICU6_IN0 ICU5_IN1 ICU5_IN0 ICU4_IN1 ICU4_IN0 ICU3_IN1 ICU3_IN0 ICU2_IN1 0 0 0 ICU0_IN0 ICU0_IN1 ICU4_IN1 ICU4_IN0 FRT4/5/6/7_TEXT ICU3_IN1 PPG0_TOUT0 PPG6/7/8/9/10/11_TIN EINT7 PPG11_TOUT2 EINT3 PPG9_TOUT0 ICU3_IN0 ICU2_IN1 ICU2_IN0 ICU1_IN1 ICU1_IN0 ICU0_IN1 ICU0_IN0 ICU1_IN1 0 0 OCU9_OTD1 OCU9_OTD0 BIN8 OCU8_OTD1 OCU8_OTD0 OCU7_OTD1 OCU7_OTD0 OCU6_OTD1 0 0 0 0 OCU6_OTD0 OCU5_OTD1 OCU5_OTD0 OCU4_OTD1 OCU4_OTD0 0 0 OCU0_OTD0 OCU0_OTD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN18 OCU0_OTD0 WOT TOT18 0 0 0 TOT19 0 0 0 TIN19 0 0 0 0 0 SCK9 SOT9 0 0 0 0 0 SIN8 SCK8 SOT8 0 0 0 0 0 0 0 0 0 0 OCU2_OTD0 SGO0 TOT32 SOT10 0 0 0 0 SIN9 OCU2_OTD1 SGA0 TIN32 SCK10 0 0 0 OCU3_OTD0 SGA1 TOT33 SIN10 0 0 0 OCU3_OTD1 SGO1 TIN33 SOT11 OCU0_OTD1 0 0 SOT10 OCU4_OTD0 SGA2 TOT34 SCK11 OCU1_OTD0 0 0 SCK10 OCU4_OTD1 SGO2 TIN34 SIN11 OCU1_OTD1 0 OCU3_OTD0 SGA3 0 AIN8 OCU3_OTD1 SGO3 OCU2_OTD1 ZIN8 0 0 SIN9 SCK9 SOT9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BN1(BL1) BP1(BH1) AN1(AL1) AP1(AH1) BN0(BL0) BP0(BH0) AN0(AL0) AP0(AH0) 0 0 0 0 0 TX6 RX6 TX5 RX5 0 0 TX6 RX6 TX5 RX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_DATA1_6 DSP1_DATA0_7 DSP1_DATA1_7 VCC53 VSS VCC12 VCC12 DSP1_DATA0_8 DSP1_DATA1_8 DSP1_DATA0_9 DSP1_DATA1_9 0 DSP1_DATA1_11 0 DSP1_DATA0_6 0 DSP1_DATA0_11 0 DSP1_DATA1_5 0 DSP1_DATA1_10 0 DSP1_DATA0_5 0 DSP1_DATA0_10 0 DSP1_DATA1_4 VCC53 VSS VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN19 AN18 AN17 AN16 AN15 0 VSS VCC5 Y Y Y Y Y Y Y - - - - Y Y Y Y Y Y Y Y - - - X X W W W W W W W W V V V U - - 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 0 TOT17 0 MFS8_CS0 0 ICU9_IN1 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 MFS10_SDA 0 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 D D D D C - - E - - E E E E E - E - - E E E E E - - F F F - - - G H I J J I I I I I J J I I I I I L - VCC3 DSP0_DATA0_9 DSP0_DATA_D9+ CAP0_DATA21 0 DSP0_DATA1_9 DSP0_DATA_D9- DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK DSP0_CTRL0 VCC12 VSS M_SCLK0 VSS VCC3 M_SDATA0_0 M_SDATA0_2 M_SDATA0_1 M_SSEL0 M_SDATA0_3 VSS 0 VSS VCC3 M_SDATA1_0 M_SDATA1_2 M_SDATA1_1 M_SSEL1 M_SDATA1_3 VSS VCC3 MLBDAT MLBSIG MLBCLK VCC12 VSS VCC5 PSC_1 0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 DSP0_CTRL2 0 0 0 0 0 G_SDATA1_0 G_SDATA1_2 G_SDATA1_1 G_SSEL1 G_SDATA1_3 0 G_SCLK0 0 0 G_SDATA0_0 G_SDATA0_2 G_SDATA0_1 G_SSEL0 G_SDATA0_3 0 0 DSP0_CTRL2 DSP0_CTRL3 DSP0_CTRL4 0 0 0 0 0 0 SOT0 SCK0 SIN0 0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 CAP0_DATA34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0_DATA25 0 0 0 CAP0_DATA24 0 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 RXCLK TIN33 I2S0_SCK DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 I2S1_SD DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 TXCLK TOT33 I2S0_WS COL 0 TXER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 TOT35 I2S1_WS TIN35 I2S1_SCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN0 TIN1 TIN2 TIN3 TOT0 TOT1 TOT2 TOT3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGO0 SGA0 SGA1 SGO1 SGA2 SGO2 SGA3 SGO3 SGO0 SGA0 SGA1 SGO1 TOT16 SGO2 TIN17 0 0 0 TIN16 SGA2 0 0 TIN49 0 0 0 0 0 0 0 0 DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU9_OTD0 OCU8_OTD1 OCU5_OTD1 0 0 OCU6_OTD0 OCU7_OTD0 OCU6_OTD1 OCU8_OTD0 OCU7_OTD1 0 0 0 0 0 0 OCU3_OTD0 OCU5_OTD1 OCU6_OTD0 OCU8_OTD0 OCU8_OTD1 OCU9_OTD0 OCU9_OTD1 ICU8_IN1 ICU9_IN0 0 0 0 0 ICU9_IN0 ICU9_IN1 ICU8_IN1 0 ICU5_IN1 0 0 ICU6_IN0 ICU7_IN0 ICU6_IN1 ICU8_IN0 ICU7_IN1 0 0 0 0 ICU4_IN1 0 0 0 0 ICU3_IN0 ICU4_IN0 ICU4_IN1 ICU5_IN0 ICU5_IN1 ICU6_IN0 ICU6_IN1 ICU7_IN0 ICU7_IN1 ICU8_IN0 ICU8_IN1 ICU9_IN0 ICU9_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPG6_TOUT2 PPG7_TOUT0 PPG7_TOUT2 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 0 0 0 PPG9_TOUT0 PPG8_TOUT2 PPG5_TOUT2 0 0 PPG6_TOUT0 PPG7_TOUT0 PPG6_TOUT2 PPG8_TOUT0 PPG7_TOUT2 0 0 0 0 PPG4_TOUT2 0 0 0 0 PPG3_TOUT0 PPG4_TOUT0 PPG4_TOUT2 PPG5_TOUT0 PPG5_TOUT2 PPG6_TOUT2 PPG7_TOUT0 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG9_TOUT2 EINT1 EINT2 0 0 0 0 0 0 EINT6 EINT8 EINT7 0 0 EINT1 EINT2 EINT3 0 0 0 0 EINT6 EINT8 EINT9 0 P0_30 M_RWDS_0 0 0 P1_01 M_DQ4_0 P1_00 M_DQ5_0 P1_02 M_DQ7_0 0 P0_28 0 0 0 0 0 0 P2_24 0 P2_25 0 P3_00 0 P3_01 0 P3_02 0 P3_03 0 P3_04 0 P3_05 0 P3_06 0 0 0 P2_22 0 0 0 P0_27 0 0 0 P0_26 0 0 0 P0_31 M_CS#2_0 0 0 EINT15 P2_31 0 0 0 0 EINT14 P2_30 0 PPG11_TOUT0 EINT6 0 0 EINT13 P2_29 0 EINT3 0 0 P1_09 M_CK_0 EINT12 P2_28 0 EINT2 0 0 0 0 0 G_DQ4_2 G_DQ5_2 G_DQ6_2 G_DQ7_2 0 0 0 0 0 G_CK_1 0 0 G_DQ3_1 G_DQ2_1 G_DQ1_1 G_DQ0_1 0 0 G_DQ5_1 G_DQ6_1 G_DQ7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP0_CTRL2 DSP0_CLK DSP0_CTRL0 DSP0_CTRL1 0 0 0 0 0 0 0 0 0 0 0 G_CS#2_1 0 G_DQ4_1 0 G_RWDS_1 0 0 0 G_CS#1_1 0 EINT11 P2_27 INDICATOR0_0 0 EINT1 0 EINT10 P2_26 0 EINT0 P5_22 0 EINT10 P1_03 M_DQ6_0 EINT9 P0_17 0 EINT11 P1_04 M_DQ0_0 EINT5 P0_16 0 EINT13 P1_06 M_DQ1_0 0 P0_15 0 EINT12 P1_05 M_DQ3_0 PPG10_TOUT2 EINT5 0 EINT0 PPG10_TOUT0 EINT4 0 EINT15 P0_14 0 PPG10_TOUT2 EINT15 P1_08 M_CS#1_0 0 EINT14 P0_13 0 PPG10_TOUT0 EINT14 P1_07 M_DQ2_0 PPG9_TOUT2 EINT13 P0_12 0 PPG11_TOUT0 EINT0 0 0 PPG10_TOUT0 EINT4 FRT8/9/10/11_TEXT PPG7_TOUT2 0 0 PPG0/1/2/3/4/5_TIN1 PPG6_TOUT0 OCU11_OTD0 ICU11_IN0 0 0 0 OCU10_OTD1 ICU10_IN1 0 0 ICU8_IN0 OCU10_OTD0 ICU10_IN0 0 0 ICU7_IN1 OCU10_OTD1 ICU10_IN1 0 0 ICU7_IN0 OCU10_OTD0 ICU10_IN0 0 OCU9_OTD1 ICU6_IN1 OCU11_OTD0 ICU11_IN0 0 ZIN9 OCU7_OTD1 0 0 BIN9 OCU7_OTD0 0 0 0 OCU10_OTD0 ICU10_IN0 0 AIN9 OCU6_OTD1 0 OCU9_OTD0 ZIN8 OCU5_OTD0 0 OCU8_OTD1 BIN8 OCU4_OTD1 0 OCU8_OTD0 AIN8 OCU4_OTD0 0 OCU7_OTD1 SIN1 OCU4_OTD1 0 OCU7_OTD0 SCK1 0 0 OCU6_OTD1 SOT1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 CAP0_DATA22 0 0 0 0 62 D 0 61 D 0 60 - 0 59 0 58 0 57 0 56 0 55 Page 23 of 222 Document Number: 002-05682 Rev. *K PPG9_TOUT2 0 0 0 P0_03 EINT4 PPG2_TOUT0 ICU2_IN0 OCU2_OTD0 0 TIN16 CRS CAP0_DATA12 DSP0_DATA_D4- DSP0_DATA1_4 D 45 118 Q RSTX 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 46 117 P MODE 0 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 47 116 N2 JTAG_TMS 0 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 48 115 N2 JTAG_TCK 0 0 0 0 0 0 0 0 0 CAP0_DATA14 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 49 114 N2 JTAG_TDI 0 0 0 0 0 0 0 0 0 CAP0_DATA15 G_DQ0_2 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 50 113 O JTAG_TDO 0 0 0 0 0 0 0 0 0 0 G_CS#1_2 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 51 112 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 0 G_RWDS_2 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 52 111 M X0 0 0 0 0 0 0 0 0 0 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 53 110 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 54 109 - VSS 0 0 0 0 0 0 0 0 0 0 EINT11 0 0 SEG9 0 G_CK_2 0 P5_11 0 CAP0_DATA11 0 MFS9_CS0 0 PPG8_TOUT0 EINT8 P3_24 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 28 135 S AN28 0 BP0(BH0) PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 29 134 S AN27 0 AN0(AL0) PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 30 133 S AN26 0 AP0(AH0) PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 0 0 0 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 DSP0_DATA0_4 MDC CAP0_DATA0 0 DSP0_CTRL1 C 31 132 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK+ DSP0_CLK D 32 131 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 130 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 129 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 128 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 0 CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 127 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 126 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 125 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 0 CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 39 124 H 0 0 0 0 OCU6_OTD0 ICU6_IN0 PPG6_TOUT0 EINT4 P3_20 0 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 123 H 0 0 SGO3 TIN35 OCU5_OTD1 ICU5_IN1 PPG5_TOUT2 EINT3 P3_19 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 122 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 121 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 120 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_02 EINT3 PPG1_TOUT2 ICU1_IN1 OCU1_OTD1 0 TOT16 COL CAP0_DATA11 DSP0_DATA_D4+ DSP0_DATA0_4 D 44 119 - VCC5 0 0 0 0 0 0 0 0 0 0 MFS10_SCL OCU8_OTD0 ICU8_IN0 0 201 PWM2M0 0 202 BN0(BL0) 0 - 0 DSP0_DATA1_11 Y AN29 0 VCC53 S 0 DSP1_DATA0_4 136 TOP VIEW TEQFP-216 DSP0_DATA0_11 0 27 0 0 - 0 0 VCC3_LVDS_Tx 0 0 0 DSP0_DATA1_10 0 0 0 0 SIN10 0 0 0 0 0 0 0 0 AIN9 0 0 0 0 0 0 0 0 0 ICU10_IN0 OCU10_OTD0 0 0 0 0 0 P3_25 0 0 P3_26 PPG8_TOUT2 EINT9 0 0 PPG9_TOUT0 EINT10 OCU8_OTD1 ICU8_IN1 0 EINT12 PPG10_TOUT0 OCU9_OTD0 ICU9_IN0 PWM1P1 0 0 PWM1M1 AP1(AH1) 0 SEG8 AN1(AL1) 0 0 0 0 AN30 0 P5_12 AN31 S 0 0 0 S 137 0 MFS9_CS1 0 138 26 0 0 25 - 0 0 B VSS_LVDS_Tx 0 203 TxDOUT0- 0 0 - 0 0 0 VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P3_27 0 0 PPG9_TOUT2 EINT11 0 0 OCU9_OTD1 ICU9_IN1 0 0 PWM2P1 0 0 BP1(BH1) 0 0 0 0 0 0 AN32 0 0 S 0 204 139 0 Y 24 0 DSP1_DATA1_3 B 0 0 TxDOUT0+ 0 DSP0_CTRL0 0 0 0 0 0 0 0 0 0 ICU10_IN1 OCU10_OTD1 BIN9 0 0 EINT13 PPG10_TOUT2 0 0 SEG7 0 0 P5_13 0 0 0 0 0 P3_28 0 0 PPG10_TOUT0 EINT12 0 205 OCU10_OTD0ICU10_IN0 0 Y PWM2M1 0 DSP1_DATA0_3 BN1(BL1) 0 0 0 0 DSP0_CTRL1 AN33 0 0 SOT11 S 0 0 ZIN9 140 0 0 0 ICU11_IN0 OCU11_OTD0 23 0 0 EINT14 PPG11_TOUT0 B 0 0 SEG6 TxDOUT10 0 P5_14 0 0 0 MFS8_CS3 0 0 0 0 0 0 0 0 206 0 0 0 207 0 0 0 Y 0 0 0 Y 0 0 0 DSP1_DATA1_2 0 0 0 DSP1_DATA0_2 0 0 0 DSP1_CLK 0 0 0 DSP0_CTRL2 DSP1_CTRL2 0 0 0 DSP0_CTRL3 0 0 0 0 SCK11 0 0 0 0 SIN11 0 0 0 0 0 DVSS 0 0 DVCC - 0 OCU0_OTD0 141 0 ICU0_IN0 142 22 0 0 ICU11_IN1 OCU11_OTD1 21 B 0 0 B TxDOUT1+ 0 PPG0_TOUT0 TxCLK- 0 0 EINT0 0 0 0 EINT15 PPG11_TOUT2 0 0 0 SEG5 0 0 0 SEG4 0 0 0 P5_15 0 0 0 P5_16 P3_29 0 MFS8_CS1 0 PPG10_TOUT2 EINT13 0 MFS8_CS2 0 OCU10_OTD1ICU10_IN1 0 0 PWM1P2 0 0 0 0 208 0 0 Y AN34 0 0 DSP1_DATA1_1 S 0 0 0 DSP0_CTRL4 DSP1_CTRL0 143 0 0 0 0 0 20 0 0 0 0 0 0 B 0 0 0 0 0 0 TxCLK+ 0 0 0 0 0 OCU0_OTD1 0 0 0 0 0 0 ICU0_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 PPG0_TOUT2 0 0 0 0 0 0 0 EINT1 P3_30 0 0 0 0 0 SEG3 PPG11_TOUT0 EINT14 0 0 0 0 0 P5_17 OCU11_OTD0ICU11_IN0 0 0 0 0 0 0 0 PWM1M2 0 0 0 0 0 0 0 0 0 209 0 0 0 Y AN35 0 DSP1_DATA0_1 S 0 DSP0_CTRL5 DSP1_CTRL1 144 0 0 0 SOT12 19 0 0 0 B 0 0 OCU1_OTD0 TxDOUT20 0 ICU1_IN0 0 0 0 0 0 0 0 PPG1_TOUT0 0 0 0 0 EINT2 0 P3_31 0 0 SEG2 0 P4_00 PPG11_TOUT2 EINT15 0 0 P5_18 0 P4_01 PPG0_TOUT0 EINT0 OCU11_OTD1ICU11_IN1 0 0 MFS12_SDA 0 0 P4_02 PPG0_TOUT2 EINT1 OCU0_OTD0 ICU0_IN0 PWM2P2 0 0 0 P4_03 PPG1_TOUT0 EINT2 OCU0_OTD1 ICU0_IN1 PWM2M2 0 0 0 210 PPG1_TOUT2 EINT3 OCU1_OTD0 ICU1_IN0 PWM1P3 0 0 0 0 211 OCU1_OTD1 ICU1_IN1 PWM1M3 0 0 AN36 0 0 Y PWM2P3 0 0 AN37 S 0 Y 0 SOT2 AN38 S 145 0 DSP1_DATA1_0 SCK2 AN39 S 146 18 0 DSP1_DATA0_0 AN40 S 147 17 B 0 0 S 148 16 B TxDOUT2+ 0 0 149 15 B TxDOUT3- 0 0 DSP0_CTRL6 14 - TxDOUT3+ 0 0 0 DSP0_CTRL7 - VSS_LVDS_Tx 0 0 0 0 SCK12 VCC3_LVDS_Tx 0 0 0 0 SIN12 0 0 0 0 0 0 0 0 0 OCU1_OTD1 0 P4_04 0 OCU2_OTD0 0 0 ICU1_IN1 0 PPG2_TOUT0 EINT4 0 ICU2_IN0 0 0 0 0 OCU2_OTD0 ICU2_IN0 0 0 0 PWM2M3 0 PPG1_TOUT2 0 0 0 PPG2_TOUT0 0 SIN2 0 EINT3 0 AN41 0 EINT4 DVSS S 0 SEG1 150 0 SEG0 151 13 0 P5_19 12 0 P5_20 - AVCC3_LVDS_PLL 0 0 0 AVSS_LVDS_PLL 0 0 MFS12_SCL 0 0 0 0 0 0 0 0 0 212 0 0 213 0 0 214 0 0 215 0 0 216 0 0 0 - 0 0 0 Y 0 0 0 Y DVCC 0 0 Y - 0 0 Y 152 0 0 VCC53 11 0 0 DSP1_CLK 0 0 DSP1_CTRL2 VCC12 0 0 DSP1_CTRL1 0 0 0 DSP1_CTRL0 P4_05 0 0 0 PPG2_TOUT2 EINT5 0 0 0 OCU2_OTD1 ICU2_IN1 0 0 0 PWM1P4 0 0 0 0 0 0 0 0 0 0 AN42 DAC_L DSP0_CTRL8 S 0 DSP0_CTRL9 153 0 0 0 10 0 0 0 0 SOT11 0 VSS 0 0 SCK11 DSP0_CTRL10 0 MFS0_CS0 0 0 SIN11 DSP0_CTRL11 MFS2_CS0 P4_06 0 0 P4_07 PPG3_TOUT0 EINT6 0 0 PPG3_TOUT2 EINT7 OCU3_OTD0 ICU3_IN0 0 0 OCU3_OTD1 ICU3_IN1 PWM1M4 0 0 PWM2P4 0 0 0 0 SOT3 0 OCU0_OTD1 SCK3 AN43 0 OCU1_OTD0 SGA1 AN44 S 0 OCU1_OTD1 SGO1 S 154 0 OCU2_OTD0 155 9 0 0 8 - ICU0_IN1 A AVCC3_DAC ICU1_IN0 0 C_L AVSS 0 ICU1_IN1 MFS2_CS1 0 ICU2_IN0 P4_08 0 0 PPG4_TOUT0 EINT8 0 0 OCU4_OTD0 ICU4_IN0 0 0 PWM2M4 0 0 0 0 0 SIN3 0 0 AN45 0 PPG0_TOUT2 S 0 PPG1_TOUT0 156 0 PPG1_TOUT2 0 7 0 PPG2_TOUT0 0 A 0 0 P4_09 0 EINT9 PPG4_TOUT2 EINT9 0 EINT10 OCU4_OTD1 ICU4_IN1 0 EINT11 PWM1P5 5 EINT12 0 4 VSS 0 0 3 A AVSS COM3 AN46 2 A C_R 0 COM2 S - DAC_R 0 0 COM1 MFS4_SDA 157 1 AVSS 0 0 0 COM0 MFS4_SCL MFS0_CS3 6 - 0 0 0 0 0 0 MFS0_CS1 P4_10 0 0 0 0 0 P4_25 MFS0_CS2 P4_11 0 0 0 0 0 P4_26 0 P4_12 PPG5_TOUT0 EINT10 0 0 0 0 0 P4_27 0 0 PPG5_TOUT2 EINT11 0 0 0 0 0 P4_28 0 0 PPG6_TOUT0 EINT12 OCU5_OTD0 ICU5_IN0 0 0 0 0 0 0 0 0 0 OCU5_OTD1 ICU5_IN1 PWM1M5 0 0 0 0 0 0 0 0 0 OCU6_OTD0 ICU6_IN0 PWM2P5 0 0 0 0 0 0 0 0 0 0 PWM2M5 RX1 SOT4 0 0 0 0 0 0 0 0 0 TX1 SCK4 AN47 0 0 0 0 0 0 0 0 0 SIN4 AN48 S 0 0 0 0 0 0 0 0 AN49 S 158 0 0 0 0 0 0 0 DVSS S 159 0 0 0 0 0 0 DVCC 160 0 0 0 0 0 161 0 0 0 0 162 0 0 0 Note: - The pins highlighted in "red" font are not supported for products with revision A and C. S6J3200 Series Figure 4-3: TEQFP-216 (S6J327CLxx) MFS10_SCL MFS10_SDA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFS9_CS0 0 MFS8_CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDICATOR0_1 0 0 0 MFS8_CS2 0 MFS8_CS1 0 MFS8_CS3 0 MFS9_CS1 0 MFS9_CS0 0 MFS8_CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_11 P5_10 P5_09 P5_08 P5_07 P5_06 P5_05 0 0 0 0 P5_04 P5_03 P5_02 P5_01 P5_00 P4_31 P4_30 P4_29 0 0 0 P2_16 P2_17 P3_17 P3_16 P3_15 P3_14 P3_13 P3_12 P3_11 P3_10 P3_09 P3_08 P3_07 P2_19 0 0 0 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 0 0 0 0 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 0 0 0 0 0 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 V0 V1 V2 V3 0 0 EINT12 PPG10_TOUT0 EINT11 EINT10 EINT9 EINT8 EINT7 EINT6 EINT5 0 0 0 0 EINT4 EINT3 EINT2 EINT1 EINT0 EINT15 EINT14 EINT13 0 0 0 EINT0 EINT1 EINT1 EINT0 EINT15 EINT14 EINT13 EINT12 EINT11 EINT10 EINT9 EINT8 0 0 PPG9_TOUT0 PPG8_TOUT2 PPG8_TOUT0 PPG7_TOUT2 PPG7_TOUT0 PPG6_TOUT2 0 0 0 0 PPG6_TOUT0 PPG5_TOUT2 PPG5_TOUT0 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 0 0 0 PPG0_TOUT0 PPG0_TOUT2 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 PPG2_TOUT0 PPG1_TOUT2 PPG1_TOUT0 PPG0_TOUT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRT4/5/6/7_TEXT 0 0 0 0 0 0 PPG0_TOUT0 PPG6/7/8/9/10/11_TIN EINT7 PPG11_TOUT2 EINT3 PPG9_TOUT2 0 0 ICU9_IN0 ICU8_IN1 ICU8_IN0 ICU7_IN1 ICU7_IN0 ICU6_IN1 0 0 0 0 ICU6_IN0 ICU5_IN1 ICU5_IN0 ICU4_IN1 ICU4_IN0 ICU3_IN1 ICU3_IN0 ICU2_IN1 0 0 0 ICU0_IN0 ICU0_IN1 ICU4_IN1 ICU4_IN0 ICU3_IN1 ICU3_IN0 ICU2_IN1 ICU2_IN0 ICU1_IN1 ICU1_IN0 ICU0_IN1 ICU0_IN0 ICU1_IN1 0 0 OCU9_OTD1 OCU9_OTD0 OCU8_OTD1 OCU8_OTD0 OCU7_OTD1 OCU7_OTD0 OCU6_OTD1 0 0 0 0 OCU6_OTD0 OCU5_OTD1 OCU5_OTD0 OCU4_OTD1 OCU4_OTD0 0 0 0 OCU0_OTD0 OCU0_OTD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN18 WOT TOT18 0 TOT17 0 0 0 TOT19 0 0 0 TIN19 0 0 0 0 0 0 SIN9 SCK9 SOT9 0 0 0 0 0 SIN8 SCK8 SOT8 0 0 0 0 0 0 0 0 0 0 SIN11 SIN10 OCU2_OTD0 SGO0 TOT32 SOT10 0 0 0 SOT10 OCU2_OTD1 SGA0 TIN32 SCK10 0 0 0 SCK10 OCU3_OTD0 SGA1 TOT33 OCU0_OTD0 0 0 SIN10 OCU3_OTD1 SGO1 TIN33 SOT11 OCU0_OTD1 AIN8 0 OCU4_OTD0 SGA2 TOT34 SCK11 OCU1_OTD0 BIN8 0 OCU4_OTD1 SGO2 TIN34 OCU1_OTD1 ZIN8 OCU3_OTD0 SGA3 OCU2_OTD1 0 AIN9 OCU3_OTD1 SGO3 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 TIN48 ICU9_IN1 0 0 ICU10_IN0 OCU10_OTD0 0 0 SIN9 SCK9 SOT9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BN1(BL1) BP1(BH1) AN1(AL1) AP1(AH1) BN0(BL0) BP0(BH0) AN0(AL0) AP0(AH0) 0 0 0 0 0 TX6 RX6 TX5 RX5 0 0 TX6 RX6 TX5 RX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_DATA0_6 DSP1_DATA1_6 DSP1_DATA0_7 DSP1_DATA1_7 VCC53 VSS VCC12 VCC12 DSP1_DATA0_8 DSP1_DATA1_8 DSP1_DATA0_9 DSP1_DATA1_9 0 DSP1_DATA1_11 0 DSP1_DATA1_5 0 DSP1_DATA0_11 0 DSP1_DATA0_5 0 DSP1_DATA1_10 0 DSP1_DATA1_4 0 DSP1_DATA0_10 0 VCC53 DSP1_DATA0_4 VCC53 VSS VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN19 AN18 AN17 AN16 AN15 0 VSS VCC5 - Y Y Y Y Y Y Y Y - - - - Y Y Y Y Y Y Y Y - - - X X W W W W W W W W V V V U - - 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 0 VSS - 203 0 0 P5_12 0 0 0 0 MFS9_CS1 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT0- B 25 138 S AN31 0 AN1(AL1) PWM1M1 OCU9_OTD0 ICU9_IN0 PPG9_TOUT0 EINT10 P3_26 0 0 0 0 0 0 0 0 0 0 0 VSS_LVDS_Tx - 26 137 S AN30 0 AP1(AH1) PWM1P1 OCU8_OTD1 ICU8_IN1 PPG8_TOUT2 EINT9 P3_25 0 0 0 0 0 0 0 0 0 0 0 VCC3_LVDS_Tx - 27 136 S AN29 0 BN0(BL0) PWM2M0 OCU8_OTD0 ICU8_IN0 PPG8_TOUT0 EINT8 P3_24 0 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 28 135 S AN28 0 BP0(BH0) PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 29 134 S AN27 0 AN0(AL0) PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 133 S AN26 0 AP0(AH0) PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 0 132 - DVCC 0 0 0 0 0 0 0 0 0 131 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 30 0 0 0 0 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 DSP0_DATA0_4 MDC CAP0_DATA0 0 DSP0_CTRL1 C 31 DSP0_DATA0_11 0 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK+ DSP0_CLK D 32 DSP0_DATA1_11 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 130 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 129 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 128 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 0 CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 127 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 126 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 125 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 0 CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 39 124 H 0 0 0 0 OCU6_OTD0 ICU6_IN0 PPG6_TOUT0 EINT4 P3_20 0 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 123 H 0 0 SGO3 TIN35 OCU5_OTD1 ICU5_IN1 PPG5_TOUT2 EINT3 P3_19 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 122 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 121 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 120 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_02 EINT3 PPG1_TOUT2 ICU1_IN1 OCU1_OTD1 0 TOT16 COL CAP0_DATA11 DSP0_DATA_D4+ DSP0_DATA0_4 D 44 119 - VCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_03 EINT4 PPG2_TOUT0 ICU2_IN0 OCU2_OTD0 0 TIN16 CRS CAP0_DATA12 DSP0_DATA_D4- DSP0_DATA1_4 D 45 118 Q RSTX 0 0 0 0 0 0 0 0 0 CAP0_DATA11 G_CK_2 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 46 117 P MODE 0 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 47 116 N2 JTAG_TMS 0 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 48 115 N2 JTAG_TCK 0 0 0 0 0 0 0 0 0 CAP0_DATA14 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 49 114 N2 JTAG_TDI 0 0 0 0 0 0 0 0 0 CAP0_DATA15 G_DQ0_2 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 50 113 O JTAG_TDO 0 0 0 0 0 0 0 0 0 0 G_CS#1_2 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 51 112 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 0 G_RWDS_2 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 52 111 M X0 0 0 0 0 0 0 0 0 0 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 53 110 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 54 109 - VSS 0 0 0 0 0 0 0 0 0 TOP VIEW TEQFP-216 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 J J I I I I I J J I I I I I L - AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 SOT0 SCK0 SIN0 0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 0 0 0 0 TIN0 TIN1 TIN2 TIN3 TOT0 TOT1 TOT2 TOT3 SGA1 SGO1 SGA2 SGO2 SGA3 SGO3 SGO0 SGA0 SGA1 SGO1 TOT16 SGO2 TIN17 0 0 SGA0 TIN16 SGA2 0 SGO0 0 0 AIN8 OCU4_OTD0 BIN8 OCU4_OTD1 ZIN8 OCU5_OTD0 0 0 BIN9 OCU7_OTD0 ZIN9 OCU7_OTD1 0 0 0 0 0 0 0 0 OCU6_OTD0 AIN9 OCU6_OTD1 0 OCU5_OTD1 OCU8_OTD0 OCU8_OTD1 OCU9_OTD0 OCU9_OTD1 ICU5_IN0 ICU5_IN1 ICU6_IN0 ICU6_IN1 ICU7_IN0 ICU7_IN1 ICU8_IN0 ICU8_IN1 ICU9_IN0 ICU9_IN1 0 0 0 0 0 0 0 0 0 0 PPG4_TOUT2 PPG5_TOUT0 PPG5_TOUT2 PPG6_TOUT2 PPG7_TOUT0 FRT8/9/10/11_TEXT PPG7_TOUT2 0 PPG4_TOUT0 PPG0/1/2/3/4/5_TIN1 PPG6_TOUT0 OCU11_OTD0 ICU11_IN0 0 0 0 OCU10_OTD1 ICU10_IN1 0 0 ICU4_IN1 0 OCU10_OTD0 ICU10_IN0 0 0 ICU4_IN0 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG9_TOUT2 EINT12 P2_28 0 EINT13 P2_29 0 EINT14 P2_30 0 EINT15 P2_31 0 EINT1 EINT2 EINT3 PPG11_TOUT0 EINT6 0 0 P2_25 0 P3_00 0 P3_01 0 P3_02 0 P3_03 0 P3_04 0 P3_05 0 P3_06 0 0 0 0 0 0 0 0 EINT11 P2_27 INDICATOR0_0 0 EINT0 P2_24 0 EINT10 P2_26 0 PPG10_TOUT2 EINT5 0 EINT9 PPG10_TOUT0 EINT4 0 EINT8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 0 0 0 0 0 0 AN0 0 I 0 92 0 0 0 0 P2_22 0 0 0 0 EINT6 P0_28 0 0 0 PPG3_TOUT0 P0_27 0 0 0 0 0 P0_26 0 0 ICU3_IN0 EINT3 0 G_DQ7_1 0 OCU3_OTD0 0 EINT2 0 0 G_DQ6_1 0 PPG4_TOUT2 0 G_DQ5_1 TIN49 0 0 EINT1 P1_02 M_DQ7_0 G_DQ4_1 0 G_CS#2_1 0 0 0 0 0 P1_00 M_DQ5_0 0 0 0 0 0 P1_01 M_DQ4_0 EINT10 P1_03 M_DQ6_0 EINT9 0 P0_31 M_CS#2_0 0 0 0 EINT7 0 0 0 0 PPG7_TOUT2 EINT8 0 ICU4_IN1 0 PPG8_TOUT0 EINT6 H 0 0 PPG6_TOUT2 0 91 0 0 PPG7_TOUT0 0 0 0 PPG6_TOUT0 0 0 0 0 0 0 SIN1 OCU4_OTD1 ICU7_IN1 0 0 0 SCK1 0 ICU8_IN0 0 0 0 0 SOT1 0 0 0 ICU6_IN1 0 0 G_RWDS_1 0 0 0 G_CS#1_1 0 0 0 0 0 OCU7_OTD1 ICU7_IN0 G_DQ0_1 0 0 0 0 OCU8_OTD0 ICU6_IN0 G_DQ1_1 0 0 0 0 OCU6_OTD1 0 0 G_DQ2_1 0 0 0 0 0 OCU7_OTD0 0 G_DQ3_1 DSP0_CTRL1 0 0 0 0 OCU6_OTD0 P0_30 M_RWDS_0 0 DSP0_CTRL0 0 0 0 0 0 0 0 0 DSP0_CLK 0 0 0 0 0 EINT5 G_CK_1 DSP0_CTRL2 0 CRS 0 0 0 0 0 0 0 0 0 0 0 EINT11 P1_04 M_DQ0_0 0 0 0 0 0 0 0 EINT13 P1_06 M_DQ1_0 0 0 0 0 0 0 0 PPG5_TOUT2 EINT12 P1_05 M_DQ3_0 PPG10_TOUT2 EINT15 P1_08 M_CS#1_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1_09 M_CK_0 G_DQ7_2 0 0 0 0 ICU5_IN1 0 0 G_DQ6_2 0 CAP0_DATA25 0 0 0 0 0 0 0 0 0 G_DQ5_2 0 0 0 CAP0_DATA24 0 0 0 0 OCU5_OTD1 0 P5_22 0 G_DQ4_2 0 DSP0_CTRL4 0 0 0 0 PPG8_TOUT2 0 P0_17 0 PPG10_TOUT0 EINT14 P1_07 M_DQ2_0 PPG9_TOUT2 0 P0_16 0 0 0 DSP0_CTRL3 0 0 0 0 OCU10_OTD1 ICU10_IN1 0 PPG9_TOUT0 EINT2 P0_15 0 0 VCC12 DSP0_CTRL2 0 0 0 0 0 EINT1 PPG11_TOUT0 EINT0 0 EINT0 0 MLBCLK 0 0 0 0 0 ICU8_IN1 0 0 EINT15 P0_14 0 PPG10_TOUT0 EINT4 0 EINT14 P0_13 0 0 MLBSIG 0 0 0 0 0 OCU8_OTD1 ICU9_IN1 PPG9_TOUT0 EINT13 P0_12 0 0 - MLBDAT G_SDATA0_3 0 0 0 0 OCU10_OTD0 ICU10_IN0 0 OCU9_OTD1 0 PPG8_TOUT2 0 0 F VCC3 G_SSEL0 0 0 0 0 ICU9_IN0 0 PPG8_TOUT0 0 F VSS G_SDATA0_1 0 0 0 0 0 OCU9_OTD0 0 0 PPG7_TOUT2 0 F M_SDATA1_3 G_SDATA0_2 0 0 0 0 0 0 PPG7_TOUT0 PSC_1 - M_SSEL1 G_SDATA0_0 0 0 0 0 0 0 0 OCU11_OTD0 ICU11_IN0 0 0 0 0 PPG6_TOUT2 VCC5 87 - M_SDATA1_1 0 0 0 0 0 0 0 0 0 G 86 E M_SDATA1_2 0 0 0 0 0 0 0 - 85 E M_SDATA1_0 0 0 0 0 0 0 0 90 84 E VCC3 0 0 0 0 0 0 0 0 89 83 E G_SCLK0 0 0 0 0 0 ICU9_IN0 0 0 82 E VSS 0 0 0 0 0 ICU8_IN1 0 0 81 - 0 G_SDATA1_3 0 0 0 0 ICU8_IN0 0 80 - VSS G_SSEL1 0 0 0 ICU7_IN1 OCU10_OTD0 ICU10_IN0 0 0 ICU7_IN0 0 79 E M_SDATA0_3 G_SDATA1_1 0 0 0 OCU9_OTD0 ICU6_IN1 0 78 - M_SSEL0 G_SDATA1_2 0 0 OCU8_OTD1 0 0 77 E M_SDATA0_1 G_SDATA1_0 0 0 0 OCU8_OTD0 0 76 E M_SDATA0_2 0 0 0 OCU7_OTD1 0 75 E M_SDATA0_0 0 0 0 0 OCU7_OTD0 0 74 E VCC3 0 0 0 0 OCU6_OTD1 0 73 E VSS 0 0 0 0 0 0 72 - M_SCLK0 0 TXER TIN35 I2S1_SCK 0 0 71 - VSS 0 CAP0_DATA34 0 TOT35 I2S1_WS 0 0 70 E VCC12 DSP0_CTRL2 0 0 0 69 - DSP0_CTRL0 COL 0 0 68 - DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK RXCLK TIN33 I2S0_SCK DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 I2S1_SD DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 TXCLK TOT33 I2S0_WS DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 VSS 67 C DSP0_DATA1_9 DSP0_DATA_D9- - 66 D DSP0_DATA0_9 DSP0_DATA_D9+ CAP0_DATA21 0 88 65 D VCC3 0 CAP0_DATA22 0 0 0 64 D 0 63 D 0 0 62 D 0 61 D 0 60 - 0 59 0 58 0 57 0 56 0 55 Page 24 of 222 Document Number: 002-05682 Rev. *K Condition on PCB Set to ground Package Pin Number 12 to 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP0_DATA1_10 0 0 0 0 0 0 P3_27 0 0 PPG9_TOUT2 EINT11 0 0 0 OCU9_OTD1 ICU9_IN1 0 0 PWM2P1 0 204 BP1(BH1) 0 Y 0 0 DSP1_DATA1_3 AN32 0 0 S 0 DSP0_CTRL0 139 0 0 24 0 0 B 0 BIN9 TxDOUT0+ 0 0 ICU10_IN1 OCU10_OTD1 0 0 EINT13 PPG10_TOUT2 0 0 SEG7 0 0 P5_13 0 0 0 0 0 0 0 0 0 205 0 0 Y 0 0 0 DSP1_DATA0_3 0 P3_28 0 0 0 0 DSP0_CTRL1 0 PPG10_TOUT0 EINT12 0 0 SOT11 0 0 ZIN9 0 OCU10_OTD0ICU10_IN0 0 0 ICU11_IN0 OCU11_OTD0 0 PWM2M1 0 EINT14 PPG11_TOUT0 0 BN1(BL1) 0 SEG6 0 0 0 P5_14 0 AN33 0 MFS8_CS3 0 DVSS S 0 0 140 0 206 141 23 0 207 22 B 0 Y B TxDOUT1- 0 Y TxDOUT1+ 0 0 DSP1_DATA1_2 0 0 0 DSP1_DATA0_2 0 0 0 0 DSP1_CLK 0 0 0 0 DSP0_CTRL2 DSP1_CTRL2 0 0 0 0 DSP0_CTRL3 0 0 0 0 SIN11 0 0 0 0 0 SCK11 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU0_OTD0 0 0 ICU0_IN0 0 0 0 ICU11_IN1 OCU11_OTD1 0 0 0 0 0 PPG0_TOUT0 0 0 EINT0 DVCC 0 EINT15 PPG11_TOUT2 0 SEG5 142 0 SEG4 21 0 P5_15 B 0 P5_16 TxCLK0 MFS8_CS1 0 0 0 MFS8_CS2 0 0 0 0 0 0 0 0 0 208 0 0 Y 0 0 0 DSP1_DATA1_1 P3_29 0 DSP0_CTRL4 DSP1_CTRL0 PPG10_TOUT2 EINT13 0 0 OCU10_OTD1ICU10_IN1 0 0 PWM1P2 0 0 0 0 OCU0_OTD1 0 0 ICU0_IN1 AN34 0 0 S 0 0 PPG0_TOUT2 143 0 0 0 EINT1 20 0 0 0 0 SEG3 B 0 0 0 0 0 P5_17 TxCLK+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 209 0 0 0 0 0 0 0 Y 0 0 0 0 0 0 0 DSP1_DATA0_1 0 0 0 0 0 0 0 0 DSP0_CTRL5 DSP1_CTRL1 0 P3_30 0 0 0 0 0 0 0 SOT12 0 P3_31 PPG11_TOUT0 EINT14 0 0 0 0 0 0 0 P4_00 PPG11_TOUT2 EINT15 OCU11_OTD0ICU11_IN0 0 0 0 0 OCU1_OTD0 0 P4_01 PPG0_TOUT0 EINT0 OCU11_OTD1ICU11_IN1 PWM1M2 0 0 0 ICU1_IN0 0 P4_02 PPG0_TOUT2 EINT1 OCU0_OTD0 ICU0_IN0 PWM2P2 0 0 0 0 P4_03 PPG1_TOUT0 EINT2 OCU0_OTD1 ICU0_IN1 PWM2M2 0 0 0 PPG1_TOUT0 PPG1_TOUT2 EINT3 OCU1_OTD0 ICU1_IN0 PWM1P3 0 0 AN35 0 EINT2 OCU1_OTD1 ICU1_IN1 PWM1M3 0 0 AN36 S 0 SEG2 PWM2P3 0 0 AN37 S 144 0 P5_18 0 SOT2 AN38 S 145 19 0 MFS12_SDA 0 SCK2 AN39 S 146 18 B 0 0 AN40 S 147 17 B TxDOUT20 210 S 148 16 B TxDOUT2+ 0 0 211 149 15 B TxDOUT3- 0 0 0 Y 14 - TxDOUT3+ 0 0 0 0 Y - VSS_LVDS_Tx 0 0 0 0 0 DSP1_DATA1_0 VCC3_LVDS_Tx 0 0 0 0 0 DSP1_DATA0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP0_CTRL6 0 0 DSP0_CTRL7 0 0 SIN12 P4_04 0 0 SCK12 PPG2_TOUT0 EINT4 0 0 OCU2_OTD0 ICU2_IN0 0 0 PWM2M3 0 0 0 0 OCU1_OTD1 SIN2 0 OCU2_OTD0 AN41 0 ICU1_IN1 S 0 ICU2_IN0 150 0 0 13 0 0 0 PPG1_TOUT2 AVCC3_LVDS_PLL 0 PPG2_TOUT0 0 0 0 EINT3 0 0 0 EINT4 0 0 0 SEG1 0 0 0 SEG0 0 0 0 P5_19 0 0 0 P5_20 0 0 0 0 0 0 0 0 MFS12_SCL 0 0 0 0 0 0 0 0 0 0 0 0 212 0 0 0 213 DVSS 0 0 214 - 0 0 215 151 0 216 12 0 - 0 Y AVSS_LVDS_PLL 0 Y 0 0 Y 0 0 Y 0 0 VCC53 0 0 DSP1_CLK 0 0 DSP1_CTRL2 0 0 0 DSP1_CTRL1 P4_05 0 0 DSP1_CTRL0 PPG2_TOUT2 EINT5 0 0 0 OCU2_OTD1 ICU2_IN1 0 0 0 PWM1P4 0 0 0 0 0 0 0 0 DVCC 0 0 AN42 - 0 0 S 152 C_L DSP0_CTRL8 153 11 0 DSP0_CTRL9 10 0 0 0 - VCC12 0 SIN11 DSP0_CTRL11 VSS 0 0 0 0 0 0 0 SOT11 MFS0_CS0 0 0 SCK11 DSP0_CTRL10 P4_06 0 0 PPG3_TOUT0 EINT6 0 0 OCU3_OTD0 ICU3_IN0 0 0 PWM1M4 0 0 0 0 0 SOT3 0 0 AN43 0 OCU0_OTD1 S 0 OCU1_OTD0 SGA1 154 0 OCU1_OTD1 SGO1 9 0 OCU2_OTD0 - A 0 0 AVSS - DAC_L ICU0_IN1 MFS2_CS0 AVCC3_DAC 0 ICU1_IN0 P4_07 0 0 ICU1_IN1 PPG3_TOUT2 EINT7 0 0 ICU2_IN0 OCU3_OTD1 ICU3_IN1 0 0 0 PWM2P4 0 0 0 0 0 0 0 SCK3 0 0 0 AN44 0 0 0 S 0 0 0 155 0 0 PPG0_TOUT2 8 0 0 PPG1_TOUT0 0 A 0 0 PPG1_TOUT2 0 MFS2_CS1 0 0 PPG2_TOUT0 0 P4_08 0 0 0 P4_09 PPG4_TOUT0 EINT8 0 0 EINT9 PPG4_TOUT2 EINT9 OCU4_OTD0 ICU4_IN0 0 0 EINT10 OCU4_OTD1 ICU4_IN1 PWM2M4 0 EINT11 PWM1P5 0 5 EINT12 0 SIN3 4 VSS 0 0 AN45 3 A AVSS COM3 AN46 S 2 A C_R 0 COM2 S 156 - DAC_R 0 0 COM1 MFS4_SDA 157 7 1 AVSS 0 0 0 COM0 MFS4_SCL MFS0_CS3 6 - 0 0 0 0 0 0 MFS0_CS1 P4_10 0 0 0 0 0 P4_25 MFS0_CS2 P4_11 0 0 0 0 0 P4_26 0 P4_12 PPG5_TOUT0 EINT10 0 0 0 0 0 P4_27 0 0 PPG5_TOUT2 EINT11 0 0 0 0 0 P4_28 0 0 PPG6_TOUT0 EINT12 OCU5_OTD0 ICU5_IN0 0 0 0 0 0 0 0 0 0 OCU5_OTD1 ICU5_IN1 PWM1M5 0 0 0 0 0 0 0 0 0 OCU6_OTD0 ICU6_IN0 PWM2P5 0 0 0 0 0 0 0 0 0 0 PWM2M5 RX1 SOT4 0 0 0 0 0 0 0 0 0 TX1 SCK4 AN47 0 0 0 0 0 0 0 0 0 SIN4 AN48 S 0 0 0 0 0 0 0 0 AN49 S 158 0 0 0 0 0 0 0 DVSS S 159 0 0 0 0 0 0 DVCC 160 0 0 0 0 0 161 0 0 0 0 Any function at the following pins is not supported. - 162 0 0 0 Notes: - The pins highlighted in "red" font are not supported for products with revision A and C. S6J3200 Series Figure 4-4: TEQFP-216 (S6J326CLxx, S6J32LELxx) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDICATOR0_1 0 0 0 MFS8_CS2 0 MFS8_CS1 0 MFS8_CS3 0 MFS9_CS1 0 MFS9_CS0 0 MFS8_CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_10 P5_09 P5_08 P5_07 P5_06 P5_05 0 0 0 0 P5_04 P5_03 P5_02 P5_01 P5_00 P4_31 P4_30 P4_29 0 0 0 P2_16 P2_17 P3_17 P3_16 P3_15 P3_14 P3_13 P3_12 P3_11 P3_10 P3_09 P3_08 P3_07 P2_19 0 0 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 0 0 0 0 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 0 0 0 0 0 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 V0 V1 V2 V3 0 0 EINT10 EINT9 EINT8 EINT7 EINT6 EINT5 0 0 0 0 EINT4 EINT3 EINT2 EINT1 EINT0 EINT15 EINT14 EINT13 0 0 0 EINT0 EINT1 EINT1 EINT0 EINT15 EINT14 EINT13 EINT12 EINT11 EINT10 EINT9 EINT8 0 0 PPG8_TOUT2 PPG8_TOUT0 PPG7_TOUT2 PPG7_TOUT0 PPG6_TOUT2 0 0 0 0 PPG6_TOUT0 PPG5_TOUT2 PPG5_TOUT0 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 0 0 0 PPG0_TOUT0 PPG0_TOUT2 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 PPG2_TOUT0 PPG1_TOUT2 PPG1_TOUT0 PPG0_TOUT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN48 0 0 ICU9_IN0 ICU8_IN1 ICU8_IN0 ICU7_IN1 ICU7_IN0 ICU6_IN1 0 0 0 0 ICU6_IN0 ICU5_IN1 ICU5_IN0 ICU4_IN1 ICU4_IN0 ICU3_IN1 ICU3_IN0 ICU2_IN1 0 0 0 ICU0_IN0 ICU0_IN1 ICU4_IN1 ICU4_IN0 FRT4/5/6/7_TEXT ICU3_IN1 PPG0_TOUT0 PPG6/7/8/9/10/11_TIN EINT7 PPG11_TOUT2 EINT3 PPG9_TOUT0 ICU3_IN0 ICU2_IN1 ICU2_IN0 ICU1_IN1 ICU1_IN0 ICU0_IN1 ICU0_IN0 ICU1_IN1 0 0 OCU9_OTD0 BIN8 OCU8_OTD1 OCU8_OTD0 OCU7_OTD1 OCU7_OTD0 OCU6_OTD1 0 0 0 0 OCU6_OTD0 OCU5_OTD1 OCU5_OTD0 OCU4_OTD1 OCU4_OTD0 0 0 OCU0_OTD0 OCU0_OTD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN18 OCU0_OTD0 WOT TOT18 0 0 0 TOT19 0 0 0 TIN19 0 0 0 0 0 SOT9 0 0 0 0 0 SIN8 SCK8 SOT8 0 0 0 0 0 0 0 0 0 0 OCU2_OTD0 SGO0 TOT32 SOT10 0 0 0 OCU2_OTD1 SGA0 TIN32 SCK10 0 0 0 SIN9 SCK9 OCU3_OTD0 SGA1 TOT33 SIN10 0 0 0 OCU3_OTD1 SGO1 TIN33 SOT11 OCU0_OTD1 0 0 0 OCU4_OTD0 SGA2 TOT34 SCK11 OCU1_OTD0 0 0 OCU4_OTD1 SGO2 TIN34 SIN11 OCU1_OTD1 0 OCU3_OTD0 SGA3 0 0 OCU3_OTD1 SGO3 OCU2_OTD1 AIN8 0 SOT10 0 0 SIN9 SCK9 SOT9 0 0 0 0 0 0 0 0 0 0 0 0 0 BN1(BL1) BP1(BH1) AN1(AL1) AP1(AH1) BN0(BL0) BP0(BH0) AN0(AL0) AP0(AH0) 0 0 0 0 0 TX6 RX6 TX5 RX5 0 0 TX6 RX6 TX5 RX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_DATA0_6 DSP1_DATA1_6 DSP1_DATA0_7 DSP1_DATA1_7 VCC53 VSS VCC12 VCC12 DSP1_DATA0_8 DSP1_DATA1_8 DSP1_DATA0_9 DSP1_DATA1_9 0 DSP1_DATA1_11 0 DSP1_DATA1_5 0 DSP1_DATA0_11 0 DSP1_DATA0_5 0 DSP1_DATA1_10 0 DSP1_DATA1_4 0 DSP1_DATA0_10 0 DSP1_DATA0_4 VCC53 VSS VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN19 AN18 AN17 AN16 AN15 0 VSS VCC5 Y Y Y Y Y Y Y Y - - - - Y Y Y Y Y Y Y Y - - - X X W W W W W W W W V V V U - - 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 0 TOT17 0 MFS8_CS0 0 0 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 MFS10_SDA 0 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 D D D D C - - E - - E E E E E - E - - E E E E E - - F F F - - - G H I J J I I I I I J J I I I I I L - VCC3 DSP0_DATA0_9 DSP0_DATA_D9+ CAP0_DATA21 0 DSP0_DATA1_9 DSP0_DATA_D9- DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK DSP0_CTRL0 VCC12 VSS M_SCLK0 VSS VCC3 M_SDATA0_0 M_SDATA0_2 M_SDATA0_1 M_SSEL0 M_SDATA0_3 VSS 0 VSS VCC3 M_SDATA1_0 M_SDATA1_2 M_SDATA1_1 M_SSEL1 M_SDATA1_3 VSS VCC3 MLBDAT MLBSIG MLBCLK VCC12 VSS VCC5 PSC_1 0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 DSP0_CTRL2 0 0 0 0 0 G_SDATA1_0 G_SDATA1_2 G_SDATA1_1 G_SSEL1 G_SDATA1_3 0 G_SCLK0 0 0 G_SDATA0_0 G_SDATA0_2 G_SDATA0_1 G_SSEL0 G_SDATA0_3 0 0 DSP0_CTRL2 DSP0_CTRL3 DSP0_CTRL4 0 0 0 0 0 0 SOT0 SCK0 SIN0 0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 CAP0_DATA34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0_DATA25 0 0 0 CAP0_DATA24 0 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 RXCLK TIN33 I2S0_SCK DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 I2S1_SD DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 TXCLK TOT33 I2S0_WS COL 0 TXER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 TOT35 I2S1_WS TIN35 I2S1_SCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN0 TIN1 TIN2 TIN3 TOT0 TOT1 TOT2 TOT3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGO0 SGA0 SGA1 SGO1 SGA2 SGO2 SGA3 SGO3 SGO0 SGA0 SGA1 SGO1 TOT16 SGO2 TIN17 0 0 0 TIN16 SGA2 0 0 TIN49 0 0 0 0 0 0 0 0 DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU9_OTD0 OCU8_OTD1 OCU5_OTD1 0 0 OCU6_OTD0 OCU7_OTD0 OCU6_OTD1 OCU8_OTD0 OCU7_OTD1 0 0 0 0 0 0 OCU3_OTD0 OCU5_OTD1 OCU6_OTD0 OCU8_OTD0 OCU8_OTD1 OCU9_OTD0 OCU9_OTD1 ICU8_IN1 ICU9_IN0 0 0 0 0 ICU9_IN0 ICU9_IN1 ICU8_IN1 0 ICU5_IN1 0 0 ICU6_IN0 ICU7_IN0 ICU6_IN1 ICU8_IN0 ICU7_IN1 0 0 0 0 ICU4_IN1 0 0 0 0 ICU3_IN0 ICU4_IN0 ICU4_IN1 ICU5_IN0 ICU5_IN1 ICU6_IN0 ICU6_IN1 ICU7_IN0 ICU7_IN1 ICU8_IN0 ICU8_IN1 ICU9_IN0 ICU9_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPG6_TOUT2 PPG7_TOUT0 PPG7_TOUT2 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 0 0 0 PPG9_TOUT0 PPG8_TOUT2 PPG5_TOUT2 0 0 PPG6_TOUT0 PPG7_TOUT0 PPG6_TOUT2 PPG8_TOUT0 PPG7_TOUT2 0 0 0 0 PPG4_TOUT2 0 0 0 0 PPG3_TOUT0 PPG4_TOUT0 PPG4_TOUT2 PPG5_TOUT0 PPG5_TOUT2 PPG6_TOUT2 PPG7_TOUT0 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG9_TOUT2 EINT1 EINT2 0 0 0 0 0 0 EINT6 EINT8 EINT7 0 0 EINT1 EINT2 EINT3 0 0 0 0 EINT6 EINT8 EINT9 0 P0_30 M_RWDS_0 0 0 P1_00 M_DQ5_0 P1_02 M_DQ7_0 P0_28 0 0 0 0 0 0 P2_24 0 P2_25 0 P3_00 0 P3_01 0 P3_02 0 P3_03 0 P3_04 0 P3_05 0 P3_06 0 0 0 P2_22 0 0 0 P0_27 0 0 0 P0_26 0 0 0 P1_01 M_DQ4_0 0 0 P0_31 M_CS#2_0 0 0 EINT15 P2_31 0 0 0 0 EINT14 P2_30 0 PPG11_TOUT0 EINT6 0 EINT13 P2_29 0 EINT3 P1_09 M_CK_0 0 0 EINT12 P2_28 0 EINT2 0 0 0 0 0 G_DQ4_2 G_DQ5_2 G_DQ6_2 G_DQ7_2 0 0 0 0 0 G_CK_1 0 0 G_DQ3_1 G_DQ2_1 G_DQ1_1 G_DQ0_1 0 0 G_DQ5_1 G_DQ6_1 G_DQ7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP0_CTRL2 DSP0_CLK DSP0_CTRL0 DSP0_CTRL1 0 0 0 0 0 0 0 0 0 0 0 G_CS#2_1 0 G_DQ4_1 0 G_RWDS_1 0 0 0 G_CS#1_1 0 EINT11 P2_27 INDICATOR0_0 0 EINT1 0 EINT10 P2_26 0 EINT0 P5_22 0 EINT10 P1_03 M_DQ6_0 EINT9 P0_17 0 EINT11 P1_04 M_DQ0_0 EINT5 P0_16 0 EINT13 P1_06 M_DQ1_0 0 P0_15 0 EINT12 P1_05 M_DQ3_0 PPG10_TOUT2 EINT5 0 EINT0 PPG10_TOUT0 EINT4 0 EINT15 P0_14 0 PPG10_TOUT2 EINT15 P1_08 M_CS#1_0 0 EINT14 P0_13 0 PPG10_TOUT0 EINT14 P1_07 M_DQ2_0 PPG9_TOUT2 EINT13 P0_12 0 PPG11_TOUT0 EINT0 0 0 PPG10_TOUT0 EINT4 FRT8/9/10/11_TEXT PPG7_TOUT2 0 0 PPG0/1/2/3/4/5_TIN1 PPG6_TOUT0 OCU11_OTD0 ICU11_IN0 0 0 0 OCU10_OTD1 ICU10_IN1 0 0 ICU8_IN0 OCU10_OTD0 ICU10_IN0 0 0 ICU7_IN1 OCU10_OTD1 ICU10_IN1 0 0 ICU7_IN0 OCU10_OTD0 ICU10_IN0 0 OCU9_OTD1 ICU6_IN1 OCU11_OTD0 ICU11_IN0 0 ZIN9 OCU7_OTD1 0 0 BIN9 OCU7_OTD0 0 0 0 OCU10_OTD0 ICU10_IN0 0 AIN9 OCU6_OTD1 0 OCU9_OTD0 ZIN8 OCU5_OTD0 0 OCU8_OTD1 BIN8 OCU4_OTD1 0 OCU8_OTD0 AIN8 OCU4_OTD0 0 OCU7_OTD1 SIN1 OCU4_OTD1 0 OCU7_OTD0 SCK1 0 0 OCU6_OTD1 SOT1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 CAP0_DATA22 0 0 0 0 62 D 0 61 D 0 60 - 0 59 0 58 0 57 0 56 0 55 Page 25 of 222 Document Number: 002-05682 Rev. *K 0 SCK10 0 0 0 P0_03 EINT4 PPG2_TOUT0 ICU2_IN0 OCU2_OTD0 0 TIN16 CRS CAP0_DATA12 DSP0_DATA_D4- DSP0_DATA1_4 D 45 118 Q RSTX 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 46 117 P MODE 0 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 47 116 N2 JTAG_TMS 0 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 48 115 N2 JTAG_TCK 0 0 0 0 0 0 0 0 0 CAP0_DATA14 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 49 114 N2 JTAG_TDI 0 0 0 0 0 0 0 0 0 CAP0_DATA15 G_DQ0_2 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 50 113 O JTAG_TDO 0 0 0 0 0 0 0 0 0 0 G_CS#1_2 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 51 112 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 0 G_RWDS_2 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 52 111 M X0 0 0 0 0 0 0 0 0 0 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 53 110 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 54 109 - VSS 0 0 0 0 0 0 0 0 0 0 0 SIN10 0 0 ZIN8 0 G_CK_2 0 AIN9 0 CAP0_DATA11 0 OCU9_OTD1 PPG8_TOUT0 EINT8 P3_24 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 28 135 S AN28 0 BP0(BH0) PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 29 134 S AN27 0 AN0(AL0) PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 30 133 S AN26 0 AP0(AH0) PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 0 0 0 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 DSP0_DATA0_4 MDC CAP0_DATA0 0 DSP0_CTRL1 C 31 132 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK+ DSP0_CLK D 32 131 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 130 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 129 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 128 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 0 CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 127 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 126 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 125 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 0 CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 39 124 H 0 0 0 0 OCU6_OTD0 ICU6_IN0 PPG6_TOUT0 EINT4 P3_20 0 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 123 H 0 0 SGO3 TIN35 OCU5_OTD1 ICU5_IN1 PPG5_TOUT2 EINT3 P3_19 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 122 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 121 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 120 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_02 EINT3 PPG1_TOUT2 ICU1_IN1 OCU1_OTD1 0 TOT16 COL CAP0_DATA11 DSP0_DATA_D4+ DSP0_DATA0_4 D 44 119 - VCC5 0 0 0 0 0 0 0 0 0 0 ICU9_IN1 OCU8_OTD0 ICU8_IN0 0 0 PWM2M0 0 0 ICU10_IN0 OCU10_OTD0 BN0(BL0) 0 PPG9_TOUT2 0 DSP0_DATA1_11 EINT11 AN29 0 EINT12 PPG10_TOUT0 S 0 SEG9 136 DSP0_DATA0_11 SEG8 27 0 P5_11 - 0 P5_12 VCC3_LVDS_Tx 0 MFS9_CS0 0 0 DSP0_DATA1_10 MFS9_CS1 0 0 0 0 0 0 MFS10_SCL 0 0 202 0 0 - 0 0 VCC53 0 0 0 0 0 0 0 0 0 0 0 P3_25 0 0 P3_26 PPG8_TOUT2 EINT9 0 0 PPG9_TOUT0 EINT10 OCU8_OTD1 ICU8_IN1 0 0 OCU9_OTD0 ICU9_IN0 PWM1P1 0 0 PWM1M1 AP1(AH1) 0 0 AN1(AL1) 0 0 0 0 AN30 0 0 AN31 S 0 0 S 137 TOP VIEW TEQFP-216 0 0 138 26 0 0 0 25 - 0 0 B VSS_LVDS_Tx 0 203 TxDOUT0- 0 0 - 0 0 0 VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P3_27 0 0 PPG9_TOUT2 EINT11 0 0 OCU9_OTD1 ICU9_IN1 0 0 PWM2P1 0 0 BP1(BH1) 0 0 0 0 0 0 AN32 0 0 S 0 204 139 0 205 24 0 Y B 0 Y TxDOUT0+ 0 DSP1_DATA1_3 0 0 DSP1_DATA0_3 0 0 0 0 0 0 0 0 DSP0_CTRL0 0 0 DSP0_CTRL1 0 0 0 0 0 0 0 P3_28 0 0 SOT11 PPG10_TOUT0 EINT12 0 ZIN9 OCU10_OTD0ICU10_IN0 0 0 ICU10_IN1 OCU10_OTD1 BIN9 PWM2M1 0 0 ICU11_IN0 OCU11_OTD0 BN1(BL1) 0 EINT13 PPG10_TOUT2 0 0 EINT14 PPG11_TOUT0 AN33 0 SEG7 S 0 0 SEG6 140 0 0 P5_13 23 0 0 P5_14 B 0 0 0 0 TxDOUT10 0 MFS8_CS3 0 0 0 0 0 0 0 0 0 0 0 0 206 0 0 0 Y 0 0 0 DSP1_DATA1_2 0 0 0 DSP0_CTRL2 DSP1_CTRL2 0 0 0 0 SCK11 0 0 0 0 0 0 0 0 ICU11_IN1 OCU11_OTD1 0 0 0 EINT15 PPG11_TOUT2 0 0 0 SEG5 0 0 0 P5_15 0 0 0 MFS8_CS1 0 0 0 0 0 0 DVSS 0 207 DVCC - 0 Y 141 0 DSP1_DATA0_2 142 22 0 DSP1_CLK 21 B 0 DSP0_CTRL3 B TxDOUT1+ 0 0 SIN11 TxCLK- 0 0 0 0 0 0 OCU0_OTD0 0 0 0 ICU0_IN0 0 0 0 0 0 0 0 PPG0_TOUT0 0 0 0 EINT0 P3_29 0 SEG4 PPG10_TOUT2 EINT13 0 P5_16 OCU10_OTD1ICU10_IN1 0 MFS8_CS2 0 PWM1P2 0 0 0 0 208 0 0 209 AN34 0 0 Y S 0 0 0 Y 143 0 0 0 0 DSP1_DATA1_1 20 0 0 0 0 0 DSP1_DATA0_1 B 0 0 0 0 0 DSP0_CTRL4 DSP1_CTRL0 TxCLK+ 0 0 0 0 0 DSP0_CTRL5 DSP1_CTRL1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOT12 0 0 0 0 0 0 0 0 P3_30 0 0 0 0 0 0 PPG11_TOUT0 EINT14 0 0 0 0 0 OCU0_OTD1 OCU11_OTD0ICU11_IN0 0 0 0 0 0 OCU1_OTD0 PWM1M2 0 0 0 0 ICU0_IN1 0 0 0 0 ICU1_IN0 0 0 0 0 AN35 0 0 S 0 PPG0_TOUT2 144 0 0 PPG1_TOUT0 19 0 0 EINT1 B 0 0 EINT2 TxDOUT20 0 SEG3 0 0 0 SEG2 0 0 0 P5_17 0 0 0 0 P5_18 0 P3_31 0 0 0 0 0 P4_00 PPG11_TOUT2 EINT15 0 0 MFS12_SDA 0 0 P4_01 PPG0_TOUT0 EINT0 OCU11_OTD1ICU11_IN1 0 0 0 0 P4_02 PPG0_TOUT2 EINT1 OCU0_OTD0 ICU0_IN0 PWM2P2 0 0 0 P4_03 PPG1_TOUT0 EINT2 OCU0_OTD1 ICU0_IN1 PWM2M2 0 0 0 210 PPG1_TOUT2 EINT3 OCU1_OTD0 ICU1_IN0 PWM1P3 0 0 0 0 Y OCU1_OTD1 ICU1_IN1 PWM1M3 0 0 AN36 0 0 DSP1_DATA1_0 PWM2P3 0 0 AN37 S 0 0 0 SOT2 AN38 S 145 0 DSP0_CTRL6 SCK2 AN39 S 146 18 0 0 SCK12 AN40 S 147 17 B 0 0 S 148 16 B TxDOUT2+ 0 OCU1_OTD1 149 15 B TxDOUT3- 0 0 ICU1_IN1 14 - TxDOUT3+ 0 0 0 0 - VSS_LVDS_Tx 0 0 0 PPG1_TOUT2 VCC3_LVDS_Tx 0 0 0 EINT3 0 0 0 SEG1 0 0 P5_19 0 0 MFS12_SCL 0 0 P4_04 0 0 0 0 211 0 PPG2_TOUT0 EINT4 0 Y 0 0 DSP1_DATA0_0 0 OCU2_OTD0 ICU2_IN0 0 0 0 PWM2M3 0 DSP0_CTRL7 0 0 0 0 SIN12 0 SIN2 0 0 0 AN41 0 OCU2_OTD0 DVSS S 0 ICU2_IN0 150 0 0 151 13 0 PPG2_TOUT0 12 0 EINT4 - AVCC3_LVDS_PLL 0 SEG0 AVSS_LVDS_PLL 0 0 P5_20 0 0 0 0 0 0 0 0 0 212 0 0 213 0 0 214 0 0 215 0 0 216 0 0 0 - 0 0 0 Y 0 0 0 Y DVCC 0 0 Y - 0 0 Y 152 0 0 VCC53 11 0 0 DSP1_CLK 0 0 DSP1_CTRL2 VCC12 0 0 DSP1_CTRL1 0 0 0 DSP1_CTRL0 P4_05 0 0 0 PPG2_TOUT2 EINT5 0 0 0 OCU2_OTD1 ICU2_IN1 0 0 0 PWM1P4 0 0 0 0 0 0 0 0 0 0 AN42 DAC_L DSP0_CTRL8 S 0 DSP0_CTRL9 153 0 0 0 10 0 0 0 0 SOT11 0 VSS 0 0 SCK11 DSP0_CTRL10 0 MFS0_CS0 0 0 SIN11 DSP0_CTRL11 MFS2_CS0 P4_06 0 0 P4_07 PPG3_TOUT0 EINT6 0 0 PPG3_TOUT2 EINT7 OCU3_OTD0 ICU3_IN0 0 0 OCU3_OTD1 ICU3_IN1 PWM1M4 0 0 PWM2P4 0 0 0 0 SOT3 0 OCU0_OTD1 SCK3 AN43 0 OCU1_OTD0 SGA1 AN44 S 0 OCU1_OTD1 SGO1 S 154 0 OCU2_OTD0 155 9 0 0 8 - ICU0_IN1 A AVCC3_DAC ICU1_IN0 0 C_L AVSS 0 ICU1_IN1 MFS2_CS1 0 ICU2_IN0 P4_08 0 0 PPG4_TOUT0 EINT8 0 0 OCU4_OTD0 ICU4_IN0 0 0 PWM2M4 0 0 0 0 0 SIN3 0 0 AN45 0 PPG0_TOUT2 S 0 PPG1_TOUT0 156 0 PPG1_TOUT2 0 7 0 PPG2_TOUT0 0 A 0 0 P4_09 0 EINT9 PPG4_TOUT2 EINT9 0 EINT10 OCU4_OTD1 ICU4_IN1 0 EINT11 PWM1P5 5 EINT12 0 4 VSS 0 0 3 A AVSS COM3 AN46 2 A C_R 0 COM2 S - DAC_R 0 0 COM1 MFS4_SDA 157 1 AVSS 0 0 0 COM0 MFS4_SCL MFS0_CS3 6 - 0 0 0 0 0 0 MFS0_CS1 P4_10 0 0 0 0 0 P4_25 MFS0_CS2 P4_11 0 0 0 0 0 P4_26 0 P4_12 PPG5_TOUT0 EINT10 0 0 0 0 0 P4_27 0 0 PPG5_TOUT2 EINT11 0 0 0 0 0 P4_28 0 0 PPG6_TOUT0 EINT12 OCU5_OTD0 ICU5_IN0 0 0 0 0 0 0 0 0 0 OCU5_OTD1 ICU5_IN1 PWM1M5 0 0 0 0 0 0 0 0 0 OCU6_OTD0 ICU6_IN0 PWM2P5 0 0 0 0 0 0 0 0 0 0 PWM2M5 RX1 SOT4 0 0 0 0 0 0 0 0 0 TX1 SCK4 AN47 0 0 0 0 0 0 0 0 0 SIN4 AN48 S 0 0 0 0 0 0 0 0 AN49 S 158 0 0 0 0 0 0 0 DVSS S 159 0 0 0 0 0 0 DVCC 160 0 0 0 0 0 161 0 0 0 0 162 0 0 0 S6J3200 Series Figure 4-5: TEQFP-216 (S6J325CLxx, S6J32NELxx) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDICATOR0_1 0 0 0 MFS8_CS2 0 MFS8_CS1 0 MFS8_CS3 0 MFS9_CS1 0 MFS9_CS0 0 MFS8_CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_10 P5_09 P5_08 P5_07 P5_06 P5_05 0 0 0 0 P5_04 P5_03 P5_02 P5_01 P5_00 P4_31 P4_30 P4_29 0 0 0 P2_16 P2_17 P3_17 P3_16 P3_15 P3_14 P3_13 P3_12 P3_11 P3_10 P3_09 P3_08 P3_07 P2_19 0 0 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 0 0 0 0 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 0 0 0 0 0 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 V0 V1 V2 V3 0 0 EINT10 EINT9 EINT8 EINT7 EINT6 EINT5 0 0 0 0 EINT4 EINT3 EINT2 EINT1 EINT0 EINT15 EINT14 EINT13 0 0 0 EINT0 EINT1 EINT1 EINT0 EINT15 EINT14 EINT13 EINT12 EINT11 EINT10 EINT9 EINT8 0 0 PPG8_TOUT2 PPG8_TOUT0 PPG7_TOUT2 PPG7_TOUT0 PPG6_TOUT2 0 0 0 0 PPG6_TOUT0 PPG5_TOUT2 PPG5_TOUT0 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 0 0 0 PPG0_TOUT0 PPG0_TOUT2 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 PPG2_TOUT0 PPG1_TOUT2 PPG1_TOUT0 PPG0_TOUT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN48 0 0 ICU9_IN0 ICU8_IN1 ICU8_IN0 ICU7_IN1 ICU7_IN0 ICU6_IN1 0 0 0 0 ICU6_IN0 ICU5_IN1 ICU5_IN0 ICU4_IN1 ICU4_IN0 ICU3_IN1 ICU3_IN0 ICU2_IN1 0 0 0 ICU0_IN0 ICU0_IN1 ICU4_IN1 ICU4_IN0 FRT4/5/6/7_TEXT ICU3_IN1 PPG0_TOUT0 PPG6/7/8/9/10/11_TIN EINT7 PPG11_TOUT2 EINT3 PPG9_TOUT0 ICU3_IN0 ICU2_IN1 ICU2_IN0 ICU1_IN1 ICU1_IN0 ICU0_IN1 ICU0_IN0 ICU1_IN1 0 0 OCU9_OTD0 BIN8 OCU8_OTD1 OCU8_OTD0 OCU7_OTD1 OCU7_OTD0 OCU6_OTD1 0 0 0 0 OCU6_OTD0 OCU5_OTD1 OCU5_OTD0 OCU4_OTD1 OCU4_OTD0 0 0 OCU0_OTD0 OCU0_OTD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN18 OCU0_OTD0 WOT TOT18 0 0 0 TOT19 0 0 0 TIN19 0 0 0 0 0 SCK9 SOT9 0 0 0 0 0 SIN8 SCK8 SOT8 0 0 0 0 0 0 0 0 0 0 OCU2_OTD0 SGO0 TOT32 SOT10 0 0 0 0 SIN9 OCU2_OTD1 SGA0 TIN32 SCK10 0 0 0 OCU3_OTD0 SGA1 TOT33 SIN10 0 0 0 OCU3_OTD1 SGO1 TIN33 SOT11 OCU0_OTD1 0 0 SOT10 OCU4_OTD0 SGA2 TOT34 SCK11 OCU1_OTD0 0 0 SCK10 OCU4_OTD1 SGO2 TIN34 SIN11 OCU1_OTD1 0 OCU3_OTD0 SGA3 0 AIN8 OCU3_OTD1 SGO3 OCU2_OTD1 ZIN8 0 0 SIN9 SCK9 SOT9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BN1(BL1) BP1(BH1) AN1(AL1) AP1(AH1) BN0(BL0) BP0(BH0) AN0(AL0) AP0(AH0) 0 0 0 0 0 TX6 RX6 TX5 RX5 0 0 TX6 RX6 TX5 RX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_DATA1_6 DSP1_DATA0_7 DSP1_DATA1_7 VCC53 VSS VCC12 VCC12 DSP1_DATA0_8 DSP1_DATA1_8 DSP1_DATA0_9 DSP1_DATA1_9 0 DSP1_DATA1_11 0 DSP1_DATA0_6 0 DSP1_DATA0_11 0 DSP1_DATA1_5 0 DSP1_DATA1_10 0 DSP1_DATA0_5 0 DSP1_DATA0_10 0 DSP1_DATA1_4 VCC53 VSS VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN19 AN18 AN17 AN16 AN15 0 VSS VCC5 Y Y Y Y Y Y Y - - - - Y Y Y Y Y Y Y Y - - - X X W W W W W W W W V V V U - - 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 0 TOT17 0 MFS8_CS0 0 OCU9_OTD1 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 MFS10_SDA ICU9_IN1 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 J J I I I I I J J I I I I I L - AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 SOT0 SCK0 SIN0 0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 0 0 0 0 TIN0 TIN1 TIN2 TIN3 TOT0 TOT1 TOT2 TOT3 SGA1 SGO1 SGA2 SGO2 SGA3 SGO3 SGO0 SGA0 SGA1 SGO1 TOT16 SGO2 TIN17 0 0 SGA0 TIN16 SGA2 0 SGO0 0 0 AIN8 OCU4_OTD0 BIN8 OCU4_OTD1 ZIN8 OCU5_OTD0 0 0 BIN9 OCU7_OTD0 ZIN9 OCU7_OTD1 0 0 0 0 0 0 0 0 OCU6_OTD0 AIN9 OCU6_OTD1 0 OCU5_OTD1 OCU8_OTD0 OCU8_OTD1 OCU9_OTD0 OCU9_OTD1 ICU5_IN0 ICU5_IN1 ICU6_IN0 ICU6_IN1 ICU7_IN0 ICU7_IN1 ICU8_IN0 ICU8_IN1 ICU9_IN0 ICU9_IN1 0 0 0 0 0 0 0 0 0 0 PPG4_TOUT2 PPG5_TOUT0 PPG5_TOUT2 PPG6_TOUT2 PPG7_TOUT0 FRT8/9/10/11_TEXT PPG7_TOUT2 0 PPG4_TOUT0 PPG0/1/2/3/4/5_TIN1 PPG6_TOUT0 OCU11_OTD0 ICU11_IN0 0 0 0 OCU10_OTD1 ICU10_IN1 0 0 ICU4_IN1 0 OCU10_OTD0 ICU10_IN0 0 0 ICU4_IN0 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG9_TOUT2 EINT12 P2_28 0 EINT13 P2_29 0 EINT14 P2_30 0 EINT15 P2_31 0 EINT1 EINT2 EINT3 PPG11_TOUT0 EINT6 0 0 P2_25 0 P3_00 0 P3_01 0 P3_02 0 P3_03 0 P3_04 0 P3_05 0 P3_06 0 0 0 0 0 0 0 0 EINT11 P2_27 INDICATOR0_0 0 EINT0 P2_24 0 EINT10 P2_26 0 PPG10_TOUT2 EINT5 0 EINT9 PPG10_TOUT0 EINT4 0 EINT8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 0 0 0 0 0 0 AN0 0 I 0 92 0 0 0 0 P2_22 0 0 0 0 EINT6 P0_28 0 0 0 PPG3_TOUT0 P0_27 0 0 0 0 0 P0_26 0 0 ICU3_IN0 EINT3 0 G_DQ7_1 0 OCU3_OTD0 0 EINT2 0 0 G_DQ6_1 0 PPG4_TOUT2 0 G_DQ5_1 TIN49 0 0 EINT1 P1_02 M_DQ7_0 G_DQ4_1 0 G_CS#2_1 0 0 0 0 0 P1_00 M_DQ5_0 0 0 0 0 0 P1_01 M_DQ4_0 EINT10 P1_03 M_DQ6_0 EINT9 0 P0_31 M_CS#2_0 0 0 0 EINT7 0 0 0 0 PPG7_TOUT2 EINT8 0 ICU4_IN1 0 PPG8_TOUT0 EINT6 H 0 0 PPG6_TOUT2 0 91 0 0 PPG7_TOUT0 0 0 0 PPG6_TOUT0 0 0 0 0 0 0 SIN1 OCU4_OTD1 ICU7_IN1 0 0 0 SCK1 0 ICU8_IN0 0 0 0 0 SOT1 0 0 0 ICU6_IN1 0 0 G_RWDS_1 0 0 0 G_CS#1_1 0 0 0 0 0 OCU7_OTD1 ICU7_IN0 G_DQ0_1 0 0 0 0 OCU8_OTD0 ICU6_IN0 G_DQ1_1 0 0 0 0 OCU6_OTD1 0 0 G_DQ2_1 0 0 0 0 0 OCU7_OTD0 0 G_DQ3_1 DSP0_CTRL1 0 0 0 0 OCU6_OTD0 P0_30 M_RWDS_0 0 DSP0_CTRL0 0 0 0 0 0 0 0 0 DSP0_CLK 0 0 0 0 0 EINT5 G_CK_1 DSP0_CTRL2 0 CRS 0 0 0 0 0 0 0 0 0 0 0 EINT11 P1_04 M_DQ0_0 0 0 0 0 0 0 0 EINT13 P1_06 M_DQ1_0 0 0 0 0 0 0 0 PPG5_TOUT2 EINT12 P1_05 M_DQ3_0 PPG10_TOUT2 EINT15 P1_08 M_CS#1_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1_09 M_CK_0 G_DQ7_2 0 0 0 0 ICU5_IN1 0 0 G_DQ6_2 0 CAP0_DATA25 0 0 0 0 0 0 0 0 0 G_DQ5_2 0 0 0 CAP0_DATA24 0 0 0 0 OCU5_OTD1 0 P5_22 0 G_DQ4_2 0 DSP0_CTRL4 0 0 0 0 PPG8_TOUT2 0 P0_17 0 PPG10_TOUT0 EINT14 P1_07 M_DQ2_0 PPG9_TOUT2 0 P0_16 0 0 0 DSP0_CTRL3 0 0 0 0 OCU10_OTD1 ICU10_IN1 0 PPG9_TOUT0 EINT2 P0_15 0 0 VCC12 DSP0_CTRL2 0 0 0 0 0 EINT1 PPG11_TOUT0 EINT0 0 EINT0 0 MLBCLK 0 0 0 0 0 ICU8_IN1 0 0 EINT15 P0_14 0 PPG10_TOUT0 EINT4 0 EINT14 P0_13 0 0 MLBSIG 0 0 0 0 0 OCU8_OTD1 ICU9_IN1 PPG9_TOUT0 EINT13 P0_12 0 0 - MLBDAT G_SDATA0_3 0 0 0 0 OCU10_OTD0 ICU10_IN0 0 OCU9_OTD1 0 PPG8_TOUT2 0 0 F VCC3 G_SSEL0 0 0 0 0 ICU9_IN0 0 PPG8_TOUT0 0 F VSS G_SDATA0_1 0 0 0 0 0 OCU9_OTD0 0 0 PPG7_TOUT2 0 F M_SDATA1_3 G_SDATA0_2 0 0 0 0 0 0 PPG7_TOUT0 PSC_1 - M_SSEL1 G_SDATA0_0 0 0 0 0 0 0 0 OCU11_OTD0 ICU11_IN0 0 0 0 0 PPG6_TOUT2 VCC5 87 - M_SDATA1_1 0 0 0 0 0 0 0 0 0 G 86 E M_SDATA1_2 0 0 0 0 0 0 0 - 85 E M_SDATA1_0 0 0 0 0 0 0 0 90 84 E VCC3 0 0 0 0 0 0 0 0 89 83 E G_SCLK0 0 0 0 0 0 ICU9_IN0 0 0 82 E VSS 0 0 0 0 0 ICU8_IN1 0 0 81 - 0 G_SDATA1_3 0 0 0 0 ICU8_IN0 0 80 - VSS G_SSEL1 0 0 0 ICU7_IN1 OCU10_OTD0 ICU10_IN0 0 0 ICU7_IN0 0 79 E M_SDATA0_3 G_SDATA1_1 0 0 0 OCU9_OTD0 ICU6_IN1 0 78 - M_SSEL0 G_SDATA1_2 0 0 OCU8_OTD1 0 0 77 E M_SDATA0_1 G_SDATA1_0 0 0 0 OCU8_OTD0 0 76 E M_SDATA0_2 0 0 0 OCU7_OTD1 0 75 E M_SDATA0_0 0 0 0 0 OCU7_OTD0 0 74 E VCC3 0 0 0 0 OCU6_OTD1 0 73 E VSS 0 0 0 0 0 0 72 - M_SCLK0 0 TXER TIN35 I2S1_SCK 0 0 71 - VSS 0 CAP0_DATA34 0 TOT35 I2S1_WS 0 0 70 E VCC12 DSP0_CTRL2 0 0 0 69 - DSP0_CTRL0 COL 0 0 68 - DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK RXCLK TIN33 I2S0_SCK DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 I2S1_SD DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 TXCLK TOT33 I2S0_WS DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 VSS 67 C DSP0_DATA1_9 DSP0_DATA_D9- - 66 D DSP0_DATA0_9 DSP0_DATA_D9+ CAP0_DATA21 0 88 65 D VCC3 0 CAP0_DATA22 0 0 0 64 D 0 63 D 0 0 62 D 0 61 D 0 60 - 0 59 0 58 0 57 0 56 0 55 Page 26 of 222 Document Number: 002-05682 Rev. *K Condition on PCB Set to ground Open Package Pin Number 2, 5, 6, 9, and 12 to 27 3, 4, 7, 8 0 0 0 0 P0_03 EINT4 PPG2_TOUT0 ICU2_IN0 OCU2_OTD0 0 TIN16 CRS CAP0_DATA12 DSP0_DATA_D4- DSP0_DATA1_4 D 45 118 Q RSTX 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 46 117 P MODE 0 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 47 116 N2 JTAG_TMS 0 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 48 115 N2 JTAG_TCK 0 0 0 0 0 0 0 0 0 CAP0_DATA14 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 49 114 N2 JTAG_TDI 0 0 0 0 0 0 0 0 0 CAP0_DATA15 G_DQ0_2 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 50 113 O JTAG_TDO 0 0 0 0 0 0 0 0 0 0 G_CS#1_2 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 51 112 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 0 G_RWDS_2 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 52 111 M X0 0 0 0 0 0 0 0 0 0 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 53 110 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 54 109 - VSS 0 0 0 0 0 0 0 0 0 0 PPG9_TOUT2 0 0 EINT11 0 G_CK_2 0 SEG9 0 CAP0_DATA11 0 P5_11 OCU8_OTD0 ICU8_IN0 PPG8_TOUT0 EINT8 P3_24 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 28 135 S AN28 0 BP0(BH0) PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 29 134 S AN27 0 AN0(AL0) PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 30 133 S AN26 0 AP0(AH0) PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 0 0 0 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 DSP0_DATA0_4 MDC CAP0_DATA0 0 DSP0_CTRL1 C 31 132 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK+ DSP0_CLK D 32 131 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 130 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 129 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 128 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 0 CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 127 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 126 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 125 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 0 CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 39 124 H 0 0 0 0 OCU6_OTD0 ICU6_IN0 PPG6_TOUT0 EINT4 P3_20 0 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 123 H 0 0 SGO3 TIN35 OCU5_OTD1 ICU5_IN1 PPG5_TOUT2 EINT3 P3_19 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 122 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 121 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 120 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_02 EINT3 PPG1_TOUT2 ICU1_IN1 OCU1_OTD1 0 TOT16 COL CAP0_DATA11 DSP0_DATA_D4+ DSP0_DATA0_4 D 44 119 - VCC5 0 0 0 0 0 0 0 0 0 0 MFS9_CS0 0 PWM2M0 0 MFS10_SCL BN0(BL0) 0 201 0 0 202 AN29 DSP0_DATA1_11 - S 0 Y 136 0 VCC53 27 DSP0_DATA0_11 DSP1_DATA0_4 - 0 0 VCC3_LVDS_Tx 0 0 0 0 0 0 DSP0_DATA1_10 0 0 0 0 0 0 0 SIN10 0 0 0 0 0 0 0 0 AIN9 0 0 0 0 0 0 0 0 P3_25 0 0 ICU10_IN0 OCU10_OTD0 P3_26 PPG8_TOUT2 EINT9 0 0 PPG9_TOUT0 EINT10 OCU8_OTD1 ICU8_IN1 0 0 OCU9_OTD0 ICU9_IN0 PWM1P1 0 0 PWM1M1 AP1(AH1) 0 EINT12 PPG10_TOUT0 AN1(AL1) 0 0 0 0 AN30 0 SEG8 AN31 S 0 0 S 137 TOP VIEW TEQFP-216 0 P5_12 138 26 0 0 0 25 - 0 MFS9_CS1 0 B VSS_LVDS_Tx 0 0 TxDOUT0- 0 0 0 0 0 0 203 0 0 0 - 0 0 0 VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P3_27 0 0 PPG9_TOUT2 EINT11 0 0 OCU9_OTD1 ICU9_IN1 0 0 PWM2P1 0 0 BP1(BH1) 0 0 0 0 0 AN32 0 0 S 0 0 0 139 0 0 24 0 204 B 0 Y TxDOUT0+ 0 DSP1_DATA1_3 0 0 0 0 0 DSP0_CTRL0 0 0 0 0 0 0 0 0 0 ICU10_IN1 OCU10_OTD1 BIN9 0 0 EINT13 PPG10_TOUT2 0 0 0 SEG7 P3_28 0 P5_13 PPG10_TOUT0 EINT12 0 0 0 OCU10_OTD0ICU10_IN0 0 0 PWM2M1 0 205 BN1(BL1) 0 Y 0 0 DSP1_DATA0_3 AN33 0 0 S 0 DSP0_CTRL1 140 0 0 SOT11 23 0 ZIN9 B 0 0 ICU11_IN0 OCU11_OTD0 TxDOUT10 EINT14 PPG11_TOUT0 0 0 SEG6 0 0 P5_14 0 0 MFS8_CS3 0 0 0 0 0 0 206 0 0 0 207 0 0 Y 0 0 Y 0 0 0 DSP1_DATA1_2 0 0 0 DSP1_DATA0_2 0 0 0 DSP1_CLK 0 0 0 DSP0_CTRL2 DSP1_CTRL2 0 0 0 DSP0_CTRL3 0 0 0 0 SCK11 DVSS 0 0 0 SIN11 - 0 0 0 141 0 0 0 22 0 0 OCU0_OTD0 B 0 0 ICU0_IN0 TxDOUT1+ 0 0 ICU11_IN1 OCU11_OTD1 0 0 0 0 0 PPG0_TOUT0 0 0 EINT0 0 0 EINT15 PPG11_TOUT2 0 0 0 SEG5 0 0 SEG4 0 0 P5_15 0 0 0 P5_16 P3_29 0 0 MFS8_CS1 0 PPG10_TOUT2 EINT13 0 0 MFS8_CS2 0 OCU10_OTD1ICU10_IN1 0 0 0 PWM1P2 0 0 0 0 0 0 208 0 DVCC 0 Y AN34 - 0 0 DSP1_DATA1_1 S 142 0 0 0 DSP0_CTRL4 DSP1_CTRL0 143 21 0 0 0 0 0 20 B 0 0 0 0 0 0 B TxCLK0 0 0 0 0 0 TxCLK+ 0 0 0 0 0 0 OCU0_OTD1 0 0 0 0 0 0 0 ICU0_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPG0_TOUT2 0 0 0 0 0 0 0 EINT1 P3_30 0 0 0 0 0 SEG3 PPG11_TOUT0 EINT14 0 0 0 0 0 P5_17 OCU11_OTD0ICU11_IN0 0 0 0 0 0 0 0 PWM1M2 0 0 0 0 0 0 0 0 0 209 0 0 0 Y AN35 0 DSP1_DATA0_1 S 0 DSP0_CTRL5 DSP1_CTRL1 144 0 0 0 SOT12 19 0 0 0 B 0 0 OCU1_OTD0 TxDOUT20 0 ICU1_IN0 0 0 0 0 0 0 0 PPG1_TOUT0 0 0 0 0 EINT2 0 P3_31 0 0 SEG2 0 P4_00 PPG11_TOUT2 EINT15 0 0 P5_18 0 P4_01 PPG0_TOUT0 EINT0 OCU11_OTD1ICU11_IN1 0 0 MFS12_SDA 0 0 P4_02 PPG0_TOUT2 EINT1 OCU0_OTD0 ICU0_IN0 PWM2P2 0 0 0 P4_03 PPG1_TOUT0 EINT2 OCU0_OTD1 ICU0_IN1 PWM2M2 0 0 0 210 PPG1_TOUT2 EINT3 OCU1_OTD0 ICU1_IN0 PWM1P3 0 0 0 0 211 OCU1_OTD1 ICU1_IN1 PWM1M3 0 0 AN36 0 0 Y PWM2P3 0 0 AN37 S 0 Y 0 SOT2 AN38 S 145 0 DSP1_DATA1_0 SCK2 AN39 S 146 18 0 DSP1_DATA0_0 AN40 S 147 17 B 0 0 S 148 16 B TxDOUT2+ 0 0 149 15 B TxDOUT3- 0 0 DSP0_CTRL6 14 - TxDOUT3+ 0 0 0 DSP0_CTRL7 - VSS_LVDS_Tx 0 0 0 0 SCK12 VCC3_LVDS_Tx 0 0 0 0 SIN12 0 0 0 0 0 0 0 0 0 OCU1_OTD1 0 P4_04 0 OCU2_OTD0 0 0 ICU1_IN1 0 PPG2_TOUT0 EINT4 0 ICU2_IN0 0 0 0 0 OCU2_OTD0 ICU2_IN0 0 0 0 PWM2M3 0 PPG1_TOUT2 0 0 0 PPG2_TOUT0 0 SIN2 0 EINT3 0 AN41 0 EINT4 DVSS S 0 SEG1 150 0 SEG0 151 13 0 P5_19 12 0 P5_20 - AVCC3_LVDS_PLL 0 0 0 AVSS_LVDS_PLL 0 0 MFS12_SCL 0 0 0 0 0 0 0 0 0 212 0 0 213 0 0 214 0 0 215 0 0 216 0 0 0 - 0 0 0 Y 0 0 0 Y DVCC 0 0 Y - 0 0 Y 152 0 0 VCC53 11 0 0 DSP1_CLK 0 0 DSP1_CTRL2 VCC12 0 0 DSP1_CTRL1 0 0 0 DSP1_CTRL0 P4_05 0 0 0 PPG2_TOUT2 EINT5 0 0 0 OCU2_OTD1 ICU2_IN1 0 0 0 PWM1P4 0 0 0 0 0 0 0 0 0 0 AN42 DAC_L DSP0_CTRL8 S 0 DSP0_CTRL9 153 0 0 0 10 0 0 0 0 SOT11 0 VSS 0 0 SCK11 DSP0_CTRL10 0 MFS0_CS0 0 0 SIN11 DSP0_CTRL11 MFS2_CS0 P4_06 0 0 P4_07 PPG3_TOUT0 EINT6 0 0 PPG3_TOUT2 EINT7 OCU3_OTD0 ICU3_IN0 0 0 OCU3_OTD1 ICU3_IN1 PWM1M4 0 0 PWM2P4 0 0 0 0 SOT3 0 OCU0_OTD1 SCK3 AN43 0 OCU1_OTD0 SGA1 AN44 S 0 OCU1_OTD1 SGO1 S 154 0 OCU2_OTD0 155 9 0 0 8 - ICU0_IN1 A AVCC3_DAC ICU1_IN0 0 C_L AVSS 0 ICU1_IN1 MFS2_CS1 0 ICU2_IN0 P4_08 0 0 PPG4_TOUT0 EINT8 0 0 OCU4_OTD0 ICU4_IN0 0 0 PWM2M4 0 0 0 0 0 SIN3 0 0 AN45 0 PPG0_TOUT2 S 0 PPG1_TOUT0 156 0 PPG1_TOUT2 0 7 0 PPG2_TOUT0 0 A 0 0 P4_09 0 EINT9 PPG4_TOUT2 EINT9 0 EINT10 OCU4_OTD1 ICU4_IN1 0 EINT11 PWM1P5 5 EINT12 0 4 VSS 0 0 3 A AVSS COM3 AN46 2 A C_R 0 COM2 S - DAC_R 0 0 COM1 MFS4_SDA 157 1 AVSS 0 0 0 COM0 MFS4_SCL MFS0_CS3 6 - 0 0 0 0 0 0 MFS0_CS1 P4_10 0 0 0 0 0 P4_25 MFS0_CS2 P4_11 0 0 0 0 0 P4_26 0 P4_12 PPG5_TOUT0 EINT10 0 0 0 0 0 P4_27 0 0 PPG5_TOUT2 EINT11 0 0 0 0 0 P4_28 0 0 PPG6_TOUT0 EINT12 OCU5_OTD0 ICU5_IN0 0 0 0 0 0 0 0 0 0 OCU5_OTD1 ICU5_IN1 PWM1M5 0 0 0 0 0 0 0 0 0 OCU6_OTD0 ICU6_IN0 PWM2P5 0 0 0 0 0 0 0 0 0 0 PWM2M5 RX1 SOT4 0 0 0 0 0 0 0 0 0 TX1 SCK4 AN47 0 0 0 0 0 0 0 0 0 SIN4 AN48 S 0 0 0 0 0 0 0 0 AN49 S 158 0 0 0 0 0 0 0 DVSS S 159 0 0 0 0 0 0 DVCC 160 0 0 0 0 0 161 0 0 0 0 Any function at the following pins is not supported. - 162 0 0 0 Notes: - The pins highlighted in "red" font are not supported for products with revision A and C. S6J3200 Series Figure 4-6: TEQFP-216 (S6J324CLxx) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDICATOR0_1 0 0 0 MFS8_CS2 0 MFS8_CS1 0 MFS8_CS3 0 MFS9_CS1 0 MFS9_CS0 0 MFS8_CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_10 P5_09 P5_08 P5_07 P5_06 P5_05 0 0 0 0 P5_04 P5_03 P5_02 P5_01 P5_00 P4_31 P4_30 P4_29 0 0 0 P2_16 P2_17 P3_17 P3_16 P3_15 P3_14 P3_13 P3_12 P3_11 P3_10 P3_09 P3_08 P3_07 P2_19 0 0 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 0 0 0 0 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 0 0 0 0 0 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 V0 V1 V2 V3 0 0 EINT10 EINT9 EINT8 EINT7 EINT6 EINT5 0 0 0 0 EINT4 EINT3 EINT2 EINT1 EINT0 EINT15 EINT14 EINT13 0 0 0 EINT0 EINT1 EINT1 EINT0 EINT15 EINT14 EINT13 EINT12 EINT11 EINT10 EINT9 EINT8 0 0 PPG8_TOUT2 PPG8_TOUT0 PPG7_TOUT2 PPG7_TOUT0 PPG6_TOUT2 0 0 0 0 PPG6_TOUT0 PPG5_TOUT2 PPG5_TOUT0 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 0 0 0 PPG0_TOUT0 PPG0_TOUT2 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 PPG2_TOUT0 PPG1_TOUT2 PPG1_TOUT0 PPG0_TOUT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN48 0 0 ICU9_IN0 ICU8_IN1 ICU8_IN0 ICU7_IN1 ICU7_IN0 ICU6_IN1 0 0 0 0 ICU6_IN0 ICU5_IN1 ICU5_IN0 ICU4_IN1 ICU4_IN0 ICU3_IN1 ICU3_IN0 ICU2_IN1 0 0 0 ICU0_IN0 ICU0_IN1 ICU4_IN1 ICU4_IN0 FRT4/5/6/7_TEXT ICU3_IN1 PPG0_TOUT0 PPG6/7/8/9/10/11_TIN EINT7 PPG11_TOUT2 EINT3 PPG9_TOUT0 ICU3_IN0 ICU2_IN1 ICU2_IN0 ICU1_IN1 ICU1_IN0 ICU0_IN1 ICU0_IN0 ICU1_IN1 0 0 OCU9_OTD0 BIN8 OCU8_OTD1 OCU8_OTD0 OCU7_OTD1 OCU7_OTD0 OCU6_OTD1 0 0 0 0 OCU6_OTD0 OCU5_OTD1 OCU5_OTD0 OCU4_OTD1 OCU4_OTD0 0 0 OCU0_OTD0 OCU0_OTD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN18 OCU0_OTD0 WOT TOT18 0 0 0 TOT19 0 0 0 TIN19 0 0 0 0 0 SCK9 SOT9 0 0 0 0 0 SIN8 SCK8 SOT8 0 0 0 0 0 0 0 0 0 0 OCU2_OTD0 SGO0 TOT32 SOT10 0 0 0 0 SIN9 OCU2_OTD1 SGA0 TIN32 SCK10 0 0 0 OCU3_OTD0 SGA1 TOT33 SIN10 0 0 0 OCU3_OTD1 SGO1 TIN33 SOT11 OCU0_OTD1 0 0 SOT10 OCU4_OTD0 SGA2 TOT34 SCK11 OCU1_OTD0 0 0 SCK10 OCU4_OTD1 SGO2 TIN34 SIN11 OCU1_OTD1 0 OCU3_OTD0 SGA3 0 AIN8 OCU3_OTD1 SGO3 OCU2_OTD1 ZIN8 0 0 SIN9 SCK9 SOT9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BN1(BL1) BP1(BH1) AN1(AL1) AP1(AH1) BN0(BL0) BP0(BH0) AN0(AL0) AP0(AH0) 0 0 0 0 0 TX6 RX6 TX5 RX5 0 0 TX6 RX6 TX5 RX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_DATA1_6 DSP1_DATA0_7 DSP1_DATA1_7 VCC53 VSS VCC12 VCC12 DSP1_DATA0_8 DSP1_DATA1_8 DSP1_DATA0_9 DSP1_DATA1_9 0 DSP1_DATA1_11 0 DSP1_DATA0_6 0 DSP1_DATA0_11 0 DSP1_DATA1_5 0 DSP1_DATA1_10 0 DSP1_DATA0_5 0 DSP1_DATA0_10 0 DSP1_DATA1_4 VCC53 VSS VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN19 AN18 AN17 AN16 AN15 0 VSS VCC5 Y Y Y Y Y Y Y - - - - Y Y Y Y Y Y Y Y - - - X X W W W W W W W W V V V U - - 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 0 TOT17 0 MFS8_CS0 0 OCU9_OTD1 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 MFS10_SDA ICU9_IN1 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 D D D D C - - E - - E E E E E - E - - E E E E E - - F F F - - - G H I J J I I I I I J J I I I I I L - VCC3 DSP0_DATA0_9 DSP0_DATA_D9+ CAP0_DATA21 0 DSP0_DATA1_9 DSP0_DATA_D9- DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK DSP0_CTRL0 VCC12 VSS M_SCLK0 VSS VCC3 M_SDATA0_0 M_SDATA0_2 M_SDATA0_1 M_SSEL0 M_SDATA0_3 VSS 0 VSS VCC3 M_SDATA1_0 M_SDATA1_2 M_SDATA1_1 M_SSEL1 M_SDATA1_3 VSS VCC3 MLBDAT MLBSIG MLBCLK VCC12 VSS VCC5 PSC_1 0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 DSP0_CTRL2 0 0 0 0 0 G_SDATA1_0 G_SDATA1_2 G_SDATA1_1 G_SSEL1 G_SDATA1_3 0 G_SCLK0 0 0 G_SDATA0_0 G_SDATA0_2 G_SDATA0_1 G_SSEL0 G_SDATA0_3 0 0 DSP0_CTRL2 DSP0_CTRL3 DSP0_CTRL4 0 0 0 0 0 0 SOT0 SCK0 SIN0 0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 CAP0_DATA34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0_DATA25 0 0 0 CAP0_DATA24 0 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 RXCLK TIN33 I2S0_SCK DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 I2S1_SD DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 TXCLK TOT33 I2S0_WS COL 0 TXER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 TOT35 I2S1_WS TIN35 I2S1_SCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN0 TIN1 TIN2 TIN3 TOT0 TOT1 TOT2 TOT3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGO0 SGA0 SGA1 SGO1 SGA2 SGO2 SGA3 SGO3 SGO0 SGA0 SGA1 SGO1 TOT16 SGO2 TIN17 0 0 0 TIN16 SGA2 0 0 TIN49 0 0 0 0 0 0 0 0 DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU9_OTD0 OCU8_OTD1 OCU5_OTD1 0 0 OCU6_OTD0 OCU7_OTD0 OCU6_OTD1 OCU8_OTD0 OCU7_OTD1 0 0 0 0 0 0 OCU3_OTD0 OCU5_OTD1 OCU6_OTD0 OCU8_OTD0 OCU8_OTD1 OCU9_OTD0 OCU9_OTD1 ICU8_IN1 ICU9_IN0 0 0 0 0 ICU9_IN0 ICU9_IN1 ICU8_IN1 0 ICU5_IN1 0 0 ICU6_IN0 ICU7_IN0 ICU6_IN1 ICU8_IN0 ICU7_IN1 0 0 0 0 ICU4_IN1 0 0 0 0 ICU3_IN0 ICU4_IN0 ICU4_IN1 ICU5_IN0 ICU5_IN1 ICU6_IN0 ICU6_IN1 ICU7_IN0 ICU7_IN1 ICU8_IN0 ICU8_IN1 ICU9_IN0 ICU9_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPG6_TOUT2 PPG7_TOUT0 PPG7_TOUT2 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 0 0 0 PPG9_TOUT0 PPG8_TOUT2 PPG5_TOUT2 0 0 PPG6_TOUT0 PPG7_TOUT0 PPG6_TOUT2 PPG8_TOUT0 PPG7_TOUT2 0 0 0 0 PPG4_TOUT2 0 0 0 0 PPG3_TOUT0 PPG4_TOUT0 PPG4_TOUT2 PPG5_TOUT0 PPG5_TOUT2 PPG6_TOUT2 PPG7_TOUT0 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG9_TOUT2 EINT1 EINT2 0 0 0 0 0 0 EINT6 EINT8 EINT7 0 0 EINT1 EINT2 EINT3 0 0 0 0 EINT6 EINT8 EINT9 0 P0_30 M_RWDS_0 0 0 P1_01 M_DQ4_0 P1_00 M_DQ5_0 P1_02 M_DQ7_0 0 P0_28 0 0 0 0 0 0 P2_24 0 P2_25 0 P3_00 0 P3_01 0 P3_02 0 P3_03 0 P3_04 0 P3_05 0 P3_06 0 0 0 P2_22 0 0 0 P0_27 0 0 0 P0_26 0 0 0 P0_31 M_CS#2_0 0 0 EINT15 P2_31 0 0 0 0 EINT14 P2_30 0 PPG11_TOUT0 EINT6 0 0 EINT13 P2_29 0 EINT3 0 0 P1_09 M_CK_0 EINT12 P2_28 0 EINT2 0 0 0 0 0 G_DQ4_2 G_DQ5_2 G_DQ6_2 G_DQ7_2 0 0 0 0 0 G_CK_1 0 0 G_DQ3_1 G_DQ2_1 G_DQ1_1 G_DQ0_1 0 0 G_DQ5_1 G_DQ6_1 G_DQ7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP0_CTRL2 DSP0_CLK DSP0_CTRL0 DSP0_CTRL1 0 0 0 0 0 0 0 0 0 0 0 G_CS#2_1 0 G_DQ4_1 0 G_RWDS_1 0 0 0 G_CS#1_1 0 EINT11 P2_27 INDICATOR0_0 0 EINT1 0 EINT10 P2_26 0 EINT0 P5_22 0 EINT10 P1_03 M_DQ6_0 EINT9 P0_17 0 EINT11 P1_04 M_DQ0_0 EINT5 P0_16 0 EINT13 P1_06 M_DQ1_0 0 P0_15 0 EINT12 P1_05 M_DQ3_0 PPG10_TOUT2 EINT5 0 EINT0 PPG10_TOUT0 EINT4 0 EINT15 P0_14 0 PPG10_TOUT2 EINT15 P1_08 M_CS#1_0 0 EINT14 P0_13 0 PPG10_TOUT0 EINT14 P1_07 M_DQ2_0 PPG9_TOUT2 EINT13 P0_12 0 PPG11_TOUT0 EINT0 0 0 PPG10_TOUT0 EINT4 FRT8/9/10/11_TEXT PPG7_TOUT2 0 0 PPG0/1/2/3/4/5_TIN1 PPG6_TOUT0 OCU11_OTD0 ICU11_IN0 0 0 0 OCU10_OTD1 ICU10_IN1 0 0 ICU8_IN0 OCU10_OTD0 ICU10_IN0 0 0 ICU7_IN1 OCU10_OTD1 ICU10_IN1 0 0 ICU7_IN0 OCU10_OTD0 ICU10_IN0 0 OCU9_OTD1 ICU6_IN1 OCU11_OTD0 ICU11_IN0 0 ZIN9 OCU7_OTD1 0 0 BIN9 OCU7_OTD0 0 0 0 OCU10_OTD0 ICU10_IN0 0 AIN9 OCU6_OTD1 0 OCU9_OTD0 ZIN8 OCU5_OTD0 0 OCU8_OTD1 BIN8 OCU4_OTD1 0 OCU8_OTD0 AIN8 OCU4_OTD0 0 OCU7_OTD1 SIN1 OCU4_OTD1 0 OCU7_OTD0 SCK1 0 0 OCU6_OTD1 SOT1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 CAP0_DATA22 0 0 0 0 62 D 0 61 D 0 60 - 0 59 0 58 0 57 0 56 0 55 Page 27 of 222 Document Number: 002-05682 Rev. *K Condition on PCB Set to ground Package Pin Number 12 to 27 0 0 0 0 P0_03 EINT4 PPG2_TOUT0 ICU2_IN0 OCU2_OTD0 0 TIN16 CRS CAP0_DATA12 DSP0_DATA_D4- DSP0_DATA1_4 D 45 118 Q RSTX 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 46 117 P MODE 0 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 47 116 N2 JTAG_TMS 0 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 48 115 N2 JTAG_TCK 0 0 0 0 0 0 0 0 0 CAP0_DATA14 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 49 114 N2 JTAG_TDI 0 0 0 0 0 0 0 0 0 CAP0_DATA15 G_DQ0_2 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 50 113 O JTAG_TDO 0 0 0 0 0 0 0 0 0 0 G_CS#1_2 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 51 112 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 0 G_RWDS_2 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 52 111 M X0 0 0 0 0 0 0 0 0 0 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 53 110 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 54 109 - VSS 0 0 0 0 0 0 0 0 0 0 PPG9_TOUT2 0 0 EINT11 0 G_CK_2 0 SEG9 0 CAP0_DATA11 0 P5_11 OCU8_OTD0 ICU8_IN0 PPG8_TOUT0 EINT8 P3_24 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 28 135 S AN28 0 BP0(BH0) PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 29 134 S AN27 0 AN0(AL0) PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 30 133 S AN26 0 AP0(AH0) PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 0 0 0 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 DSP0_DATA0_4 MDC CAP0_DATA0 0 DSP0_CTRL1 C 31 132 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK+ DSP0_CLK D 32 131 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 130 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 129 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 128 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 0 CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 127 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 126 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 125 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 0 CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 39 124 H 0 0 0 0 OCU6_OTD0 ICU6_IN0 PPG6_TOUT0 EINT4 P3_20 0 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 123 H 0 0 SGO3 TIN35 OCU5_OTD1 ICU5_IN1 PPG5_TOUT2 EINT3 P3_19 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 122 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 121 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 120 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_02 EINT3 PPG1_TOUT2 ICU1_IN1 OCU1_OTD1 0 TOT16 COL CAP0_DATA11 DSP0_DATA_D4+ DSP0_DATA0_4 D 44 119 - VCC5 0 0 0 0 0 0 0 0 0 0 MFS9_CS0 0 PWM2M0 0 MFS10_SCL BN0(BL0) 0 201 0 0 202 AN29 DSP0_DATA1_11 - S 0 Y 136 0 VCC53 27 DSP0_DATA0_11 DSP1_DATA0_4 - 0 0 VCC3_LVDS_Tx 0 0 0 0 0 0 DSP0_DATA1_10 0 0 0 0 0 0 0 SIN10 0 0 0 0 0 0 0 0 AIN9 0 0 0 0 0 0 0 0 P3_25 0 0 ICU10_IN0 OCU10_OTD0 P3_26 PPG8_TOUT2 EINT9 0 0 PPG9_TOUT0 EINT10 OCU8_OTD1 ICU8_IN1 0 0 OCU9_OTD0 ICU9_IN0 PWM1P1 0 0 PWM1M1 AP1(AH1) 0 EINT12 PPG10_TOUT0 AN1(AL1) 0 0 0 0 AN30 0 SEG8 AN31 S 0 0 S 137 TOP VIEW TEQFP-216 0 P5_12 138 26 0 0 0 25 - 0 MFS9_CS1 0 B VSS_LVDS_Tx 0 0 TxDOUT0- 0 0 0 0 0 0 203 0 0 0 - 0 0 0 VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P3_27 0 0 PPG9_TOUT2 EINT11 0 0 OCU9_OTD1 ICU9_IN1 0 0 PWM2P1 0 0 BP1(BH1) 0 0 0 0 0 AN32 0 0 S 0 0 0 139 0 0 24 0 204 B 0 Y TxDOUT0+ 0 DSP1_DATA1_3 0 0 0 0 0 DSP0_CTRL0 0 0 0 0 0 0 0 0 0 ICU10_IN1 OCU10_OTD1 BIN9 0 0 EINT13 PPG10_TOUT2 0 0 0 SEG7 P3_28 0 P5_13 PPG10_TOUT0 EINT12 0 0 0 OCU10_OTD0ICU10_IN0 0 0 PWM2M1 0 205 BN1(BL1) 0 Y 0 0 DSP1_DATA0_3 AN33 0 0 S 0 DSP0_CTRL1 140 0 0 SOT11 23 0 ZIN9 B 0 0 ICU11_IN0 OCU11_OTD0 TxDOUT10 EINT14 PPG11_TOUT0 0 0 SEG6 0 0 P5_14 0 0 MFS8_CS3 0 0 0 0 0 0 206 0 0 0 207 0 0 Y 0 0 Y 0 0 0 DSP1_DATA1_2 0 0 0 DSP1_DATA0_2 0 0 0 DSP1_CLK 0 0 0 DSP0_CTRL2 DSP1_CTRL2 0 0 0 DSP0_CTRL3 0 0 0 0 SCK11 DVSS 0 0 0 SIN11 - 0 0 0 141 0 0 0 22 0 0 OCU0_OTD0 B 0 0 ICU0_IN0 TxDOUT1+ 0 0 ICU11_IN1 OCU11_OTD1 0 0 0 0 0 PPG0_TOUT0 0 0 EINT0 0 0 EINT15 PPG11_TOUT2 0 0 0 SEG5 0 0 SEG4 0 0 P5_15 0 0 0 P5_16 P3_29 0 0 MFS8_CS1 0 PPG10_TOUT2 EINT13 0 0 MFS8_CS2 0 OCU10_OTD1ICU10_IN1 0 0 0 PWM1P2 0 0 0 0 0 0 208 0 DVCC 0 Y AN34 - 0 0 DSP1_DATA1_1 S 142 0 0 0 DSP0_CTRL4 DSP1_CTRL0 143 21 0 0 0 0 0 20 B 0 0 0 0 0 0 B TxCLK0 0 0 0 0 0 TxCLK+ 0 0 0 0 0 0 OCU0_OTD1 0 0 0 0 0 0 0 ICU0_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPG0_TOUT2 0 0 0 0 0 0 0 EINT1 P3_30 0 0 0 0 0 SEG3 PPG11_TOUT0 EINT14 0 0 0 0 0 P5_17 OCU11_OTD0ICU11_IN0 0 0 0 0 0 0 0 PWM1M2 0 0 0 0 0 0 0 0 0 209 0 0 0 Y AN35 0 DSP1_DATA0_1 S 0 DSP0_CTRL5 DSP1_CTRL1 144 0 0 0 SOT12 19 0 0 0 B 0 0 OCU1_OTD0 TxDOUT20 0 ICU1_IN0 0 0 0 0 0 0 0 PPG1_TOUT0 0 0 0 0 EINT2 0 P3_31 0 0 SEG2 0 P4_00 PPG11_TOUT2 EINT15 0 0 P5_18 0 P4_01 PPG0_TOUT0 EINT0 OCU11_OTD1ICU11_IN1 0 0 MFS12_SDA 0 0 P4_02 PPG0_TOUT2 EINT1 OCU0_OTD0 ICU0_IN0 PWM2P2 0 0 0 P4_03 PPG1_TOUT0 EINT2 OCU0_OTD1 ICU0_IN1 PWM2M2 0 0 0 210 PPG1_TOUT2 EINT3 OCU1_OTD0 ICU1_IN0 PWM1P3 0 0 0 0 211 OCU1_OTD1 ICU1_IN1 PWM1M3 0 0 AN36 0 0 Y PWM2P3 0 0 AN37 S 0 Y 0 SOT2 AN38 S 145 0 DSP1_DATA1_0 SCK2 AN39 S 146 18 0 DSP1_DATA0_0 AN40 S 147 17 B 0 0 S 148 16 B TxDOUT2+ 0 0 149 15 B TxDOUT3- 0 0 DSP0_CTRL6 14 - TxDOUT3+ 0 0 0 DSP0_CTRL7 - VSS_LVDS_Tx 0 0 0 0 SCK12 VCC3_LVDS_Tx 0 0 0 0 SIN12 0 0 0 0 0 0 0 0 0 OCU1_OTD1 0 P4_04 0 OCU2_OTD0 0 0 ICU1_IN1 0 PPG2_TOUT0 EINT4 0 ICU2_IN0 0 0 0 0 OCU2_OTD0 ICU2_IN0 0 0 0 PWM2M3 0 PPG1_TOUT2 0 0 0 PPG2_TOUT0 0 SIN2 0 EINT3 0 AN41 0 EINT4 DVSS S 0 SEG1 150 0 SEG0 151 13 0 P5_19 12 0 P5_20 - AVCC3_LVDS_PLL 0 0 0 AVSS_LVDS_PLL 0 0 MFS12_SCL 0 0 0 0 0 0 0 0 0 212 0 0 213 0 0 214 0 0 215 0 0 216 0 0 0 - 0 0 0 Y 0 0 0 Y DVCC 0 0 Y - 0 0 Y 152 0 0 VCC53 11 0 0 DSP1_CLK 0 0 DSP1_CTRL2 VCC12 0 0 DSP1_CTRL1 0 0 0 DSP1_CTRL0 P4_05 0 0 0 PPG2_TOUT2 EINT5 0 0 0 OCU2_OTD1 ICU2_IN1 0 0 0 PWM1P4 0 0 0 0 0 0 0 0 0 0 AN42 DAC_L DSP0_CTRL8 S 0 DSP0_CTRL9 153 0 0 0 10 0 0 0 0 SOT11 0 VSS 0 0 SCK11 DSP0_CTRL10 0 MFS0_CS0 0 0 SIN11 DSP0_CTRL11 MFS2_CS0 P4_06 0 0 P4_07 PPG3_TOUT0 EINT6 0 0 PPG3_TOUT2 EINT7 OCU3_OTD0 ICU3_IN0 0 0 OCU3_OTD1 ICU3_IN1 PWM1M4 0 0 PWM2P4 0 0 0 0 SOT3 0 OCU0_OTD1 SCK3 AN43 0 OCU1_OTD0 SGA1 AN44 S 0 OCU1_OTD1 SGO1 S 154 0 OCU2_OTD0 155 9 0 0 8 - ICU0_IN1 A AVCC3_DAC ICU1_IN0 0 C_L AVSS 0 ICU1_IN1 MFS2_CS1 0 ICU2_IN0 P4_08 0 0 PPG4_TOUT0 EINT8 0 0 OCU4_OTD0 ICU4_IN0 0 0 PWM2M4 0 0 0 0 0 SIN3 0 0 AN45 0 PPG0_TOUT2 S 0 PPG1_TOUT0 156 0 PPG1_TOUT2 0 7 0 PPG2_TOUT0 0 A 0 0 P4_09 0 EINT9 PPG4_TOUT2 EINT9 0 EINT10 OCU4_OTD1 ICU4_IN1 0 EINT11 PWM1P5 5 EINT12 0 4 VSS 0 0 3 A AVSS COM3 AN46 2 A C_R 0 COM2 S - DAC_R 0 0 COM1 MFS4_SDA 157 1 AVSS 0 0 0 COM0 MFS4_SCL MFS0_CS3 6 - 0 0 0 0 0 0 MFS0_CS1 P4_10 0 0 0 0 0 P4_25 MFS0_CS2 P4_11 0 0 0 0 0 P4_26 0 P4_12 PPG5_TOUT0 EINT10 0 0 0 0 0 P4_27 0 0 PPG5_TOUT2 EINT11 0 0 0 0 0 P4_28 0 0 PPG6_TOUT0 EINT12 OCU5_OTD0 ICU5_IN0 0 0 0 0 0 0 0 0 0 OCU5_OTD1 ICU5_IN1 PWM1M5 0 0 0 0 0 0 0 0 0 OCU6_OTD0 ICU6_IN0 PWM2P5 0 0 0 0 0 0 0 0 0 0 PWM2M5 RX1 SOT4 0 0 0 0 0 0 0 0 0 TX1 SCK4 AN47 0 0 0 0 0 0 0 0 0 SIN4 AN48 S 0 0 0 0 0 0 0 0 AN49 S 158 0 0 0 0 0 0 0 DVSS S 159 0 0 0 0 0 0 DVCC 160 0 0 0 0 0 161 0 0 0 0 Any function at the following pins is not supported. - 162 0 0 0 Notes: - The pins highlighted in "red" font are not supported for products with revision A and C. S6J3200 Series Figure 4-7: TEQFP-216 (S6J323CLxx) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDICATOR0_1 0 0 0 MFS8_CS2 0 MFS8_CS1 0 MFS8_CS3 0 MFS9_CS1 0 MFS9_CS0 0 MFS8_CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_10 P5_09 P5_08 P5_07 P5_06 P5_05 0 0 0 0 P5_04 P5_03 P5_02 P5_01 P5_00 P4_31 P4_30 P4_29 0 0 0 P2_16 P2_17 P3_17 P3_16 P3_15 P3_14 P3_13 P3_12 P3_11 P3_10 P3_09 P3_08 P3_07 P2_19 0 0 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 0 0 0 0 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 0 0 0 0 0 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 V0 V1 V2 V3 0 0 EINT10 EINT9 EINT8 EINT7 EINT6 EINT5 0 0 0 0 EINT4 EINT3 EINT2 EINT1 EINT0 EINT15 EINT14 EINT13 0 0 0 EINT0 EINT1 EINT1 EINT0 EINT15 EINT14 EINT13 EINT12 EINT11 EINT10 EINT9 EINT8 0 0 PPG8_TOUT2 PPG8_TOUT0 PPG7_TOUT2 PPG7_TOUT0 PPG6_TOUT2 0 0 0 0 PPG6_TOUT0 PPG5_TOUT2 PPG5_TOUT0 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 0 0 0 PPG0_TOUT0 PPG0_TOUT2 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 PPG2_TOUT0 PPG1_TOUT2 PPG1_TOUT0 PPG0_TOUT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN48 0 0 ICU9_IN0 ICU8_IN1 ICU8_IN0 ICU7_IN1 ICU7_IN0 ICU6_IN1 0 0 0 0 ICU6_IN0 ICU5_IN1 ICU5_IN0 ICU4_IN1 ICU4_IN0 ICU3_IN1 ICU3_IN0 ICU2_IN1 0 0 0 ICU0_IN0 ICU0_IN1 ICU4_IN1 ICU4_IN0 FRT4/5/6/7_TEXT ICU3_IN1 PPG0_TOUT0 PPG6/7/8/9/10/11_TIN EINT7 PPG11_TOUT2 EINT3 PPG9_TOUT0 ICU3_IN0 ICU2_IN1 ICU2_IN0 ICU1_IN1 ICU1_IN0 ICU0_IN1 ICU0_IN0 ICU1_IN1 0 0 OCU9_OTD0 BIN8 OCU8_OTD1 OCU8_OTD0 OCU7_OTD1 OCU7_OTD0 OCU6_OTD1 0 0 0 0 OCU6_OTD0 OCU5_OTD1 OCU5_OTD0 OCU4_OTD1 OCU4_OTD0 0 0 OCU0_OTD0 OCU0_OTD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN18 OCU0_OTD0 WOT TOT18 0 0 0 TOT19 0 0 0 TIN19 0 0 0 0 0 SCK9 SOT9 0 0 0 0 0 SIN8 SCK8 SOT8 0 0 0 0 0 0 0 0 0 0 OCU2_OTD0 SGO0 TOT32 SOT10 0 0 0 0 SIN9 OCU2_OTD1 SGA0 TIN32 SCK10 0 0 0 OCU3_OTD0 SGA1 TOT33 SIN10 0 0 0 OCU3_OTD1 SGO1 TIN33 SOT11 OCU0_OTD1 0 0 SOT10 OCU4_OTD0 SGA2 TOT34 SCK11 OCU1_OTD0 0 0 SCK10 OCU4_OTD1 SGO2 TIN34 SIN11 OCU1_OTD1 0 OCU3_OTD0 SGA3 0 AIN8 OCU3_OTD1 SGO3 OCU2_OTD1 ZIN8 0 0 SIN9 SCK9 SOT9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BN1(BL1) BP1(BH1) AN1(AL1) AP1(AH1) BN0(BL0) BP0(BH0) AN0(AL0) AP0(AH0) 0 0 0 0 0 TX6 RX6 TX5 RX5 0 0 TX6 RX6 TX5 RX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_DATA1_6 DSP1_DATA0_7 DSP1_DATA1_7 VCC53 VSS VCC12 VCC12 DSP1_DATA0_8 DSP1_DATA1_8 DSP1_DATA0_9 DSP1_DATA1_9 0 DSP1_DATA1_11 0 DSP1_DATA0_6 0 DSP1_DATA0_11 0 DSP1_DATA1_5 0 DSP1_DATA1_10 0 DSP1_DATA0_5 0 DSP1_DATA0_10 0 DSP1_DATA1_4 VCC53 VSS VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN19 AN18 AN17 AN16 AN15 0 VSS VCC5 Y Y Y Y Y Y Y - - - - Y Y Y Y Y Y Y Y - - - X X W W W W W W W W V V V U - - 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 0 TOT17 0 MFS8_CS0 0 OCU9_OTD1 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 MFS10_SDA ICU9_IN1 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 J J I I I I I J J I I I I I L - AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 SOT0 SCK0 SIN0 0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 0 0 0 0 TIN0 TIN1 TIN2 TIN3 TOT0 TOT1 TOT2 TOT3 SGA1 SGO1 SGA2 SGO2 SGA3 SGO3 SGO0 SGA0 SGA1 SGO1 TOT16 SGO2 TIN17 0 0 SGA0 TIN16 SGA2 0 SGO0 0 0 AIN8 OCU4_OTD0 BIN8 OCU4_OTD1 ZIN8 OCU5_OTD0 0 0 BIN9 OCU7_OTD0 ZIN9 OCU7_OTD1 0 0 0 0 0 0 0 0 OCU6_OTD0 AIN9 OCU6_OTD1 0 OCU5_OTD1 OCU8_OTD0 OCU8_OTD1 OCU9_OTD0 OCU9_OTD1 ICU5_IN0 ICU5_IN1 ICU6_IN0 ICU6_IN1 ICU7_IN0 ICU7_IN1 ICU8_IN0 ICU8_IN1 ICU9_IN0 ICU9_IN1 0 0 0 0 0 0 0 0 0 0 PPG4_TOUT2 PPG5_TOUT0 PPG5_TOUT2 PPG6_TOUT2 PPG7_TOUT0 FRT8/9/10/11_TEXT PPG7_TOUT2 0 PPG4_TOUT0 PPG0/1/2/3/4/5_TIN1 PPG6_TOUT0 OCU11_OTD0 ICU11_IN0 0 0 0 OCU10_OTD1 ICU10_IN1 0 0 ICU4_IN1 0 OCU10_OTD0 ICU10_IN0 0 0 ICU4_IN0 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG9_TOUT2 EINT12 P2_28 0 EINT13 P2_29 0 EINT14 P2_30 0 EINT15 P2_31 0 EINT1 EINT2 EINT3 PPG11_TOUT0 EINT6 0 0 P2_25 0 P3_00 0 P3_01 0 P3_02 0 P3_03 0 P3_04 0 P3_05 0 P3_06 0 0 0 0 0 0 0 0 EINT11 P2_27 INDICATOR0_0 0 EINT0 P2_24 0 EINT10 P2_26 0 PPG10_TOUT2 EINT5 0 EINT9 PPG10_TOUT0 EINT4 0 EINT8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 0 0 0 0 0 0 AN0 0 I 0 92 0 0 0 0 P2_22 0 0 0 0 EINT6 P0_28 0 0 0 PPG3_TOUT0 P0_27 0 0 0 0 0 P0_26 0 0 ICU3_IN0 EINT3 0 G_DQ7_1 0 OCU3_OTD0 0 EINT2 0 0 G_DQ6_1 0 PPG4_TOUT2 0 G_DQ5_1 TIN49 0 0 EINT1 P1_02 M_DQ7_0 G_DQ4_1 0 G_CS#2_1 0 0 0 0 0 P1_00 M_DQ5_0 0 0 0 0 0 P1_01 M_DQ4_0 EINT10 P1_03 M_DQ6_0 EINT9 0 P0_31 M_CS#2_0 0 0 0 EINT7 0 0 0 0 PPG7_TOUT2 EINT8 0 ICU4_IN1 0 PPG8_TOUT0 EINT6 H 0 0 PPG6_TOUT2 0 91 0 0 PPG7_TOUT0 0 0 0 PPG6_TOUT0 0 0 0 0 0 0 SIN1 OCU4_OTD1 ICU7_IN1 0 0 0 SCK1 0 ICU8_IN0 0 0 0 0 SOT1 0 0 0 ICU6_IN1 0 0 G_RWDS_1 0 0 0 G_CS#1_1 0 0 0 0 0 OCU7_OTD1 ICU7_IN0 G_DQ0_1 0 0 0 0 OCU8_OTD0 ICU6_IN0 G_DQ1_1 0 0 0 0 OCU6_OTD1 0 0 G_DQ2_1 0 0 0 0 0 OCU7_OTD0 0 G_DQ3_1 DSP0_CTRL1 0 0 0 0 OCU6_OTD0 P0_30 M_RWDS_0 0 DSP0_CTRL0 0 0 0 0 0 0 0 0 DSP0_CLK 0 0 0 0 0 EINT5 G_CK_1 DSP0_CTRL2 0 CRS 0 0 0 0 0 0 0 0 0 0 0 EINT11 P1_04 M_DQ0_0 0 0 0 0 0 0 0 EINT13 P1_06 M_DQ1_0 0 0 0 0 0 0 0 PPG5_TOUT2 EINT12 P1_05 M_DQ3_0 PPG10_TOUT2 EINT15 P1_08 M_CS#1_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1_09 M_CK_0 G_DQ7_2 0 0 0 0 ICU5_IN1 0 0 G_DQ6_2 0 CAP0_DATA25 0 0 0 0 0 0 0 0 0 G_DQ5_2 0 0 0 CAP0_DATA24 0 0 0 0 OCU5_OTD1 0 P5_22 0 G_DQ4_2 0 DSP0_CTRL4 0 0 0 0 PPG8_TOUT2 0 P0_17 0 PPG10_TOUT0 EINT14 P1_07 M_DQ2_0 PPG9_TOUT2 0 P0_16 0 0 0 DSP0_CTRL3 0 0 0 0 OCU10_OTD1 ICU10_IN1 0 PPG9_TOUT0 EINT2 P0_15 0 0 VCC12 DSP0_CTRL2 0 0 0 0 0 EINT1 PPG11_TOUT0 EINT0 0 EINT0 0 MLBCLK 0 0 0 0 0 ICU8_IN1 0 0 EINT15 P0_14 0 PPG10_TOUT0 EINT4 0 EINT14 P0_13 0 0 MLBSIG 0 0 0 0 0 OCU8_OTD1 ICU9_IN1 PPG9_TOUT0 EINT13 P0_12 0 0 - MLBDAT G_SDATA0_3 0 0 0 0 OCU10_OTD0 ICU10_IN0 0 OCU9_OTD1 0 PPG8_TOUT2 0 0 F VCC3 G_SSEL0 0 0 0 0 ICU9_IN0 0 PPG8_TOUT0 0 F VSS G_SDATA0_1 0 0 0 0 0 OCU9_OTD0 0 0 PPG7_TOUT2 0 F M_SDATA1_3 G_SDATA0_2 0 0 0 0 0 0 PPG7_TOUT0 PSC_1 - M_SSEL1 G_SDATA0_0 0 0 0 0 0 0 0 OCU11_OTD0 ICU11_IN0 0 0 0 0 PPG6_TOUT2 VCC5 87 - M_SDATA1_1 0 0 0 0 0 0 0 0 0 G 86 E M_SDATA1_2 0 0 0 0 0 0 0 - 85 E M_SDATA1_0 0 0 0 0 0 0 0 90 84 E VCC3 0 0 0 0 0 0 0 0 89 83 E G_SCLK0 0 0 0 0 0 ICU9_IN0 0 0 82 E VSS 0 0 0 0 0 ICU8_IN1 0 0 81 - 0 G_SDATA1_3 0 0 0 0 ICU8_IN0 0 80 - VSS G_SSEL1 0 0 0 ICU7_IN1 OCU10_OTD0 ICU10_IN0 0 0 ICU7_IN0 0 79 E M_SDATA0_3 G_SDATA1_1 0 0 0 OCU9_OTD0 ICU6_IN1 0 78 - M_SSEL0 G_SDATA1_2 0 0 OCU8_OTD1 0 0 77 E M_SDATA0_1 G_SDATA1_0 0 0 0 OCU8_OTD0 0 76 E M_SDATA0_2 0 0 0 OCU7_OTD1 0 75 E M_SDATA0_0 0 0 0 0 OCU7_OTD0 0 74 E VCC3 0 0 0 0 OCU6_OTD1 0 73 E VSS 0 0 0 0 0 0 72 - M_SCLK0 0 TXER TIN35 I2S1_SCK 0 0 71 - VSS 0 CAP0_DATA34 0 TOT35 I2S1_WS 0 0 70 E VCC12 DSP0_CTRL2 0 0 0 69 - DSP0_CTRL0 COL 0 0 68 - DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK RXCLK TIN33 I2S0_SCK DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 I2S1_SD DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 TXCLK TOT33 I2S0_WS DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 VSS 67 C DSP0_DATA1_9 DSP0_DATA_D9- - 66 D DSP0_DATA0_9 DSP0_DATA_D9+ CAP0_DATA21 0 88 65 D VCC3 0 CAP0_DATA22 0 0 0 64 D 0 63 D 0 0 62 D 0 61 D 0 60 - 0 59 0 58 0 57 0 56 0 55 Page 28 of 222 Document Number: 002-05682 Rev. *K Condition on PCB Set to ground Open Package Pin Number 2, 5, 6, 9, and 12 to 27 3, 4, 7, 8 0 0 0 0 P0_03 EINT4 PPG2_TOUT0 ICU2_IN0 OCU2_OTD0 0 TIN16 CRS CAP0_DATA12 DSP0_DATA_D4- DSP0_DATA1_4 D 45 118 Q RSTX 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 46 117 P MODE 0 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 47 116 N2 JTAG_TMS 0 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 48 115 N2 JTAG_TCK 0 0 0 0 0 0 0 0 0 CAP0_DATA14 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 49 114 N2 JTAG_TDI 0 0 0 0 0 0 0 0 0 CAP0_DATA15 G_DQ0_2 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 50 113 O JTAG_TDO 0 0 0 0 0 0 0 0 0 0 G_CS#1_2 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 51 112 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 0 G_RWDS_2 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 52 111 M X0 0 0 0 0 0 0 0 0 0 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 53 110 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 54 109 - VSS 0 0 0 0 0 0 0 0 0 0 PPG9_TOUT2 0 0 EINT11 0 G_CK_2 0 SEG9 0 CAP0_DATA11 0 P5_11 OCU8_OTD0 ICU8_IN0 PPG8_TOUT0 EINT8 P3_24 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 28 135 S AN28 0 BP0(BH0) PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 29 134 S AN27 0 AN0(AL0) PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 30 133 S AN26 0 AP0(AH0) PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 0 0 0 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 DSP0_DATA0_4 MDC CAP0_DATA0 0 DSP0_CTRL1 C 31 132 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK+ DSP0_CLK D 32 131 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 130 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 129 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 128 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 0 CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 127 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 126 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 125 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 0 CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 39 124 H 0 0 0 0 OCU6_OTD0 ICU6_IN0 PPG6_TOUT0 EINT4 P3_20 0 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 123 H 0 0 SGO3 TIN35 OCU5_OTD1 ICU5_IN1 PPG5_TOUT2 EINT3 P3_19 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 122 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 121 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 120 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_02 EINT3 PPG1_TOUT2 ICU1_IN1 OCU1_OTD1 0 TOT16 COL CAP0_DATA11 DSP0_DATA_D4+ DSP0_DATA0_4 D 44 119 - VCC5 0 0 0 0 0 0 0 0 0 0 MFS9_CS0 0 PWM2M0 0 MFS10_SCL BN0(BL0) 0 201 0 0 202 AN29 DSP0_DATA1_11 - S 0 Y 136 0 VCC53 27 DSP0_DATA0_11 DSP1_DATA0_4 - 0 0 VCC3_LVDS_Tx 0 0 0 0 0 0 DSP0_DATA1_10 0 0 0 0 0 0 0 SIN10 0 0 0 0 0 0 0 0 AIN9 0 0 0 0 0 0 0 0 P3_25 0 0 ICU10_IN0 OCU10_OTD0 P3_26 PPG8_TOUT2 EINT9 0 0 PPG9_TOUT0 EINT10 OCU8_OTD1 ICU8_IN1 0 0 OCU9_OTD0 ICU9_IN0 PWM1P1 0 0 PWM1M1 AP1(AH1) 0 EINT12 PPG10_TOUT0 AN1(AL1) 0 0 0 0 AN30 0 SEG8 AN31 S 0 0 S 137 TOP VIEW TEQFP-216 0 P5_12 138 26 0 0 0 25 - 0 MFS9_CS1 0 B VSS_LVDS_Tx 0 0 TxDOUT0- 0 0 0 0 0 0 203 0 0 0 - 0 0 0 VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P3_27 0 0 PPG9_TOUT2 EINT11 0 0 OCU9_OTD1 ICU9_IN1 0 0 PWM2P1 0 0 BP1(BH1) 0 0 0 0 0 AN32 0 0 S 0 0 0 139 0 0 24 0 204 B 0 Y TxDOUT0+ 0 DSP1_DATA1_3 0 0 0 0 0 DSP0_CTRL0 0 0 0 0 0 0 0 0 0 ICU10_IN1 OCU10_OTD1 BIN9 0 0 EINT13 PPG10_TOUT2 0 0 0 SEG7 P3_28 0 P5_13 PPG10_TOUT0 EINT12 0 0 0 OCU10_OTD0ICU10_IN0 0 0 PWM2M1 0 205 BN1(BL1) 0 Y 0 0 DSP1_DATA0_3 AN33 0 0 S 0 DSP0_CTRL1 140 0 0 SOT11 23 0 ZIN9 B 0 0 ICU11_IN0 OCU11_OTD0 TxDOUT10 EINT14 PPG11_TOUT0 0 0 SEG6 0 0 P5_14 0 0 MFS8_CS3 0 0 0 0 0 0 206 0 0 0 207 0 0 Y 0 0 Y 0 0 0 DSP1_DATA1_2 0 0 0 DSP1_DATA0_2 0 0 0 DSP1_CLK 0 0 0 DSP0_CTRL2 DSP1_CTRL2 0 0 0 DSP0_CTRL3 0 0 0 0 SCK11 DVSS 0 0 0 SIN11 - 0 0 0 141 0 0 0 22 0 0 OCU0_OTD0 B 0 0 ICU0_IN0 TxDOUT1+ 0 0 ICU11_IN1 OCU11_OTD1 0 0 0 0 0 PPG0_TOUT0 0 0 EINT0 0 0 EINT15 PPG11_TOUT2 0 0 0 SEG5 0 0 SEG4 0 0 P5_15 0 0 0 P5_16 P3_29 0 0 MFS8_CS1 0 PPG10_TOUT2 EINT13 0 0 MFS8_CS2 0 OCU10_OTD1ICU10_IN1 0 0 0 PWM1P2 0 0 0 0 0 0 208 0 DVCC 0 Y AN34 - 0 0 DSP1_DATA1_1 S 142 0 0 0 DSP0_CTRL4 DSP1_CTRL0 143 21 0 0 0 0 0 20 B 0 0 0 0 0 0 B TxCLK0 0 0 0 0 0 TxCLK+ 0 0 0 0 0 0 OCU0_OTD1 0 0 0 0 0 0 0 ICU0_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPG0_TOUT2 0 0 0 0 0 0 0 EINT1 P3_30 0 0 0 0 0 SEG3 PPG11_TOUT0 EINT14 0 0 0 0 0 P5_17 OCU11_OTD0ICU11_IN0 0 0 0 0 0 0 0 PWM1M2 0 0 0 0 0 0 0 0 0 209 0 0 0 Y AN35 0 DSP1_DATA0_1 S 0 DSP0_CTRL5 DSP1_CTRL1 144 0 0 0 SOT12 19 0 0 0 B 0 0 OCU1_OTD0 TxDOUT20 0 ICU1_IN0 0 0 0 0 0 0 0 PPG1_TOUT0 0 0 0 0 EINT2 0 P3_31 0 0 SEG2 0 P4_00 PPG11_TOUT2 EINT15 0 0 P5_18 0 P4_01 PPG0_TOUT0 EINT0 OCU11_OTD1ICU11_IN1 0 0 MFS12_SDA 0 0 P4_02 PPG0_TOUT2 EINT1 OCU0_OTD0 ICU0_IN0 PWM2P2 0 0 0 P4_03 PPG1_TOUT0 EINT2 OCU0_OTD1 ICU0_IN1 PWM2M2 0 0 0 210 PPG1_TOUT2 EINT3 OCU1_OTD0 ICU1_IN0 PWM1P3 0 0 0 0 211 OCU1_OTD1 ICU1_IN1 PWM1M3 0 0 AN36 0 0 Y PWM2P3 0 0 AN37 S 0 Y 0 SOT2 AN38 S 145 0 DSP1_DATA1_0 SCK2 AN39 S 146 18 0 DSP1_DATA0_0 AN40 S 147 17 B 0 0 S 148 16 B TxDOUT2+ 0 0 149 15 B TxDOUT3- 0 0 DSP0_CTRL6 14 - TxDOUT3+ 0 0 0 DSP0_CTRL7 - VSS_LVDS_Tx 0 0 0 0 SCK12 VCC3_LVDS_Tx 0 0 0 0 SIN12 0 0 0 0 0 0 0 0 0 OCU1_OTD1 0 P4_04 0 OCU2_OTD0 0 0 ICU1_IN1 0 PPG2_TOUT0 EINT4 0 ICU2_IN0 0 0 0 0 OCU2_OTD0 ICU2_IN0 0 0 0 PWM2M3 0 PPG1_TOUT2 0 0 0 PPG2_TOUT0 0 SIN2 0 EINT3 0 AN41 0 EINT4 DVSS S 0 SEG1 150 0 SEG0 151 13 0 P5_19 12 0 P5_20 - AVCC3_LVDS_PLL 0 0 0 AVSS_LVDS_PLL 0 0 MFS12_SCL 0 0 0 0 0 0 0 0 0 212 0 0 213 0 0 214 0 0 215 0 0 216 0 0 0 - 0 0 0 Y 0 0 0 Y DVCC 0 0 Y - 0 0 Y 152 0 0 VCC53 11 0 0 DSP1_CLK 0 0 DSP1_CTRL2 VCC12 0 0 DSP1_CTRL1 0 0 0 DSP1_CTRL0 P4_05 0 0 0 PPG2_TOUT2 EINT5 0 0 0 OCU2_OTD1 ICU2_IN1 0 0 0 PWM1P4 0 0 0 0 0 0 0 0 0 0 AN42 DAC_L DSP0_CTRL8 S 0 DSP0_CTRL9 153 0 0 0 10 0 0 0 0 SOT11 0 VSS 0 0 SCK11 DSP0_CTRL10 0 MFS0_CS0 0 0 SIN11 DSP0_CTRL11 MFS2_CS0 P4_06 0 0 P4_07 PPG3_TOUT0 EINT6 0 0 PPG3_TOUT2 EINT7 OCU3_OTD0 ICU3_IN0 0 0 OCU3_OTD1 ICU3_IN1 PWM1M4 0 0 PWM2P4 0 0 0 0 SOT3 0 OCU0_OTD1 SCK3 AN43 0 OCU1_OTD0 SGA1 AN44 S 0 OCU1_OTD1 SGO1 S 154 0 OCU2_OTD0 155 9 0 0 8 - ICU0_IN1 A AVCC3_DAC ICU1_IN0 0 C_L AVSS 0 ICU1_IN1 MFS2_CS1 0 ICU2_IN0 P4_08 0 0 PPG4_TOUT0 EINT8 0 0 OCU4_OTD0 ICU4_IN0 0 0 PWM2M4 0 0 0 0 0 SIN3 0 0 AN45 0 PPG0_TOUT2 S 0 PPG1_TOUT0 156 0 PPG1_TOUT2 0 7 0 PPG2_TOUT0 0 A 0 0 P4_09 0 EINT9 PPG4_TOUT2 EINT9 0 EINT10 OCU4_OTD1 ICU4_IN1 0 EINT11 PWM1P5 5 EINT12 0 4 VSS 0 0 3 A AVSS COM3 AN46 2 A C_R 0 COM2 S - DAC_R 0 0 COM1 MFS4_SDA 157 1 AVSS 0 0 0 COM0 MFS4_SCL MFS0_CS3 6 - 0 0 0 0 0 0 MFS0_CS1 P4_10 0 0 0 0 0 P4_25 MFS0_CS2 P4_11 0 0 0 0 0 P4_26 0 P4_12 PPG5_TOUT0 EINT10 0 0 0 0 0 P4_27 0 0 PPG5_TOUT2 EINT11 0 0 0 0 0 P4_28 0 0 PPG6_TOUT0 EINT12 OCU5_OTD0 ICU5_IN0 0 0 0 0 0 0 0 0 0 OCU5_OTD1 ICU5_IN1 PWM1M5 0 0 0 0 0 0 0 0 0 OCU6_OTD0 ICU6_IN0 PWM2P5 0 0 0 0 0 0 0 0 0 0 PWM2M5 RX1 SOT4 0 0 0 0 0 0 0 0 0 TX1 SCK4 AN47 0 0 0 0 0 0 0 0 0 SIN4 AN48 S 0 0 0 0 0 0 0 0 AN49 S 158 0 0 0 0 0 0 0 DVSS S 159 0 0 0 0 0 0 DVCC 160 0 0 0 0 0 161 0 0 0 0 Any function at the following pins is not supported. - 162 0 0 0 Notes: - The pins highlighted in "red" font are not supported for products with revision A and C. S6J3200 Series Figure 4-8: TEQFP-216 (S6J32KELxx) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDICATOR0_1 0 0 0 MFS8_CS2 0 MFS8_CS1 0 MFS8_CS3 0 MFS9_CS1 0 MFS9_CS0 0 MFS8_CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P2_16 P2_17 P3_17 P3_16 P3_15 P3_14 P3_13 P3_12 P3_11 P3_10 P3_09 P3_08 P3_07 P2_19 0 0 0 0 0 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 V0 V1 V2 V3 0 0 0 EINT0 EINT1 EINT1 EINT0 EINT15 EINT14 EINT13 EINT12 EINT11 EINT10 EINT9 EINT8 0 0 PPG0_TOUT2 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 PPG2_TOUT0 PPG1_TOUT2 PPG1_TOUT0 PPG0_TOUT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN48 0 0 0 ICU0_IN0 ICU0_IN1 ICU4_IN1 ICU4_IN0 FRT4/5/6/7_TEXT ICU3_IN1 PPG0_TOUT0 PPG6/7/8/9/10/11_TIN EINT7 PPG11_TOUT2 EINT3 0 PPG0_TOUT0 ICU3_IN0 ICU2_IN1 ICU2_IN0 ICU1_IN1 ICU1_IN0 ICU0_IN1 ICU0_IN0 ICU1_IN1 0 0 0 OCU0_OTD0 OCU0_OTD1 0 0 TIN18 OCU0_OTD0 WOT TOT18 0 0 TOT19 0 0 0 0 0 0 OCU2_OTD0 SGO0 TOT32 SOT10 0 TIN19 0 OCU2_OTD1 SGA0 TIN32 SCK10 0 0 0 OCU3_OTD0 SGA1 TOT33 SIN10 0 0 OCU3_OTD1 SGO1 TIN33 SOT11 OCU0_OTD1 0 0 OCU4_OTD0 SGA2 TOT34 SCK11 OCU1_OTD0 0 OCU4_OTD1 SGO2 TIN34 SIN11 OCU1_OTD1 0 0 0 SIN9 SCK9 SOT9 0 0 0 0 0 0 TX6 RX6 TX5 RX5 0 0 TX6 RX6 TX5 RX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN19 AN18 AN17 AN16 AN15 0 VSS VCC5 - X X W W W W W W W W V V V U - - 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_10 P5_09 P5_08 P5_07 P5_06 P5_05 0 0 0 0 P5_04 P5_03 P5_02 P5_01 P5_00 P4_31 P4_30 P4_29 0 0 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 0 0 0 0 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 0 0 EINT10 EINT9 EINT8 EINT7 EINT6 EINT5 0 0 0 0 EINT4 EINT3 EINT2 EINT1 EINT0 EINT15 EINT14 EINT13 0 0 PPG9_TOUT0 PPG8_TOUT2 PPG8_TOUT0 PPG7_TOUT2 PPG7_TOUT0 PPG6_TOUT2 0 0 0 0 PPG6_TOUT0 PPG5_TOUT2 PPG5_TOUT0 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICU9_IN0 ICU8_IN1 ICU8_IN0 ICU7_IN1 ICU7_IN0 ICU6_IN1 0 0 0 0 ICU6_IN0 ICU5_IN1 ICU5_IN0 ICU4_IN1 ICU4_IN0 ICU3_IN1 ICU3_IN0 ICU2_IN1 0 0 OCU9_OTD0 BIN8 OCU8_OTD1 OCU8_OTD0 OCU7_OTD1 OCU7_OTD0 OCU6_OTD1 0 0 0 0 OCU6_OTD0 OCU5_OTD1 OCU5_OTD0 OCU4_OTD1 OCU4_OTD0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU3_OTD0 SGA3 0 0 OCU3_OTD1 SGO3 OCU2_OTD1 AIN8 0 0 0 0 SOT10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIN9 SCK9 SOT9 0 0 0 0 0 SIN8 SCK8 SOT8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BN1(BL1) BP1(BH1) AN1(AL1) AP1(AH1) BN0(BL0) BP0(BH0) AN0(AL0) AP0(AH0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_DATA0_5 DSP1_DATA1_5 DSP1_DATA0_6 DSP1_DATA1_6 DSP1_DATA0_7 DSP1_DATA1_7 VCC53 VSS VCC12 VCC12 DSP1_DATA0_8 DSP1_DATA1_8 DSP1_DATA0_9 DSP1_DATA1_9 0 DSP1_DATA1_10 0 DSP1_DATA0_11 0 DSP1_DATA1_11 0 DSP1_DATA1_4 0 DSP1_DATA0_10 0 DSP1_DATA0_4 VCC53 VSS Y Y Y Y Y Y Y Y - - - - Y Y Y Y Y Y Y Y - - 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 0 TOT17 0 0 MFS8_CS0 0 0 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 0 MFS10_SDA 0 SCK10 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 H I J J I I I I I J J I I I I I L - 0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 0 0 SOT0 SCK0 SIN0 0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 TIN49 0 0 0 0 0 TIN0 TIN1 TIN2 TIN3 TOT0 TOT1 TOT2 TOT3 SGA1 SGO1 SGA2 SGO2 SGA3 SGO3 SGO0 SGA0 SGA1 SGO1 TOT16 SGO2 TIN17 0 0 SGA0 TIN16 SGA2 0 SGO0 0 0 0 BIN8 OCU4_OTD1 ZIN8 OCU5_OTD0 0 ZIN9 OCU7_OTD1 0 0 0 0 0 0 0 OCU6_OTD0 BIN9 OCU7_OTD0 0 OCU5_OTD1 AIN9 OCU6_OTD1 0 OCU3_OTD0 AIN8 OCU4_OTD0 0 0 OCU8_OTD0 OCU8_OTD1 OCU9_OTD0 OCU9_OTD1 ICU4_IN0 ICU4_IN1 ICU5_IN0 ICU5_IN1 ICU6_IN0 ICU6_IN1 ICU7_IN0 ICU7_IN1 ICU8_IN0 ICU8_IN1 ICU9_IN0 ICU9_IN1 0 0 0 0 0 0 0 0 0 0 0 0 PPG3_TOUT0 PPG4_TOUT0 PPG4_TOUT2 PPG5_TOUT0 PPG5_TOUT2 PPG6_TOUT2 PPG7_TOUT0 FRT8/9/10/11_TEXT PPG7_TOUT2 0 0 PPG0/1/2/3/4/5_TIN1 PPG6_TOUT0 OCU11_OTD0 ICU11_IN0 0 0 0 OCU10_OTD1 ICU10_IN1 0 0 ICU3_IN0 0 OCU10_OTD0 ICU10_IN0 0 0 0 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG9_TOUT2 EINT8 EINT9 EINT15 P2_31 0 PPG11_TOUT0 EINT6 0 0 P2_25 0 EINT14 P2_30 0 EINT3 P2_24 0 EINT13 P2_29 0 EINT2 P2_22 0 EINT12 P2_28 0 EINT1 P3_00 0 P3_01 0 P3_02 0 P3_03 0 P3_04 0 P3_05 0 P3_06 0 0 0 0 0 0 0 0 0 0 0 EINT11 P2_27 INDICATOR0_0 0 EINT0 0 EINT10 P2_26 0 PPG10_TOUT2 EINT5 0 EINT6 PPG10_TOUT0 EINT4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC_1 0 G P0_28 0 0 0 90 P0_27 0 0 0 0 EINT3 0 P0_26 0 G_DQ7_1 0 0 EINT2 0 0 G_DQ6_1 0 0 PPG4_TOUT2 EINT1 0 G_DQ5_1 0 G_CS#2_1 0 G_DQ4_1 0 0 0 0 P1_02 M_DQ7_0 0 0 G_RWDS_1 0 0 0 G_CS#1_1 0 0 0 0 0 0 0 G_DQ0_1 0 0 0 0 EINT9 P1_00 M_DQ5_0 EINT10 P1_03 M_DQ6_0 G_DQ1_1 0 0 ICU4_IN1 0 0 P1_01 M_DQ4_0 G_DQ2_1 0 0 0 0 PPG7_TOUT2 EINT7 0 P0_31 M_CS#2_0 G_DQ3_1 DSP0_CTRL1 0 0 0 PPG8_TOUT0 EINT8 0 0 0 0 SIN1 OCU4_OTD1 0 0 PPG6_TOUT2 EINT6 0 0 DSP0_CTRL0 0 SCK1 0 0 0 PPG7_TOUT0 0 P0_30 M_RWDS_0 G_CK_1 DSP0_CLK 0 0 SOT1 0 ICU7_IN1 0 PPG6_TOUT0 0 0 DSP0_CTRL2 0 0 0 ICU8_IN0 0 0 EINT5 0 0 0 0 0 OCU7_OTD1 ICU6_IN1 0 0 0 0 0 0 0 0 OCU8_OTD0 ICU7_IN0 0 PPG5_TOUT2 0 0 VCC5 0 0 0 OCU6_OTD1 ICU6_IN0 0 EINT11 P1_04 M_DQ0_0 0 0 - CRS 0 0 0 OCU7_OTD0 0 0 0 EINT13 P1_06 M_DQ1_0 0 0 G_DQ7_2 89 0 0 0 0 OCU6_OTD0 0 0 G_DQ6_2 0 0 0 0 0 0 ICU5_IN1 P1_09 M_CK_0 0 0 EINT12 P1_05 M_DQ3_0 0 0 0 G_DQ5_2 0 0 0 0 0 0 0 0 PPG10_TOUT2 EINT15 P1_08 M_CS#1_0 0 0 P5_22 0 G_DQ4_2 0 0 0 0 0 OCU5_OTD1 0 PPG8_TOUT2 0 P0_17 0 PPG10_TOUT0 EINT14 P1_07 M_DQ2_0 PPG9_TOUT2 0 P0_16 0 0 0 CAP0_DATA25 0 0 0 CAP0_DATA24 0 0 0 0 0 0 PPG9_TOUT0 EINT2 P0_15 0 0 DSP0_CTRL4 0 0 0 0 0 0 0 OCU10_OTD1 ICU10_IN1 0 0 ICU8_IN1 0 EINT1 PPG11_TOUT0 EINT0 0 EINT0 0 DSP0_CTRL3 0 0 0 0 0 0 ICU9_IN1 0 EINT15 P0_14 0 PPG10_TOUT0 EINT4 0 EINT14 P0_13 0 0 MLBCLK DSP0_CTRL2 0 0 0 0 0 0 OCU8_OTD1 0 OCU10_OTD0 ICU10_IN0 0 OCU9_OTD1 0 PPG9_TOUT0 EINT13 P0_12 0 0 MLBSIG 0 0 0 0 0 0 0 ICU9_IN0 0 PPG8_TOUT2 0 0 F MLBDAT 0 0 0 0 0 0 0 0 PPG8_TOUT0 0 F VCC3 G_SDATA0_3 0 0 0 0 0 0 OCU9_OTD0 0 PPG7_TOUT2 0 F VSS G_SSEL0 0 0 0 0 0 0 0 0 OCU11_OTD0 ICU11_IN0 0 0 0 PPG7_TOUT0 0 - M_SDATA1_3 G_SDATA0_1 0 0 0 0 0 0 0 PPG6_TOUT2 0 - M_SSEL1 G_SDATA0_2 0 0 0 0 0 0 0 0 0 86 E M_SDATA1_1 G_SDATA0_0 0 0 0 0 0 0 0 0 85 E M_SDATA1_2 0 0 0 0 0 0 0 0 0 0 84 E M_SDATA1_0 0 0 0 0 0 0 0 0 OCU10_OTD0 ICU10_IN0 0 0 ICU9_IN0 0 0 83 E VCC3 G_SCLK0 0 0 0 0 0 0 ICU8_IN1 0 0 82 E VSS 0 0 0 0 0 0 ICU8_IN0 0 81 - 0 G_SDATA1_3 0 0 0 0 0 ICU7_IN1 0 80 - VSS G_SSEL1 0 0 0 0 ICU7_IN0 0 79 E M_SDATA0_3 G_SDATA1_1 0 0 0 0 OCU9_OTD0 ICU6_IN1 0 78 - M_SSEL0 G_SDATA1_2 0 0 0 OCU8_OTD1 0 0 77 E M_SDATA0_1 G_SDATA1_0 0 0 0 OCU8_OTD0 0 76 E M_SDATA0_2 0 0 0 TXER OCU7_OTD1 0 75 E M_SDATA0_0 0 0 0 OCU7_OTD0 0 74 E VCC3 0 0 0 OCU6_OTD1 0 73 E VSS 0 CAP0_DATA34 0 0 0 0 72 - M_SCLK0 0 0 0 71 - VSS DSP0_CTRL2 TIN35 I2S1_SCK 0 0 70 E VCC12 0 TOT35 I2S1_WS 0 VSS 69 - DSP0_CTRL0 COL 0 VCC12 68 - DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK RXCLK TIN33 I2S0_SCK DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 I2S1_SD DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 TXCLK TOT33 I2S0_WS DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 - 67 C DSP0_DATA1_9 DSP0_DATA_D9- - 66 D DSP0_DATA0_9 DSP0_DATA_D9+ CAP0_DATA21 0 88 65 D VCC3 87 64 D 0 63 D 0 CAP0_DATA22 0 0 0 0 62 D 0 61 D 0 60 - 0 59 0 58 0 57 0 56 0 55 Page 29 of 222 Document Number: 002-05682 Rev. *K Condition on PCB Set to ground Open Package Pin Number 2, 5, 6, 9 3, 4, 7, 8 0 SIN10 0 0 0 0 0 0 0 0 0 VCC12 - 28 135 S AN28 0 BP0(BH0) PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 29 134 S AN27 0 AN0(AL0) PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 30 133 S AN26 0 AP0(AH0) PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 0 0 0 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 DSP0_DATA0_4 MDC CAP0_DATA0 0 DSP0_CTRL1 C 31 132 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK+ DSP0_CLK D 32 131 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 130 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 129 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 128 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 0 CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 127 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 126 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 125 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 0 CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 39 124 H 0 0 0 0 OCU6_OTD0 ICU6_IN0 PPG6_TOUT0 EINT4 P3_20 0 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 123 H 0 0 SGO3 TIN35 OCU5_OTD1 ICU5_IN1 PPG5_TOUT2 EINT3 P3_19 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 122 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 121 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 120 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_02 EINT3 PPG1_TOUT2 ICU1_IN1 OCU1_OTD1 0 TOT16 COL CAP0_DATA11 DSP0_DATA_D4+ DSP0_DATA0_4 D 44 119 - VCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_03 EINT4 PPG2_TOUT0 ICU2_IN0 OCU2_OTD0 0 TIN16 CRS CAP0_DATA12 DSP0_DATA_D4- DSP0_DATA1_4 D 45 118 Q RSTX 0 0 0 0 0 0 0 0 0 CAP0_DATA11 G_CK_2 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 46 117 P MODE 0 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 47 116 N2 JTAG_TMS 0 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 48 115 N2 JTAG_TCK 0 0 0 0 0 0 0 0 0 CAP0_DATA14 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 49 114 N2 JTAG_TDI 0 0 0 0 0 0 0 0 0 CAP0_DATA15 G_DQ0_2 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 50 113 O JTAG_TDO 0 0 0 0 0 0 0 0 0 0 G_CS#1_2 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 51 112 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 0 G_RWDS_2 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 52 111 M X0 0 0 0 0 0 0 0 0 0 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 53 110 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 54 109 - VSS 0 0 0 0 0 0 0 0 0 0 ZIN8 0 0 0 AIN9 P3_24 0 OCU9_OTD1 PPG8_TOUT0 EINT8 0 ICU9_IN1 OCU8_OTD0 ICU8_IN0 0 0 PWM2M0 0 0 ICU10_IN0 OCU10_OTD0 BN0(BL0) 0 PPG9_TOUT2 0 DSP0_DATA1_11 EINT11 AN29 0 EINT12 PPG10_TOUT0 S 0 SEG9 136 TOP VIEW TEQFP-216 DSP0_DATA0_11 SEG8 27 0 P5_11 - 0 P5_12 VCC3_LVDS_Tx 0 MFS9_CS0 0 0 DSP0_DATA1_10 MFS9_CS1 0 0 0 0 0 0 MFS10_SCL 0 0 202 0 0 - 0 0 VCC53 0 0 0 0 0 0 0 0 0 0 0 P3_25 0 0 P3_26 PPG8_TOUT2 EINT9 0 0 PPG9_TOUT0 EINT10 OCU8_OTD1 ICU8_IN1 0 0 OCU9_OTD0 ICU9_IN0 PWM1P1 0 0 PWM1M1 AP1(AH1) 0 0 AN1(AL1) 0 0 0 0 AN30 0 0 AN31 S 0 0 S 137 0 0 138 26 0 0 0 25 - 0 0 B VSS_LVDS_Tx 0 203 TxDOUT0- 0 0 - 0 0 0 VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P3_27 0 0 PPG9_TOUT2 EINT11 0 0 OCU9_OTD1 ICU9_IN1 0 0 PWM2P1 0 0 BP1(BH1) 0 0 0 0 0 0 AN32 0 0 S 0 204 139 0 205 24 0 Y B 0 Y TxDOUT0+ 0 DSP1_DATA1_3 0 0 DSP1_DATA0_3 0 0 0 0 0 0 0 0 DSP0_CTRL0 0 0 DSP0_CTRL1 0 0 0 0 0 0 0 P3_28 0 0 SOT11 PPG10_TOUT0 EINT12 0 ZIN9 OCU10_OTD0ICU10_IN0 0 0 ICU10_IN1 OCU10_OTD1 BIN9 PWM2M1 0 0 ICU11_IN0 OCU11_OTD0 BN1(BL1) 0 EINT13 PPG10_TOUT2 0 0 EINT14 PPG11_TOUT0 AN33 0 SEG7 S 0 0 SEG6 140 0 0 P5_13 23 0 0 P5_14 B 0 0 0 0 TxDOUT10 0 MFS8_CS3 0 0 0 0 0 0 0 0 0 0 0 0 206 0 0 0 Y 0 0 0 DSP1_DATA1_2 0 0 0 DSP0_CTRL2 DSP1_CTRL2 0 0 0 0 SCK11 0 0 0 0 0 0 0 0 ICU11_IN1 OCU11_OTD1 0 0 0 EINT15 PPG11_TOUT2 0 0 0 SEG5 0 0 0 P5_15 0 0 0 MFS8_CS1 0 0 0 0 0 0 DVSS 0 207 DVCC - 0 Y 141 0 DSP1_DATA0_2 142 22 0 DSP1_CLK 21 B 0 DSP0_CTRL3 B TxDOUT1+ 0 0 SIN11 TxCLK- 0 0 0 0 0 0 OCU0_OTD0 0 0 0 ICU0_IN0 0 0 0 0 0 0 0 PPG0_TOUT0 0 0 0 EINT0 P3_29 0 SEG4 PPG10_TOUT2 EINT13 0 P5_16 OCU10_OTD1ICU10_IN1 0 MFS8_CS2 0 PWM1P2 0 0 0 0 208 0 0 209 AN34 0 0 Y S 0 0 0 Y 143 0 0 0 0 DSP1_DATA1_1 20 0 0 0 0 0 DSP1_DATA0_1 B 0 0 0 0 0 DSP0_CTRL4 DSP1_CTRL0 TxCLK+ 0 0 0 0 0 DSP0_CTRL5 DSP1_CTRL1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOT12 0 0 0 0 0 0 0 0 P3_30 0 0 0 0 0 0 PPG11_TOUT0 EINT14 0 0 0 0 0 OCU0_OTD1 OCU11_OTD0ICU11_IN0 0 0 0 0 0 OCU1_OTD0 PWM1M2 0 0 0 0 ICU0_IN1 0 0 0 0 ICU1_IN0 0 0 0 0 AN35 0 0 S 0 PPG0_TOUT2 144 0 0 PPG1_TOUT0 19 0 0 EINT1 B 0 0 EINT2 TxDOUT20 0 SEG3 0 0 0 SEG2 0 0 0 P5_17 0 0 0 0 P5_18 0 P3_31 0 0 0 0 0 P4_00 PPG11_TOUT2 EINT15 0 0 MFS12_SDA 0 0 P4_01 PPG0_TOUT0 EINT0 OCU11_OTD1ICU11_IN1 0 0 0 0 P4_02 PPG0_TOUT2 EINT1 OCU0_OTD0 ICU0_IN0 PWM2P2 0 0 0 P4_03 PPG1_TOUT0 EINT2 OCU0_OTD1 ICU0_IN1 PWM2M2 0 0 0 210 PPG1_TOUT2 EINT3 OCU1_OTD0 ICU1_IN0 PWM1P3 0 0 0 0 Y OCU1_OTD1 ICU1_IN1 PWM1M3 0 0 AN36 0 0 DSP1_DATA1_0 PWM2P3 0 0 AN37 S 0 0 0 SOT2 AN38 S 145 0 DSP0_CTRL6 SCK2 AN39 S 146 18 0 0 SCK12 AN40 S 147 17 B 0 0 S 148 16 B TxDOUT2+ 0 OCU1_OTD1 149 15 B TxDOUT3- 0 0 ICU1_IN1 14 - TxDOUT3+ 0 0 0 0 - VSS_LVDS_Tx 0 0 0 PPG1_TOUT2 VCC3_LVDS_Tx 0 0 0 EINT3 0 0 0 SEG1 0 0 P5_19 0 0 MFS12_SCL 0 0 P4_04 0 0 0 0 211 0 PPG2_TOUT0 EINT4 0 Y 0 0 DSP1_DATA0_0 0 OCU2_OTD0 ICU2_IN0 0 0 0 PWM2M3 0 DSP0_CTRL7 0 0 0 0 SIN12 0 SIN2 0 0 0 AN41 0 OCU2_OTD0 DVSS S 0 ICU2_IN0 150 0 0 151 13 0 PPG2_TOUT0 12 0 EINT4 - AVCC3_LVDS_PLL 0 SEG0 AVSS_LVDS_PLL 0 0 P5_20 0 0 0 0 0 0 0 0 0 212 0 0 213 0 0 214 0 0 215 0 0 216 0 0 0 - 0 0 0 Y 0 0 0 Y DVCC 0 0 Y - 0 0 Y 152 0 0 VCC53 11 0 0 DSP1_CLK 0 0 DSP1_CTRL2 VCC12 0 0 DSP1_CTRL1 0 0 0 DSP1_CTRL0 P4_05 0 0 0 PPG2_TOUT2 EINT5 0 0 0 OCU2_OTD1 ICU2_IN1 0 0 0 PWM1P4 0 0 0 0 0 0 0 0 0 0 AN42 DAC_L DSP0_CTRL8 S 0 DSP0_CTRL9 153 0 0 0 10 0 0 0 0 SOT11 0 VSS 0 0 SCK11 DSP0_CTRL10 0 MFS0_CS0 0 0 SIN11 DSP0_CTRL11 MFS2_CS0 P4_06 0 0 P4_07 PPG3_TOUT0 EINT6 0 0 PPG3_TOUT2 EINT7 OCU3_OTD0 ICU3_IN0 0 0 OCU3_OTD1 ICU3_IN1 PWM1M4 0 0 PWM2P4 0 0 0 0 SOT3 0 OCU0_OTD1 SCK3 AN43 0 OCU1_OTD0 SGA1 AN44 S 0 OCU1_OTD1 SGO1 S 154 0 OCU2_OTD0 155 9 0 0 8 - ICU0_IN1 A AVCC3_DAC ICU1_IN0 0 C_L AVSS 0 ICU1_IN1 MFS2_CS1 0 ICU2_IN0 P4_08 0 0 PPG4_TOUT0 EINT8 0 0 OCU4_OTD0 ICU4_IN0 0 0 PWM2M4 0 0 0 0 0 SIN3 0 0 AN45 0 PPG0_TOUT2 S 0 PPG1_TOUT0 156 0 PPG1_TOUT2 0 7 0 PPG2_TOUT0 0 A 0 0 P4_09 0 EINT9 PPG4_TOUT2 EINT9 0 EINT10 OCU4_OTD1 ICU4_IN1 0 EINT11 PWM1P5 5 EINT12 0 4 VSS 0 0 3 A AVSS COM3 AN46 2 A C_R 0 COM2 S - DAC_R 0 0 COM1 MFS4_SDA 157 1 AVSS 0 0 0 COM0 MFS4_SCL MFS0_CS3 6 - 0 0 0 0 0 0 MFS0_CS1 P4_10 0 0 0 0 0 P4_25 MFS0_CS2 P4_11 0 0 0 0 0 P4_26 0 P4_12 PPG5_TOUT0 EINT10 0 0 0 0 0 P4_27 0 0 PPG5_TOUT2 EINT11 0 0 0 0 0 P4_28 0 0 PPG6_TOUT0 EINT12 OCU5_OTD0 ICU5_IN0 0 0 0 0 0 0 0 0 0 OCU5_OTD1 ICU5_IN1 PWM1M5 0 0 0 0 0 0 0 0 0 OCU6_OTD0 ICU6_IN0 PWM2P5 0 0 0 0 0 0 0 0 0 0 PWM2M5 RX1 SOT4 0 0 0 0 0 0 0 0 0 TX1 SCK4 AN47 0 0 0 0 0 0 0 0 0 SIN4 AN48 S 0 0 0 0 0 0 0 0 AN49 S 158 0 0 0 0 0 0 0 DVSS S 159 0 0 0 0 0 0 DVCC 160 0 0 0 0 0 161 0 0 0 0 Any function at the following pins is not supported. - 162 0 0 0 Notes: - The pins highlighted in "red" font are not supported for products with revision A and C. S6J3200 Series TEQPF-208 Pin Assignment 4.1.2 Figure 4-9: TEQFP-208 (S6J328CKxx, S6J329CKxx, S6J32MEKxx) 0 0 P2_19 0 0 0 0 0 0 V1 EINT8 0 0 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 PPG2_TOUT0 PPG0_TOUT2 0 0 0 0 0 FRT4/5/6/7_TEXT 0 0 0 0 PPG0_TOUT0 PPG6/7/8/9/10/11_TIN V2 EINT7 PPG11_TOUT2 V3 EINT3 PPG4_TOUT2 0 ICU2_IN1 0 0 0 ICU0_IN0 ICU0_IN1 ICU4_IN1 ICU4_IN0 ICU3_IN1 ICU3_IN0 ICU2_IN1 ICU2_IN0 ICU0_IN1 ICU0_IN0 OCU4_OTD0 0 0 OCU0_OTD0 OCU0_OTD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIN8 SCK8 SOT8 0 0 0 0 0 0 0 0 0 0 OCU3_OTD1 SGO1 TIN33 SOT11 OCU3_OTD0 SGA1 TOT33 SIN10 OCU2_OTD1 SGA0 TIN32 SCK10 OCU2_OTD0 SGO0 TOT32 SOT10 OCU0_OTD0 WOT TOT18 0 OCU4_OTD0 SGA2 TOT34 SCK11 0 TIN18 0 OCU4_OTD1 SGO2 TIN34 SIN11 OCU0_OTD1 0 OCU3_OTD0 SGA3 0 0 OCU3_OTD1 SGO3 OCU2_OTD1 0 0 SIN9 SCK9 SOT9 0 0 0 0 0 BN1(BL1) BP1(BH1) AN1(AL1) AP1(AH1) BN0(BL0) BP0(BH0) AN0(AL0) AP0(AH0) 0 0 0 0 0 TX6 RX6 TX5 RX5 0 0 TX5 RX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC12 DSP1_DATA0_8 DSP1_DATA1_8 DSP1_DATA0_9 DSP1_DATA1_9 0 DSP1_DATA1_11 0 VCC12 0 DSP1_DATA0_11 0 VSS 0 DSP1_DATA1_10 0 VCC53 0 DSP1_DATA0_10 0 DSP1_DATA1_7 VCC53 VSS VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN17 AN16 AN15 0 Y - - - - Y Y Y Y Y Y Y Y - - - X X W W W W W W V V V U 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 157 0 0 P3_07 V0 EINT9 PPG0_TOUT2 0 ICU3_IN0 OCU4_OTD1 0 0 158 0 MFS8_CS0 0 P3_12 SEG29 EINT12 PPG0_TOUT0 0 ICU3_IN1 OCU5_OTD0 0 0 - 0 MFS9_CS0 0 P3_13 SEG28 EINT13 0 0 ICU4_IN0 OCU5_OTD1 0 - 0 0 MFS9_CS1 0 P3_14 SEG27 EINT14 0 0 P3_08 EINT0 MFS8_CS3 0 P3_15 SEG26 EINT15 0 0 P3_09 EINT1 0 0 ICU4_IN1 0 OCU6_OTD0 0 VSS 0 0 MFS8_CS1 0 P3_16 SEG25 EINT1 0 0 ICU5_IN0 0 0 VCC5 0 0 MFS8_CS2 0 P3_17 SEG24 EINT0 PPG2_TOUT2 0 ICU5_IN1 0 0 0 0 0 0 PPG3_TOUT0 0 0 ICU6_IN0 0 0 0 0 0 0 PPG3_TOUT2 0 0 OCU6_OTD1 187 0 0 0 0 PPG4_TOUT0 0 0 188 0 0 0 0 0 P2_17 0 PPG4_TOUT2 0 0 Y 189 0 0 0 0 PPG5_TOUT0 0 ICU6_IN1 Y 190 0 0 0 0 PPG5_TOUT2 0 DSP1_DATA0_7 Y 191 0 0 0 0 0 0 0 PPG6_TOUT0 0 DSP1_DATA1_6 Y 0 0 0 0 0 INDICATOR0_1 0 P2_16 0 0 0 P4_29 SEG23 EINT13 0 EINT0 0 0 P4_30 SEG22 EINT14 0 EINT1 0 0 P4_31 SEG21 EINT15 0 0 EINT2 0 0 0 DSP1_DATA0_6 Y 0 0 0 0 0 P5_00 SEG20 EINT3 0 0 DSP1_DATA1_5 0 0 0 0 0 P5_01 SEG19 0 EINT4 0 0 0 DSP1_DATA0_5 0 0 0 0 0 P5_02 SEG18 0 PPG6_TOUT2 0 0 0 0 0 0 0 P5_03 SEG17 0 SOT9 0 0 0 0 0 0 0 0 P5_04 SEG16 0 0 SCK9 0 0 0 0 0 EINT5 0 SIN9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU7_OTD0 0 0 0 0 0 0 0 0 OCU7_OTD1 0 0 SOT10 0 0 0 0 0 0 ICU7_IN0 OCU8_OTD0 AIN8 0 0 0 0 0 ICU7_IN1 OCU8_OTD1 0 0 0 0 0 0 ICU8_IN0 OCU9_OTD0 BIN8 0 0 0 0 0 P5_05 SEG15 0 ICU8_IN1 0 0 0 PPG7_TOUT0 0 ICU9_IN0 0 0 0 PPG7_TOUT2 0 0 0 0 EINT6 PPG8_TOUT0 0 0 0 0 0 P5_06 SEG14 EINT7 PPG8_TOUT2 0 0 0 0 P5_07 SEG13 EINT8 PPG9_TOUT0 ICU1_IN1 0 0 0 0 P5_08 SEG12 EINT9 TIN48 0 0 0 0 P5_09 SEG11 0 0 0 MFS8_CS0 0 P5_10 SEG10 EINT10 0 TOT17 0 0 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 0 0 MFS10_SDA - DVSS 0 0 0 0 0 0 0 0 0 134 S AN33 0 BN1(BL1) PWM2M1 OCU10_OTD0 ICU10_IN0 PPG10_TOUT0 EINT12 P3_28 0 24 133 S AN32 0 BP1(BH1) PWM2P1 OCU9_OTD1 ICU9_IN1 PPG9_TOUT2 EINT11 P3_27 0 B 25 132 S AN31 0 AN1(AL1) PWM1M1 OCU9_OTD0 ICU9_IN0 PPG9_TOUT0 EINT10 P3_26 0 VSS_LVDS_Tx - 26 131 S AN30 0 AP1(AH1) PWM1P1 OCU8_OTD1 ICU8_IN1 PPG8_TOUT2 EINT9 P3_25 0 0 0 0 0 0 0 0 0 0 0 VCC3_LVDS_Tx - 27 130 S AN29 0 BN0(BL0) PWM2M0 OCU8_OTD0 ICU8_IN0 PPG8_TOUT0 EINT8 P3_24 0 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 28 129 S AN28 0 BP0(BH0) PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 29 128 S AN27 0 AN0(AL0) PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 127 S AN26 0 AP0(AH0) PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 0 126 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 30 0 0 0 0 0 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 DSP0_DATA0_4 MDC CAP0_DATA0 0 DSP0_CTRL1 C 31 DSP0_DATA0_11 0 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK+ DSP0_CLK D 32 125 - DVSS 0 0 0 0 0 0 0 0 DSP0_DATA1_11 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 124 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 123 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 122 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 0 CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 121 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 120 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 119 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 0 CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 39 118 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 117 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 116 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 115 - VCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 114 Q RSTX 0 0 0 0 0 0 0 0 CAP0_DATA11 G_CK_2 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 44 113 P MODE 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 45 112 N2 JTAG_TMS 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 46 111 N2 JTAG_TCK 0 0 0 0 0 0 0 0 CAP0_DATA14 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 47 110 N2 JTAG_TDI 0 0 0 0 0 0 0 0 CAP0_DATA15 G_DQ0_2 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 48 109 O JTAG_TDO 0 0 0 0 0 0 0 0 0 G_CS#1_2 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 49 108 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 G_RWDS_2 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 50 107 M X0 0 0 0 0 0 0 0 0 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 51 106 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 52 105 - VSS 0 0 0 0 0 0 0 0 TOP VIEW TEQFP-208 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 D D D D C - - E - - E E E E E - E - - E E E E E - - F F F - - - G H J J I I I I J J I I I I I L - VCC3 DSP0_DATA0_9 DSP0_DATA_D9+ CAP0_DATA21 0 DSP0_DATA1_9 DSP0_DATA_D9- DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK DSP0_CTRL0 VCC12 VSS M_SCLK0 VSS VCC3 M_SDATA0_0 M_SDATA0_2 M_SDATA0_1 M_SSEL0 M_SDATA0_3 VSS 0 VSS VCC3 M_SDATA1_0 M_SDATA1_2 M_SDATA1_1 M_SSEL1 M_SDATA1_3 VSS VCC3 MLBDAT MLBSIG MLBCLK VCC12 VSS VCC5 PSC_1 0 AN1 AN2 AN3 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 DSP0_CTRL2 0 0 0 0 0 G_SDATA1_0 G_SDATA1_2 G_SDATA1_1 G_SSEL1 G_SDATA1_3 0 G_SCLK0 0 0 G_SDATA0_0 G_SDATA0_2 G_SDATA0_1 G_SSEL0 G_SDATA0_3 0 0 DSP0_CTRL2 DSP0_CTRL3 DSP0_CTRL4 0 0 0 0 0 SOT0 SCK0 SIN0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 CAP0_DATA34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0_DATA25 0 0 0 CAP0_DATA24 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 RXCLK TIN33 I2S0_SCK DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 I2S1_SD DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 TXCLK TOT33 I2S0_WS COL 0 TXER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 TOT35 I2S1_WS TIN35 I2S1_SCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN1 TIN2 TIN3 TOT0 TOT1 TOT2 TOT3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGA0 SGA1 SGO1 SGO2 SGA3 SGO3 SGO0 SGA0 SGA1 SGO1 TOT16 SGO2 TIN17 0 0 0 TIN16 SGA2 0 0 TIN49 0 0 0 0 0 0 0 0 DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU9_OTD0 OCU8_OTD1 OCU5_OTD1 0 0 OCU6_OTD0 OCU7_OTD0 OCU6_OTD1 OCU8_OTD0 OCU7_OTD1 0 0 0 0 0 0 OCU3_OTD0 OCU5_OTD1 OCU8_OTD0 OCU8_OTD1 OCU9_OTD0 OCU9_OTD1 ICU8_IN1 ICU9_IN0 0 0 0 0 ICU9_IN0 ICU9_IN1 ICU8_IN1 0 ICU5_IN1 0 0 ICU6_IN0 ICU7_IN0 ICU6_IN1 ICU8_IN0 ICU7_IN1 0 0 0 0 ICU4_IN1 0 0 0 0 ICU3_IN0 ICU4_IN1 ICU5_IN0 ICU5_IN1 ICU6_IN1 ICU7_IN0 ICU7_IN1 ICU8_IN0 ICU8_IN1 ICU9_IN0 ICU9_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPG6_TOUT2 PPG7_TOUT0 PPG7_TOUT2 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 0 0 0 PPG9_TOUT0 PPG8_TOUT2 PPG5_TOUT2 0 0 PPG6_TOUT0 PPG7_TOUT0 PPG6_TOUT2 PPG8_TOUT0 PPG7_TOUT2 0 0 0 0 PPG4_TOUT2 0 0 0 0 PPG3_TOUT0 PPG4_TOUT2 PPG5_TOUT0 PPG5_TOUT2 PPG6_TOUT2 PPG7_TOUT0 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG9_TOUT2 EINT1 EINT2 0 0 0 0 0 0 EINT6 EINT8 EINT7 0 0 EINT1 EINT2 EINT3 0 0 0 0 EINT6 EINT9 0 0 P0_30 M_RWDS_0 0 0 P1_00 M_DQ5_0 P1_02 M_DQ7_0 P0_28 0 0 0 0 0 0 P2_25 0 P3_00 0 P3_01 0 P3_02 0 P3_03 0 P3_04 0 P3_05 0 P3_06 0 0 0 P2_22 0 0 0 P0_27 0 0 0 P0_26 0 0 0 P1_01 M_DQ4_0 0 0 P0_31 M_CS#2_0 0 0 EINT15 P2_31 0 PPG11_TOUT0 EINT6 0 0 EINT14 P2_30 0 EINT3 0 0 P1_09 M_CK_0 0 0 EINT13 P2_29 0 EINT2 0 0 0 0 G_DQ4_2 G_DQ5_2 G_DQ6_2 G_DQ7_2 0 0 0 0 0 G_CK_1 0 0 G_DQ3_1 G_DQ2_1 G_DQ1_1 G_DQ0_1 0 0 G_DQ5_1 G_DQ6_1 G_DQ7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP0_CTRL2 DSP0_CLK DSP0_CTRL0 DSP0_CTRL1 0 0 0 0 0 0 0 0 0 0 0 G_CS#2_1 0 G_DQ4_1 0 G_RWDS_1 0 0 0 G_CS#1_1 0 EINT11 P2_27 INDICATOR0_0 0 EINT1 0 EINT10 P2_26 0 EINT0 P5_22 0 EINT10 P1_03 M_DQ6_0 EINT9 P0_17 0 EINT11 P1_04 M_DQ0_0 EINT5 P0_16 0 EINT13 P1_06 M_DQ1_0 0 P0_15 0 EINT12 P1_05 M_DQ3_0 PPG10_TOUT2 EINT5 0 EINT0 PPG10_TOUT0 EINT4 0 EINT15 P0_14 0 PPG10_TOUT2 EINT15 P1_08 M_CS#1_0 0 EINT14 P0_13 0 PPG10_TOUT0 EINT14 P1_07 M_DQ2_0 PPG9_TOUT2 EINT13 P0_12 0 PPG11_TOUT0 EINT0 0 0 PPG10_TOUT0 EINT4 FRT8/9/10/11_TEXT PPG7_TOUT2 OCU11_OTD0 ICU11_IN0 0 0 0 OCU10_OTD1 ICU10_IN1 0 0 ICU8_IN0 OCU10_OTD0 ICU10_IN0 0 0 ICU7_IN1 OCU10_OTD1 ICU10_IN1 0 0 ICU7_IN0 OCU10_OTD0 ICU10_IN0 0 OCU9_OTD1 ICU6_IN1 OCU11_OTD0 ICU11_IN0 0 ZIN9 OCU7_OTD1 0 0 0 OCU10_OTD0 ICU10_IN0 0 BIN9 OCU7_OTD0 0 OCU9_OTD0 AIN9 OCU6_OTD1 0 OCU8_OTD1 ZIN8 OCU5_OTD0 0 OCU8_OTD0 BIN8 OCU4_OTD1 0 OCU7_OTD1 SIN1 OCU4_OTD1 0 OCU7_OTD0 SCK1 0 0 OCU6_OTD1 SOT1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 CAP0_DATA22 0 0 0 0 60 D 0 59 D 0 58 - 0 57 0 56 0 55 0 54 0 53 Page 30 of 222 Document Number: 002-05682 Rev. *K 192 135 23 B TxDOUT0- 0 0 0 Y 22 B TxDOUT0+ 0 0 DSP0_DATA1_10 0 DSP1_DATA1_4 B TxDOUT1- 0 0 0 0 0 TxDOUT1+ 0 0 0 0 0 0 0 0 0 0 0 0 0 SCK10 0 0 0 0 0 0 ZIN8 0 0 0 0 0 0 OCU9_OTD1 0 0 0 0 0 0 ICU9_IN1 0 0 0 0 0 0 0 0 0 0 0 0 PPG9_TOUT2 0 0 0 0 SEG9 EINT11 0 0 0 MFS9_CS0 0 P5_11 0 0 0 MFS10_SCL 0 0 193 0 0 0 Y P3_29 0 0 DSP1_DATA0_4 EINT13 0 0 0 PPG10_TOUT2 0 0 0 ICU10_IN1 0 0 0 SIN10 OCU10_OTD1 0 0 AIN9 PWM1P2 0 0 0 ICU10_IN0 OCU10_OTD0 0 0 0 SEG8 EINT12 PPG10_TOUT0 0 DVCC 0 MFS9_CS1 0 P5_12 AN34 - 0 0 S 136 0 0 137 21 0 194 20 B 0 - B TxCLK- 0 VCC53 TxCLK+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P3_30 0 0 EINT14 0 0 PPG11_TOUT0 0 0 0 ICU11_IN0 0 0 OCU11_OTD0 0 0 PWM1M2 0 195 0 0 196 0 0 - AN35 0 Y S 0 VSS 138 0 DSP1_DATA1_3 19 0 0 B 0 0 TxDOUT2- 0 0 0 0 DSP0_CTRL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P3_31 0 0 EINT15 0 0 ICU10_IN1 OCU10_OTD1 BIN9 PPG11_TOUT2 0 0 ICU11_IN1 0 0 OCU11_OTD1 0 0 PWM2P2 0 SEG7 EINT13 PPG10_TOUT2 0 0 0 0 0 0 0 AN36 0 0 0 P5_13 S 0 0 139 0 0 18 0 0 B 0 0 TxDOUT2+ 0 197 0 0 Y 0 0 DSP1_DATA0_3 0 0 0 0 0 DSP0_CTRL1 0 0 0 SOT11 0 0 ZIN9 0 0 0 0 ICU11_IN0 OCU11_OTD0 0 P4_00 0 SEG6 EINT14 PPG11_TOUT0 P4_01 EINT0 0 MFS8_CS3 0 P5_14 EINT1 PPG0_TOUT0 0 0 PPG0_TOUT2 ICU0_IN0 0 0 ICU0_IN1 OCU0_OTD0 0 198 OCU0_OTD1 PWM2M2 0 Y PWM1P3 0 0 DSP1_DATA1_2 0 0 0 0 DSP0_CTRL2 DSP1_CTRL2 0 AN37 0 0 0 SCK11 AN38 S 0 0 0 S 140 0 0 0 ICU11_IN1 OCU11_OTD1 141 17 0 0 SEG5 EINT15 PPG11_TOUT2 16 B 0 0 MFS8_CS1 0 P5_15 B TxDOUT30 0 0 TxDOUT3+ 0 0 0 0 0 0 0 0 199 0 0 0 0 200 0 0 0 Y 0 0 0 Y 0 0 0 DSP1_DATA0_2 0 0 DSP1_DATA1_1 P4_02 0 DSP1_CLK EINT2 0 DSP0_CTRL3 PPG1_TOUT0 0 DSP0_CTRL4 DSP1_CTRL0 ICU1_IN0 0 0 OCU1_OTD0 0 0 SIN11 PWM1M3 0 0 0 0 0 SOT2 0 0 AN39 0 OCU0_OTD0 S 0 OCU0_OTD1 142 0 ICU0_IN0 15 0 ICU0_IN1 0 0 VSS_LVDS_Tx 0 0 0 0 PPG0_TOUT0 0 0 PPG0_TOUT2 0 0 EINT0 0 0 0 EINT1 0 0 SEG4 P4_03 0 SEG3 EINT3 0 0 0 P5_17 PPG1_TOUT2 0 MFS8_CS2 0 P5_16 ICU1_IN1 0 0 OCU1_OTD1 0 0 PWM2P3 0 0 0 0 0 SCK2 0 201 AN40 0 Y S 0 DSP1_DATA0_1 143 0 DSP0_CTRL5 DSP1_CTRL1 14 0 0 SOT12 0 0 VCC3_LVDS_Tx 0 OCU1_OTD0 0 0 ICU1_IN0 0 0 0 0 0 0 PPG1_TOUT0 0 0 EINT2 P4_04 0 0 SEG2 EINT4 0 0 MFS12_SDA 0 P5_18 PPG2_TOUT0 0 0 0 ICU2_IN0 0 0 0 OCU2_OTD0 0 0 202 PWM2M3 0 0 Y 0 0 0 DSP1_DATA1_0 SIN2 0 0 0 AN41 0 0 DSP0_CTRL6 S 0 0 0 SCK12 144 0 0 0 13 0 0 OCU1_OTD1 0 0 ICU1_IN1 AVCC3_LVDS_PLL 0 0 0 0 0 PPG1_TOUT2 0 0 0 EINT3 0 0 0 SEG1 0 0 0 MFS12_SCL 0 P5_19 0 0 0 0 0 0 0 0 0 0 0 203 0 0 0 Y 0 0 0 DSP1_DATA0_0 0 0 0 0 0 0 0 DSP0_CTRL7 0 DVSS 0 0 SIN12 DVCC - 0 0 145 0 OCU2_OTD0 146 12 0 ICU2_IN0 11 0 0 - AVSS_LVDS_PLL 0 PPG2_TOUT0 VCC12 0 0 EINT4 0 0 0 SEG0 0 0 0 0 P5_20 P4_05 0 0 EINT5 0 0 PPG2_TOUT2 0 204 ICU2_IN1 0 205 OCU2_OTD1 0 206 PWM1P4 0 207 0 0 208 0 0 - AN42 0 Y S 0 Y 147 0 Y 10 0 Y 0 VCC53 0 VSS C_L DSP1_CLK MFS0_CS0 0 DSP1_CTRL2 P4_06 0 DSP1_CTRL1 EINT6 0 DSP1_CTRL0 PPG3_TOUT0 0 0 ICU3_IN0 0 0 OCU3_OTD0 0 0 PWM1M4 0 0 0 0 0 SOT3 0 0 AN43 0 DSP0_CTRL8 S 0 DSP0_CTRL9 148 0 0 0 9 0 0 0 0 SOT11 0 AVSS 0 0 SCK11 DSP0_CTRL10 MFS2_CS0 0 0 SIN11 DSP0_CTRL11 P4_07 A 0 EINT7 - DAC_L 0 PPG3_TOUT2 AVCC3_DAC 0 0 ICU3_IN1 0 0 0 OCU3_OTD1 0 0 0 PWM2P4 0 0 OCU0_OTD1 0 0 0 OCU1_OTD0 SGA1 SCK3 0 0 OCU1_OTD1 SGO1 AN44 0 0 OCU2_OTD0 S 0 0 0 149 0 0 ICU0_IN1 8 0 0 ICU1_IN0 0 A 0 0 ICU1_IN1 0 MFS2_CS1 0 0 ICU2_IN0 0 P4_08 0 0 0 P4_09 EINT8 0 0 0 EINT9 PPG4_TOUT0 0 0 0 PPG4_TOUT2 ICU4_IN0 0 0 0 ICU4_IN1 OCU4_OTD0 0 0 OCU4_OTD1 PWM2M4 5 0 PWM1P5 0 4 VSS PPG0_TOUT2 0 SIN3 3 A AVSS PPG1_TOUT0 0 AN45 2 A C_R 0 PPG1_TOUT2 AN46 S - DAC_R 0 0 PPG2_TOUT0 0 MFS4_SDA S 150 1 AVSS 0 0 0 0 0 MFS4_SCL MFS0_CS3 151 7 - 0 0 0 0 0 0 P4_25 COM3 EINT9 0 MFS0_CS1 P4_10 6 0 0 0 0 0 0 0 P4_26 COM2 EINT10 MFS0_CS2 P4_11 EINT10 0 0 0 0 0 0 0 P4_27 COM1 EINT11 P4_12 EINT11 PPG5_TOUT0 0 0 0 0 0 0 0 P4_28 COM0 EINT12 0 EINT12 PPG5_TOUT2 ICU5_IN0 0 0 0 0 0 0 0 0 0 PPG6_TOUT0 ICU5_IN1 OCU5_OTD0 0 0 0 0 0 0 0 0 ICU6_IN0 OCU5_OTD1 PWM1M5 0 0 0 0 0 0 0 0 OCU6_OTD0 PWM2P5 0 0 0 0 0 0 0 0 0 PWM2M5 RX1 SOT4 0 0 0 0 0 0 0 0 TX1 SCK4 AN47 0 0 0 0 0 0 0 0 SIN4 AN48 S 0 0 0 0 0 0 0 0 AN49 S 152 0 0 0 0 0 0 0 DVSS S 153 0 0 0 0 0 0 DVCC 154 0 0 0 0 0 155 0 0 0 0 156 0 0 0 Notes: - The pins highlighted in "red" font are not supported for products with revision A and C. S6J3200 Series Figure 4-10: TEQFP-208 (S6J327CKxx) 0 0 0 0 0 0 0 ICU2_IN1 ICU2_IN0 ICU0_IN1 ICU0_IN0 0 0 0 0 0 0 OCU3_OTD1 SGO1 TIN33 SOT11 OCU3_OTD0 SGA1 TOT33 SIN10 OCU2_OTD1 SGA0 TIN32 SCK10 OCU2_OTD0 SGO0 TOT32 SOT10 OCU0_OTD0 WOT TOT18 0 OCU4_OTD0 SGA2 TOT34 SCK11 0 TIN18 0 OCU4_OTD1 SGO2 TIN34 SIN11 OCU0_OTD1 0 0 0 SIN9 SCK9 SOT9 BP0(BH0) AN0(AL0) AP0(AH0) 0 0 0 0 0 TX6 RX6 TX5 RX5 0 0 TX5 RX5 0 0 0 DSP1_DATA0_11 0 DSP1_DATA1_11 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_DATA1_9 0 DSP1_DATA1_10 0 DSP1_DATA0_9 0 DSP1_DATA0_10 0 DSP1_DATA1_8 VCC53 VSS VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN17 AN16 AN15 - Y Y Y Y Y Y Y Y - - - X X W W W W W W V V V 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 157 0 0 V3 EINT3 0 PPG0_TOUT0 PPG6/7/8/9/10/11_TIN V2 EINT7 PPG11_TOUT2 0 ICU3_IN0 0 0 0 BN0(BL0) 0 - 185 - 0 0 P2_19 V1 EINT8 PPG0_TOUT2 FRT4/5/6/7_TEXT ICU3_IN1 0 ICU4_IN0 OCU0_OTD1 0 0 0 AP1(AH1) 0 VCC12 DSP1_DATA0_8 - VCC5 0 0 P3_07 PPG2_TOUT0 0 ICU4_IN1 0 OCU0_OTD0 0 0 0 AN1(AL1) 0 VCC12 - 0 0 0 P3_08 V0 EINT9 PPG2_TOUT2 0 ICU0_IN1 0 0 0 0 BP1(BH1) 0 VSS 0 0 0 0 P3_09 PPG3_TOUT0 0 0 ICU0_IN0 0 0 0 SOT8 0 VCC53 0 0 MFS8_CS0 0 P3_12 SEG29 EINT12 PPG3_TOUT2 0 0 OCU3_OTD0 SGA3 0 SCK8 0 BN1(BL1) 0 186 0 0 0 MFS9_CS0 0 P3_13 SEG28 EINT13 PPG4_TOUT0 0 0 OCU3_OTD1 SGO3 OCU2_OTD1 0 0 0 0 187 0 0 0 MFS9_CS1 0 P3_14 SEG27 EINT14 PPG4_TOUT2 0 ICU2_IN1 0 0 0 SIN8 0 Y 0 0 0 MFS8_CS3 0 P3_15 SEG26 EINT15 PPG0_TOUT2 0 ICU3_IN0 OCU4_OTD0 0 0 0 0 Y 188 0 0 0 EINT0 0 PPG0_TOUT0 0 ICU3_IN1 OCU4_OTD1 0 0 0 DSP1_DATA1_7 189 0 0 0 MFS8_CS1 0 P3_16 SEG25 EINT1 0 0 ICU4_IN0 OCU5_OTD0 0 0 0 DSP1_DATA0_7 Y 0 0 0 MFS8_CS2 0 P3_17 SEG24 EINT1 0 0 ICU4_IN1 OCU5_OTD1 0 0 0 Y 0 0 0 0 0 EINT0 PPG2_TOUT2 0 ICU5_IN0 0 0 0 DSP1_DATA1_6 158 0 0 0 PPG3_TOUT0 0 ICU5_IN1 0 OCU6_OTD0 0 0 DSP1_DATA0_6 - 0 0 0 P2_17 0 0 PPG3_TOUT2 0 0 0 0 0 VSS 0 0 0 0 0 PPG4_TOUT0 0 0 ICU6_IN0 0 0 0 0 0 0 0 0 0 0 PPG4_TOUT2 0 0 0 SOT9 0 0 0 0 0 0 INDICATOR0_1 0 P2_16 0 0 0 P4_29 SEG23 EINT13 PPG5_TOUT0 0 0 0 0 0 0 0 0 0 P4_30 SEG22 EINT14 0 EINT0 0 0 P4_31 SEG21 EINT15 0 0 EINT1 PPG5_TOUT2 0 0 0 SIN9 SCK9 0 0 0 0 0 P5_00 SEG20 EINT2 0 PPG6_TOUT0 0 0 0 0 0 0 0 0 P5_01 SEG19 EINT3 0 0 0 0 0 0 0 0 0 P5_02 SEG18 0 EINT4 0 OCU6_OTD1 0 0 0 0 0 0 P5_03 SEG17 0 0 OCU7_OTD0 0 0 0 0 0 0 0 P5_04 SEG16 0 ICU6_IN1 OCU7_OTD1 0 0 0 0 0 ICU7_IN0 OCU8_OTD0 0 0 0 0 0 0 ICU7_IN1 159 0 0 0 0 0 ICU8_IN0 U 0 0 0 0 0 PPG6_TOUT2 0 0 0 0 0 0 0 PPG7_TOUT0 0 0 0 0 0 0 EINT5 PPG7_TOUT2 0 0 0 0 0 EINT6 PPG8_TOUT0 0 0 0 0 0 0 P5_05 SEG15 EINT7 AIN8 0 0 0 0 0 P5_06 SEG14 EINT8 OCU8_OTD1 0 0 0 0 0 P5_07 SEG13 ICU8_IN1 0 0 0 0 0 P5_08 SEG12 0 ICU1_IN1 0 0 PPG8_TOUT2 TIN48 0 0 EINT9 0 0 0 0 P5_09 SEG11 0 0 0 0 DSP1_DATA0_5 DSP1_DATA1_5 Y Y 191 190 0 TOT17 0 0 0 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 0 0 SOT10 0 OCU9_OTD0 BIN8 PPG9_TOUT0 ICU9_IN0 MFS8_CS0 0 P5_10 SEG10 EINT10 192 0 MFS10_SDA Y OCU9_OTD1 DSP1_DATA1_4 ICU9_IN1 0 0 0 PPG9_TOUT2 0 SCK10 SEG9 EINT11 ZIN8 MFS9_CS0 0 P5_11 ICU11_IN0 PPG11_TOUT0 EINT14 P3_30 0 OCU10_OTD1 ICU10_IN1 PPG10_TOUT2 EINT13 P3_29 0 0 0 0 0 0 0 0 0 0 0 TxCLK- B 21 136 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT1+ B 22 135 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT1- B 23 134 S AN33 0 BN1(BL1) PWM2M1 OCU10_OTD0 ICU10_IN0 PPG10_TOUT0 EINT12 P3_28 0 0 0 0 0 0 0 0 0 0 0 TxDOUT0+ B 24 133 S AN32 0 BP1(BH1) PWM2P1 OCU9_OTD1 ICU9_IN1 PPG9_TOUT2 EINT11 P3_27 0 0 0 0 0 0 0 0 0 0 0 TxDOUT0- B 25 132 S AN31 0 AN1(AL1) PWM1M1 OCU9_OTD0 ICU9_IN0 PPG9_TOUT0 EINT10 P3_26 0 0 0 0 0 0 0 0 0 0 0 0 VSS_LVDS_Tx - 26 131 S AN30 0 AP1(AH1) PWM1P1 OCU8_OTD1 ICU8_IN1 PPG8_TOUT2 EINT9 P3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3_LVDS_Tx - 27 130 S AN29 0 BN0(BL0) PWM2M0 OCU8_OTD0 ICU8_IN0 PPG8_TOUT0 EINT8 P3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 28 129 S AN28 0 BP0(BH0) PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 29 128 S AN27 0 AN0(AL0) PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 30 127 S AN26 0 AP0(AH0) PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 0 0 0 0 0 0 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 DSP0_DATA0_4 MDC CAP0_DATA0 0 DSP0_CTRL1 C 31 126 - DVCC 0 0 0 0 0 0 0 0 DSP0_DATA0_11 0 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK+ DSP0_CLK D 32 125 - DVSS 0 0 0 0 0 0 0 0 DSP0_DATA1_11 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 124 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 123 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 122 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 0 CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 121 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 120 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 119 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 0 CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 39 118 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 117 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 116 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 115 - VCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 114 Q RSTX 0 0 0 0 0 0 0 0 CAP0_DATA11 G_CK_2 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 44 113 P MODE 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 45 112 N2 JTAG_TMS 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 46 111 N2 JTAG_TCK 0 0 0 0 0 0 0 0 CAP0_DATA14 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 47 110 N2 JTAG_TDI 0 0 0 0 0 0 0 0 CAP0_DATA15 G_DQ0_2 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 48 109 O JTAG_TDO 0 0 0 0 0 0 0 0 0 G_CS#1_2 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 49 108 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 G_RWDS_2 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 50 107 M X0 0 0 0 0 0 0 0 0 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 51 106 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 52 105 - VSS 0 0 0 0 0 0 0 0 TOP VIEW TEQFP-208 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 D D D D C - - E - - E E E E E - E - - E E E E E - - F F F - - - G H J J I I I I J J I I I I I L - VCC3 DSP0_DATA0_9 DSP0_DATA_D9+ CAP0_DATA21 0 DSP0_DATA1_9 DSP0_DATA_D9- DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK DSP0_CTRL0 VCC12 VSS M_SCLK0 VSS VCC3 M_SDATA0_0 M_SDATA0_2 M_SDATA0_1 M_SSEL0 M_SDATA0_3 VSS 0 VSS VCC3 M_SDATA1_0 M_SDATA1_2 M_SDATA1_1 M_SSEL1 M_SDATA1_3 VSS VCC3 MLBDAT MLBSIG MLBCLK VCC12 VSS VCC5 PSC_1 0 AN1 AN2 AN3 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 DSP0_CTRL2 0 0 0 0 0 G_SDATA1_0 G_SDATA1_2 G_SDATA1_1 G_SSEL1 G_SDATA1_3 0 G_SCLK0 0 0 G_SDATA0_0 G_SDATA0_2 G_SDATA0_1 G_SSEL0 G_SDATA0_3 0 0 DSP0_CTRL2 DSP0_CTRL3 DSP0_CTRL4 0 0 0 0 0 SOT0 SCK0 SIN0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 CAP0_DATA34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0_DATA25 0 0 0 CAP0_DATA24 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 RXCLK TIN33 I2S0_SCK DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 I2S1_SD DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 TXCLK TOT33 I2S0_WS COL 0 TXER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 TOT35 I2S1_WS TIN35 I2S1_SCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN1 TIN2 TIN3 TOT0 TOT1 TOT2 TOT3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGA0 SGA1 SGO1 SGO2 SGA3 SGO3 SGO0 SGA0 SGA1 SGO1 TOT16 SGO2 TIN17 0 0 0 TIN16 SGA2 0 0 TIN49 0 0 0 0 0 0 0 0 DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU9_OTD0 OCU8_OTD1 OCU5_OTD1 0 0 OCU6_OTD0 OCU7_OTD0 OCU6_OTD1 OCU8_OTD0 OCU7_OTD1 0 0 0 0 0 0 OCU3_OTD0 OCU5_OTD1 OCU8_OTD0 OCU8_OTD1 OCU9_OTD0 OCU9_OTD1 ICU8_IN1 ICU9_IN0 0 0 0 0 ICU9_IN0 ICU9_IN1 ICU8_IN1 0 ICU5_IN1 0 0 ICU6_IN0 ICU7_IN0 ICU6_IN1 ICU8_IN0 ICU7_IN1 0 0 0 0 ICU4_IN1 0 0 0 0 ICU3_IN0 ICU4_IN1 ICU5_IN0 ICU5_IN1 ICU6_IN1 ICU7_IN0 ICU7_IN1 ICU8_IN0 ICU8_IN1 ICU9_IN0 ICU9_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPG6_TOUT2 PPG7_TOUT0 PPG7_TOUT2 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 0 0 0 PPG9_TOUT0 PPG8_TOUT2 PPG5_TOUT2 0 0 PPG6_TOUT0 PPG7_TOUT0 PPG6_TOUT2 PPG8_TOUT0 PPG7_TOUT2 0 0 0 0 PPG4_TOUT2 0 0 0 0 PPG3_TOUT0 PPG4_TOUT2 PPG5_TOUT0 PPG5_TOUT2 PPG6_TOUT2 PPG7_TOUT0 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG9_TOUT2 EINT1 EINT2 0 0 0 0 0 0 EINT6 EINT8 EINT7 0 0 EINT1 EINT2 EINT3 0 0 0 0 EINT6 EINT9 0 0 0 P0_30 M_RWDS_0 0 0 P1_00 M_DQ5_0 P1_02 M_DQ7_0 P0_28 0 0 0 0 0 0 P2_25 0 P3_00 0 P3_01 0 P3_02 0 P3_03 0 P3_04 0 P3_05 0 P3_06 0 0 0 P2_22 0 0 0 P0_27 0 0 0 P0_26 0 0 0 P1_01 M_DQ4_0 0 0 P0_31 M_CS#2_0 0 0 EINT15 P2_31 0 PPG11_TOUT0 EINT6 0 0 EINT14 P2_30 0 EINT3 0 0 P1_09 M_CK_0 EINT13 P2_29 0 EINT2 0 0 0 0 0 G_DQ4_2 G_DQ5_2 G_DQ6_2 G_DQ7_2 0 0 0 0 0 G_CK_1 0 0 G_DQ3_1 G_DQ2_1 G_DQ1_1 G_DQ0_1 0 0 G_DQ5_1 G_DQ6_1 G_DQ7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP0_CTRL2 DSP0_CLK DSP0_CTRL0 DSP0_CTRL1 0 0 0 0 0 0 0 0 0 0 0 G_CS#2_1 0 G_DQ4_1 0 G_RWDS_1 0 0 0 G_CS#1_1 0 EINT11 P2_27 INDICATOR0_0 0 EINT1 0 EINT10 P2_26 0 EINT0 P5_22 0 EINT10 P1_03 M_DQ6_0 EINT9 P0_17 0 EINT11 P1_04 M_DQ0_0 EINT5 P0_16 0 EINT13 P1_06 M_DQ1_0 0 P0_15 0 EINT12 P1_05 M_DQ3_0 PPG10_TOUT2 EINT5 0 EINT0 PPG10_TOUT0 EINT4 0 EINT15 P0_14 0 PPG10_TOUT2 EINT15 P1_08 M_CS#1_0 0 EINT14 P0_13 0 PPG10_TOUT0 EINT14 P1_07 M_DQ2_0 PPG9_TOUT2 EINT13 P0_12 0 PPG11_TOUT0 EINT0 0 0 PPG10_TOUT0 EINT4 FRT8/9/10/11_TEXT PPG7_TOUT2 OCU11_OTD0 ICU11_IN0 0 0 0 OCU10_OTD1 ICU10_IN1 0 0 ICU8_IN0 OCU10_OTD0 ICU10_IN0 0 0 ICU7_IN1 OCU10_OTD1 ICU10_IN1 0 0 ICU7_IN0 OCU10_OTD0 ICU10_IN0 0 OCU9_OTD1 ICU6_IN1 OCU11_OTD0 ICU11_IN0 0 ZIN9 OCU7_OTD1 0 0 0 OCU10_OTD0 ICU10_IN0 0 BIN9 OCU7_OTD0 0 OCU9_OTD0 AIN9 OCU6_OTD1 0 OCU8_OTD1 ZIN8 OCU5_OTD0 0 OCU8_OTD0 BIN8 OCU4_OTD1 0 OCU7_OTD1 SIN1 OCU4_OTD1 0 OCU7_OTD0 SCK1 0 0 OCU6_OTD1 SOT1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 CAP0_DATA22 0 0 0 0 60 D 0 59 D 0 58 - 0 57 0 56 0 55 0 54 0 53 Page 31 of 222 Document Number: 002-05682 Rev. *K Condition on PCB Set to ground Package Pin Number 12 to 27 0 MFS10_SCL OCU11_OTD0 PWM1P2 0 193 PWM1M2 0 0 194 0 0 DSP0_DATA1_10 - 0 AN34 0 Y AN35 S 0 VCC53 S 137 0 DSP1_DATA0_4 138 20 0 0 19 B 0 0 B TxCLK+ 0 0 TxDOUT2- 0 0 0 0 0 0 0 0 0 0 0 SIN10 0 0 0 0 0 0 0 0 0 0 0 AIN9 0 0 0 0 0 0 0 0 0 0 0 0 ICU10_IN0 OCU10_OTD0 0 0 0 0 0 0 P3_31 0 0 EINT15 0 0 PPG11_TOUT2 0 SEG8 EINT12 PPG10_TOUT0 ICU11_IN1 0 0 OCU11_OTD1 0 0 0 PWM2P2 0 MFS9_CS1 0 P5_12 0 0 0 0 0 0 AN36 0 0 S 0 0 139 0 195 18 0 - B 0 VSS TxDOUT2+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P4_00 0 0 EINT0 0 0 PPG0_TOUT0 0 0 0 ICU0_IN0 0 0 OCU0_OTD0 0 0 PWM2M2 0 196 0 0 Y 0 0 DSP1_DATA1_3 AN37 0 0 S 0 DSP0_CTRL0 140 0 0 17 0 0 B 0 0 ICU10_IN1 OCU10_OTD1 BIN9 TxDOUT3- 0 SEG7 EINT13 PPG10_TOUT2 0 0 0 0 P5_13 0 0 0 0 0 0 0 0 197 0 0 Y 0 0 DSP1_DATA0_3 0 0 0 0 0 0 DSP0_CTRL1 P4_01 0 0 SOT11 EINT1 0 ZIN9 PPG0_TOUT2 0 0 ICU11_IN0 OCU11_OTD0 ICU0_IN1 0 SEG6 EINT14 PPG11_TOUT0 OCU0_OTD1 0 MFS8_CS3 0 P5_14 PWM1P3 0 0 0 0 0 0 0 198 AN38 0 199 S 0 Y 141 0 Y 16 0 DSP1_DATA1_2 B 0 DSP1_DATA0_2 TxDOUT3+ 0 DSP1_CLK 0 0 DSP0_CTRL2 DSP1_CTRL2 0 0 DSP0_CTRL3 0 0 0 SCK11 0 0 0 SIN11 0 0 0 0 0 0 0 0 0 0 OCU0_OTD0 0 P4_02 0 ICU0_IN0 P4_03 EINT2 0 0 ICU11_IN1 OCU11_OTD1 EINT3 PPG1_TOUT0 0 0 PPG1_TOUT2 ICU1_IN0 0 PPG0_TOUT0 ICU1_IN1 OCU1_OTD0 0 EINT0 OCU1_OTD1 PWM1M3 0 SEG5 EINT15 PPG11_TOUT2 PWM2P3 0 0 0 SEG4 0 SOT2 0 0 MFS8_CS1 0 P5_15 SCK2 AN39 0 0 MFS8_CS2 0 P5_16 AN40 S 0 0 0 S 142 0 0 0 143 15 0 0 0 14 0 0 0 - VSS_LVDS_Tx 0 0 200 VCC3_LVDS_Tx 0 0 0 Y 0 0 0 0 DSP1_DATA1_1 0 0 0 DSP0_CTRL4 DSP1_CTRL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU0_OTD1 P4_04 0 ICU0_IN1 EINT4 0 0 PPG2_TOUT0 0 PPG0_TOUT2 ICU2_IN0 0 EINT1 OCU2_OTD0 0 SEG3 PWM2M3 0 0 0 P5_17 0 0 0 SIN2 0 0 AN41 0 201 S 0 Y 144 0 DSP1_DATA0_1 13 0 DSP0_CTRL5 DSP1_CTRL1 0 0 SOT12 AVCC3_LVDS_PLL 0 0 0 0 OCU1_OTD0 0 0 ICU1_IN0 0 0 0 0 0 0 PPG1_TOUT0 0 0 EINT2 0 0 SEG2 0 0 MFS12_SDA 0 P5_18 0 0 0 0 0 0 0 0 202 0 0 203 0 0 Y 0 0 Y DVSS 0 DSP1_DATA1_0 - 0 DSP1_DATA0_0 145 0 0 12 0 0 0 DSP0_CTRL6 AVSS_LVDS_PLL 0 DSP0_CTRL7 0 0 0 SCK12 0 0 0 SIN12 0 0 0 0 0 0 0 0 0 0 0 OCU1_OTD1 0 0 0 OCU2_OTD0 0 0 0 ICU1_IN1 0 0 0 ICU2_IN0 0 0 0 0 0 0 0 0 0 0 0 PPG1_TOUT2 0 0 0 PPG2_TOUT0 DVCC 0 0 EINT3 - 0 0 EINT4 146 0 0 SEG1 11 0 0 SEG0 0 0 0 0 P5_20 VCC12 0 MFS12_SCL 0 P5_19 0 0 0 0 0 0 0 0 0 0 0 MFS0_CS0 P4_05 0 0 P4_06 EINT5 0 204 EINT6 PPG2_TOUT2 0 205 PPG3_TOUT0 ICU2_IN1 0 206 ICU3_IN0 OCU2_OTD1 0 207 OCU3_OTD0 PWM1P4 0 208 PWM1M4 0 0 - 0 0 0 Y SOT3 AN42 0 Y AN43 S 0 Y S 147 0 Y 148 10 0 VCC53 9 0 DSP1_CLK - VSS DAC_L DSP1_CTRL2 AVSS 0 0 DSP1_CTRL1 0 0 0 DSP1_CTRL0 MFS2_CS0 0 0 P4_07 0 0 EINT7 0 0 PPG3_TOUT2 0 0 ICU3_IN1 0 0 OCU3_OTD1 0 0 PWM2P4 0 DSP0_CTRL8 0 0 DSP0_CTRL9 SCK3 0 0 0 AN44 0 0 S 0 0 SOT11 149 0 0 SCK11 DSP0_CTRL10 8 0 0 SIN11 DSP0_CTRL11 A 0 0 0 C_L - 0 MFS2_CS1 - AVCC3_DAC 0 P4_08 AVSS 0 0 EINT8 0 0 0 PPG4_TOUT0 0 0 OCU0_OTD1 ICU4_IN0 0 0 OCU1_OTD0 SGA1 OCU4_OTD0 0 0 OCU1_OTD1 SGO1 PWM2M4 0 0 OCU2_OTD0 0 0 0 0 SIN3 0 0 ICU0_IN1 AN45 0 0 ICU1_IN0 S 0 0 ICU1_IN1 0 150 0 0 ICU2_IN0 MFS4_SDA 0 7 0 0 0 MFS0_CS3 P4_09 A 0 0 0 P4_10 EINT9 0 0 0 EINT10 PPG4_TOUT2 0 0 0 PPG5_TOUT0 ICU4_IN1 0 0 0 ICU5_IN0 OCU4_OTD1 0 0 OCU5_OTD0 PWM1P5 4 PPG0_TOUT2 PWM1M5 0 3 A VSS PPG1_TOUT0 0 0 2 A C_R PPG1_TOUT2 SOT4 AN46 - DAC_R 0 PPG2_TOUT0 0 AN47 S 1 AVSS 0 0 0 0 MFS4_SCL S 151 - 0 0 0 0 0 P4_25 COM3 EINT9 0 MFS0_CS1 152 6 0 0 0 0 0 0 P4_26 COM2 EINT10 MFS0_CS2 P4_11 5 0 0 0 0 0 0 P4_27 COM1 EINT11 P4_12 EINT11 0 0 0 0 0 0 P4_28 COM0 EINT12 0 EINT12 PPG5_TOUT2 0 0 0 0 0 0 0 0 PPG6_TOUT0 ICU5_IN1 0 0 0 0 0 0 0 ICU6_IN0 OCU5_OTD1 0 0 0 0 0 0 0 OCU6_OTD0 PWM2P5 0 0 0 0 0 0 0 PWM2M5 RX1 0 0 0 0 0 0 0 TX1 SCK4 0 0 0 0 0 0 0 SIN4 AN48 0 0 0 0 0 0 0 AN49 S 0 0 0 0 0 0 DVSS S 153 0 0 0 0 0 DVCC 154 0 0 0 0 0 155 0 0 0 0 Any function at the following pins is not supported. - 156 0 0 0 Notes: - The pins highlighted in "red" character are not supported for products with revision A and C. S6J3200 Series Figure 4-11: TEQFP-208 (S6J326CKxx, S6J32LEKxx) 0 0 0 0 0 0 0 ICU2_IN1 ICU2_IN0 ICU0_IN1 ICU0_IN0 0 0 0 0 0 0 OCU3_OTD1 SGO1 TIN33 SOT11 OCU3_OTD0 SGA1 TOT33 SIN10 OCU2_OTD1 SGA0 TIN32 SCK10 OCU2_OTD0 SGO0 TOT32 SOT10 OCU0_OTD0 WOT TOT18 0 OCU4_OTD0 SGA2 TOT34 SCK11 0 TIN18 0 OCU4_OTD1 SGO2 TIN34 SIN11 OCU0_OTD1 0 0 0 SIN9 SCK9 SOT9 BP0(BH0) AN0(AL0) AP0(AH0) 0 0 0 0 0 TX6 RX6 TX5 RX5 0 0 TX5 RX5 0 0 0 DSP1_DATA0_11 0 DSP1_DATA1_11 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_DATA1_9 0 DSP1_DATA1_10 0 DSP1_DATA0_9 0 DSP1_DATA0_10 0 DSP1_DATA1_8 VCC53 VSS VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN17 AN16 AN15 - Y Y Y Y Y Y Y Y - - - X X W W W W W W V V V 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 157 0 0 V3 EINT3 0 PPG0_TOUT0 PPG6/7/8/9/10/11_TIN V2 EINT7 PPG11_TOUT2 0 ICU3_IN0 0 0 0 BN0(BL0) 0 - 185 - 0 0 P2_19 V1 EINT8 PPG0_TOUT2 FRT4/5/6/7_TEXT ICU3_IN1 0 ICU4_IN0 OCU0_OTD1 0 0 0 AP1(AH1) 0 VCC12 DSP1_DATA0_8 - VCC5 0 0 P3_07 PPG2_TOUT0 0 ICU4_IN1 0 OCU0_OTD0 0 0 0 AN1(AL1) 0 VCC12 - 0 0 0 P3_08 V0 EINT9 PPG2_TOUT2 0 ICU0_IN1 0 0 0 0 BP1(BH1) 0 VSS 0 0 0 0 P3_09 PPG3_TOUT0 0 0 ICU0_IN0 0 0 0 SOT8 0 VCC53 0 0 MFS8_CS0 0 P3_12 SEG29 EINT12 PPG3_TOUT2 0 0 OCU3_OTD0 SGA3 0 SCK8 0 BN1(BL1) 0 186 0 0 0 MFS9_CS0 0 P3_13 SEG28 EINT13 PPG4_TOUT0 0 0 OCU3_OTD1 SGO3 OCU2_OTD1 0 0 0 0 187 0 0 0 MFS9_CS1 0 P3_14 SEG27 EINT14 PPG4_TOUT2 0 ICU2_IN1 0 0 0 SIN8 0 Y 0 0 0 MFS8_CS3 0 P3_15 SEG26 EINT15 PPG0_TOUT2 0 ICU3_IN0 OCU4_OTD0 0 0 0 0 Y 188 0 0 0 EINT0 0 PPG0_TOUT0 0 ICU3_IN1 OCU4_OTD1 0 0 0 DSP1_DATA1_7 189 0 0 0 MFS8_CS1 0 P3_16 SEG25 EINT1 0 0 ICU4_IN0 OCU5_OTD0 0 0 0 DSP1_DATA0_7 Y 0 0 0 MFS8_CS2 0 P3_17 SEG24 EINT1 0 0 ICU4_IN1 OCU5_OTD1 0 0 0 Y 0 0 0 0 0 EINT0 PPG2_TOUT2 0 ICU5_IN0 0 0 0 DSP1_DATA1_6 158 0 0 0 PPG3_TOUT0 0 ICU5_IN1 0 OCU6_OTD0 0 0 DSP1_DATA0_6 - 0 0 0 P2_17 0 0 PPG3_TOUT2 0 0 0 0 0 VSS 0 0 0 0 0 PPG4_TOUT0 0 0 ICU6_IN0 0 0 0 0 0 0 0 0 0 0 PPG4_TOUT2 0 0 0 SOT9 0 0 0 0 0 0 INDICATOR0_1 0 P2_16 0 0 0 P4_29 SEG23 EINT13 PPG5_TOUT0 0 0 0 0 0 0 0 0 0 P4_30 SEG22 EINT14 0 EINT0 0 0 P4_31 SEG21 EINT15 0 0 EINT1 PPG5_TOUT2 0 0 0 SIN9 SCK9 0 0 0 0 0 P5_00 SEG20 EINT2 0 PPG6_TOUT0 0 0 0 0 0 0 0 0 P5_01 SEG19 EINT3 0 0 0 0 0 0 0 0 0 P5_02 SEG18 0 EINT4 0 OCU6_OTD1 0 0 0 0 0 0 P5_03 SEG17 0 0 OCU7_OTD0 0 0 0 0 0 0 0 P5_04 SEG16 0 ICU6_IN1 OCU7_OTD1 0 0 0 0 0 ICU7_IN0 OCU8_OTD0 0 0 0 0 0 0 ICU7_IN1 159 0 0 0 0 0 ICU8_IN0 U 0 0 0 0 0 PPG6_TOUT2 0 0 0 0 0 0 0 PPG7_TOUT0 0 0 0 0 0 0 EINT5 PPG7_TOUT2 0 0 0 0 0 EINT6 PPG8_TOUT0 0 0 0 0 0 0 P5_05 SEG15 EINT7 AIN8 0 0 0 0 0 P5_06 SEG14 EINT8 OCU8_OTD1 0 0 0 0 0 P5_07 SEG13 ICU8_IN1 0 0 0 0 0 P5_08 SEG12 0 ICU1_IN1 0 0 PPG8_TOUT2 TIN48 0 0 EINT9 0 0 0 0 P5_09 SEG11 0 0 0 0 0 DSP1_DATA0_5 DSP1_DATA1_5 Y Y 191 190 0 TOT17 0 0 0 SOT10 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 0 OCU9_OTD0 BIN8 0 ICU9_IN0 PPG9_TOUT0 192 MFS8_CS0 0 P5_10 SEG10 EINT10 Y 0 MFS10_SDA DSP1_DATA1_4 OCU9_OTD1 0 ICU9_IN1 0 0 0 SCK10 PPG9_TOUT2 ZIN8 SEG9 EINT11 ICU10_IN1 PPG10_TOUT2 EINT13 P3_29 0 0 0 0 0 0 0 0 0 0 0 TxCLK- B 21 136 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT1+ B 22 135 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT1- B 23 134 S AN33 0 BN1(BL1) PWM2M1 OCU10_OTD0 ICU10_IN0 PPG10_TOUT0 EINT12 P3_28 0 0 0 0 0 0 0 0 0 0 0 TxDOUT0+ B 24 133 S AN32 0 BP1(BH1) PWM2P1 OCU9_OTD1 ICU9_IN1 PPG9_TOUT2 EINT11 P3_27 0 0 0 0 0 0 0 0 0 0 0 TxDOUT0- B 25 132 S AN31 0 AN1(AL1) PWM1M1 OCU9_OTD0 ICU9_IN0 PPG9_TOUT0 EINT10 P3_26 0 0 0 0 0 0 0 0 0 0 0 0 VSS_LVDS_Tx - 26 131 S AN30 0 AP1(AH1) PWM1P1 OCU8_OTD1 ICU8_IN1 PPG8_TOUT2 EINT9 P3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3_LVDS_Tx - 27 130 S AN29 0 BN0(BL0) PWM2M0 OCU8_OTD0 ICU8_IN0 PPG8_TOUT0 EINT8 P3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 28 129 S AN28 0 BP0(BH0) PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 29 128 S AN27 0 AN0(AL0) PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 30 127 S AN26 0 AP0(AH0) PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 0 0 0 0 0 0 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 DSP0_DATA0_4 MDC CAP0_DATA0 0 DSP0_CTRL1 C 31 126 - DVCC 0 0 0 0 0 0 0 0 DSP0_DATA0_11 0 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK+ DSP0_CLK D 32 125 - DVSS 0 0 0 0 0 0 0 0 DSP0_DATA1_11 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 124 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 123 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 122 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 0 CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 121 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 120 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 119 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 0 CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 39 118 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 117 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 116 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 115 - VCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 114 Q RSTX 0 0 0 0 0 0 0 0 CAP0_DATA11 G_CK_2 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 44 113 P MODE 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 45 112 N2 JTAG_TMS 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 46 111 N2 JTAG_TCK 0 0 0 0 0 0 0 0 CAP0_DATA14 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 47 110 N2 JTAG_TDI 0 0 0 0 0 0 0 0 CAP0_DATA15 G_DQ0_2 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 48 109 O JTAG_TDO 0 0 0 0 0 0 0 0 0 G_CS#1_2 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 49 108 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 G_RWDS_2 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 50 107 M X0 0 0 0 0 0 0 0 0 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 51 106 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 52 105 - VSS 0 0 0 0 0 0 0 0 TOP VIEW TEQFP-208 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 D D D D C - - E - - E E E E E - E - - E E E E E - - F F F - - - G H J J I I I I J J I I I I I L - VCC3 DSP0_DATA0_9 DSP0_DATA_D9+ CAP0_DATA21 0 DSP0_DATA1_9 DSP0_DATA_D9- DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK DSP0_CTRL0 VCC12 VSS M_SCLK0 VSS VCC3 M_SDATA0_0 M_SDATA0_2 M_SDATA0_1 M_SSEL0 M_SDATA0_3 VSS 0 VSS VCC3 M_SDATA1_0 M_SDATA1_2 M_SDATA1_1 M_SSEL1 M_SDATA1_3 VSS VCC3 MLBDAT MLBSIG MLBCLK VCC12 VSS VCC5 PSC_1 0 AN1 AN2 AN3 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 DSP0_CTRL2 0 0 0 0 0 G_SDATA1_0 G_SDATA1_2 G_SDATA1_1 G_SSEL1 G_SDATA1_3 0 G_SCLK0 0 0 G_SDATA0_0 G_SDATA0_2 G_SDATA0_1 G_SSEL0 G_SDATA0_3 0 0 DSP0_CTRL2 DSP0_CTRL3 DSP0_CTRL4 0 0 0 0 0 SOT0 SCK0 SIN0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 CAP0_DATA34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0_DATA25 0 0 0 CAP0_DATA24 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 RXCLK TIN33 I2S0_SCK DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 I2S1_SD DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 TXCLK TOT33 I2S0_WS COL 0 TXER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 TOT35 I2S1_WS TIN35 I2S1_SCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN1 TIN2 TIN3 TOT0 TOT1 TOT2 TOT3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGA0 SGA1 SGO1 SGO2 SGA3 SGO3 SGO0 SGA0 SGA1 SGO1 TOT16 SGO2 TIN17 0 0 0 TIN16 SGA2 0 0 TIN49 0 0 0 0 0 0 0 0 DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU9_OTD0 OCU8_OTD1 OCU5_OTD1 0 0 OCU6_OTD0 OCU7_OTD0 OCU6_OTD1 OCU8_OTD0 OCU7_OTD1 0 0 0 0 0 0 OCU3_OTD0 OCU5_OTD1 OCU8_OTD0 OCU8_OTD1 OCU9_OTD0 OCU9_OTD1 ICU8_IN1 ICU9_IN0 0 0 0 0 ICU9_IN0 ICU9_IN1 ICU8_IN1 0 ICU5_IN1 0 0 ICU6_IN0 ICU7_IN0 ICU6_IN1 ICU8_IN0 ICU7_IN1 0 0 0 0 ICU4_IN1 0 0 0 0 ICU3_IN0 ICU4_IN1 ICU5_IN0 ICU5_IN1 ICU6_IN1 ICU7_IN0 ICU7_IN1 ICU8_IN0 ICU8_IN1 ICU9_IN0 ICU9_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPG6_TOUT2 PPG7_TOUT0 PPG7_TOUT2 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 0 0 0 PPG9_TOUT0 PPG8_TOUT2 PPG5_TOUT2 0 0 PPG6_TOUT0 PPG7_TOUT0 PPG6_TOUT2 PPG8_TOUT0 PPG7_TOUT2 0 0 0 0 PPG4_TOUT2 0 0 0 0 PPG3_TOUT0 PPG4_TOUT2 PPG5_TOUT0 PPG5_TOUT2 PPG6_TOUT2 PPG7_TOUT0 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG9_TOUT2 EINT1 EINT2 0 0 0 0 0 0 EINT6 EINT8 EINT7 0 0 EINT1 EINT2 EINT3 0 0 0 0 EINT6 EINT9 0 0 0 P0_30 M_RWDS_0 0 0 P1_00 M_DQ5_0 P1_02 M_DQ7_0 P0_28 0 0 0 0 0 0 P2_25 0 P3_00 0 P3_01 0 P3_02 0 P3_03 0 P3_04 0 P3_05 0 P3_06 0 0 0 P2_22 0 0 0 P0_27 0 0 0 P0_26 0 0 0 P1_01 M_DQ4_0 0 0 P0_31 M_CS#2_0 0 0 EINT15 P2_31 0 PPG11_TOUT0 EINT6 0 0 EINT14 P2_30 0 EINT3 0 0 P1_09 M_CK_0 EINT13 P2_29 0 EINT2 0 0 0 0 0 G_DQ4_2 G_DQ5_2 G_DQ6_2 G_DQ7_2 0 0 0 0 0 G_CK_1 0 0 G_DQ3_1 G_DQ2_1 G_DQ1_1 G_DQ0_1 0 0 G_DQ5_1 G_DQ6_1 G_DQ7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP0_CTRL2 DSP0_CLK DSP0_CTRL0 DSP0_CTRL1 0 0 0 0 0 0 0 0 0 0 0 G_CS#2_1 0 G_DQ4_1 0 G_RWDS_1 0 0 0 G_CS#1_1 0 EINT11 P2_27 INDICATOR0_0 0 EINT1 0 EINT10 P2_26 0 EINT0 P5_22 0 EINT10 P1_03 M_DQ6_0 EINT9 P0_17 0 EINT11 P1_04 M_DQ0_0 EINT5 P0_16 0 EINT13 P1_06 M_DQ1_0 0 P0_15 0 EINT12 P1_05 M_DQ3_0 PPG10_TOUT2 EINT5 0 EINT0 PPG10_TOUT0 EINT4 0 EINT15 P0_14 0 PPG10_TOUT2 EINT15 P1_08 M_CS#1_0 0 EINT14 P0_13 0 PPG10_TOUT0 EINT14 P1_07 M_DQ2_0 PPG9_TOUT2 EINT13 P0_12 0 PPG11_TOUT0 EINT0 0 0 PPG10_TOUT0 EINT4 FRT8/9/10/11_TEXT PPG7_TOUT2 OCU11_OTD0 ICU11_IN0 0 0 0 OCU10_OTD1 ICU10_IN1 0 0 ICU8_IN0 OCU10_OTD0 ICU10_IN0 0 0 ICU7_IN1 OCU10_OTD1 ICU10_IN1 0 0 ICU7_IN0 OCU10_OTD0 ICU10_IN0 0 OCU9_OTD1 ICU6_IN1 OCU11_OTD0 ICU11_IN0 0 ZIN9 OCU7_OTD1 0 0 0 OCU10_OTD0 ICU10_IN0 0 BIN9 OCU7_OTD0 0 OCU9_OTD0 AIN9 OCU6_OTD1 0 OCU8_OTD1 ZIN8 OCU5_OTD0 0 OCU8_OTD0 BIN8 OCU4_OTD1 0 OCU7_OTD1 SIN1 OCU4_OTD1 0 OCU7_OTD0 SCK1 0 0 OCU6_OTD1 SOT1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 CAP0_DATA22 0 0 0 0 60 D 0 59 D 0 58 - 0 57 0 56 0 55 0 54 0 53 Page 32 of 222 Document Number: 002-05682 Rev. *K MFS9_CS0 0 P5_11 OCU10_OTD1 0 0 MFS10_SCL PWM1P2 0 193 0 DSP0_DATA1_10 194 0 0 - AN34 0 Y S 0 VCC53 137 0 DSP1_DATA0_4 20 0 0 B 0 0 TxCLK+ 0 0 0 0 0 0 0 0 0 0 0 SIN10 0 0 0 0 0 0 0 0 AIN9 0 0 0 0 0 0 0 0 0 ICU10_IN0 OCU10_OTD0 0 0 0 0 P3_30 0 0 P3_31 EINT14 0 0 EINT15 PPG11_TOUT0 0 0 PPG11_TOUT2 ICU11_IN0 0 SEG8 EINT12 PPG10_TOUT0 ICU11_IN1 OCU11_OTD0 0 0 OCU11_OTD1 PWM1M2 0 0 0 PWM2P2 0 0 MFS9_CS1 0 P5_12 0 0 0 0 0 AN35 0 0 AN36 S 0 0 S 138 0 0 139 19 0 195 18 B 0 - B TxDOUT2- 0 VSS TxDOUT2+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P4_00 0 0 EINT0 0 0 PPG0_TOUT0 0 0 0 ICU0_IN0 0 0 OCU0_OTD0 0 0 PWM2M2 0 196 0 0 Y 0 0 DSP1_DATA1_3 AN37 0 0 S 0 DSP0_CTRL0 140 0 0 17 0 0 B 0 0 ICU10_IN1 OCU10_OTD1 BIN9 TxDOUT3- 0 SEG7 EINT13 PPG10_TOUT2 0 0 0 0 P5_13 0 0 0 0 0 0 0 0 197 0 0 Y 0 0 DSP1_DATA0_3 0 0 0 0 0 0 DSP0_CTRL1 P4_01 0 0 SOT11 EINT1 0 ZIN9 PPG0_TOUT2 0 0 ICU11_IN0 OCU11_OTD0 ICU0_IN1 0 SEG6 EINT14 PPG11_TOUT0 OCU0_OTD1 0 MFS8_CS3 0 P5_14 PWM1P3 0 0 0 0 0 0 0 198 AN38 0 199 S 0 Y 141 0 Y 16 0 DSP1_DATA1_2 B 0 DSP1_DATA0_2 TxDOUT3+ 0 DSP1_CLK 0 0 DSP0_CTRL2 DSP1_CTRL2 0 0 DSP0_CTRL3 0 0 0 SCK11 0 0 0 SIN11 0 0 0 0 0 0 0 0 0 0 OCU0_OTD0 0 P4_02 0 ICU0_IN0 P4_03 EINT2 0 0 ICU11_IN1 OCU11_OTD1 EINT3 PPG1_TOUT0 0 0 PPG1_TOUT2 ICU1_IN0 0 PPG0_TOUT0 ICU1_IN1 OCU1_OTD0 0 EINT0 OCU1_OTD1 PWM1M3 0 SEG5 EINT15 PPG11_TOUT2 PWM2P3 0 0 0 SEG4 0 SOT2 0 0 MFS8_CS1 0 P5_15 SCK2 AN39 0 0 MFS8_CS2 0 P5_16 AN40 S 0 0 0 S 142 0 0 0 143 15 0 0 0 14 0 0 0 - VSS_LVDS_Tx 0 0 200 VCC3_LVDS_Tx 0 0 0 Y 0 0 0 0 DSP1_DATA1_1 0 0 0 DSP0_CTRL4 DSP1_CTRL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU0_OTD1 P4_04 0 ICU0_IN1 EINT4 0 0 PPG2_TOUT0 0 PPG0_TOUT2 ICU2_IN0 0 EINT1 OCU2_OTD0 0 SEG3 PWM2M3 0 0 0 P5_17 0 0 0 SIN2 0 0 AN41 0 201 S 0 Y 144 0 DSP1_DATA0_1 13 0 DSP0_CTRL5 DSP1_CTRL1 0 0 SOT12 AVCC3_LVDS_PLL 0 0 0 0 OCU1_OTD0 0 0 ICU1_IN0 0 0 0 0 0 0 PPG1_TOUT0 0 0 EINT2 0 0 SEG2 0 0 MFS12_SDA 0 P5_18 0 0 0 0 0 0 0 0 202 0 0 203 0 0 Y 0 0 Y DVSS 0 DSP1_DATA1_0 - 0 DSP1_DATA0_0 145 0 0 12 0 0 0 DSP0_CTRL6 AVSS_LVDS_PLL 0 DSP0_CTRL7 0 0 0 SCK12 0 0 0 SIN12 0 0 0 0 0 0 0 0 0 0 0 OCU1_OTD1 0 0 0 OCU2_OTD0 0 0 0 ICU1_IN1 0 0 0 ICU2_IN0 0 0 0 0 0 0 0 0 0 0 0 PPG1_TOUT2 0 0 0 PPG2_TOUT0 DVCC 0 0 EINT3 - 0 0 EINT4 146 0 0 SEG1 11 0 0 SEG0 0 0 0 0 P5_20 VCC12 0 MFS12_SCL 0 P5_19 0 0 0 0 0 0 0 0 0 0 0 MFS0_CS0 P4_05 0 0 P4_06 EINT5 0 204 EINT6 PPG2_TOUT2 0 205 PPG3_TOUT0 ICU2_IN1 0 206 ICU3_IN0 OCU2_OTD1 0 207 OCU3_OTD0 PWM1P4 0 208 PWM1M4 0 0 - 0 0 0 Y SOT3 AN42 0 Y AN43 S 0 Y S 147 0 Y 148 10 0 VCC53 9 0 DSP1_CLK - VSS DAC_L DSP1_CTRL2 AVSS 0 0 DSP1_CTRL1 0 0 0 DSP1_CTRL0 MFS2_CS0 0 0 P4_07 0 0 EINT7 0 0 PPG3_TOUT2 0 0 ICU3_IN1 0 0 OCU3_OTD1 0 0 PWM2P4 0 DSP0_CTRL8 0 0 DSP0_CTRL9 SCK3 0 0 0 AN44 0 0 S 0 0 SOT11 149 0 0 SCK11 DSP0_CTRL10 8 0 0 SIN11 DSP0_CTRL11 A 0 0 0 C_L - 0 MFS2_CS1 AVCC3_DAC 0 P4_08 0 0 EINT8 0 0 PPG4_TOUT0 0 OCU0_OTD1 ICU4_IN0 0 OCU1_OTD0 SGA1 OCU4_OTD0 0 OCU1_OTD1 SGO1 PWM2M4 0 OCU2_OTD0 0 0 0 SIN3 0 ICU0_IN1 AN45 0 ICU1_IN0 S 0 ICU1_IN1 0 150 0 ICU2_IN0 0 7 0 0 P4_09 A 0 0 EINT9 0 0 PPG4_TOUT2 0 0 ICU4_IN1 0 0 OCU4_OTD1 5 0 PWM1P5 4 VSS PPG0_TOUT2 0 3 A AVSS PPG1_TOUT0 0 2 A C_R 0 PPG1_TOUT2 AN46 - DAC_R 0 0 PPG2_TOUT0 0 MFS4_SDA S 1 AVSS 0 0 0 0 0 MFS4_SCL MFS0_CS3 151 - 0 0 0 0 0 0 P4_25 COM3 EINT9 0 MFS0_CS1 P4_10 6 0 0 0 0 0 0 0 P4_26 COM2 EINT10 MFS0_CS2 P4_11 EINT10 0 0 0 0 0 0 0 P4_27 COM1 EINT11 P4_12 EINT11 PPG5_TOUT0 0 0 0 0 0 0 0 P4_28 COM0 EINT12 0 EINT12 PPG5_TOUT2 ICU5_IN0 0 0 0 0 0 0 0 0 0 PPG6_TOUT0 ICU5_IN1 OCU5_OTD0 0 0 0 0 0 0 0 0 ICU6_IN0 OCU5_OTD1 PWM1M5 0 0 0 0 0 0 0 0 OCU6_OTD0 PWM2P5 0 0 0 0 0 0 0 0 0 PWM2M5 RX1 SOT4 0 0 0 0 0 0 0 0 TX1 SCK4 AN47 0 0 0 0 0 0 0 0 SIN4 AN48 S 0 0 0 0 0 0 0 0 AN49 S 152 0 0 0 0 0 0 0 DVSS S 153 0 0 0 0 0 0 DVCC 154 0 0 0 0 0 155 0 0 0 0 156 0 0 0 Notes: - The pins highlighted in "red" font are not supported for products with revision A and C. S6J3200 Series Figure 4-12: TEQFP-208 (S6J325CKxx, S6J32NEKxx) 0 0 0 0 0 0 0 ICU2_IN1 ICU2_IN0 ICU0_IN1 ICU0_IN0 0 0 0 0 0 0 OCU3_OTD1 SGO1 TIN33 SOT11 OCU3_OTD0 SGA1 TOT33 SIN10 OCU2_OTD1 SGA0 TIN32 SCK10 OCU2_OTD0 SGO0 TOT32 SOT10 OCU0_OTD0 WOT TOT18 0 OCU4_OTD0 SGA2 TOT34 SCK11 0 TIN18 0 OCU4_OTD1 SGO2 TIN34 SIN11 OCU0_OTD1 0 0 0 SIN9 SCK9 SOT9 BP0(BH0) AN0(AL0) AP0(AH0) 0 0 0 0 0 TX6 RX6 TX5 RX5 0 0 TX5 RX5 0 0 0 DSP1_DATA0_11 0 DSP1_DATA1_11 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_DATA1_9 0 DSP1_DATA1_10 0 DSP1_DATA0_9 0 DSP1_DATA0_10 0 DSP1_DATA1_8 VCC53 VSS VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN17 AN16 AN15 - Y Y Y Y Y Y Y Y - - - X X W W W W W W V V V 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 157 0 0 V3 EINT3 0 PPG0_TOUT0 PPG6/7/8/9/10/11_TIN V2 EINT7 PPG11_TOUT2 0 ICU3_IN0 0 0 0 BN0(BL0) 0 - 185 - 0 0 P2_19 V1 EINT8 PPG0_TOUT2 FRT4/5/6/7_TEXT ICU3_IN1 0 ICU4_IN0 OCU0_OTD1 0 0 0 AP1(AH1) 0 VCC12 DSP1_DATA0_8 - VCC5 0 0 P3_07 PPG2_TOUT0 0 ICU4_IN1 0 OCU0_OTD0 0 0 0 AN1(AL1) 0 VCC12 - 0 0 0 P3_08 V0 EINT9 PPG2_TOUT2 0 ICU0_IN1 0 0 0 0 BP1(BH1) 0 VSS 0 0 0 0 P3_09 PPG3_TOUT0 0 0 ICU0_IN0 0 0 0 SOT8 0 VCC53 0 0 MFS8_CS0 0 P3_12 SEG29 EINT12 PPG3_TOUT2 0 0 OCU3_OTD0 SGA3 0 SCK8 0 BN1(BL1) 0 186 0 0 0 MFS9_CS0 0 P3_13 SEG28 EINT13 PPG4_TOUT0 0 0 OCU3_OTD1 SGO3 OCU2_OTD1 0 0 0 0 187 0 0 0 MFS9_CS1 0 P3_14 SEG27 EINT14 PPG4_TOUT2 0 ICU2_IN1 0 0 0 SIN8 0 Y 0 0 0 MFS8_CS3 0 P3_15 SEG26 EINT15 PPG0_TOUT2 0 ICU3_IN0 OCU4_OTD0 0 0 0 0 Y 188 0 0 0 EINT0 0 PPG0_TOUT0 0 ICU3_IN1 OCU4_OTD1 0 0 0 DSP1_DATA1_7 189 0 0 0 MFS8_CS1 0 P3_16 SEG25 EINT1 0 0 ICU4_IN0 OCU5_OTD0 0 0 0 DSP1_DATA0_7 Y 0 0 0 MFS8_CS2 0 P3_17 SEG24 EINT1 0 0 ICU4_IN1 OCU5_OTD1 0 0 0 Y 0 0 0 0 0 EINT0 PPG2_TOUT2 0 ICU5_IN0 0 0 0 DSP1_DATA1_6 158 0 0 0 PPG3_TOUT0 0 ICU5_IN1 0 OCU6_OTD0 0 0 DSP1_DATA0_6 - 0 0 0 P2_17 0 0 PPG3_TOUT2 0 0 0 0 0 VSS 0 0 0 0 0 PPG4_TOUT0 0 0 ICU6_IN0 0 0 0 0 0 0 0 0 0 0 PPG4_TOUT2 0 0 0 SOT9 0 0 0 0 0 0 INDICATOR0_1 0 P2_16 0 0 0 P4_29 SEG23 EINT13 PPG5_TOUT0 0 0 0 0 0 0 0 0 0 P4_30 SEG22 EINT14 0 EINT0 0 0 P4_31 SEG21 EINT15 0 0 EINT1 PPG5_TOUT2 0 0 0 SIN9 SCK9 0 0 0 0 0 P5_00 SEG20 EINT2 0 PPG6_TOUT0 0 0 0 0 0 0 0 0 P5_01 SEG19 EINT3 0 0 0 0 0 0 0 0 0 P5_02 SEG18 0 EINT4 0 OCU6_OTD1 0 0 0 0 0 0 P5_03 SEG17 0 0 OCU7_OTD0 0 0 0 0 0 0 0 P5_04 SEG16 0 ICU6_IN1 OCU7_OTD1 0 0 0 0 0 ICU7_IN0 OCU8_OTD0 0 0 0 0 0 0 ICU7_IN1 159 0 0 0 0 0 ICU8_IN0 U 0 0 0 0 0 PPG6_TOUT2 0 0 0 0 0 0 0 PPG7_TOUT0 0 0 0 0 0 0 EINT5 PPG7_TOUT2 0 0 0 0 0 EINT6 PPG8_TOUT0 0 0 0 0 0 0 P5_05 SEG15 EINT7 AIN8 0 0 0 0 0 P5_06 SEG14 EINT8 OCU8_OTD1 0 0 0 0 0 P5_07 SEG13 ICU8_IN1 0 0 0 0 0 P5_08 SEG12 0 ICU1_IN1 0 0 PPG8_TOUT2 TIN48 0 0 EINT9 0 0 0 0 P5_09 SEG11 0 0 0 0 DSP1_DATA0_5 DSP1_DATA1_5 Y Y 191 190 0 TOT17 0 0 0 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 0 0 SOT10 0 OCU9_OTD0 BIN8 PPG9_TOUT0 ICU9_IN0 MFS8_CS0 0 P5_10 SEG10 EINT10 192 0 MFS10_SDA Y OCU9_OTD1 DSP1_DATA1_4 ICU9_IN1 0 0 0 PPG9_TOUT2 0 SCK10 SEG9 EINT11 ZIN8 MFS9_CS0 0 P5_11 ICU11_IN0 PPG11_TOUT0 EINT14 P3_30 0 OCU10_OTD1 ICU10_IN1 PPG10_TOUT2 EINT13 P3_29 0 0 0 0 0 0 0 0 0 0 0 TxCLK- B 21 136 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT1+ B 22 135 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT1- B 23 134 S AN33 0 BN1(BL1) PWM2M1 OCU10_OTD0 ICU10_IN0 PPG10_TOUT0 EINT12 P3_28 0 0 0 0 0 0 0 0 0 0 0 TxDOUT0+ B 24 133 S AN32 0 BP1(BH1) PWM2P1 OCU9_OTD1 ICU9_IN1 PPG9_TOUT2 EINT11 P3_27 0 0 0 0 0 0 0 0 0 0 0 TxDOUT0- B 25 132 S AN31 0 AN1(AL1) PWM1M1 OCU9_OTD0 ICU9_IN0 PPG9_TOUT0 EINT10 P3_26 0 0 0 0 0 0 0 0 0 0 0 0 VSS_LVDS_Tx - 26 131 S AN30 0 AP1(AH1) PWM1P1 OCU8_OTD1 ICU8_IN1 PPG8_TOUT2 EINT9 P3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3_LVDS_Tx - 27 130 S AN29 0 BN0(BL0) PWM2M0 OCU8_OTD0 ICU8_IN0 PPG8_TOUT0 EINT8 P3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 28 129 S AN28 0 BP0(BH0) PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 29 128 S AN27 0 AN0(AL0) PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 30 127 S AN26 0 AP0(AH0) PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 0 0 0 0 0 0 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 DSP0_DATA0_4 MDC CAP0_DATA0 0 DSP0_CTRL1 C 31 126 - DVCC 0 0 0 0 0 0 0 0 DSP0_DATA0_11 0 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK+ DSP0_CLK D 32 125 - DVSS 0 0 0 0 0 0 0 0 DSP0_DATA1_11 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 124 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 123 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 122 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 0 CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 121 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 120 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 119 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 0 CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 39 118 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 117 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 116 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 115 - VCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 114 Q RSTX 0 0 0 0 0 0 0 0 CAP0_DATA11 G_CK_2 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 44 113 P MODE 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 45 112 N2 JTAG_TMS 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 46 111 N2 JTAG_TCK 0 0 0 0 0 0 0 0 CAP0_DATA14 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 47 110 N2 JTAG_TDI 0 0 0 0 0 0 0 0 CAP0_DATA15 G_DQ0_2 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 48 109 O JTAG_TDO 0 0 0 0 0 0 0 0 0 G_CS#1_2 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 49 108 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 G_RWDS_2 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 50 107 M X0 0 0 0 0 0 0 0 0 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 51 106 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 52 105 - VSS 0 0 0 0 0 0 0 0 TOP VIEW TEQFP-208 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 D D D D C - - E - - E E E E E - E - - E E E E E - - F F F - - - G H J J I I I I J J I I I I I L - VCC3 DSP0_DATA0_9 DSP0_DATA_D9+ CAP0_DATA21 0 DSP0_DATA1_9 DSP0_DATA_D9- DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK DSP0_CTRL0 VCC12 VSS M_SCLK0 VSS VCC3 M_SDATA0_0 M_SDATA0_2 M_SDATA0_1 M_SSEL0 M_SDATA0_3 VSS 0 VSS VCC3 M_SDATA1_0 M_SDATA1_2 M_SDATA1_1 M_SSEL1 M_SDATA1_3 VSS VCC3 MLBDAT MLBSIG MLBCLK VCC12 VSS VCC5 PSC_1 0 AN1 AN2 AN3 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 DSP0_CTRL2 0 0 0 0 0 G_SDATA1_0 G_SDATA1_2 G_SDATA1_1 G_SSEL1 G_SDATA1_3 0 G_SCLK0 0 0 G_SDATA0_0 G_SDATA0_2 G_SDATA0_1 G_SSEL0 G_SDATA0_3 0 0 DSP0_CTRL2 DSP0_CTRL3 DSP0_CTRL4 0 0 0 0 0 SOT0 SCK0 SIN0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 CAP0_DATA34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0_DATA25 0 0 0 CAP0_DATA24 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 RXCLK TIN33 I2S0_SCK DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 I2S1_SD DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 TXCLK TOT33 I2S0_WS COL 0 TXER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 TOT35 I2S1_WS TIN35 I2S1_SCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN1 TIN2 TIN3 TOT0 TOT1 TOT2 TOT3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGA0 SGA1 SGO1 SGO2 SGA3 SGO3 SGO0 SGA0 SGA1 SGO1 TOT16 SGO2 TIN17 0 0 0 TIN16 SGA2 0 0 TIN49 0 0 0 0 0 0 0 0 DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU9_OTD0 OCU8_OTD1 OCU5_OTD1 0 0 OCU6_OTD0 OCU7_OTD0 OCU6_OTD1 OCU8_OTD0 OCU7_OTD1 0 0 0 0 0 0 OCU3_OTD0 OCU5_OTD1 OCU8_OTD0 OCU8_OTD1 OCU9_OTD0 OCU9_OTD1 ICU8_IN1 ICU9_IN0 0 0 0 0 ICU9_IN0 ICU9_IN1 ICU8_IN1 0 ICU5_IN1 0 0 ICU6_IN0 ICU7_IN0 ICU6_IN1 ICU8_IN0 ICU7_IN1 0 0 0 0 ICU4_IN1 0 0 0 0 ICU3_IN0 ICU4_IN1 ICU5_IN0 ICU5_IN1 ICU6_IN1 ICU7_IN0 ICU7_IN1 ICU8_IN0 ICU8_IN1 ICU9_IN0 ICU9_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPG6_TOUT2 PPG7_TOUT0 PPG7_TOUT2 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 0 0 0 PPG9_TOUT0 PPG8_TOUT2 PPG5_TOUT2 0 0 PPG6_TOUT0 PPG7_TOUT0 PPG6_TOUT2 PPG8_TOUT0 PPG7_TOUT2 0 0 0 0 PPG4_TOUT2 0 0 0 0 PPG3_TOUT0 PPG4_TOUT2 PPG5_TOUT0 PPG5_TOUT2 PPG6_TOUT2 PPG7_TOUT0 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG9_TOUT2 EINT1 EINT2 0 0 0 0 0 0 EINT6 EINT8 EINT7 0 0 EINT1 EINT2 EINT3 0 0 0 0 EINT6 EINT9 0 0 0 P0_30 M_RWDS_0 0 0 P1_00 M_DQ5_0 P1_02 M_DQ7_0 P0_28 0 0 0 0 0 0 P2_25 0 P3_00 0 P3_01 0 P3_02 0 P3_03 0 P3_04 0 P3_05 0 P3_06 0 0 0 P2_22 0 0 0 P0_27 0 0 0 P0_26 0 0 0 P1_01 M_DQ4_0 0 0 P0_31 M_CS#2_0 0 0 EINT15 P2_31 0 PPG11_TOUT0 EINT6 0 0 EINT14 P2_30 0 EINT3 0 0 P1_09 M_CK_0 EINT13 P2_29 0 EINT2 0 0 0 0 0 G_DQ4_2 G_DQ5_2 G_DQ6_2 G_DQ7_2 0 0 0 0 0 G_CK_1 0 0 G_DQ3_1 G_DQ2_1 G_DQ1_1 G_DQ0_1 0 0 G_DQ5_1 G_DQ6_1 G_DQ7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP0_CTRL2 DSP0_CLK DSP0_CTRL0 DSP0_CTRL1 0 0 0 0 0 0 0 0 0 0 0 G_CS#2_1 0 G_DQ4_1 0 G_RWDS_1 0 0 0 G_CS#1_1 0 EINT11 P2_27 INDICATOR0_0 0 EINT1 0 EINT10 P2_26 0 EINT0 P5_22 0 EINT10 P1_03 M_DQ6_0 EINT9 P0_17 0 EINT11 P1_04 M_DQ0_0 EINT5 P0_16 0 EINT13 P1_06 M_DQ1_0 0 P0_15 0 EINT12 P1_05 M_DQ3_0 PPG10_TOUT2 EINT5 0 EINT0 PPG10_TOUT0 EINT4 0 EINT15 P0_14 0 PPG10_TOUT2 EINT15 P1_08 M_CS#1_0 0 EINT14 P0_13 0 PPG10_TOUT0 EINT14 P1_07 M_DQ2_0 PPG9_TOUT2 EINT13 P0_12 0 PPG11_TOUT0 EINT0 0 0 PPG10_TOUT0 EINT4 FRT8/9/10/11_TEXT PPG7_TOUT2 OCU11_OTD0 ICU11_IN0 0 0 0 OCU10_OTD1 ICU10_IN1 0 0 ICU8_IN0 OCU10_OTD0 ICU10_IN0 0 0 ICU7_IN1 OCU10_OTD1 ICU10_IN1 0 0 ICU7_IN0 OCU10_OTD0 ICU10_IN0 0 OCU9_OTD1 ICU6_IN1 OCU11_OTD0 ICU11_IN0 0 ZIN9 OCU7_OTD1 0 0 0 OCU10_OTD0 ICU10_IN0 0 BIN9 OCU7_OTD0 0 OCU9_OTD0 AIN9 OCU6_OTD1 0 OCU8_OTD1 ZIN8 OCU5_OTD0 0 OCU8_OTD0 BIN8 OCU4_OTD1 0 OCU7_OTD1 SIN1 OCU4_OTD1 0 OCU7_OTD0 SCK1 0 0 OCU6_OTD1 SOT1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 CAP0_DATA22 0 0 0 0 60 D 0 59 D 0 58 - 0 57 0 56 0 55 0 54 0 53 Page 33 of 222 Document Number: 002-05682 Rev. *K Condition on PCB Set to ground Open Package Pin Number 2, 5, 6, 9, and 12 to 27 3, 4, 7, 8 0 MFS10_SCL OCU11_OTD0 PWM1P2 0 193 PWM1M2 0 0 194 0 0 DSP0_DATA1_10 - 0 AN34 0 Y AN35 S 0 VCC53 S 137 0 DSP1_DATA0_4 138 20 0 0 19 B 0 0 B TxCLK+ 0 0 TxDOUT2- 0 0 0 0 0 0 0 0 0 0 0 SIN10 0 0 0 0 0 0 0 0 0 0 0 AIN9 0 0 0 0 0 0 0 0 0 0 0 0 ICU10_IN0 OCU10_OTD0 0 0 0 0 0 0 P3_31 0 0 EINT15 0 0 PPG11_TOUT2 0 SEG8 EINT12 PPG10_TOUT0 ICU11_IN1 0 0 OCU11_OTD1 0 0 0 PWM2P2 0 MFS9_CS1 0 P5_12 0 0 0 0 0 0 AN36 0 0 S 0 0 139 0 195 18 0 - B 0 VSS TxDOUT2+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P4_00 0 0 EINT0 0 0 PPG0_TOUT0 0 0 0 ICU0_IN0 0 0 OCU0_OTD0 0 0 PWM2M2 0 196 0 0 Y 0 0 DSP1_DATA1_3 AN37 0 0 S 0 DSP0_CTRL0 140 0 0 17 0 0 B 0 0 ICU10_IN1 OCU10_OTD1 BIN9 TxDOUT3- 0 SEG7 EINT13 PPG10_TOUT2 0 0 0 0 P5_13 0 0 0 0 0 0 0 0 197 0 0 Y 0 0 DSP1_DATA0_3 0 0 0 0 0 0 DSP0_CTRL1 P4_01 0 0 SOT11 EINT1 0 ZIN9 PPG0_TOUT2 0 0 ICU11_IN0 OCU11_OTD0 ICU0_IN1 0 SEG6 EINT14 PPG11_TOUT0 OCU0_OTD1 0 MFS8_CS3 0 P5_14 PWM1P3 0 0 0 0 0 0 0 198 AN38 0 199 S 0 Y 141 0 Y 16 0 DSP1_DATA1_2 B 0 DSP1_DATA0_2 TxDOUT3+ 0 DSP1_CLK 0 0 DSP0_CTRL2 DSP1_CTRL2 0 0 DSP0_CTRL3 0 0 0 SCK11 0 0 0 SIN11 0 0 0 0 0 0 0 0 0 0 OCU0_OTD0 0 P4_02 0 ICU0_IN0 P4_03 EINT2 0 0 ICU11_IN1 OCU11_OTD1 EINT3 PPG1_TOUT0 0 0 PPG1_TOUT2 ICU1_IN0 0 PPG0_TOUT0 ICU1_IN1 OCU1_OTD0 0 EINT0 OCU1_OTD1 PWM1M3 0 SEG5 EINT15 PPG11_TOUT2 PWM2P3 0 0 0 SEG4 0 SOT2 0 0 MFS8_CS1 0 P5_15 SCK2 AN39 0 0 MFS8_CS2 0 P5_16 AN40 S 0 0 0 S 142 0 0 0 143 15 0 0 0 14 0 0 0 - VSS_LVDS_Tx 0 0 200 VCC3_LVDS_Tx 0 0 0 Y 0 0 0 0 DSP1_DATA1_1 0 0 0 DSP0_CTRL4 DSP1_CTRL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU0_OTD1 P4_04 0 ICU0_IN1 EINT4 0 0 PPG2_TOUT0 0 PPG0_TOUT2 ICU2_IN0 0 EINT1 OCU2_OTD0 0 SEG3 PWM2M3 0 0 0 P5_17 0 0 0 SIN2 0 0 AN41 0 201 S 0 Y 144 0 DSP1_DATA0_1 13 0 DSP0_CTRL5 DSP1_CTRL1 0 0 SOT12 AVCC3_LVDS_PLL 0 0 0 0 OCU1_OTD0 0 0 ICU1_IN0 0 0 0 0 0 0 PPG1_TOUT0 0 0 EINT2 0 0 SEG2 0 0 MFS12_SDA 0 P5_18 0 0 0 0 0 0 0 0 202 0 0 203 0 0 Y 0 0 Y DVSS 0 DSP1_DATA1_0 - 0 DSP1_DATA0_0 145 0 0 12 0 0 0 DSP0_CTRL6 AVSS_LVDS_PLL 0 DSP0_CTRL7 0 0 0 SCK12 0 0 0 SIN12 0 0 0 0 0 0 0 0 0 0 0 OCU1_OTD1 0 0 0 OCU2_OTD0 0 0 0 ICU1_IN1 0 0 0 ICU2_IN0 0 0 0 0 0 0 0 0 0 0 0 PPG1_TOUT2 0 0 0 PPG2_TOUT0 DVCC 0 0 EINT3 - 0 0 EINT4 146 0 0 SEG1 11 0 0 SEG0 0 0 0 0 P5_20 VCC12 0 MFS12_SCL 0 P5_19 0 0 0 0 0 0 0 0 0 0 0 MFS0_CS0 P4_05 0 0 P4_06 EINT5 0 204 EINT6 PPG2_TOUT2 0 205 PPG3_TOUT0 ICU2_IN1 0 206 ICU3_IN0 OCU2_OTD1 0 207 OCU3_OTD0 PWM1P4 0 208 PWM1M4 0 0 - 0 0 0 Y SOT3 AN42 0 Y AN43 S 0 Y S 147 0 Y 148 10 0 VCC53 9 0 DSP1_CLK - VSS DAC_L DSP1_CTRL2 AVSS 0 0 DSP1_CTRL1 0 0 0 DSP1_CTRL0 MFS2_CS0 0 0 P4_07 0 0 EINT7 0 0 PPG3_TOUT2 0 0 ICU3_IN1 0 0 OCU3_OTD1 0 0 PWM2P4 0 DSP0_CTRL8 0 0 DSP0_CTRL9 SCK3 0 0 0 AN44 0 0 S 0 0 SOT11 149 0 0 SCK11 DSP0_CTRL10 8 0 0 SIN11 DSP0_CTRL11 A 0 0 0 C_L - 0 MFS2_CS1 - AVCC3_DAC 0 P4_08 AVSS 0 0 EINT8 0 0 0 PPG4_TOUT0 0 0 OCU0_OTD1 ICU4_IN0 0 0 OCU1_OTD0 SGA1 OCU4_OTD0 0 0 OCU1_OTD1 SGO1 PWM2M4 0 0 OCU2_OTD0 0 0 0 0 SIN3 0 0 ICU0_IN1 AN45 0 0 ICU1_IN0 S 0 0 ICU1_IN1 0 150 0 0 ICU2_IN0 MFS4_SDA 0 7 0 0 0 MFS0_CS3 P4_09 A 0 0 0 P4_10 EINT9 0 0 0 EINT10 PPG4_TOUT2 0 0 0 PPG5_TOUT0 ICU4_IN1 0 0 0 ICU5_IN0 OCU4_OTD1 0 0 OCU5_OTD0 PWM1P5 4 PPG0_TOUT2 PWM1M5 0 3 A VSS PPG1_TOUT0 0 0 2 A C_R PPG1_TOUT2 SOT4 AN46 - DAC_R 0 PPG2_TOUT0 0 AN47 S 1 AVSS 0 0 0 0 MFS4_SCL S 151 - 0 0 0 0 0 P4_25 COM3 EINT9 0 MFS0_CS1 152 6 0 0 0 0 0 0 P4_26 COM2 EINT10 MFS0_CS2 P4_11 5 0 0 0 0 0 0 P4_27 COM1 EINT11 P4_12 EINT11 0 0 0 0 0 0 P4_28 COM0 EINT12 0 EINT12 PPG5_TOUT2 0 0 0 0 0 0 0 0 PPG6_TOUT0 ICU5_IN1 0 0 0 0 0 0 0 ICU6_IN0 OCU5_OTD1 0 0 0 0 0 0 0 OCU6_OTD0 PWM2P5 0 0 0 0 0 0 0 PWM2M5 RX1 0 0 0 0 0 0 0 TX1 SCK4 0 0 0 0 0 0 0 SIN4 AN48 0 0 0 0 0 0 0 AN49 S 0 0 0 0 0 0 DVSS S 153 0 0 0 0 0 DVCC 154 0 0 0 0 0 155 0 0 0 0 Any function at the following pins is not supported. - 156 0 0 0 Notes: - The pins highlighted in "red" font are not supported for products with revision A and C. S6J3200 Series Figure 4-13: TEQFP-208 (S6J324CKxx) 0 0 0 0 0 0 0 ICU2_IN1 ICU2_IN0 ICU0_IN1 ICU0_IN0 0 0 0 0 0 0 OCU3_OTD1 SGO1 TIN33 SOT11 OCU3_OTD0 SGA1 TOT33 SIN10 OCU2_OTD1 SGA0 TIN32 SCK10 OCU2_OTD0 SGO0 TOT32 SOT10 OCU0_OTD0 WOT TOT18 0 OCU4_OTD0 SGA2 TOT34 SCK11 0 TIN18 0 OCU4_OTD1 SGO2 TIN34 SIN11 OCU0_OTD1 0 0 0 SIN9 SCK9 SOT9 BP0(BH0) AN0(AL0) AP0(AH0) 0 0 0 0 0 TX6 RX6 TX5 RX5 0 0 TX5 RX5 0 0 0 DSP1_DATA0_11 0 DSP1_DATA1_11 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_DATA1_9 0 DSP1_DATA1_10 0 DSP1_DATA0_9 0 DSP1_DATA0_10 0 DSP1_DATA1_8 VCC53 VSS VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN17 AN16 AN15 - Y Y Y Y Y Y Y Y - - - X X W W W W W W V V V 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 157 0 0 V3 EINT3 0 PPG0_TOUT0 PPG6/7/8/9/10/11_TIN V2 EINT7 PPG11_TOUT2 0 ICU3_IN0 0 0 0 BN0(BL0) 0 - 185 - 0 0 P2_19 V1 EINT8 PPG0_TOUT2 FRT4/5/6/7_TEXT ICU3_IN1 0 ICU4_IN0 OCU0_OTD1 0 0 0 AP1(AH1) 0 VCC12 DSP1_DATA0_8 - VCC5 0 0 P3_07 PPG2_TOUT0 0 ICU4_IN1 0 OCU0_OTD0 0 0 0 AN1(AL1) 0 VCC12 - 0 0 0 P3_08 V0 EINT9 PPG2_TOUT2 0 ICU0_IN1 0 0 0 0 BP1(BH1) 0 VSS 0 0 0 0 P3_09 PPG3_TOUT0 0 0 ICU0_IN0 0 0 0 SOT8 0 VCC53 0 0 MFS8_CS0 0 P3_12 SEG29 EINT12 PPG3_TOUT2 0 0 OCU3_OTD0 SGA3 0 SCK8 0 BN1(BL1) 0 186 0 0 0 MFS9_CS0 0 P3_13 SEG28 EINT13 PPG4_TOUT0 0 0 OCU3_OTD1 SGO3 OCU2_OTD1 0 0 0 0 187 0 0 0 MFS9_CS1 0 P3_14 SEG27 EINT14 PPG4_TOUT2 0 ICU2_IN1 0 0 0 SIN8 0 Y 0 0 0 MFS8_CS3 0 P3_15 SEG26 EINT15 PPG0_TOUT2 0 ICU3_IN0 OCU4_OTD0 0 0 0 0 Y 188 0 0 0 EINT0 0 PPG0_TOUT0 0 ICU3_IN1 OCU4_OTD1 0 0 0 DSP1_DATA1_7 189 0 0 0 MFS8_CS1 0 P3_16 SEG25 EINT1 0 0 ICU4_IN0 OCU5_OTD0 0 0 0 DSP1_DATA0_7 Y 0 0 0 MFS8_CS2 0 P3_17 SEG24 EINT1 0 0 ICU4_IN1 OCU5_OTD1 0 0 0 Y 0 0 0 0 0 EINT0 PPG2_TOUT2 0 ICU5_IN0 0 0 0 DSP1_DATA1_6 158 0 0 0 PPG3_TOUT0 0 ICU5_IN1 0 OCU6_OTD0 0 0 DSP1_DATA0_6 - 0 0 0 P2_17 0 0 PPG3_TOUT2 0 0 0 0 0 VSS 0 0 0 0 0 PPG4_TOUT0 0 0 ICU6_IN0 0 0 0 0 0 0 0 0 0 0 PPG4_TOUT2 0 0 0 SOT9 0 0 0 0 0 0 INDICATOR0_1 0 P2_16 0 0 0 P4_29 SEG23 EINT13 PPG5_TOUT0 0 0 0 0 0 0 0 0 0 P4_30 SEG22 EINT14 0 EINT0 0 0 P4_31 SEG21 EINT15 0 0 EINT1 PPG5_TOUT2 0 0 0 SIN9 SCK9 0 0 0 0 0 P5_00 SEG20 EINT2 0 PPG6_TOUT0 0 0 0 0 0 0 0 0 P5_01 SEG19 EINT3 0 0 0 0 0 0 0 0 0 P5_02 SEG18 0 EINT4 0 OCU6_OTD1 0 0 0 0 0 0 P5_03 SEG17 0 0 OCU7_OTD0 0 0 0 0 0 0 0 P5_04 SEG16 0 ICU6_IN1 OCU7_OTD1 0 0 0 0 0 ICU7_IN0 OCU8_OTD0 0 0 0 0 0 0 ICU7_IN1 159 0 0 0 0 0 ICU8_IN0 U 0 0 0 0 0 PPG6_TOUT2 0 0 0 0 0 0 0 PPG7_TOUT0 0 0 0 0 0 0 EINT5 PPG7_TOUT2 0 0 0 0 0 EINT6 PPG8_TOUT0 0 0 0 0 0 0 P5_05 SEG15 EINT7 AIN8 0 0 0 0 0 P5_06 SEG14 EINT8 OCU8_OTD1 0 0 0 0 0 P5_07 SEG13 ICU8_IN1 0 0 0 0 0 P5_08 SEG12 0 ICU1_IN1 0 0 PPG8_TOUT2 TIN48 0 0 EINT9 0 0 0 0 P5_09 SEG11 0 0 0 DSP1_DATA0_5 DSP1_DATA1_5 Y Y 191 190 0 TOT17 0 0 0 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 0 0 0 0 SOT10 PPG9_TOUT0 OCU9_OTD0 BIN8 MFS8_CS0 0 P5_10 SEG10 EINT10 ICU9_IN0 0 MFS10_SDA 192 OCU9_OTD1 Y ICU9_IN1 DSP1_DATA1_4 0 0 PPG9_TOUT2 0 SEG9 EINT11 0 SCK10 MFS9_CS0 0 P5_11 ZIN8 0 MFS10_SCL 193 195 194 196 - 197 Y Y 198 VCC53 VSS Y 199 DSP1_DATA0_4 0 DSP1_DATA1_3 Y 0 0 0 DSP1_DATA0_3 Y 0 0 0 DSP0_CTRL0 DSP1_DATA1_2 0 0 0 0 DSP1_DATA0_2 0 0 DSP0_CTRL1 DSP1_CLK DSP0_CTRL2 DSP1_CTRL2 0 0 0 SOT11 DSP0_CTRL3 0 SIN10 0 ICU10_IN1 OCU10_OTD1 BIN9 0 SCK11 0 ZIN9 0 SIN11 AIN9 0 0 SEG8 EINT12 PPG10_TOUT0 0 ICU11_IN0 OCU11_OTD0 0 0 0 OCU0_OTD0 0 ICU10_IN0 OCU10_OTD0 0 0 MFS9_CS1 0 P5_12 SEG7 EINT13 PPG10_TOUT2 ICU0_IN0 0 ICU11_IN1 OCU11_OTD1 0 0 0 SEG6 EINT14 PPG11_TOUT0 0 0 0 0 0 PPG0_TOUT0 0 0 0 0 P5_13 EINT0 SEG5 EINT15 PPG11_TOUT2 200 0 0 0 MFS8_CS3 0 P5_14 SEG4 Y 0 0 MFS8_CS1 0 P5_15 DSP1_DATA1_1 0 0 0 MFS8_CS2 0 P5_16 DSP0_CTRL4 DSP1_CTRL0 0 0 0 0 0 0 0 0 0 0 OCU0_OTD1 0 0 ICU0_IN1 0 0 32 PPG0_TOUT2 D EINT1 DSP0_CLK SEG3 DSP0_CLK+ 0 0 P5_17 CAP0_DATA1 0 MDIO 0 0 201 0 Y OCU3_OTD1 DSP1_DATA0_1 ICU3_IN1 DSP0_CTRL5 DSP1_CTRL1 PPG3_TOUT2 0 SOT12 EINT15 0 P0_18 OCU1_OTD0 0 ICU1_IN0 0 0 0 PPG1_TOUT0 0 EINT2 0 SEG2 DSP0_DATA0_11 MFS12_SDA 0 P5_18 31 0 C 0 DSP0_CTRL1 202 0 203 CAP0_DATA0 Y MDC Y DSP0_DATA0_4 DSP1_DATA1_0 0 DSP1_DATA0_0 OCU9_OTD1 0 ICU9_IN1 0 PPG9_TOUT2 DSP0_CTRL6 EINT3 DSP0_CTRL7 P5_21 0 SCK12 0 0 SIN12 0 0 0 0 0 0 OCU1_OTD1 0 0 OCU2_OTD0 0 DSP0_DATA1_10 ICU1_IN1 0 30 ICU2_IN0 0 - 0 0 VCC3 0 0 0 PPG1_TOUT2 0 0 PPG2_TOUT0 DVSS 0 EINT3 - 0 EINT4 125 0 SEG1 0 0 SEG0 0 0 0 0 P5_20 0 0 MFS12_SCL 0 P5_19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 204 DVCC 0 205 - 0 206 0 126 0 207 P3_21 29 208 EINT5 28 - - PPG6_TOUT2 - VSS Y ICU6_IN1 VCC12 Y OCU6_OTD1 0 0 Y AP0(AH0) PWM1P0 0 0 Y 0 0 0 VCC53 AN26 0 0 DSP1_CLK S 0 0 DSP1_CTRL2 0 0 127 0 0 DSP1_CTRL1 P3_23 P3_22 0 0 DSP1_CTRL0 EINT7 EINT6 0 0 0 PPG7_TOUT2 PPG7_TOUT0 0 0 0 ICU7_IN1 ICU7_IN0 0 0 0 OCU7_OTD1 OCU7_OTD0 0 0 0 BP0(BH0) PWM2P0 AN0(AL0) PWM1M0 0 0 0 0 0 0 0 0 AN28 AN27 0 0 DSP0_CTRL8 S S 0 0 DSP0_CTRL9 129 128 0 0 0 0 27 0 - 0 SOT11 VCC3_LVDS_Tx 0 SCK11 DSP0_CTRL10 0 0 SIN11 DSP0_CTRL11 0 0 0 0 0 0 0 0 0 0 0 OCU0_OTD1 0 OCU1_OTD0 SGA1 0 OCU1_OTD1 SGO1 0 OCU2_OTD0 0 0 0 ICU0_IN1 0 0 ICU1_IN0 P3_24 0 ICU1_IN1 EINT8 0 ICU2_IN0 PPG8_TOUT0 0 0 ICU8_IN0 26 0 OCU8_OTD0 - 0 BN0(BL0) PWM2M0 VSS_LVDS_Tx 0 0 0 0 AN29 0 0 S 0 PPG0_TOUT2 0 130 0 PPG1_TOUT0 P3_25 0 PPG1_TOUT2 EINT9 0 PPG2_TOUT0 0 PPG8_TOUT2 0 0 0 ICU8_IN1 0 0 0 P4_25 COM3 EINT9 OCU8_OTD1 0 0 0 P4_26 COM2 EINT10 AP1(AH1) PWM1P1 0 0 0 P4_27 COM1 EINT11 0 0 0 0 P4_28 COM0 EINT12 AN30 0 0 0 S 0 0 0 131 0 0 0 0 P3_26 0 0 P3_28 P3_27 EINT10 0 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 D D D D C - - E - - E E E E E - E - - E E E E E - - F F F - - - G H J J I I I I J J I I I I I L - VCC3 DSP0_DATA0_9 DSP0_DATA_D9+ CAP0_DATA21 0 DSP0_DATA1_9 DSP0_DATA_D9- DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK DSP0_CTRL0 VCC12 VSS M_SCLK0 VSS VCC3 M_SDATA0_0 M_SDATA0_2 M_SDATA0_1 M_SSEL0 M_SDATA0_3 VSS 0 VSS VCC3 M_SDATA1_0 M_SDATA1_2 M_SDATA1_1 M_SSEL1 M_SDATA1_3 VSS VCC3 MLBDAT MLBSIG MLBCLK VCC12 VSS VCC5 PSC_1 0 AN1 AN2 AN3 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 DSP0_CTRL2 0 0 0 0 0 G_SDATA1_0 G_SDATA1_2 G_SDATA1_1 G_SSEL1 G_SDATA1_3 0 G_SCLK0 0 0 G_SDATA0_0 G_SDATA0_2 G_SDATA0_1 G_SSEL0 G_SDATA0_3 0 0 DSP0_CTRL2 DSP0_CTRL3 DSP0_CTRL4 0 0 0 0 0 SOT0 SCK0 SIN0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 CAP0_DATA34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0_DATA25 0 0 0 CAP0_DATA24 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 RXCLK TIN33 I2S0_SCK DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 I2S1_SD DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 TXCLK TOT33 I2S0_WS COL 0 TXER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 TOT35 I2S1_WS TIN35 I2S1_SCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN1 TIN2 TIN3 TOT0 TOT1 TOT2 TOT3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGA0 SGA1 SGO1 SGO2 SGA3 SGO3 SGO0 SGA0 SGA1 SGO1 TOT16 SGO2 TIN17 0 0 0 TIN16 SGA2 0 0 TIN49 0 0 0 0 0 0 0 0 DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU9_OTD0 OCU8_OTD1 OCU5_OTD1 0 0 OCU6_OTD0 OCU7_OTD0 OCU6_OTD1 OCU8_OTD0 OCU7_OTD1 0 0 0 0 0 0 OCU3_OTD0 OCU5_OTD1 OCU8_OTD0 OCU8_OTD1 OCU9_OTD0 OCU9_OTD1 ICU8_IN1 ICU9_IN0 0 0 0 0 ICU9_IN0 ICU9_IN1 ICU8_IN1 0 ICU5_IN1 0 0 ICU6_IN0 ICU7_IN0 ICU6_IN1 ICU8_IN0 ICU7_IN1 0 0 0 0 ICU4_IN1 0 0 0 0 ICU3_IN0 ICU4_IN1 ICU5_IN0 ICU5_IN1 ICU6_IN1 ICU7_IN0 ICU7_IN1 ICU8_IN0 ICU8_IN1 ICU9_IN0 ICU9_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPG6_TOUT2 PPG7_TOUT0 PPG7_TOUT2 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 0 0 0 PPG9_TOUT0 PPG8_TOUT2 PPG5_TOUT2 0 0 PPG6_TOUT0 PPG7_TOUT0 PPG6_TOUT2 PPG8_TOUT0 PPG7_TOUT2 0 0 0 0 PPG4_TOUT2 0 0 0 0 PPG3_TOUT0 PPG4_TOUT2 PPG5_TOUT0 PPG5_TOUT2 PPG6_TOUT2 PPG7_TOUT0 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG9_TOUT2 EINT1 EINT2 0 0 0 0 0 0 EINT6 EINT8 EINT7 0 0 EINT1 EINT2 EINT3 0 0 0 0 EINT6 EINT9 0 0 0 P0_30 M_RWDS_0 0 0 P1_00 M_DQ5_0 P1_02 M_DQ7_0 P0_28 0 0 0 0 0 0 P2_25 0 P3_00 0 P3_01 0 P3_02 0 P3_03 0 P3_04 0 P3_05 0 P3_06 0 0 0 P2_22 0 0 0 P0_27 0 0 0 P0_26 0 0 0 P1_01 M_DQ4_0 0 0 P0_31 M_CS#2_0 0 0 EINT15 P2_31 0 PPG11_TOUT0 EINT6 0 0 EINT14 P2_30 0 EINT3 0 0 P1_09 M_CK_0 EINT13 P2_29 0 EINT2 0 0 0 0 0 G_DQ4_2 G_DQ5_2 G_DQ6_2 G_DQ7_2 0 0 0 0 0 G_CK_1 0 0 G_DQ3_1 G_DQ2_1 G_DQ1_1 G_DQ0_1 0 0 G_DQ5_1 G_DQ6_1 G_DQ7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP0_CTRL2 DSP0_CLK DSP0_CTRL0 DSP0_CTRL1 0 0 0 0 0 0 0 0 0 0 0 G_CS#2_1 0 G_DQ4_1 0 G_RWDS_1 0 0 0 G_CS#1_1 0 EINT11 P2_27 INDICATOR0_0 0 EINT1 0 EINT10 P2_26 0 EINT0 P5_22 0 EINT10 P1_03 M_DQ6_0 EINT9 P0_17 0 EINT11 P1_04 M_DQ0_0 EINT5 P0_16 0 EINT13 P1_06 M_DQ1_0 0 P0_15 0 EINT12 P1_05 M_DQ3_0 PPG10_TOUT2 EINT5 0 EINT0 PPG10_TOUT0 EINT4 0 EINT15 P0_14 0 PPG10_TOUT2 EINT15 P1_08 M_CS#1_0 0 EINT14 P0_13 0 PPG10_TOUT0 EINT14 P1_07 M_DQ2_0 PPG9_TOUT2 EINT13 P0_12 0 PPG11_TOUT0 EINT0 0 0 PPG10_TOUT0 EINT4 FRT8/9/10/11_TEXT PPG7_TOUT2 OCU11_OTD0 ICU11_IN0 0 0 0 OCU10_OTD1 ICU10_IN1 0 0 ICU8_IN0 OCU10_OTD0 ICU10_IN0 0 0 ICU7_IN1 OCU10_OTD1 ICU10_IN1 0 0 ICU7_IN0 OCU10_OTD0 ICU10_IN0 0 OCU9_OTD1 ICU6_IN1 OCU11_OTD0 ICU11_IN0 0 ZIN9 OCU7_OTD1 0 0 0 OCU10_OTD0 ICU10_IN0 0 BIN9 OCU7_OTD0 0 OCU9_OTD0 AIN9 OCU6_OTD1 0 OCU8_OTD1 ZIN8 OCU5_OTD0 0 OCU8_OTD0 BIN8 OCU4_OTD1 0 OCU7_OTD1 SIN1 OCU4_OTD1 0 OCU7_OTD0 SCK1 0 0 OCU6_OTD1 SOT1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 CAP0_DATA22 0 0 0 0 60 D 0 59 D 0 58 - 0 57 0 56 0 55 0 54 0 53 Page 34 of 222 Document Number: 002-05682 Rev. *K EINT12 EINT11 PPG9_TOUT0 25 Condition on PCB Set to ground Package Pin Number 12 to 27 PPG10_TOUT0 PPG9_TOUT2 ICU9_IN0 23 24 B 0 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 47 110 N2 JTAG_TDI 0 0 0 0 0 0 0 0 G_DQ0_2 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 48 109 O JTAG_TDO 0 0 0 0 0 0 0 0 0 G_CS#1_2 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 49 108 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 G_RWDS_2 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 50 107 M X0 0 0 0 0 0 0 0 0 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 51 106 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 52 105 - VSS 0 0 0 0 0 0 0 0 0 ICU10_IN0 ICU9_IN1 OCU9_OTD0 B B TxDOUT0- 0 CAP0_DATA14 CAP0_DATA15 0 OCU10_OTD0 OCU9_OTD1 TxDOUT1- TxDOUT0+ 0 0 4 0 3 A VSS 0 2 A C_R 0 - DAC_R 0 0 Any function at the following pins is not supported. - 1 AVSS 0 0 AN1(AL1) PWM1M1 0 0 0 MFS4_SCL - 0 0 0 BN1(BL1) PWM2M1 0 0 0 0 MFS0_CS1 0 0 0 0 BP1(BH1) PWM2P1 0 0 0 MFS0_CS2 P4_11 0 0 0 0 0 0 0 0 P4_12 EINT11 0 0 0 0 0 0 0 0 0 EINT12 PPG5_TOUT2 0 0 0 0 0 0 0 0 0 0 PPG6_TOUT0 ICU5_IN1 0 0 0 0 AN31 0 0 0 0 0 ICU6_IN0 OCU5_OTD1 0 0 0 0 AN33 0 0 0 0 0 OCU6_OTD0 PWM2P5 0 0 0 0 AN32 0 0 0 0 0 PWM2M5 RX1 0 0 0 0 S 0 0 0 0 0 TX1 SCK4 0 0 0 0 S 0 0 0 0 0 SIN4 AN48 0 0 0 0 S 0 0 0 0 0 AN49 S 0 0 0 0 132 0 0 0 0 DVSS S 153 0 0 0 0 134 0 0 0 DVCC 154 0 0 0 0 133 0 0 0 155 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT2- B 19 138 S AN35 0 0 PWM1M2 OCU11_OTD0 ICU11_IN0 PPG11_TOUT0 EINT14 P3_30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxCLK+ B 20 137 S AN34 0 0 PWM1P2 OCU10_OTD1 ICU10_IN1 PPG10_TOUT2 EINT13 P3_29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxCLK- B 21 136 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT1+ B 22 135 - DVSS 0 0 0 0 0 0 0 0 0 TOP VIEW TEQFP-208 0 0 156 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVSS - 5 152 S AN47 SOT4 0 PWM1M5 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT10 P4_10 MFS0_CS3 MFS4_SDA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVCC3_DAC - 6 151 S AN46 0 0 PWM1P5 OCU4_OTD1 ICU4_IN1 PPG4_TOUT2 EINT9 P4_09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC_L A 7 150 S AN45 SIN3 0 PWM2M4 OCU4_OTD0 ICU4_IN0 PPG4_TOUT0 EINT8 P4_08 MFS2_CS1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C_L A 8 149 S AN44 SCK3 0 PWM2P4 OCU3_OTD1 ICU3_IN1 PPG3_TOUT2 EINT7 P4_07 MFS2_CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVSS - 9 148 S AN43 SOT3 0 PWM1M4 OCU3_OTD0 ICU3_IN0 PPG3_TOUT0 EINT6 P4_06 MFS0_CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 10 147 S AN42 0 0 PWM1P4 OCU2_OTD1 ICU2_IN1 PPG2_TOUT2 EINT5 P4_05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 11 146 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVSS_LVDS_PLL - 12 145 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVCC3_LVDS_PLL - 13 144 S AN41 SIN2 0 PWM2M3 OCU2_OTD0 ICU2_IN0 PPG2_TOUT0 EINT4 P4_04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3_LVDS_Tx - 14 143 S AN40 SCK2 0 PWM2P3 OCU1_OTD1 ICU1_IN1 PPG1_TOUT2 EINT3 P4_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS_LVDS_Tx - 15 142 S AN39 SOT2 0 PWM1M3 OCU1_OTD0 ICU1_IN0 PPG1_TOUT0 EINT2 P4_02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT3+ B 16 141 S AN38 0 0 PWM1P3 OCU0_OTD1 ICU0_IN1 PPG0_TOUT2 EINT1 P4_01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT3- B 17 140 S AN37 0 0 PWM2M2 OCU0_OTD0 ICU0_IN0 PPG0_TOUT0 EINT0 P4_00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT2+ B 18 139 S AN36 0 0 PWM2P2 OCU11_OTD1 ICU11_IN1 PPG11_TOUT2 EINT15 P3_31 0 DSP0_DATA1_11 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 124 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 123 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 122 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 120 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 119 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 P6_00 EINT13 EINT0 PPG10_TOUT2 PPG0_TOUT0 ICU10_IN1 ICU0_IN0 OCU10_OTD1 OCU0_OTD0 0 0 TOT1 TIN2 0 0 CAP0_DATA5 CAP0_DATA8 DSP0_DATA_D1+ DSP0_DATA_D2- DSP0_DATA0_1 DSP0_DATA1_2 D D 36 39 121 118 - H AVSS ADTRG 0 0 0 SGA3 0 TOT35 0 OCU5_OTD0 0 ICU5_IN0 0 PPG5_TOUT0 0 EINT2 P3_18 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 117 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 116 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 115 - VCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 114 Q RSTX 0 0 0 0 0 0 0 0 CAP0_DATA11 G_CK_2 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 44 113 P MODE 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 45 112 N2 JTAG_TMS 0 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 46 111 N2 JTAG_TCK 0 0 0 0 0 0 0 0 Notes: - The pins highlighted in "red" font are not supported for products with revision A and C. S6J3200 Series Figure 4-14: TEQFP-208 (S6J323CKxx) 0 0 0 0 0 0 0 ICU2_IN1 ICU2_IN0 ICU0_IN1 ICU0_IN0 0 0 0 0 0 0 OCU3_OTD1 SGO1 TIN33 SOT11 OCU3_OTD0 SGA1 TOT33 SIN10 OCU2_OTD1 SGA0 TIN32 SCK10 OCU2_OTD0 SGO0 TOT32 SOT10 OCU0_OTD0 WOT TOT18 0 OCU4_OTD0 SGA2 TOT34 SCK11 0 TIN18 0 OCU4_OTD1 SGO2 TIN34 SIN11 OCU0_OTD1 0 0 0 SIN9 SCK9 SOT9 BP0(BH0) AN0(AL0) AP0(AH0) 0 0 0 0 0 TX6 RX6 TX5 RX5 0 0 TX5 RX5 0 0 0 DSP1_DATA0_11 0 DSP1_DATA1_11 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_DATA1_9 0 DSP1_DATA1_10 0 DSP1_DATA0_9 0 DSP1_DATA0_10 0 DSP1_DATA1_8 VCC53 VSS VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN17 AN16 AN15 - Y Y Y Y Y Y Y Y - - - X X W W W W W W V V V 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 157 0 0 V3 EINT3 0 PPG0_TOUT0 PPG6/7/8/9/10/11_TIN V2 EINT7 PPG11_TOUT2 0 ICU3_IN0 0 0 0 BN0(BL0) 0 - 185 - 0 0 P2_19 V1 EINT8 PPG0_TOUT2 FRT4/5/6/7_TEXT ICU3_IN1 0 ICU4_IN0 OCU0_OTD1 0 0 0 AP1(AH1) 0 VCC12 DSP1_DATA0_8 - VCC5 0 0 P3_07 PPG2_TOUT0 0 ICU4_IN1 0 OCU0_OTD0 0 0 0 AN1(AL1) 0 VCC12 - 0 0 0 P3_08 V0 EINT9 PPG2_TOUT2 0 ICU0_IN1 0 0 0 0 BP1(BH1) 0 VSS 0 0 0 0 P3_09 PPG3_TOUT0 0 0 ICU0_IN0 0 0 0 SOT8 0 VCC53 0 0 MFS8_CS0 0 P3_12 SEG29 EINT12 PPG3_TOUT2 0 0 OCU3_OTD0 SGA3 0 SCK8 0 BN1(BL1) 0 186 0 0 0 MFS9_CS0 0 P3_13 SEG28 EINT13 PPG4_TOUT0 0 0 OCU3_OTD1 SGO3 OCU2_OTD1 0 0 0 0 187 0 0 0 MFS9_CS1 0 P3_14 SEG27 EINT14 PPG4_TOUT2 0 ICU2_IN1 0 0 0 SIN8 0 Y 0 0 0 MFS8_CS3 0 P3_15 SEG26 EINT15 PPG0_TOUT2 0 ICU3_IN0 OCU4_OTD0 0 0 0 0 Y 188 0 0 0 EINT0 0 PPG0_TOUT0 0 ICU3_IN1 OCU4_OTD1 0 0 0 DSP1_DATA1_7 189 0 0 0 MFS8_CS1 0 P3_16 SEG25 EINT1 0 0 ICU4_IN0 OCU5_OTD0 0 0 0 DSP1_DATA0_7 Y 0 0 0 MFS8_CS2 0 P3_17 SEG24 EINT1 0 0 ICU4_IN1 OCU5_OTD1 0 0 0 Y 0 0 0 0 0 EINT0 PPG2_TOUT2 0 ICU5_IN0 0 0 0 DSP1_DATA1_6 158 0 0 0 PPG3_TOUT0 0 ICU5_IN1 0 OCU6_OTD0 0 0 DSP1_DATA0_6 - 0 0 0 P2_17 0 0 PPG3_TOUT2 0 0 0 0 0 VSS 0 0 0 0 0 PPG4_TOUT0 0 0 ICU6_IN0 0 0 0 0 0 0 0 0 0 0 PPG4_TOUT2 0 0 0 SOT9 0 0 0 0 0 0 INDICATOR0_1 0 P2_16 0 0 0 P4_29 SEG23 EINT13 PPG5_TOUT0 0 0 0 0 0 0 0 0 0 P4_30 SEG22 EINT14 0 EINT0 0 0 P4_31 SEG21 EINT15 0 0 EINT1 PPG5_TOUT2 0 0 0 SIN9 SCK9 0 0 0 0 0 P5_00 SEG20 EINT2 0 PPG6_TOUT0 0 0 0 0 0 0 0 0 P5_01 SEG19 EINT3 0 0 0 0 0 0 0 0 0 P5_02 SEG18 0 EINT4 0 OCU6_OTD1 0 0 0 0 0 0 P5_03 SEG17 0 0 OCU7_OTD0 0 0 0 0 0 0 0 P5_04 SEG16 0 ICU6_IN1 OCU7_OTD1 0 0 0 0 0 ICU7_IN0 OCU8_OTD0 0 0 0 0 0 0 ICU7_IN1 159 0 0 0 0 0 ICU8_IN0 U 0 0 0 0 0 PPG6_TOUT2 0 0 0 0 0 0 0 PPG7_TOUT0 0 0 0 0 0 0 EINT5 PPG7_TOUT2 0 0 0 0 0 EINT6 PPG8_TOUT0 0 0 0 0 0 0 P5_05 SEG15 EINT7 AIN8 0 0 0 0 0 P5_06 SEG14 EINT8 OCU8_OTD1 0 0 0 0 0 P5_07 SEG13 ICU8_IN1 0 0 0 0 0 P5_08 SEG12 0 ICU1_IN1 0 0 PPG8_TOUT2 TIN48 0 0 EINT9 0 0 0 0 P5_09 SEG11 0 0 0 0 DSP1_DATA0_5 DSP1_DATA1_5 Y Y 191 190 0 TOT17 0 0 0 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 0 0 SOT10 0 OCU9_OTD0 BIN8 PPG9_TOUT0 ICU9_IN0 MFS8_CS0 0 P5_10 SEG10 EINT10 192 0 MFS10_SDA Y OCU9_OTD1 DSP1_DATA1_4 ICU9_IN1 0 0 0 PPG9_TOUT2 0 SCK10 SEG9 EINT11 ZIN8 MFS9_CS0 0 P5_11 ICU11_IN0 PPG11_TOUT0 EINT14 P3_30 0 OCU10_OTD1 ICU10_IN1 PPG10_TOUT2 EINT13 P3_29 0 0 0 0 0 0 0 0 0 0 0 TxCLK- B 21 136 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT1+ B 22 135 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT1- B 23 134 S AN33 0 BN1(BL1) PWM2M1 OCU10_OTD0 ICU10_IN0 PPG10_TOUT0 EINT12 P3_28 0 0 0 0 0 0 0 0 0 0 0 TxDOUT0+ B 24 133 S AN32 0 BP1(BH1) PWM2P1 OCU9_OTD1 ICU9_IN1 PPG9_TOUT2 EINT11 P3_27 0 0 0 0 0 0 0 0 0 0 0 TxDOUT0- B 25 132 S AN31 0 AN1(AL1) PWM1M1 OCU9_OTD0 ICU9_IN0 PPG9_TOUT0 EINT10 P3_26 0 0 0 0 0 0 0 0 0 0 0 0 VSS_LVDS_Tx - 26 131 S AN30 0 AP1(AH1) PWM1P1 OCU8_OTD1 ICU8_IN1 PPG8_TOUT2 EINT9 P3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3_LVDS_Tx - 27 130 S AN29 0 BN0(BL0) PWM2M0 OCU8_OTD0 ICU8_IN0 PPG8_TOUT0 EINT8 P3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 28 129 S AN28 0 BP0(BH0) PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 29 128 S AN27 0 AN0(AL0) PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 30 127 S AN26 0 AP0(AH0) PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 0 0 0 0 0 0 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 DSP0_DATA0_4 MDC CAP0_DATA0 0 DSP0_CTRL1 C 31 126 - DVCC 0 0 0 0 0 0 0 0 DSP0_DATA0_11 0 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK+ DSP0_CLK D 32 125 - DVSS 0 0 0 0 0 0 0 0 DSP0_DATA1_11 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 124 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 123 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 122 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 0 CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 121 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 120 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 119 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 0 CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 39 118 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 117 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 116 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 115 - VCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 114 Q RSTX 0 0 0 0 0 0 0 0 CAP0_DATA11 G_CK_2 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 44 113 P MODE 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 45 112 N2 JTAG_TMS 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 46 111 N2 JTAG_TCK 0 0 0 0 0 0 0 0 CAP0_DATA14 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 47 110 N2 JTAG_TDI 0 0 0 0 0 0 0 0 CAP0_DATA15 G_DQ0_2 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 48 109 O JTAG_TDO 0 0 0 0 0 0 0 0 0 G_CS#1_2 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 49 108 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 G_RWDS_2 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 50 107 M X0 0 0 0 0 0 0 0 0 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 51 106 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 52 105 - VSS 0 0 0 0 0 0 0 0 TOP VIEW TEQFP-208 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 D D D D C - - E - - E E E E E - E - - E E E E E - - F F F - - - G H J J I I I I J J I I I I I L - VCC3 DSP0_DATA0_9 DSP0_DATA_D9+ CAP0_DATA21 0 DSP0_DATA1_9 DSP0_DATA_D9- DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK DSP0_CTRL0 VCC12 VSS M_SCLK0 VSS VCC3 M_SDATA0_0 M_SDATA0_2 M_SDATA0_1 M_SSEL0 M_SDATA0_3 VSS 0 VSS VCC3 M_SDATA1_0 M_SDATA1_2 M_SDATA1_1 M_SSEL1 M_SDATA1_3 VSS VCC3 MLBDAT MLBSIG MLBCLK VCC12 VSS VCC5 PSC_1 0 AN1 AN2 AN3 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 DSP0_CTRL2 0 0 0 0 0 G_SDATA1_0 G_SDATA1_2 G_SDATA1_1 G_SSEL1 G_SDATA1_3 0 G_SCLK0 0 0 G_SDATA0_0 G_SDATA0_2 G_SDATA0_1 G_SSEL0 G_SDATA0_3 0 0 DSP0_CTRL2 DSP0_CTRL3 DSP0_CTRL4 0 0 0 0 0 SOT0 SCK0 SIN0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 CAP0_DATA34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0_DATA25 0 0 0 CAP0_DATA24 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 RXCLK TIN33 I2S0_SCK DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 I2S1_SD DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 TXCLK TOT33 I2S0_WS COL 0 TXER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 TOT35 I2S1_WS TIN35 I2S1_SCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN1 TIN2 TIN3 TOT0 TOT1 TOT2 TOT3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGA0 SGA1 SGO1 SGO2 SGA3 SGO3 SGO0 SGA0 SGA1 SGO1 TOT16 SGO2 TIN17 0 0 0 TIN16 SGA2 0 0 TIN49 0 0 0 0 0 0 0 0 DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU9_OTD0 OCU8_OTD1 OCU5_OTD1 0 0 OCU6_OTD0 OCU7_OTD0 OCU6_OTD1 OCU8_OTD0 OCU7_OTD1 0 0 0 0 0 0 OCU3_OTD0 OCU5_OTD1 OCU8_OTD0 OCU8_OTD1 OCU9_OTD0 OCU9_OTD1 ICU8_IN1 ICU9_IN0 0 0 0 0 ICU9_IN0 ICU9_IN1 ICU8_IN1 0 ICU5_IN1 0 0 ICU6_IN0 ICU7_IN0 ICU6_IN1 ICU8_IN0 ICU7_IN1 0 0 0 0 ICU4_IN1 0 0 0 0 ICU3_IN0 ICU4_IN1 ICU5_IN0 ICU5_IN1 ICU6_IN1 ICU7_IN0 ICU7_IN1 ICU8_IN0 ICU8_IN1 ICU9_IN0 ICU9_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPG6_TOUT2 PPG7_TOUT0 PPG7_TOUT2 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 0 0 0 PPG9_TOUT0 PPG8_TOUT2 PPG5_TOUT2 0 0 PPG6_TOUT0 PPG7_TOUT0 PPG6_TOUT2 PPG8_TOUT0 PPG7_TOUT2 0 0 0 0 PPG4_TOUT2 0 0 0 0 PPG3_TOUT0 PPG4_TOUT2 PPG5_TOUT0 PPG5_TOUT2 PPG6_TOUT2 PPG7_TOUT0 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG9_TOUT2 EINT1 EINT2 0 0 0 0 0 0 EINT6 EINT8 EINT7 0 0 EINT1 EINT2 EINT3 0 0 0 0 EINT6 EINT9 0 0 0 P0_30 M_RWDS_0 0 0 P1_00 M_DQ5_0 P1_02 M_DQ7_0 P0_28 0 0 0 0 0 0 P2_25 0 P3_00 0 P3_01 0 P3_02 0 P3_03 0 P3_04 0 P3_05 0 P3_06 0 0 0 P2_22 0 0 0 P0_27 0 0 0 P0_26 0 0 0 P1_01 M_DQ4_0 0 0 P0_31 M_CS#2_0 0 0 EINT15 P2_31 0 PPG11_TOUT0 EINT6 0 0 EINT14 P2_30 0 EINT3 0 0 P1_09 M_CK_0 EINT13 P2_29 0 EINT2 0 0 0 0 0 G_DQ4_2 G_DQ5_2 G_DQ6_2 G_DQ7_2 0 0 0 0 0 G_CK_1 0 0 G_DQ3_1 G_DQ2_1 G_DQ1_1 G_DQ0_1 0 0 G_DQ5_1 G_DQ6_1 G_DQ7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP0_CTRL2 DSP0_CLK DSP0_CTRL0 DSP0_CTRL1 0 0 0 0 0 0 0 0 0 0 0 G_CS#2_1 0 G_DQ4_1 0 G_RWDS_1 0 0 0 G_CS#1_1 0 EINT11 P2_27 INDICATOR0_0 0 EINT1 0 EINT10 P2_26 0 EINT0 P5_22 0 EINT10 P1_03 M_DQ6_0 EINT9 P0_17 0 EINT11 P1_04 M_DQ0_0 EINT5 P0_16 0 EINT13 P1_06 M_DQ1_0 0 P0_15 0 EINT12 P1_05 M_DQ3_0 PPG10_TOUT2 EINT5 0 EINT0 PPG10_TOUT0 EINT4 0 EINT15 P0_14 0 PPG10_TOUT2 EINT15 P1_08 M_CS#1_0 0 EINT14 P0_13 0 PPG10_TOUT0 EINT14 P1_07 M_DQ2_0 PPG9_TOUT2 EINT13 P0_12 0 PPG11_TOUT0 EINT0 0 0 PPG10_TOUT0 EINT4 FRT8/9/10/11_TEXT PPG7_TOUT2 OCU11_OTD0 ICU11_IN0 0 0 0 OCU10_OTD1 ICU10_IN1 0 0 ICU8_IN0 OCU10_OTD0 ICU10_IN0 0 0 ICU7_IN1 OCU10_OTD1 ICU10_IN1 0 0 ICU7_IN0 OCU10_OTD0 ICU10_IN0 0 OCU9_OTD1 ICU6_IN1 OCU11_OTD0 ICU11_IN0 0 ZIN9 OCU7_OTD1 0 0 0 OCU10_OTD0 ICU10_IN0 0 BIN9 OCU7_OTD0 0 OCU9_OTD0 AIN9 OCU6_OTD1 0 OCU8_OTD1 ZIN8 OCU5_OTD0 0 OCU8_OTD0 BIN8 OCU4_OTD1 0 OCU7_OTD1 SIN1 OCU4_OTD1 0 OCU7_OTD0 SCK1 0 0 OCU6_OTD1 SOT1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 CAP0_DATA22 0 0 0 0 60 D 0 59 D 0 58 - 0 57 0 56 0 55 0 54 0 53 Page 35 of 222 Document Number: 002-05682 Rev. *K Condition on PCB Set to ground Open Package Pin Number 2, 5, 6, 9, and 12 to 27 3, 4, 7, 8 0 MFS10_SCL OCU11_OTD0 PWM1P2 0 193 PWM1M2 0 0 194 0 0 DSP0_DATA1_10 - 0 AN34 0 Y AN35 S 0 VCC53 S 137 0 DSP1_DATA0_4 138 20 0 0 19 B 0 0 B TxCLK+ 0 0 TxDOUT2- 0 0 0 0 0 0 0 0 0 0 0 SIN10 0 0 0 0 0 0 0 0 0 0 0 AIN9 0 0 0 0 0 0 0 0 0 0 0 0 ICU10_IN0 OCU10_OTD0 0 0 0 0 0 0 P3_31 0 0 EINT15 0 0 PPG11_TOUT2 0 SEG8 EINT12 PPG10_TOUT0 ICU11_IN1 0 0 OCU11_OTD1 0 0 0 PWM2P2 0 MFS9_CS1 0 P5_12 0 0 0 0 0 0 AN36 0 0 S 0 0 139 0 195 18 0 - B 0 VSS TxDOUT2+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P4_00 0 0 EINT0 0 0 PPG0_TOUT0 0 0 0 ICU0_IN0 0 0 OCU0_OTD0 0 0 PWM2M2 0 196 0 0 Y 0 0 DSP1_DATA1_3 AN37 0 0 S 0 DSP0_CTRL0 140 0 0 17 0 0 B 0 0 ICU10_IN1 OCU10_OTD1 BIN9 TxDOUT3- 0 SEG7 EINT13 PPG10_TOUT2 0 0 0 0 P5_13 0 0 0 0 0 0 0 0 197 0 0 Y 0 0 DSP1_DATA0_3 0 0 0 0 0 0 DSP0_CTRL1 P4_01 0 0 SOT11 EINT1 0 ZIN9 PPG0_TOUT2 0 0 ICU11_IN0 OCU11_OTD0 ICU0_IN1 0 SEG6 EINT14 PPG11_TOUT0 OCU0_OTD1 0 MFS8_CS3 0 P5_14 PWM1P3 0 0 0 0 0 0 0 198 AN38 0 199 S 0 Y 141 0 Y 16 0 DSP1_DATA1_2 B 0 DSP1_DATA0_2 TxDOUT3+ 0 DSP1_CLK 0 0 DSP0_CTRL2 DSP1_CTRL2 0 0 DSP0_CTRL3 0 0 0 SCK11 0 0 0 SIN11 0 0 0 0 0 0 0 0 0 0 OCU0_OTD0 0 P4_02 0 ICU0_IN0 P4_03 EINT2 0 0 ICU11_IN1 OCU11_OTD1 EINT3 PPG1_TOUT0 0 0 PPG1_TOUT2 ICU1_IN0 0 PPG0_TOUT0 ICU1_IN1 OCU1_OTD0 0 EINT0 OCU1_OTD1 PWM1M3 0 SEG5 EINT15 PPG11_TOUT2 PWM2P3 0 0 0 SEG4 0 SOT2 0 0 MFS8_CS1 0 P5_15 SCK2 AN39 0 0 MFS8_CS2 0 P5_16 AN40 S 0 0 0 S 142 0 0 0 143 15 0 0 0 14 0 0 0 - VSS_LVDS_Tx 0 0 200 VCC3_LVDS_Tx 0 0 0 Y 0 0 0 0 DSP1_DATA1_1 0 0 0 DSP0_CTRL4 DSP1_CTRL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU0_OTD1 P4_04 0 ICU0_IN1 EINT4 0 0 PPG2_TOUT0 0 PPG0_TOUT2 ICU2_IN0 0 EINT1 OCU2_OTD0 0 SEG3 PWM2M3 0 0 0 P5_17 0 0 0 SIN2 0 0 AN41 0 201 S 0 Y 144 0 DSP1_DATA0_1 13 0 DSP0_CTRL5 DSP1_CTRL1 0 0 SOT12 AVCC3_LVDS_PLL 0 0 0 0 OCU1_OTD0 0 0 ICU1_IN0 0 0 0 0 0 0 PPG1_TOUT0 0 0 EINT2 0 0 SEG2 0 0 MFS12_SDA 0 P5_18 0 0 0 0 0 0 0 0 202 0 0 203 0 0 Y 0 0 Y DVSS 0 DSP1_DATA1_0 - 0 DSP1_DATA0_0 145 0 0 12 0 0 0 DSP0_CTRL6 AVSS_LVDS_PLL 0 DSP0_CTRL7 0 0 0 SCK12 0 0 0 SIN12 0 0 0 0 0 0 0 0 0 0 0 OCU1_OTD1 0 0 0 OCU2_OTD0 0 0 0 ICU1_IN1 0 0 0 ICU2_IN0 0 0 0 0 0 0 0 0 0 0 0 PPG1_TOUT2 0 0 0 PPG2_TOUT0 DVCC 0 0 EINT3 - 0 0 EINT4 146 0 0 SEG1 11 0 0 SEG0 0 0 0 0 P5_20 VCC12 0 MFS12_SCL 0 P5_19 0 0 0 0 0 0 0 0 0 0 0 MFS0_CS0 P4_05 0 0 P4_06 EINT5 0 204 EINT6 PPG2_TOUT2 0 205 PPG3_TOUT0 ICU2_IN1 0 206 ICU3_IN0 OCU2_OTD1 0 207 OCU3_OTD0 PWM1P4 0 208 PWM1M4 0 0 - 0 0 0 Y SOT3 AN42 0 Y AN43 S 0 Y S 147 0 Y 148 10 0 VCC53 9 0 DSP1_CLK - VSS DAC_L DSP1_CTRL2 AVSS 0 0 DSP1_CTRL1 0 0 0 DSP1_CTRL0 MFS2_CS0 0 0 P4_07 0 0 EINT7 0 0 PPG3_TOUT2 0 0 ICU3_IN1 0 0 OCU3_OTD1 0 0 PWM2P4 0 DSP0_CTRL8 0 0 DSP0_CTRL9 SCK3 0 0 0 AN44 0 0 S 0 0 SOT11 149 0 0 SCK11 DSP0_CTRL10 8 0 0 SIN11 DSP0_CTRL11 A 0 0 0 C_L - 0 MFS2_CS1 - AVCC3_DAC 0 P4_08 AVSS 0 0 EINT8 0 0 0 PPG4_TOUT0 0 0 OCU0_OTD1 ICU4_IN0 0 0 OCU1_OTD0 SGA1 OCU4_OTD0 0 0 OCU1_OTD1 SGO1 PWM2M4 0 0 OCU2_OTD0 0 0 0 0 SIN3 0 0 ICU0_IN1 AN45 0 0 ICU1_IN0 S 0 0 ICU1_IN1 0 150 0 0 ICU2_IN0 MFS4_SDA 0 7 0 0 0 MFS0_CS3 P4_09 A 0 0 0 P4_10 EINT9 0 0 0 EINT10 PPG4_TOUT2 0 0 0 PPG5_TOUT0 ICU4_IN1 0 0 0 ICU5_IN0 OCU4_OTD1 0 0 OCU5_OTD0 PWM1P5 4 PPG0_TOUT2 PWM1M5 0 3 A VSS PPG1_TOUT0 0 0 2 A C_R PPG1_TOUT2 SOT4 AN46 - DAC_R 0 PPG2_TOUT0 0 AN47 S 1 AVSS 0 0 0 0 MFS4_SCL S 151 - 0 0 0 0 0 P4_25 COM3 EINT9 0 MFS0_CS1 152 6 0 0 0 0 0 0 P4_26 COM2 EINT10 MFS0_CS2 P4_11 5 0 0 0 0 0 0 P4_27 COM1 EINT11 P4_12 EINT11 0 0 0 0 0 0 P4_28 COM0 EINT12 0 EINT12 PPG5_TOUT2 0 0 0 0 0 0 0 0 PPG6_TOUT0 ICU5_IN1 0 0 0 0 0 0 0 ICU6_IN0 OCU5_OTD1 0 0 0 0 0 0 0 OCU6_OTD0 PWM2P5 0 0 0 0 0 0 0 PWM2M5 RX1 0 0 0 0 0 0 0 TX1 SCK4 0 0 0 0 0 0 0 SIN4 AN48 0 0 0 0 0 0 0 AN49 S 0 0 0 0 0 0 DVSS S 153 0 0 0 0 0 DVCC 154 0 0 0 0 0 155 0 0 0 0 Any function at the following pins is not supported. - 156 0 0 0 Notes: - The pins highlighted in "red" font are not supported for products with revision A and C. S6J3200 Series Figure 4-15: TEQFP-208 (S6J32KEKxx) 0 0 0 0 PPG0_TOUT0 PPG6/7/8/9/10/11_TIN ICU2_IN1 ICU2_IN0 ICU0_IN1 ICU0_IN0 0 0 0 0 0 0 0 OCU3_OTD1 SGO1 TIN33 SOT11 OCU3_OTD0 SGA1 TOT33 SIN10 OCU2_OTD1 SGA0 TIN32 SCK10 OCU2_OTD0 SGO0 TOT32 SOT10 0 TIN18 0 OCU4_OTD0 SGA2 TOT34 SCK11 OCU0_OTD0 WOT TOT18 0 OCU4_OTD1 SGO2 TIN34 SIN11 OCU0_OTD1 0 0 0 SIN9 SCK9 SOT9 AN0(AL0) AP0(AH0) 0 0 0 0 0 TX6 RX6 TX5 RX5 0 0 TX5 RX5 0 0 0 DSP1_DATA1_10 0 DSP1_DATA0_11 0 DSP1_DATA1_11 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_DATA1_9 0 DSP1_DATA0_10 0 DSP1_DATA0_9 VCC53 VSS VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN17 AN16 AN15 Y Y Y Y Y Y Y - - - X X W W W W W W V V V 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 157 0 0 0 0 ICU3_IN0 OCU0_OTD1 0 0 0 BP0(BH0) 0 DSP1_DATA1_8 - Y 184 - 0 0 PPG0_TOUT2 V2 EINT7 PPG11_TOUT2 V3 EINT3 PPG2_TOUT0 0 ICU4_IN0 FRT4/5/6/7_TEXT ICU3_IN1 0 ICU4_IN1 OCU0_OTD0 0 0 0 AP1(AH1) BN0(BL0) 0 VCC12 DSP1_DATA0_8 - VCC5 0 0 P2_19 V1 EINT8 PPG2_TOUT2 0 ICU0_IN1 0 0 0 0 0 - 0 0 0 P3_07 V0 EINT9 PPG3_TOUT0 0 ICU0_IN0 0 0 0 AN1(AL1) 0 VSS VCC12 0 0 0 0 P3_08 PPG3_TOUT2 0 0 0 0 0 BP1(BH1) 0 185 0 0 MFS8_CS0 0 P3_12 SEG29 EINT12 PPG4_TOUT0 0 0 OCU3_OTD0 SGA3 0 SOT8 0 BN1(BL1) 0 186 0 0 0 MFS9_CS0 0 P3_13 SEG28 EINT13 PPG4_TOUT2 0 0 OCU3_OTD1 SGO3 OCU2_OTD1 0 0 SCK8 0 - 187 0 0 0 MFS9_CS1 0 P3_14 SEG27 EINT14 0 0 P3_09 EINT0 MFS8_CS3 0 P3_15 SEG26 EINT15 PPG0_TOUT2 0 ICU2_IN1 0 0 0 SIN8 0 Y 0 0 0 EINT1 PPG0_TOUT0 0 ICU3_IN0 OCU4_OTD0 0 0 0 VCC53 Y 188 0 0 0 MFS8_CS1 0 P3_16 SEG25 EINT1 0 0 ICU3_IN1 OCU4_OTD1 0 0 0 DSP1_DATA1_7 189 0 0 0 MFS8_CS2 0 P3_17 SEG24 EINT0 0 0 ICU4_IN0 0 0 0 DSP1_DATA0_7 Y 0 0 0 0 0 0 0 ICU4_IN1 OCU5_OTD0 0 0 0 Y 0 0 0 0 0 PPG2_TOUT2 0 OCU5_OTD1 0 0 0 DSP1_DATA1_6 158 0 0 0 0 PPG3_TOUT0 0 ICU5_IN0 0 OCU6_OTD0 0 0 DSP1_DATA0_6 - 0 0 0 0 P2_17 0 PPG3_TOUT2 0 ICU5_IN1 0 0 0 0 VSS 0 0 0 PPG4_TOUT0 0 0 ICU6_IN0 0 0 0 0 0 0 0 PPG4_TOUT2 0 0 0 SOT9 0 0 0 0 0 0 0 INDICATOR0_1 0 P2_16 0 0 0 P4_29 SEG23 EINT13 PPG5_TOUT0 0 0 0 0 0 0 0 0 0 P4_30 SEG22 EINT14 0 0 EINT0 0 0 P4_31 SEG21 EINT15 0 0 EINT1 PPG5_TOUT2 0 0 0 SIN9 SCK9 0 0 0 0 0 P5_00 SEG20 EINT2 0 PPG6_TOUT0 0 0 0 0 0 0 0 0 P5_01 SEG19 EINT3 0 0 0 0 0 0 0 0 0 P5_02 SEG18 0 EINT4 0 OCU6_OTD1 0 0 0 0 0 0 P5_03 SEG17 0 0 OCU7_OTD0 0 0 0 0 0 0 0 P5_04 SEG16 0 ICU6_IN1 OCU7_OTD1 0 0 0 0 0 ICU7_IN0 OCU8_OTD0 0 0 0 0 0 0 ICU7_IN1 159 0 0 0 0 0 ICU8_IN0 U 0 0 0 0 0 0 PPG6_TOUT2 0 0 0 0 0 0 0 PPG7_TOUT0 0 0 0 0 0 0 0 EINT5 PPG7_TOUT2 0 0 0 0 0 EINT6 PPG8_TOUT0 0 0 0 0 0 0 P5_05 SEG15 EINT7 AIN8 0 0 0 0 0 P5_06 SEG14 EINT8 OCU8_OTD1 0 0 0 0 0 P5_07 SEG13 ICU8_IN1 0 0 0 0 0 P5_08 SEG12 0 ICU1_IN1 0 0 PPG8_TOUT2 TIN48 0 0 EINT9 0 0 0 0 P5_09 SEG11 PPG9_TOUT0 0 ICU9_IN0 OCU9_OTD0 BIN8 0 SOT10 0 0 0 0 0 DSP1_DATA0_5 DSP1_DATA1_5 Y Y 191 190 0 TOT17 0 0 MFS8_CS0 0 P5_10 SEG10 EINT10 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 0 0 MFS10_SDA ICU10_IN1 PPG10_TOUT2 EINT13 P3_29 0 0 0 0 0 0 0 0 0 0 0 TxCLK- B 21 136 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT1+ B 22 135 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDOUT1- B 23 134 S AN33 0 BN1(BL1) PWM2M1 OCU10_OTD0 ICU10_IN0 PPG10_TOUT0 EINT12 P3_28 0 0 0 0 0 0 0 0 0 0 0 TxDOUT0+ B 24 133 S AN32 0 BP1(BH1) PWM2P1 OCU9_OTD1 ICU9_IN1 PPG9_TOUT2 EINT11 P3_27 0 0 0 0 0 0 0 0 0 0 0 TxDOUT0- B 25 132 S AN31 0 AN1(AL1) PWM1M1 OCU9_OTD0 ICU9_IN0 PPG9_TOUT0 EINT10 P3_26 0 0 0 0 0 0 0 0 0 0 0 0 VSS_LVDS_Tx - 26 131 S AN30 0 AP1(AH1) PWM1P1 OCU8_OTD1 ICU8_IN1 PPG8_TOUT2 EINT9 P3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3_LVDS_Tx - 27 130 S AN29 0 BN0(BL0) PWM2M0 OCU8_OTD0 ICU8_IN0 PPG8_TOUT0 EINT8 P3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 28 129 S AN28 0 BP0(BH0) PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 29 128 S AN27 0 AN0(AL0) PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 30 127 S AN26 0 AP0(AH0) PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 0 0 0 0 0 0 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 DSP0_DATA0_4 MDC CAP0_DATA0 0 DSP0_CTRL1 C 31 126 - DVCC 0 0 0 0 0 0 0 0 DSP0_DATA0_11 0 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK+ DSP0_CLK D 32 125 - DVSS 0 0 0 0 0 0 0 0 DSP0_DATA1_11 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK- DSP0_CTRL2 D 33 124 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 123 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 122 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 0 CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 121 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 37 120 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 119 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 0 CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 39 118 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 117 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 116 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 115 - VCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 114 Q RSTX 0 0 0 0 0 0 0 0 CAP0_DATA11 G_CK_2 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 44 113 P MODE 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 45 112 N2 JTAG_TMS 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 46 111 N2 JTAG_TCK 0 0 0 0 0 0 0 0 CAP0_DATA14 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 47 110 N2 JTAG_TDI 0 0 0 0 0 0 0 0 CAP0_DATA15 G_DQ0_2 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 48 109 O JTAG_TDO 0 0 0 0 0 0 0 0 0 G_CS#1_2 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 49 108 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 G_RWDS_2 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 50 107 M X0 0 0 0 0 0 0 0 0 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 51 106 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 52 105 - VSS 0 0 0 0 0 0 0 0 TOP VIEW TEQFP-208 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 - - G H J J I I I I J J I I I I I L - VSS VCC5 PSC_1 0 AN1 AN2 AN3 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 0 0 0 0 SOT0 SCK0 SIN0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 0 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 0 0 0 0 0 TIN1 TIN2 TIN3 TOT0 TOT1 TOT2 TOT3 SGA0 SGA1 SGO1 SGO2 SGA3 SGO3 SGO0 SGA0 SGA1 SGO1 TOT16 SGO2 TIN17 0 0 0 TIN16 SGA2 0 0 TIN49 0 0 0 0 0 0 0 0 0 ZIN9 OCU7_OTD1 0 0 0 0 0 0 OCU5_OTD1 BIN9 OCU7_OTD0 0 OCU3_OTD0 AIN9 OCU6_OTD1 0 0 ZIN8 OCU5_OTD0 0 0 BIN8 OCU4_OTD1 0 0 OCU8_OTD0 OCU8_OTD1 OCU9_OTD0 OCU9_OTD1 0 ICU3_IN0 ICU4_IN1 ICU5_IN0 ICU5_IN1 ICU6_IN1 ICU7_IN0 ICU7_IN1 ICU8_IN0 ICU8_IN1 ICU9_IN0 ICU9_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPG3_TOUT0 PPG4_TOUT2 PPG5_TOUT0 PPG5_TOUT2 PPG6_TOUT2 PPG7_TOUT0 FRT8/9/10/11_TEXT PPG7_TOUT2 OCU11_OTD0 ICU11_IN0 0 0 0 OCU10_OTD1 ICU10_IN1 0 0 0 0 OCU10_OTD0 ICU10_IN0 0 0 0 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG9_TOUT2 0 EINT6 EINT9 PPG11_TOUT0 EINT6 0 0 P2_25 0 EINT15 P2_31 0 EINT3 P3_00 0 P3_01 0 P3_02 0 P3_03 0 P3_04 0 P3_05 0 P3_06 0 0 0 0 P2_22 0 EINT14 P2_30 0 EINT2 0 0 EINT13 P2_29 0 EINT1 0 0 0 0 0 0 0 0 0 0 0 EINT11 P2_27 INDICATOR0_0 0 EINT0 0 0 EINT10 P2_26 0 PPG10_TOUT2 EINT5 0 0 PPG10_TOUT0 EINT4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G_DQ7_1 0 0 0 0 G_DQ6_1 0 0 0 G_DQ5_1 0 G_CS#2_1 0 G_DQ4_1 0 0 0 P1_02 M_DQ7_0 0 0 G_RWDS_1 0 0 0 G_CS#1_1 0 0 0 0 0 G_DQ0_1 0 0 0 EINT9 P1_00 M_DQ5_0 EINT10 P1_03 M_DQ6_0 G_DQ1_1 0 VCC12 0 P1_01 M_DQ4_0 G_DQ2_1 0 - 0 PPG7_TOUT2 EINT7 0 P0_31 M_CS#2_0 G_DQ3_1 0 85 0 PPG8_TOUT0 EINT8 0 0 0 DSP0_CTRL1 0 0 0 PPG6_TOUT2 EINT6 0 0 DSP0_CTRL0 0 0 0 PPG7_TOUT0 0 P0_30 M_RWDS_0 G_CK_1 DSP0_CLK P0_28 0 0 ICU7_IN1 0 PPG6_TOUT0 0 0 DSP0_CTRL2 P0_27 0 0 ICU8_IN0 0 0 EINT5 0 0 EINT3 0 OCU7_OTD1 ICU6_IN1 0 0 0 0 EINT2 0 OCU8_OTD0 ICU7_IN0 0 PPG5_TOUT2 0 0 PPG4_TOUT2 0 0 OCU6_OTD1 ICU6_IN0 0 0 0 0 0 0 OCU7_OTD0 0 0 EINT11 P1_04 M_DQ0_0 G_DQ7_2 0 0 0 0 OCU6_OTD0 0 0 EINT13 P1_06 M_DQ1_0 0 0 G_DQ6_2 0 0 0 0 0 ICU5_IN1 0 0 P1_09 M_CK_0 0 0 EINT12 P1_05 M_DQ3_0 0 0 G_DQ5_2 ICU4_IN1 0 0 0 0 0 0 0 PPG10_TOUT2 EINT15 P1_08 M_CS#1_0 0 0 P5_22 0 G_DQ4_2 0 0 0 0 0 OCU5_OTD1 0 PPG8_TOUT2 0 P0_17 0 PPG10_TOUT0 EINT14 P1_07 M_DQ2_0 PPG9_TOUT2 0 P0_16 0 0 SIN1 OCU4_OTD1 0 0 0 0 0 0 PPG9_TOUT0 EINT2 P0_15 0 SCK1 0 0 0 0 0 0 OCU10_OTD1 ICU10_IN1 0 0 0 0 EINT1 PPG11_TOUT0 EINT0 0 EINT0 0 0 0 0 0 0 0 ICU8_IN1 0 0 EINT15 P0_14 0 PPG10_TOUT0 EINT4 0 EINT14 P0_13 0 0 0 0 0 0 0 0 OCU8_OTD1 ICU9_IN1 0 PPG9_TOUT0 EINT13 P0_12 0 0 0 0 0 0 0 0 0 OCU9_OTD1 ICU9_IN0 OCU10_OTD0 ICU10_IN0 0 PPG8_TOUT2 0 0 0 0 0 0 0 0 0 OCU9_OTD0 0 PPG8_TOUT0 CRS VCC3 G_SDATA0_3 0 0 0 0 0 0 0 0 PPG7_TOUT2 0 VSS G_SSEL0 0 0 0 0 0 0 0 0 PPG7_TOUT0 0 - M_SDATA1_3 G_SDATA0_1 0 0 0 0 0 0 0 0 OCU11_OTD0 ICU11_IN0 0 0 0 0 PPG6_TOUT2 0 - M_SSEL1 G_SDATA0_2 0 0 0 0 0 0 0 0 0 CAP0_DATA25 0 E M_SDATA1_1 G_SDATA0_0 0 0 0 0 0 0 0 0 OCU10_OTD0 ICU10_IN0 0 0 0 DSP0_CTRL4 E M_SDATA1_2 0 0 0 0 0 0 0 0 DSP0_CTRL3 E M_SDATA1_0 0 0 0 0 0 0 0 ICU9_IN0 0 MLBCLK 81 E VCC3 G_SCLK0 0 0 0 0 0 ICU8_IN1 0 MLBSIG 80 E VSS 0 0 0 0 0 0 ICU8_IN0 F 79 - 0 G_SDATA1_3 0 0 0 0 ICU7_IN1 F 78 - VSS G_SSEL1 0 0 0 0 ICU7_IN0 84 77 E M_SDATA0_3 G_SDATA1_1 0 0 0 OCU9_OTD0 ICU6_IN1 83 76 - M_SSEL0 G_SDATA1_2 0 0 0 OCU8_OTD1 0 0 75 E M_SDATA0_1 G_SDATA1_0 0 0 OCU8_OTD0 P0_26 0 74 E M_SDATA0_2 0 0 0 OCU7_OTD1 EINT1 73 E M_SDATA0_0 0 0 0 OCU7_OTD0 0 72 E VCC3 0 0 0 0 OCU6_OTD1 0 71 E VSS 0 0 0 0 0 70 - M_SCLK0 0 TXER 0 SOT1 0 69 - VSS CAP0_DATA34 0 TIN35 I2S1_SCK 0 0 68 E VCC12 DSP0_CTRL2 0 TOT35 I2S1_WS 0 0 67 - DSP0_CTRL0 COL 0 0 66 - DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK RXCLK TIN33 I2S0_SCK DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 I2S1_SD DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 TXCLK TOT33 I2S0_WS DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 CAP0_DATA24 0 65 C DSP0_DATA1_9 DSP0_DATA_D9- DSP0_CTRL2 64 D DSP0_DATA0_9 DSP0_DATA_D9+ CAP0_DATA21 0 MLBDAT 63 D VCC3 F 62 D 82 61 D 0 CAP0_DATA22 0 0 0 0 60 D 0 59 D 0 58 - 0 57 0 56 0 55 0 54 0 53 Page 36 of 222 Document Number: 002-05682 Rev. *K Condition on PCB Set to ground Open Package Pin Number 2, 5, 6, 9 3, 4, 7, 8 192 OCU10_OTD1 0 Y PWM1P2 0 DSP1_DATA1_4 0 0 0 0 0 0 AN34 DSP0_DATA1_10 0 SCK10 S 0 ZIN8 137 0 OCU9_OTD1 20 0 ICU9_IN1 B 0 0 TxCLK+ 0 PPG9_TOUT2 0 0 SEG9 EINT11 0 0 MFS9_CS0 0 P5_11 0 0 0 MFS10_SCL 0 0 193 0 0 Y 0 0 DSP1_DATA0_4 0 0 0 0 0 0 0 0 0 SIN10 0 0 AIN9 P3_30 0 0 ICU10_IN0 OCU10_OTD0 EINT14 0 SEG8 EINT12 PPG10_TOUT0 PPG11_TOUT0 0 MFS9_CS1 0 P5_12 ICU11_IN0 0 0 OCU11_OTD0 0 0 PWM1M2 0 194 0 0 195 0 0 - AN35 0 - S 0 VSS 138 0 VCC53 19 0 0 B 0 0 TxDOUT2- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P3_31 0 0 EINT15 0 0 PPG11_TOUT2 0 0 ICU11_IN1 0 0 OCU11_OTD1 0 0 PWM2P2 0 0 0 0 0 0 0 0 AN36 0 0 S 0 0 139 0 0 18 0 0 B 0 0 0 TxDOUT2+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 196 0 0 Y 0 0 DSP1_DATA1_3 0 0 0 0 0 P4_00 0 DSP0_CTRL0 P4_01 EINT0 0 0 EINT1 PPG0_TOUT0 0 0 PPG0_TOUT2 ICU0_IN0 0 0 ICU10_IN1 OCU10_OTD1 BIN9 ICU0_IN1 OCU0_OTD0 0 SEG7 EINT13 PPG10_TOUT2 OCU0_OTD1 PWM2M2 0 0 0 P5_13 PWM1P3 0 0 0 0 0 0 0 0 AN37 0 197 AN38 S 0 Y S 140 0 DSP1_DATA0_3 141 17 0 0 16 B 0 DSP0_CTRL1 B TxDOUT30 0 0 SOT11 TxDOUT3+ 0 0 0 ZIN9 0 0 0 0 0 ICU11_IN0 OCU11_OTD0 0 0 0 0 SEG6 EINT14 PPG11_TOUT0 0 0 0 0 MFS8_CS3 0 P5_14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 198 0 0 Y P4_02 0 DSP1_DATA1_2 EINT2 0 DSP0_CTRL2 DSP1_CTRL2 PPG1_TOUT0 0 0 SCK11 ICU1_IN0 0 0 OCU1_OTD0 0 0 ICU11_IN1 OCU11_OTD1 PWM1M3 0 SEG5 EINT15 PPG11_TOUT2 0 0 MFS8_CS1 0 P5_15 SOT2 0 0 AN39 0 0 S 0 199 142 0 200 15 0 Y 0 Y VSS_LVDS_Tx 0 DSP1_DATA0_2 0 0 DSP1_DATA1_1 0 0 DSP1_CLK 0 0 DSP0_CTRL3 0 0 DSP0_CTRL4 DSP1_CTRL0 0 0 0 0 0 0 0 SIN11 P4_03 0 0 EINT3 0 0 PPG1_TOUT2 0 0 ICU1_IN1 0 OCU0_OTD0 OCU1_OTD1 0 OCU0_OTD1 PWM2P3 0 ICU0_IN0 SCK2 0 0 ICU0_IN1 AN40 0 0 S 0 0 143 0 PPG0_TOUT0 14 0 PPG0_TOUT2 0 EINT0 VCC3_LVDS_Tx 0 EINT1 0 0 SEG4 0 0 SEG3 0 0 0 0 P5_17 0 0 0 MFS8_CS2 0 P5_16 0 0 0 P4_04 0 0 EINT4 0 0 PPG2_TOUT0 0 0 ICU2_IN0 0 201 OCU2_OTD0 0 Y PWM2M3 0 DSP1_DATA0_1 0 0 DSP0_CTRL5 DSP1_CTRL1 SIN2 0 0 SOT12 AN41 0 0 S 0 OCU1_OTD0 144 0 ICU1_IN0 13 0 0 0 PPG1_TOUT0 AVCC3_LVDS_PLL 0 EINT2 0 0 SEG2 0 0 0 MFS12_SDA 0 P5_18 0 0 0 0 0 0 0 0 0 0 0 0 202 0 0 0 Y 0 0 0 DSP1_DATA1_0 0 0 0 0 0 0 0 DSP0_CTRL6 0 0 0 0 SCK12 0 0 0 0 0 0 0 OCU1_OTD1 DVSS 0 0 ICU1_IN1 - 0 0 0 145 0 0 PPG1_TOUT2 12 0 EINT3 0 SEG1 AVSS_LVDS_PLL 0 MFS12_SCL 0 P5_19 0 0 0 0 0 0 0 0 0 0 203 0 0 0 Y P4_05 0 0 DSP1_DATA0_0 EINT5 0 0 0 PPG2_TOUT2 0 0 DSP0_CTRL7 ICU2_IN1 0 0 0 SIN12 OCU2_OTD1 0 0 0 PWM1P4 0 0 OCU2_OTD0 0 0 0 ICU2_IN0 0 DVCC 0 0 AN42 - 0 PPG2_TOUT0 S 146 0 EINT4 147 11 0 SEG0 10 0 0 0 P5_20 - VCC12 0 0 VSS 0 0 0 0 0 0 204 MFS0_CS0 0 205 P4_06 0 206 EINT6 0 207 PPG3_TOUT0 0 208 ICU3_IN0 0 - OCU3_OTD0 0 Y PWM1M4 0 Y 0 0 Y SOT3 0 Y AN43 0 VCC53 S 0 DSP1_CLK 148 DAC_L DSP1_CTRL2 9 0 DSP1_CTRL1 0 DSP1_CTRL0 0 AVSS 0 0 MFS2_CS0 0 0 P4_07 0 0 EINT7 0 0 PPG3_TOUT2 0 0 ICU3_IN1 0 0 OCU3_OTD1 0 DSP0_CTRL8 PWM2P4 0 DSP0_CTRL9 SCK3 0 0 0 0 AN44 0 0 S 0 0 SOT11 149 0 0 SCK11 DSP0_CTRL10 8 0 0 SIN11 DSP0_CTRL11 A 0 0 0 C_L - 0 MFS2_CS1 - AVCC3_DAC 0 P4_08 AVSS 0 0 EINT8 0 0 0 PPG4_TOUT0 0 0 OCU0_OTD1 ICU4_IN0 0 0 OCU1_OTD0 SGA1 OCU4_OTD0 0 0 OCU1_OTD1 SGO1 PWM2M4 0 0 OCU2_OTD0 0 0 0 0 SIN3 0 0 ICU0_IN1 AN45 0 0 ICU1_IN0 S 0 0 ICU1_IN1 0 150 0 0 ICU2_IN0 MFS4_SDA 0 7 0 0 0 MFS0_CS3 P4_09 A 0 0 0 P4_10 EINT9 0 0 0 EINT10 PPG4_TOUT2 0 0 0 PPG5_TOUT0 ICU4_IN1 0 0 0 ICU5_IN0 OCU4_OTD1 0 0 OCU5_OTD0 PWM1P5 4 PPG0_TOUT2 PWM1M5 0 3 A VSS PPG1_TOUT0 0 0 2 A C_R PPG1_TOUT2 SOT4 AN46 - DAC_R 0 PPG2_TOUT0 0 AN47 S 1 AVSS 0 0 0 0 MFS4_SCL S 151 - 0 0 0 0 0 P4_25 COM3 EINT9 0 MFS0_CS1 152 6 0 0 0 0 0 0 P4_26 COM2 EINT10 MFS0_CS2 P4_11 5 0 0 0 0 0 0 P4_27 COM1 EINT11 P4_12 EINT11 0 0 0 0 0 0 P4_28 COM0 EINT12 0 EINT12 PPG5_TOUT2 0 0 0 0 0 0 0 0 PPG6_TOUT0 ICU5_IN1 0 0 0 0 0 0 0 ICU6_IN0 OCU5_OTD1 0 0 0 0 0 0 0 OCU6_OTD0 PWM2P5 0 0 0 0 0 0 0 PWM2M5 0 0 0 0 0 0 0 TX1 SCK4 RX1 0 0 0 0 0 0 0 SIN4 AN48 0 0 0 0 0 0 0 AN49 S 0 0 0 0 0 0 DVSS S 153 0 0 0 0 0 DVCC 154 0 0 0 0 0 155 0 0 0 0 Any function at the following pins is not supported. - 156 0 0 0 Notes: - The pins highlighted in "red" font are not supported for products with revision A and C. S6J3200 Series Figure 4-16: TEQFP-208 (S6J32xAKxx) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDICATOR0_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_01 P5_00 P4_31 P4_30 P4_29 0 0 0 P2_16 P2_17 P3_17 P3_16 P3_15 P3_14 P3_13 P3_12 P3_09 P3_08 P3_07 P2_19 0 0 SEG19 SEG20 SEG21 SEG22 SEG23 0 0 0 0 0 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 V0 V1 V2 V3 0 0 EINT1 EINT0 EINT15 EINT14 EINT13 0 0 0 EINT0 EINT1 EINT1 EINT0 EINT15 EINT14 EINT13 EINT12 EINT9 EINT8 EINT7 EINT3 0 0 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 0 0 0 PPG0_TOUT0 PPG0_TOUT2 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 PPG2_TOUT0 PPG0_TOUT2 PPG0_TOUT0 PPG11_TOUT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRT4/5/6/7_TEXT 0 0 0 0 PPG6/7/8/9/10/11_TIN 0 0 ICU4_IN0 ICU3_IN1 ICU3_IN0 ICU2_IN1 0 0 0 ICU0_IN0 ICU0_IN1 ICU4_IN1 ICU4_IN0 ICU3_IN1 ICU3_IN0 ICU2_IN1 ICU2_IN0 ICU0_IN1 ICU0_IN0 ICU1_IN1 0 0 OCU4_OTD1 OCU4_OTD0 OCU3_OTD1 OCU3_OTD0 OCU2_OTD1 0 0 0 OCU0_OTD0 OCU0_OTD1 OCU4_OTD1 OCU4_OTD0 OCU3_OTD1 OCU3_OTD0 OCU2_OTD1 OCU2_OTD0 OCU0_OTD1 OCU0_OTD0 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 TIN48 ICU4_IN1 OCU5_OTD0 0 0 0 0 0 0 SGO3 SGA3 0 0 0 0 0 0 SGO2 SGA2 SGO1 SGA1 SGA0 SGO0 0 WOT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN34 TOT34 TIN33 TOT33 TIN32 TOT32 TIN18 TOT18 TOT17 0 0 0 SOT8 0 0 0 0 0 0 0 0 0 0 SIN11 SCK11 SOT11 SIN10 SCK10 SOT10 SIN9 SCK9 SOT9 0 0 0 AN1(AL1) AP1(AH1) BN0(BL0) BP0(BH0) AN0(AL0) AP0(AH0) 0 0 0 0 0 TX6 RX6 TX5 RX5 0 0 TX5 RX5 0 0 0 0 0 0 0 DSP1_DATA1_10 0 DSP1_DATA0_11 0 DSP1_DATA1_11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_DATA1_9 0 DSP1_DATA0_10 0 DSP1_DATA0_9 VCC53 VSS VCC5 X0A X1A AN25 AN24 AN23 AN22 AN21 AN20 AN17 AN16 AN15 0 VSS VCC5 Y Y Y Y Y Y - - - X X W W W W W W V V V U - - 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 0 SOT11 0 0 DSP1_DATA1_2 DSP0_CTRL2 DSP1_CTRL2 DSP0_CTRL1 DSP0_CTRL0 0 0 0 0 DSP1_DATA0_3 DSP1_DATA1_3 VSS Y Y Y - 198 197 196 195 0 0 0 ICU5_IN0 183 0 184 PPG5_TOUT0 185 EINT2 - 186 SEG18 - 187 P5_02 - 0 0 VCC12 Y 180 VSS Y Y VCC53 DSP1_DATA1_8 0 DSP1_DATA1_7 0 0 DSP1_DATA0_7 BP1(BH1) 0 SCK8 0 0 0 0 0 0 0 OCU5_OTD1 0 0 ICU5_IN1 0 0 0 0 PPG5_TOUT2 0 0 EINT3 0 SOT9 SEG17 0 P5_03 0 0 188 0 0 0 0 189 181 0 Y 190 182 0 0 Y - 0 0 DSP1_DATA1_6 Y Y 0 DSP1_DATA0_6 VCC12 0 OCU6_OTD1 0 DSP1_DATA1_5 DSP1_DATA0_8 0 OCU7_OTD0 0 0 0 0 0 0 0 ICU6_IN1 0 0 0 ICU7_IN0 SCK9 0 BN1(BL1) 0 0 0 SIN9 0 0 0 0 SIN8 0 0 0 0 0 0 0 0 0 PPG6_TOUT2 OCU7_OTD1 AIN8 0 0 PPG7_TOUT0 OCU8_OTD0 0 0 ICU7_IN1 OCU8_OTD1 191 0 0 EINT5 ICU8_IN0 Y 192 OCU6_OTD0 0 EINT6 0 ICU8_IN1 DSP1_DATA0_5 Y 0 0 0 0 DSP1_DATA1_4 ICU6_IN0 0 SEG15 PPG7_TOUT2 0 0 0 0 0 SEG14 PPG8_TOUT0 SOT10 0 0 0 EINT7 PPG8_TOUT2 0 SCK10 0 0 P5_05 EINT8 BIN8 0 PPG6_TOUT0 0 P5_06 SEG13 EINT9 OCU9_OTD0 ZIN8 0 0 SEG12 ICU9_IN0 OCU9_OTD1 EINT4 0 P5_07 SEG11 0 ICU9_IN1 0 0 P5_08 PPG9_TOUT0 0 SEG16 0 P5_09 EINT10 PPG9_TOUT2 0 0 SEG10 EINT11 P5_04 0 P5_10 SEG9 0 0 P5_11 0 0 0 SCK11 193 0 0 194 BIN9 0 - ICU10_IN1 OCU10_OTD1 0 ZIN9 Y 0 ICU11_IN0 OCU11_OTD0 VCC53 0 ICU11_IN1 OCU11_OTD1 DSP1_DATA0_4 0 0 199 0 PPG10_TOUT2 0 Y 200 0 0 PPG11_TOUT0 DSP1_DATA0_2 DSP0_CTRL3 DSP1_CLK Y 0 EINT13 PPG11_TOUT2 SIN11 DSP1_DATA1_1 DSP0_CTRL4 DSP1_CTRL0 0 0 EINT14 0 0 0 SEG7 EINT15 0 0 SIN10 0 0 SEG6 OCU0_OTD0 0 0 0 P5_13 SEG5 ICU0_IN0 OCU0_OTD1 0 0 PPG10_TOUT0 0 P5_14 0 ICU0_IN1 0 0 EINT12 0 P5_15 PPG0_TOUT0 0 AIN9 0 SEG8 0 0 EINT0 PPG0_TOUT2 201 0 0 P5_12 0 0 SEG4 EINT1 202 0 0 0 P5_16 SEG3 Y ICU10_IN0 OCU10_OTD0 0 0 0 P5_17 Y 0 0 0 DSP1_DATA1_0 0 0 0 AN39 SOT2 0 PWM1M3 OCU1_OTD0 ICU1_IN0 PPG1_TOUT0 EINT2 P4_02 S AN38 0 0 PWM1P3 OCU0_OTD1 ICU0_IN1 PPG0_TOUT2 EINT1 P4_01 0 0 0 0 0 0 NC - 17 140 S AN37 0 0 PWM2M2 OCU0_OTD0 ICU0_IN0 PPG0_TOUT0 EINT0 P4_00 0 0 0 0 0 0 0 NC - 18 139 S AN36 0 0 PWM2P2 OCU11_OTD1 ICU11_IN1 PPG11_TOUT2 EINT15 P3_31 0 0 0 0 0 0 0 0 NC - 19 138 S AN35 0 0 PWM1M2 OCU11_OTD0 ICU11_IN0 PPG11_TOUT0 EINT14 P3_30 0 0 0 0 0 0 0 0 NC - 20 137 S AN34 0 0 PWM1P2 OCU10_OTD1 ICU10_IN1 PPG10_TOUT2 EINT13 P3_29 0 0 0 0 0 0 0 0 0 NC - 21 136 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NC - 22 135 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NC - 23 134 S AN33 0 BN1(BL1) PWM2M1 OCU10_OTD0 ICU10_IN0 PPG10_TOUT0 EINT12 P3_28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NC - 24 133 S AN32 0 BP1(BH1) PWM2P1 OCU9_OTD1 ICU9_IN1 PPG9_TOUT2 EINT11 P3_27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NC - 25 132 S AN31 0 AN1(AL1) PWM1M1 OCU9_OTD0 ICU9_IN0 PPG9_TOUT0 EINT10 P3_26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NC - 26 131 S AN30 0 AP1(AH1) PWM1P1 OCU8_OTD1 ICU8_IN1 PPG8_TOUT2 EINT9 P3_25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NC - 27 130 S AN29 0 BN0(BL0) PWM2M0 OCU8_OTD0 ICU8_IN0 PPG8_TOUT0 EINT8 P3_24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC12 - 28 129 S AN28 0 BP0(BH0) PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 29 128 S AN27 0 AN0(AL0) PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 30 127 S AN26 0 AP0(AH0) PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 DSP0_DATA1_10 0 0 0 0 0 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 DSP0_DATA0_4 MDC CAP0_DATA0 0 DSP0_CTRL1 C 31 126 - DVCC 0 0 0 0 0 0 0 0 DSP0_DATA0_11 0 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK+ DSP0_CLK D 32 125 - DVSS 0 0 0 0 0 0 0 0 DSP0_DATA1_11 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 CAP0_DATA2 0 DSP0_CLK- DSP0_CTRL2 D 33 124 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 CAP0_DATA3 0 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 123 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 CAP0_DATA4 0 DSP0_DATA_D0- DSP0_DATA1_0 D 35 122 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 CAP0_DATA5 0 DSP0_DATA_D1+ DSP0_DATA0_1 D 36 121 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 CAP0_DATA6 0 DSP0_DATA_D1- DSP0_DATA1_1 D 37 120 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 CAP0_DATA7 0 DSP0_DATA_D2+ DSP0_DATA0_2 D 38 119 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 CAP0_DATA8 0 DSP0_DATA_D2- DSP0_DATA1_2 D 39 118 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 CAP0_DATA9 0 DSP0_DATA_D3+ DSP0_DATA0_3 D 40 117 - C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 41 116 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 115 - VCC5 0 0 0 0 0 0 0 0 TOP VIEW TEQFP-208 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 D D D D D C - - E - - E E E E E - E - - E E E E E - - F F F - - - G H J J I I I I J J I I I I I L - VCC3 DSP0_DATA0_9 DSP0_DATA1_9 M_SCLK0 VSS VCC3 M_SDATA0_0 M_SDATA0_2 M_SDATA0_1 M_SSEL0 M_SDATA0_3 VSS 0 VSS VCC3 M_SDATA1_0 M_SDATA1_2 M_SDATA1_1 M_SSEL1 M_SDATA1_3 VSS VCC3 MLBDAT MLBSIG MLBCLK VCC12 VSS VCC5 PSC_1 0 AN1 AN2 AN3 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 NMIX VCC5 DSP0_CTRL2 0 0 0 0 0 G_SDATA1_0 G_SDATA1_2 G_SDATA1_1 G_SSEL1 G_SDATA1_3 0 G_SCLK0 0 0 G_SDATA0_0 G_SDATA0_2 G_SDATA0_1 G_SSEL0 G_SDATA0_3 0 0 DSP0_CTRL2 DSP0_CTRL3 DSP0_CTRL4 0 0 0 0 0 SOT0 SCK0 SIN0 SOT1 SCK1 SIN1 SOT16 SCK16 SIN16 SOT8 SCK8 SIN8 0 0 0 0 CAP0_DATA21 0 CAP0_DATA22 0 DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK VSS DSP0_DATA_D9- DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 VCC12 DSP0_DATA_D9+ CAP0_DATA34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOT17 SCK17 SIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP0_DATA25 0 0 0 CAP0_DATA24 0 0 0 0 0 0 0 0 0 MFS17_SDA MFS17_SCL 0 0 0 0 MFS16_SDA MFS16_SCL 0 0 0 0 0 0 0 TXCLK TOT33 RXCLK TIN33 DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 DSP0_CTRL0 0 DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 COL 0 TXER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX0 TX0 RX1 TX1 0 0 TOT35 TIN35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIN49 0 0 0 TIN1 TIN2 TIN3 TOT0 TOT1 TOT2 TOT3 TIN16 TOT16 TIN17 0 0 0 I2S0_WS I2S0_SCK I2S1_SD I2S1_WS I2S1_SCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGA0 SGA1 SGO1 SGO2 SGA3 SGO3 SGO0 SGA0 SGA1 SGO1 SGA2 SGO2 0 0 0 0 0 0 I2S1_ECLK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU11_OTD0 0 0 OCU9_OTD0 OCU10_OTD0 OCU9_OTD1 OCU8_OTD1 OCU10_OTD1 0 OCU5_OTD1 0 0 OCU6_OTD0 OCU7_OTD0 OCU6_OTD1 OCU8_OTD0 OCU7_OTD1 0 0 0 0 0 0 OCU3_OTD0 OCU5_OTD1 ZIN9 OCU7_OTD1 0 OCU10_OTD0 BIN9 OCU7_OTD0 0 OCU9_OTD0 AIN9 OCU6_OTD1 0 OCU8_OTD1 ZIN8 OCU5_OTD0 0 OCU8_OTD0 BIN8 OCU4_OTD1 0 OCU7_OTD1 SIN1 OCU4_OTD1 0 OCU7_OTD0 SCK1 0 0 OCU6_OTD1 SOT1 0 0 0 OCU8_OTD0 OCU8_OTD1 OCU9_OTD0 OCU9_OTD1 OCU10_OTD0 OCU10_OTD1 OCU11_OTD0 0 0 0 ICU6_IN1 ICU7_IN0 ICU7_IN1 ICU8_IN0 ICU8_IN1 ICU9_IN0 0 0 ICU9_IN0 ICU8_IN1 ICU5_IN1 0 0 ICU6_IN0 ICU7_IN0 ICU6_IN1 ICU8_IN0 ICU7_IN1 0 0 0 0 ICU4_IN1 0 0 0 0 ICU3_IN0 ICU4_IN1 ICU5_IN0 ICU5_IN1 ICU6_IN1 ICU7_IN0 ICU7_IN1 ICU8_IN0 ICU8_IN1 ICU9_IN0 ICU9_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICU11_IN0 0 0 0 0 PPG6_TOUT2 PPG7_TOUT0 PPG7_TOUT2 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG10_TOUT0 0 0 PPG11_TOUT0 0 0 PPG9_TOUT0 PPG10_TOUT0 PPG9_TOUT2 PPG8_TOUT2 PPG10_TOUT2 0 PPG5_TOUT2 0 0 PPG6_TOUT0 PPG7_TOUT0 PPG6_TOUT2 PPG8_TOUT0 PPG7_TOUT2 0 0 0 0 PPG4_TOUT2 0 0 0 0 PPG3_TOUT0 PPG4_TOUT2 PPG5_TOUT0 PPG5_TOUT2 PPG6_TOUT2 PPG7_TOUT0 FRT8/9/10/11_TEXT PPG7_TOUT2 ICU10_IN1 0 0 0 ICU10_IN0 0 0 0 ICU10_IN1 0 0 0 ICU10_IN0 0 ICU9_IN1 0 ICU11_IN0 0 0 0 ICU10_IN0 0 0 0 PPG8_TOUT0 PPG8_TOUT2 PPG9_TOUT0 PPG9_TOUT2 PPG10_TOUT0 PPG10_TOUT2 PPG11_TOUT0 0 0 0 EINT13 P0_12 0 EINT14 P0_13 0 EINT15 P0_14 0 EINT0 EINT1 EINT2 EINT4 0 0 EINT0 0 0 EINT8 EINT7 0 0 EINT1 EINT2 EINT3 0 0 0 0 EINT6 EINT9 EINT5 EINT6 0 0 0 P1_01 M_DQ4_0 P1_00 M_DQ5_0 P1_02 M_DQ7_0 0 P0_28 0 0 0 0 0 0 P2_25 0 P3_00 0 P3_01 0 P3_02 0 P3_03 0 P3_04 0 P3_05 0 P3_06 0 0 0 P2_22 0 0 0 P0_27 0 0 0 P0_26 0 0 0 P0_31 M_CS#2_0 0 0 EINT15 P2_31 0 EINT4 0 EINT14 P2_30 0 EINT3 P0_30 M_RWDS_0 EINT13 P2_29 0 EINT2 0 0 EINT11 P2_27 INDICATOR0_0 EINT1 0 0 EINT10 P2_26 0 EINT0 P1_09 M_CK_0 0 0 EINT10 P1_03 M_DQ6_0 EINT9 0 0 EINT15 P1_08 M_CS#1_0 EINT6 0 EINT11 P1_04 M_DQ0_0 0 P5_22 0 EINT13 P1_06 M_DQ1_0 0 P0_17 0 EINT14 P1_07 M_DQ2_0 EINT5 P0_16 0 EINT12 P1_05 M_DQ3_0 0 P0_15 0 0 0 0 0 0 0 0 G_CK_1 0 0 G_DQ3_1 G_DQ2_1 G_DQ1_1 G_DQ0_1 0 G_DQ5_1 G_DQ6_1 G_DQ7_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G_CS#2_1 0 G_DQ4_1 DSP0_CTRL1 G_RWDS_1 0 0 DSP0_CTRL0 G_CS#1_1 0 0 DSP0_CLK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE0 TRACE1 TRACE2 TRACE3 TRACE_CLK TRACE_CTL 0 0 0 0 0 0 0 0 0 DSP0_CTRL2 0 59 D 0 58 - 0 57 0 56 0 55 0 54 0 53 Page 37 of 222 Document Number: 002-05682 Rev. *K DSP1_DATA0_1 DSP0_CTRL5 DSP1_CTRL1 0 0 0 0 0 VCC3 - 43 114 Q RSTX 0 0 0 0 0 0 0 0 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 44 113 P MODE 0 0 0 0 0 0 0 0 CAP0_DATA12 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 45 112 N2 JTAG_TMS 0 0 0 0 0 0 0 0 CAP0_DATA13 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 46 111 N2 JTAG_TCK 0 0 0 0 0 0 0 0 CAP0_DATA14 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 47 110 N2 JTAG_TDI 0 0 0 0 0 0 0 0 CAP0_DATA15 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 48 109 O JTAG_TDO 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 49 108 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK TOT32RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 50 107 M X0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32RXD3 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 51 106 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 52 105 - VSS 0 0 0 0 0 0 0 0 0 DSP0_CTRL6 0 P0_04 0 SOT12 0 0 0 0 0 0 SCK12 S 141 0 0 142 16 0 0 0 CAP0_DATA11 0 0 0 0 0 0 0 15 - 0 0 - NC 0 OCU1_OTD0 NC 0 0 OCU1_OTD1 0 0 0 0 0 0 0 0 ICU1_IN0 0 0 0 ICU1_IN1 0 0 0 0 0 0 0 0 0 0 0 0 0 P4_03 0 0 PPG1_TOUT0 EINT3 0 PPG1_TOUT2 PPG1_TOUT2 0 EINT2 ICU1_IN1 0 0 0 0 0 0 EINT3 OCU1_OTD1 0 0 0 0 0 0 SEG2 PWM2P3 0 SEG1 0 0 P5_18 SCK2 0 P5_19 AN40 0 0 0 0 0 0 0 S 0 0 143 0 0 14 0 0 - 0 203 NC 0 0 0 0 0 0 Y 0 0 DSP1_DATA0_0 0 0 0 0 0 DSP0_CTRL7 P4_04 0 0 SIN12 EINT4 0 0 PPG2_TOUT0 0 0 ICU2_IN0 0 OCU2_OTD0 OCU2_OTD0 0 ICU2_IN0 PWM2M3 0 0 0 0 PPG2_TOUT0 SIN2 0 0 0 0 0 0 EINT4 AN41 0 0 0 0 0 0 SEG0 S 0 P5_20 144 0 0 13 0 0 - 0 204 NC 0 205 0 0 206 0 0 0 0 0 0 0 207 0 0 0 208 0 0 0 - 0 0 0 Y 0 0 0 Y 0 0 0 Y 0 0 0 Y 0 0 0 VCC53 0 0 0 0 0 0 0 0 DSP1_CLK 0 DVSS 0 DSP1_CTRL2 DVCC - 0 0 DSP1_CTRL1 145 0 0 DSP1_CTRL0 146 12 0 0 0 11 0 0 0 - NC 0 0 0 VCC12 0 0 0 0 0 0 0 0 0 P4_05 0 0 0 0 0 0 0 0 0 EINT5 0 0 0 0 0 0 DSP0_CTRL8 PPG2_TOUT2 0 DSP0_CTRL9 ICU2_IN1 0 DSP0_CTRL10 OCU2_OTD1 0 DSP0_CTRL11 PWM1P4 0 0 0 0 0 0 0 SIN11 AN42 0 SOT11 S 0 SCK11 147 0 0 10 0 0 0 0 0 0 0 0 0 VSS 0 0 P4_06 0 0 0 EINT6 0 0 PPG3_TOUT0 0 0 ICU3_IN0 0 0 OCU3_OTD0 0 SGA1 PWM1M4 0 SGO1 0 0 0 SOT3 0 OCU0_OTD1 AN43 0 0 0 0 0 0 OCU1_OTD0 S C_L OCU1_OTD1 148 DAC_L 0 OCU2_OTD0 9 0 0 0 0 0 ICU0_IN1 P4_07 AVSS 0 0 ICU1_IN0 P4_08 EINT7 0 0 ICU1_IN1 EINT8 PPG3_TOUT2 0 0 ICU2_IN0 PPG4_TOUT0 ICU3_IN1 0 0 0 ICU4_IN0 OCU3_OTD1 0 0 0 OCU4_OTD0 PWM2P4 0 0 0 PWM2M4 0 0 0 0 0 SCK3 0 0 0 0 0 0 0 0 SIN3 AN44 0 0 0 0 0 0 0 AN45 S - PPG0_TOUT2 S 149 AVCC3_DAC PPG1_TOUT0 150 8 0 PPG1_TOUT2 7 A 0 PPG2_TOUT0 P4_09 A 0 0 EINT9 0 EINT9 PPG4_TOUT2 0 EINT10 ICU4_IN1 0 EINT11 OCU4_OTD1 0 EINT12 PWM1P5 0 0 0 0 COM3 0 0 COM2 AN46 0 0 0 0 0 0 COM1 S 5 COM0 151 4 VSS 0 P4_10 6 3 A AVSS P4_25 P4_11 EINT10 2 A C_R 0 P4_26 P4_12 EINT11 PPG5_TOUT0 - DAC_R 0 0 P4_27 0 EINT12 PPG5_TOUT2 ICU5_IN0 1 AVSS 0 0 0 P4_28 0 0 PPG6_TOUT0 ICU5_IN1 OCU5_OTD0 - 0 0 0 0 0 0 0 ICU6_IN0 OCU5_OTD1 PWM1M5 0 0 0 0 0 0 0 0 OCU6_OTD0 PWM2P5 0 0 0 0 0 0 0 0 0 PWM2M5 RX1 SOT4 0 0 0 0 0 0 0 0 TX1 SCK4 AN47 0 0 0 0 0 0 0 0 0 SIN4 AN48 S 0 0 0 0 0 0 0 0 AN49 S 152 0 0 0 0 0 0 0 DVSS S 153 0 0 0 0 0 0 0 0 0 0 0 DVCC 154 0 0 0 0 0 0 0 0 0 0 155 0 0 0 0 0 0 0 0 0 156 0 0 0 0 0 0 0 0 0 0 0 0 0 S6J3200 Series TEQPF-256 Pin Assignment 4.1.3 Figure 4-17: TEQFP-256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS VCC5 - 194 193 0 195 0 U 0 0 0 0 0 0 0 0 196 0 0 197 0 0 V 0 0 H 0 ICU1_IN1 AN15 0 TIN48 TRACE14 0 0 0 V3 EINT3 0 0 P2_19 0 0 0 0 0 SOT9 0 0 0 TOT17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFS8_CS2 MFS8_CS1 MFS8_CS3 MFS9_CS1 MFS9_CS0 MFS8_CS0 0 0 0 P2_16 0 P2_17 0 0 0 0 P3_17 SEG24 0 P3_16 SEG25 0 EINT3 EINT2 EINT1 EINT0 0 0 0 0 EINT0 EINT1 EINT1 EINT0 0 0 P3_15 SEG26 EINT15 0 P3_14 SEG27 EINT14 0 P3_13 SEG28 EINT13 0 P3_12 SEG29 EINT12 0 P6_18 0 0 EINT4 0 P4_29 SEG23 EINT13 0 0 0 P4_30 SEG22 EINT14 0 0 0 P4_31 SEG21 EINT15 0 0 0 P5_00 SEG20 0 0 0 P5_01 SEG19 0 0 0 P5_02 SEG18 0 0 0 P5_03 SEG17 0 P6_20 0 INDICATOR0_1 0 0 0 0 P5_04 SEG16 0 P6_21 0 0 0 0 0 0 0 PPG6_TOUT0 0 PPG5_TOUT2 PPG5_TOUT0 PPG4_TOUT2 PPG4_TOUT0 PPG3_TOUT2 PPG3_TOUT0 0 PPG2_TOUT2 0 0 0 PPG0_TOUT0 PPG0_TOUT2 PPG4_TOUT2 PPG4_TOUT0 0 PPG3_TOUT2 PPG3_TOUT0 PPG2_TOUT2 PPG2_TOUT0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICU8_IN0 ICU7_IN1 ICU7_IN0 0 ICU6_IN1 0 0 0 0 ICU6_IN0 0 ICU5_IN1 ICU5_IN0 ICU4_IN1 ICU4_IN0 ICU3_IN1 ICU3_IN0 0 ICU2_IN1 0 0 0 ICU0_IN0 ICU0_IN1 ICU4_IN1 ICU4_IN0 0 OCU8_OTD1 OCU8_OTD0 OCU7_OTD1 OCU7_OTD0 0 OCU6_OTD1 0 0 0 0 OCU6_OTD0 0 OCU5_OTD1 OCU5_OTD0 OCU4_OTD1 OCU4_OTD0 0 0 0 OCU0_OTD0 OCU0_OTD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU3_OTD0 SGA3 OCU2_OTD1 0 OCU3_OTD1 SGO3 0 AIN8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIN9 SCK9 SOT9 0 0 0 0 0 0 SIN8 0 SCK8 SOT8 0 0 0 0 0 0 0 0 0 0 0 OCU4_OTD1 SGO2 TIN34 SIN11 OCU4_OTD0 SGA2 TOT34 SCK11 0 0 0 0 0 0 0 0 0 0 BN1(BL1) 0 BP1(BH1) AN1(AL1) AP1(AH1) BN0(BL0) BP0(BH0) AN0(AL0) 0 AP0(AH0) 0 0 0 0 0 TX6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP1_DATA1_7 VCC53 VSS VCC12 VCC12 DSP1_DATA0_8 0 DSP1_DATA1_8 DSP1_DATA0_9 DSP1_DATA1_9 TRACE_CTL 0 DSP1_DATA1_11 0 DSP1_DATA0_7 0 DSP1_DATA0_11 0 DSP1_DATA1_6 0 DSP1_DATA1_10 0 DSP1_DATA0_6 0 DSP1_DATA0_10 0 DSP1_DATA1_5 VCC53 VSS VCC5 X0A X1A AN25 Y Y Y Y Z Y - - - - Y Z Y Y Y Y Y Y Z Y - - - X X W 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 0 0 0 0 0 0 0 PPG6_TOUT2 0 ICU8_IN1 0 0 0 0 0 0 PPG7_TOUT0 0 0 0 0 0 0 0 0 EINT5 PPG7_TOUT2 0 0 FRT0/1/2/3_TEXT ICU11_IN1 OCU11_OTD1 0 0 0 0 EINT6 PPG8_TOUT0 0 0 0 0 0 EINT7 PPG8_TOUT2 0 0 0 0 0 0 P5_05 SEG15 EINT8 0 V2 EINT7 PPG11_TOUT2 0 0 0 P5_06 SEG14 0 P6_22 0 0 P5_07 SEG13 EINT9 0 0 0 0 OCU9_OTD0 BIN8 0 0 SCK10 0 SOT10 0 0 0 0 0 0 0 DSP1_DATA1_4 DSP1_DATA0_5 Z Y Y 237 236 235 0 0 ZIN8 0 ICU9_IN0 0 OCU9_OTD1 0 0 0 0 0 0 P5_08 SEG12 0 0 0 0 0 P5_09 SEG11 0 0 0 0 0 0 ICU9_IN1 FRT4/5/6/7_TEXT ICU3_IN1 0 0 0 0 198 0 P3_07 V 0 AN16 0 P6_17 0 0 RX5 0 SCK9 0 OCU0_OTD0 WOT TOT18 199 0 ICU0_IN0 V PPG0_TOUT0 PPG6/7/8/9/10/11_TIN AN17 V1 EINT8 0 0 P3_08 TX5 0 SIN9 0 0 TIN18 0 OCU0_OTD1 PPG0_TOUT2 ICU0_IN1 V0 EINT9 200 0 P3_09 201 0 W 202 W 203 AN18 H 204 AN19 W 205 0 TRACE15 W 0 AN20 W 206 TX6 ICU1_IN0 0 AN21 207 RX6 ICU1_IN1 0 AN22 W 208 0 0 0 0 H 0 0 0 0 AN23 W 0 TOT19 PPG1_TOUT0 0 0 0 AN24 TRACE_CLK 0 TIN19 PPG1_TOUT2 OCU2_OTD0 SGO0 TOT32 SOT10 RX5 0 OCU1_OTD0 0 P3_10 SEG31 EINT10 0 OCU2_OTD1 SGA0 TIN32 SCK10 TX5 0 OCU1_OTD1 0 P3_11 SEG30 EINT11 ICU2_IN0 OCU3_OTD0 SGA1 TOT33 SIN10 0 0 0 ICU2_IN1 OCU3_OTD1 SGO1 TIN33 SOT11 RX6 0 0 0 ICU3_IN0 0 0 0 PPG9_TOUT0 0 0 0 0 0 P5_10 SEG10 EINT10 0 0 0 MFS8_CS0 0 PPG9_TOUT2 0 P6_19 0 0 MFS10_SDA 0 SEG9 EINT11 0 SIN10 0 0 0 DSP1_DATA0_4 Y 238 0 0 P5_11 AIN9 0 MFS9_CS0 0 0 ICU10_IN0 OCU10_OTD0 0 P6_23 0 MFS10_SCL 0 MFS9_CS1 SEG8 EINT12 PPG10_TOUT0 0 0 P5_12 0 239 127 128 I L - AN13 AN14 NMIX VCC5 SCK8 SIN8 0 0 0 0 0 0 0 0 0 0 0 0 0 TX0 RX1 TX1 0 0 TIN16 SGA2 TOT16 SGO2 TIN17 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU10_OTD1 ICU10_IN1 0 OCU11_OTD0 ICU11_IN0 0 0 0 0 0 OCU10_OTD0 ICU10_IN0 0 0 0 0 0 0 PPG10_TOUT0 EINT4 PPG10_TOUT2 EINT5 PPG11_TOUT0 EINT6 0 0 0 0 0 P6_06 0 P3_04 0 P3_05 0 P3_06 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE_CLK 0 TRACE_CTL 0 0 0 WAKE(Denso) 0 126 AN12 0 I 0 0 I 0 TRACE3 125 0 0 124 0 P3_03 0 TRACE3 EINT3 H PPG9_TOUT2 123 0 0 ICU9_IN1 0 OCU9_OTD1 0 0 0 SGO1 0 TOT3 SOT8 0 RX0 AN11 0 0 I 0 0 122 0 0 0 0 SCL1(Denso) TRACE2 0 SDA1(Denso) 0 0 0 0 0 0 0 0 0 P3_02 0 0 EINT11 P2_27 INDICATOR0_0 0 0 0 P6_05 0 0 0 0 EINT2 0 0 0 0 0 0 0 PPG9_TOUT0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICU9_IN0 0 0 0 0 0 0 0 OCU9_OTD0 0 0 0 0 0 0 0 0 0 P2_25 0 0 0 0 0 0 P2_24 0 EINT10 P2_26 0 0 P2_22 0 G_DQ7_1 0 0 SGA1 SIN16 0 0 G_DQ6_1 0 0 0 0 PPG5_TOUT2 EINT9 0 G_DQ5_1 0 G_CS#2_1 0 G_DQ4_1 0 0 TOT2 AN10 PPG5_TOUT0 EINT8 0 0 0 0 G_RWDS_1 0 0 0 G_CS#1_1 0 0 0 0 0 TRACE2 PPG4_TOUT2 EINT6 0 0 G_DQ0_1 0 0 0 I 0 PPG4_TOUT0 0 0 G_DQ1_1 0 0 H 0 PPG3_TOUT0 0 0 G_DQ2_1 0 0 121 0 0 0 P0_28 0 G_DQ3_1 0 0 120 ICU6_IN0 0 0 0 P0_27 0 0 0 0 0 0 0 0 EINT3 0 P0_26 0 0 0 TRACE1 ICU5_IN1 0 0 EINT2 0 G_CK_1 0 0 ICU5_IN0 0 PPG4_TOUT2 EINT1 0 0 DSP0_CTRL1 0 0 0 DSP0_CTRL0 0 0 0 P3_01 0 ICU4_IN1 0 0 0 0 0 DSP0_CLK 0 EINT1 ICU4_IN0 0 0 0 0 0 0 DSP0_CTRL2 0 0 0 PPG8_TOUT2 OCU6_OTD0 AIN9 OCU6_OTD1 0 0 ICU3_IN0 0 0 0 P1_02 M_DQ7_0 0 0 0 0 SGA3 0 OCU5_OTD1 0 0 0 P1_00 M_DQ5_0 EINT10 P1_03 M_DQ6_0 EINT9 P1_01 M_DQ4_0 0 0 ICU8_IN1 MFS16_SCL 0 TIN3 0 ZIN8 OCU5_OTD0 0 0 PPG7_TOUT2 EINT7 0 P0_31 M_CS#2_0 0 0 OCU8_OTD1 0 0 TIN2 SGO2 BIN8 OCU4_OTD1 0 OCU3_OTD0 AIN8 OCU4_OTD0 0 0 0 0 PPG8_TOUT0 EINT8 0 0 0 0 SCK16 0 0 SGA2 0 0 0 0 PPG6_TOUT2 EINT6 0 0 0 SGA0 AN9 0 TIN1 0 0 0 0 PPG7_TOUT0 0 0 G_DQ7_2 0 TOT1 J MFS16_SDA 0 TIN0 SGO1 0 0 ICU4_IN1 0 PPG6_TOUT0 P0_30 M_RWDS_0 G_DQ6_2 0 119 0 0 0 SGA1 0 0 0 0 0 0 EINT11 P1_04 M_DQ0_0 0 0 0 0 0 0 0 0 0 SGA0 0 0 0 0 0 0 P1_09 M_CK_0 EINT13 P1_06 M_DQ1_0 EINT5 0 0 EINT12 P1_05 M_DQ3_0 0 0 0 0 0 0 0 0 SGO0 SIN1 OCU4_OTD1 0 0 PPG5_TOUT2 0 P5_22 0 PPG10_TOUT2 EINT15 P1_08 M_CS#1_0 0 0 P6_01 0 G_DQ5_2 TRACE0 0 0 0 0 SCK1 0 0 0 PPG8_TOUT2 0 P0_17 0 PPG10_TOUT0 EINT14 P1_07 M_DQ2_0 PPG9_TOUT2 0 0 P0_16 0 G_DQ4_2 0 SOT16 0 0 0 0 0 TIN49 0 0 0 0 SOT1 0 ICU7_IN1 0 PPG9_TOUT0 0 0 0 0 P3_00 0 0 0 0 0 0 0 0 ICU8_IN0 0 0 EINT2 PPG11_TOUT0 EINT0 0 EINT1 0 P0_15 0 0 0 EINT0 SIN1 0 0 0 0 0 0 OCU7_OTD1 ICU6_IN1 0 0 0 PPG10_TOUT0 EINT4 0 0 0 PPG8_TOUT0 AN8 SCK1 0 0 0 0 0 0 OCU8_OTD0 ICU7_IN0 0 0 EINT0 0 EINT15 P0_14 0 0 TRACE1 0 0 MFS17_SCL 0 0 0 0 OCU6_OTD1 ICU6_IN0 0 PPG9_TOUT0 0 ICU8_IN0 AN7 SOT1 SIN17 MFS17_SDA 0 0 0 0 OCU7_OTD0 0 0 PPG8_TOUT2 0 OCU8_OTD0 J AN6 0 SCK17 0 0 0 0 0 OCU6_OTD0 0 0 EINT14 P0_13 0 0 H TRACE0 0 SOT17 0 0 0 0 0 0 0 0 0 EINT13 P0_12 0 SGO0 I AN5 SIN0 0 0 CRS 0 0 0 ICU5_IN1 0 PPG8_TOUT0 0 TOT0 118 I AN4 SCK0 0 0 0 0 0 0 0 0 0 PPG7_TOUT2 0 H 0 SOT0 0 0 0 0 0 0 OCU5_OTD1 ICU8_IN1 0 0 0 I AN3 0 0 0 0 0 0 0 ICU9_IN1 0 OCU10_OTD1 ICU10_IN1 0 0 ICU9_IN0 0 0 0 117 I AN2 0 0 0 0 0 0 0 0 PPG7_TOUT0 0 116 H AN1 0 0 0 0 0 0 0 OCU8_OTD1 0 0 PPG6_TOUT2 0 115 I AN0 0 CAP0_DATA25 0 0 0 0 0 0 0 OCU10_OTD0 ICU10_IN0 0 OCU9_OTD1 0 0 0 P6_04 0 114 J 0 0 0 0 0 0 0 0 0 0 113 J PSC_1 0 0 CAP0_DATA24 0 0 0 0 0 0 0 OCU9_OTD0 ICU9_IN0 0 EINT15 P2_31 0 112 I VCC5 DSP0_CTRL4 0 0 0 0 0 0 0 ICU8_IN1 0 OCU11_OTD0 ICU11_IN0 0 0 0 0 0 111 H VSS DSP0_CTRL3 0 0 0 0 0 0 0 0 0 OCU10_OTD0 ICU10_IN0 0 0 ICU8_IN0 0 0 110 G VCC12 DSP0_CTRL2 0 0 0 0 0 0 0 ICU7_IN1 FRT8/9/10/11_TEXT PPG7_TOUT2 109 - MLBCLK 0 0 0 0 0 0 0 OCU9_OTD0 0 0 108 - MLBSIG 0 0 0 0 0 0 0 OCU8_OTD1 0 ICU7_IN1 107 - MLBDAT G_SDATA0_3 0 0 0 0 0 0 ICU7_IN0 0 106 F VCC3 G_SSEL0 0 0 0 0 0 0 0 ICU6_IN1 0 105 F VSS G_SDATA0_1 0 0 0 0 0 0 OCU8_OTD0 0 ZIN9 OCU7_OTD1 104 F M_SDATA1_3 G_SDATA0_2 0 0 0 0 0 OCU7_OTD1 0 103 - M_SSEL1 G_SDATA0_0 0 0 0 0 0 0 SGO3 102 - M_SDATA1_1 0 0 0 0 0 0 0 0 101 E M_SDATA1_2 0 0 0 0 0 OCU7_OTD0 0 100 E M_SDATA1_0 G_SCLK0 0 0 0 0 0 OCU6_OTD1 0 99 E VCC3 0 0 0 0 0 0 0 EINT14 P2_30 0 98 E VSS G_SDATA1_3 0 0 0 0 PPG7_TOUT0 97 E 0 G_SSEL1 0 0 0 0 0 96 - VSS G_SDATA1_1 0 0 0 0 0 ICU7_IN0 95 - M_SDATA0_3 G_SDATA1_2 0 TXER TIN35 I2S1_SCK 0 0 TOT35 I2S1_WS 0 BIN9 OCU7_OTD0 94 E M_SSEL0 G_SDATA1_0 0 0 0 0 0 93 - M_SDATA0_1 0 0 0 0 0 0 92 E M_SDATA0_2 0 COL 0 0 0 91 E M_SDATA0_0 0 0 0 0 90 E VCC3 0 0 0 P6_03 0 89 E VSS 0 0 0 88 E M_SCLK0 0 CAP0_DATA34 0 0 0 0 EINT13 P2_29 0 87 - VSS 0 0 RXCLK TIN33 I2S0_SCK 0 86 - DSP0_CTRL2 0 TXCLK TOT33 I2S0_WS PPG6_TOUT2 85 E VCC12 0 0 0 84 - DSP0_CTRL0 0 0 0 83 - 0 DSP0_DATA1_11 DSP0_DATA_D11- CAP0_CLK 0 0 0 82 C 0 0 DSP0_DATA0_11 DSP0_DATA_D11+ CAP0_DATA33 0 0 0 CAP0_DATA22 0 ICU6_IN1 81 C VCC3 0 DSP0_DATA1_10 DSP0_DATA_D10- CAP0_DATA32 CAP0_DATA35 RXDV TIN34 I2S1_SD VSS 0 DSP0_DATA0_10 DSP0_DATA_D10+ CAP0_DATA23 CAP0_DATA32 RXER TOT34 I2S1_ECLK 0 0 80 D VCC3 0 79 D VSS 0 78 - DSP0_DATA1_9 DSP0_DATA_D9- EINT12 P2_28 0 77 - DSP0_DATA0_9 DSP0_DATA_D9+ CAP0_DATA21 0 PPG0/1/2/3/4/5_TIN1 PPG6_TOUT0 76 D VCC3 0 75 D 0 74 - P6_02 0 73 - 0 0 72 D 0 71 D 0 - 0 70 0 69 0 68 0 67 0 66 0 65 Page 38 of 222 Document Number: 002-05682 Rev. *K - 161 S AN30 0 AP1(AH1) PWM1P1 OCU8_OTD1 ICU8_IN1 PPG8_TOUT2 EINT9 P3_25 0 0 0 33 160 T TRACE7 0 0 0 0 0 0 P6_10 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 0 CAP0_DATA3 DSP0_DATA_D0+ DSP0_DATA0_0 D 34 159 S AN29 0 BN0(BL0) PWM2M0 OCU8_OTD0 ICU8_IN0 PPG8_TOUT0 EINT8 P3_24 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0 OCU10_OTD0 0 TIN0 0 CAP0_DATA4 DSP0_DATA_D0- DSP0_DATA1_0 D 35 158 S AN28 0 BP0(BH0) PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 36 157 S AN27 0 AN0(AL0) PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 37 156 T TRACE6 0 0 0 0 0 0 P6_09 0 0 0 0 0 P5_29 EINT13 PPG10_TOUT2 ICU10_IN1 OCU10_OTD1 0 TOT1 0 CAP0_DATA5 DSP0_DATA_D1+ DSP0_DATA0_1 D 38 155 S AN26 0 AP0(AH0) PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 0 0 0 0 0 0 0 P5_30 EINT14 PPG11_TOUT0 ICU11_IN0 OCU11_OTD0 SOT0 TIN1 0 CAP0_DATA6 DSP0_DATA_D1- DSP0_DATA1_1 D 39 154 - DVCC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_31 EINT15 PPG11_TOUT2 ICU11_IN1 OCU11_OTD1 SCK0 TOT2 0 CAP0_DATA7 DSP0_DATA_D2+ DSP0_DATA0_2 D 40 153 - DVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6_00 EINT0 PPG0_TOUT0 ICU0_IN0 OCU0_OTD0 0 TIN2 0 CAP0_DATA8 DSP0_DATA_D2- DSP0_DATA1_2 D 41 152 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 42 151 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 43 150 - VCC12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_00 EINT1 PPG0_TOUT2 ICU0_IN1 OCU0_OTD1 0 TOT3 0 CAP0_DATA9 DSP0_DATA_D3+ DSP0_DATA0_3 D 44 149 - AVSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_01 EINT2 PPG1_TOUT0 ICU1_IN0 OCU1_OTD0 0 TIN3 TXEN CAP0_DATA10 DSP0_DATA_D3- DSP0_DATA1_3 D 45 148 - AVRH5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 46 147 - AVCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 47 146 H 0 0 0 0 OCU6_OTD0 ICU6_IN0 PPG6_TOUT0 EINT4 P3_20 0 0 0 0 0 0 0 0 0 P0_02 EINT3 PPG1_TOUT2 ICU1_IN1 OCU1_OTD1 0 TOT16 COL CAP0_DATA11 DSP0_DATA_D4+ DSP0_DATA0_4 D 48 145 H 0 0 SGO3 TIN35 OCU5_OTD1 ICU5_IN1 PPG5_TOUT2 EINT3 P3_19 0 0 0 0 0 0 0 0 0 P0_03 EINT4 PPG2_TOUT0 ICU2_IN0 OCU2_OTD0 0 TIN16 CRS CAP0_DATA12 DSP0_DATA_D4- DSP0_DATA1_4 D 49 144 H ADTRG 0 SGA3 TOT35 OCU5_OTD0 ICU5_IN0 PPG5_TOUT0 EINT2 P3_18 0 0 0 CAP0_DATA11 G_CK_2 0 0 0 0 P0_04 EINT5 PPG2_TOUT2 ICU2_IN1 OCU2_OTD1 0 TOT17 TXD0 CAP0_DATA13 DSP0_DATA_D5+ DSP0_DATA0_5 D 50 143 - C 0 0 0 0 0 0 0 0 0 0 0 CAP0_DATA12 G_DQ3_2 0 0 0 0 P0_05 EINT6 PPG3_TOUT0 ICU3_IN0 OCU3_OTD0 SIN0 TIN17 TXD1 CAP0_DATA14 DSP0_DATA_D5- DSP0_DATA1_5 D 51 142 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 52 141 - VCC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 53 140 Q RSTX 0 0 0 0 0 0 0 0 0 0 0 CAP0_DATA13 G_DQ2_2 0 0 0 0 P0_06 EINT7 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 TOT18 TXD2 CAP0_DATA15 DSP0_DATA_D6+ DSP0_DATA0_6 D 54 139 P MODE 0 0 0 0 0 0 0 0 0 0 0 CAP0_DATA14 G_DQ1_2 0 0 0 0 P0_07 EINT8 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 TIN18 TXD3 CAP0_DATA16 DSP0_DATA_D6- DSP0_DATA1_6 D 55 138 I TRACE5 0 0 0 0 0 0 0 0 P6_08 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 56 137 N2 JTAG_TMS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 61 132 N JTAG_NTRST 0 0 0 0 0 0 0 0 0 0 0 TOT32 RXD2 CAP0_DATA19 DSP0_DATA_D8+ DSP0_DATA0_8 D 62 131 M X0 0 0 0 0 0 0 0 0 0 0 0 CAP0_DATA20 DSP0_DATA_D8- DSP0_DATA1_8 D 63 130 M X1 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 64 129 - VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 - 57 136 N2 JTAG_TCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_08 EINT9 PPG4_TOUT2 ICU4_IN1 OCU4_OTD1 0 TOT19 RXD0 CAP0_DATA17 DSP0_DATA_D7+ DSP0_DATA0_7 D 58 135 N2 JTAG_TDI 0 0 0 0 0 0 0 0 0 0 0 0 G_CS#1_2 0 0 0 0 P0_09 EINT10 PPG5_TOUT0 ICU5_IN0 OCU5_OTD0 0 TIN19 RXD1 CAP0_DATA18 DSP0_DATA_D7- DSP0_DATA1_7 D 59 134 O JTAG_TDO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS - 60 133 H TRACE4 0 0 0 0 0 0 0 0 P6_07 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G_RWDS_2 0 0 0 0 P0_10 EINT11 PPG5_TOUT2 ICU5_IN1 OCU5_OTD1 I2S0_ECLK 0 G_CS#2_2 0 0 0 0 P0_11 EINT12 PPG6_TOUT0 ICU6_IN0 OCU6_OTD0 I2S0_SD TIN32 RXD3 0 0 0 0 0 0 0 0 0 0 0 VCC53 32 D G_DQ0_2 0 0 D DSP0_CTRL2 0 0 0 DSP0_CLK DSP0_CLK- CAP0_DATA15 0 0 DSP0_CLK+ CAP0_DATA2 0 0 0 0 0 0 CAP0_DATA1 0 0 0 MDIO DSP0_DATA1_4 0 0 0 0 0 0 0 OCU4_OTD0 0 0 OCU3_OTD1 ICU4_IN0 0 0 ICU3_IN1 PPG4_TOUT0 0 0 PPG3_TOUT2 EINT0 0 0 0 EINT15 0 0 0 0 0 0 0 0 P3_26 0 0 PPG9_TOUT0 EINT10 0 0 OCU9_OTD0 ICU9_IN0 0 240 PWM1M1 0 241 AN1(AL1) 0 242 0 0 - AN31 0 Y S 0 Z 162 TOP VIEW TEQFP-256 0 0 31 0 VSS C 0 DSP1_DATA1_3 DSP0_CTRL1 0 0 0 0 0 CAP0_DATA0 0 0 MDC 0 0 DSP0_DATA0_4 0 0 0 0 DSP0_CTRL0 OCU9_OTD1 P0_19 0 ICU9_IN1 P0_18 0 0 PPG9_TOUT2 0 0 0 0 0 0 0 0 P3_27 0 0 PPG9_TOUT2 EINT11 0 0 OCU9_OTD1 ICU9_IN1 0 0 PWM2P1 0 0 BP1(BH1) 0 0 0 0 0 AN32 0 0 S DSP0_DATA1_11 0 163 DSP0_DATA0_11 0 ICU10_IN1 OCU10_OTD1 BIN9 30 EINT3 0 - P5_21 0 VCC3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP0_DATA1_10 SEG7 EINT13 PPG10_TOUT2 0 0 0 0 0 0 0 0 0 0 0 0 P6_11 0 0 P5_13 0 0 0 0 0 P3_28 0 0 0 0 PPG10_TOUT0 EINT12 0 0 0 P6_24 OCU10_OTD0ICU10_IN0 0 0 0 PWM2M1 0 0 0 BN1(BL1) 0 0 0 0 TRACE8 0 0 0 AN33 T 0 0 0 S 164 0 0 0 165 29 0 0 243 28 0 0 244 - VSS 0 0 Y VCC12 0 0 0 Y 0 0 0 0 DSP1_DATA0_3 0 0 0 0 DSP1_DATA1_2 0 0 0 0 0 0 0 DSP0_CTRL1 0 0 0 DSP0_CTRL2 DSP1_CTRL2 0 0 0 0 SOT11 0 0 0 SCK11 0 0 0 0 0 ZIN9 0 0 0 ICU11_IN0 OCU11_OTD0 0 0 0 ICU11_IN1 OCU11_OTD1 0 0 SEG6 EINT14 PPG11_TOUT0 0 0 SEG5 EINT15 PPG11_TOUT2 0 0 0 P5_14 0 0 0 P5_15 0 0 MFS8_CS3 DVSS 0 MFS8_CS1 - 0 0 166 0 0 27 0 0 0 0 VCC3_LVDS_Tx 0 245 0 0 246 0 0 Y 0 0 Z 0 0 0 0 0 0 DSP1_DATA0_2 0 0 0 0 0 0 0 DSP1_CLK 0 0 0 0 0 0 0 DSP0_CTRL3 0 0 0 0 0 0 0 0 SIN11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DVCC 0 0 OCU0_OTD0 - 0 0 0 167 0 ICU0_IN0 26 0 0 0 0 VSS_LVDS_Tx 0 0 0 0 PPG0_TOUT0 0 0 0 0 0 EINT0 0 0 0 0 0 0 0 SEG4 0 0 0 0 P6_12 P3_29 0 0 0 P5_16 0 PPG10_TOUT2 EINT13 0 0 0 0 P6_25 0 OCU10_OTD1ICU10_IN1 0 MFS8_CS2 0 PWM1P2 0 0 0 0 0 0 0 0 0 0 0 0 AN34 0 0 0 TRACE9 S 0 0 247 T 168 0 0 248 169 25 0 0 Y 24 B 0 0 Y B TxDOUT00 0 DSP1_DATA1_1 TxDOUT0+ 0 0 0 DSP1_DATA0_1 0 0 0 0 DSP0_CTRL4 DSP1_CTRL0 0 0 0 0 DSP0_CTRL5 DSP1_CTRL1 0 0 0 0 0 0 0 0 0 0 0 0 0 SOT12 P3_30 0 0 0 PPG11_TOUT0 EINT14 0 0 OCU11_OTD0ICU11_IN0 0 OCU0_OTD1 PWM1M2 0 OCU1_OTD0 0 0 ICU0_IN1 0 0 ICU1_IN0 AN35 0 0 S 0 0 170 0 PPG0_TOUT2 23 0 PPG1_TOUT0 B 0 EINT1 TxDOUT10 EINT2 0 0 SEG3 0 0 0 SEG2 0 0 0 0 P5_17 0 0 0 0 P5_18 0 P3_31 0 0 P4_00 PPG11_TOUT2 EINT15 0 MFS12_SDA PPG0_TOUT0 EINT0 OCU11_OTD1ICU11_IN1 0 0 OCU0_OTD0 ICU0_IN0 PWM2P2 0 0 PWM2M2 0 0 0 0 0 0 0 0 AN36 0 249 AN37 S 0 Y S 171 0 DSP1_DATA1_0 172 22 0 0 21 B 0 DSP0_CTRL6 B TxDOUT1+ 0 0 SCK12 TxCLK- 0 0 0 0 0 0 OCU1_OTD1 0 0 ICU1_IN1 P6_13 0 0 0 0 0 PPG1_TOUT2 0 0 0 0 EINT3 0 0 0 SEG1 0 0 0 0 P5_19 0 0 0 MFS12_SCL 0 0 0 0 TRACE10 0 0 0 T 0 0 250 173 0 0 Y 20 0 0 DSP1_DATA0_0 B 0 0 0 0 TxCLK+ 0 0 DSP0_CTRL7 0 0 0 0 SIN12 0 0 0 0 P4_01 0 0 OCU2_OTD0 PPG0_TOUT2 EINT1 0 0 ICU2_IN0 OCU0_OTD1 ICU0_IN1 0 0 0 PWM1P3 0 PPG2_TOUT0 0 TxDOUT3+ EINT4 0 0 SEG0 AN38 0 0 P5_20 S 0 0 174 0 0 19 0 0 B 0 251 0 TxDOUT2- 0 252 0 0 0 253 0 0 0 254 0 P4_02 0 255 P4_03 PPG1_TOUT0 EINT2 0 256 PPG1_TOUT2 EINT3 OCU1_OTD0 ICU1_IN0 0 - OCU1_OTD1 ICU1_IN1 PWM1M3 0 Y PWM2P3 0 0 Y 0 SOT2 0 Y SCK2 AN39 0 Z AN40 S - Y S 175 - VSS_LVDS_Tx 0 176 18 - VCC3_LVDS_Tx 0 VCC53 17 B - AVCC3_LVDS_PLL 0 0 DSP1_CLK B AVSS_LVDS_PLL 0 0 0 DSP1_CTRL2 0 TxDOUT3- TxDOUT2+ 0 0 0 0 DSP1_CTRL1 0 0 0 0 0 DSP1_CTRL0 P6_14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACE11 0 0 0 0 0 T 0 0 0 0 DSP0_CTRL8 177 0 0 0 0 DSP0_CTRL9 16 0 0 0 0 0 B 0 0 0 0 0 0 0 0 0 0 0 11 0 SOT11 0 0 P4_04 - 0 SCK11 DSP0_CTRL10 0 0 - VCC12 0 0 0 0 PPG2_TOUT0 EINT4 - VSS 0 0 SIN11 DSP0_CTRL11 0 0 0 A AVSS 0 0 0 0 0 0 OCU2_OTD0 ICU2_IN0 C_L 0 0 0 0 P4_05 0 0 PWM2M3 0 0 0 0 0 PPG2_TOUT2 EINT5 0 0 0 0 0 0 0 0 OCU2_OTD1 ICU2_IN1 0 0 SIN2 0 0 0 0 0 PWM1P4 0 0 AN41 0 0 0 0 0 0 0 DVSS S 0 0 0 0 0 0 DVCC 178 0 0 0 0 OCU0_OTD1 AN42 179 15 0 0 0 0 OCU1_OTD0 SGA1 S 180 14 0 0 0 0 OCU1_OTD1 SGO1 181 13 0 0 0 0 OCU2_OTD0 0 12 0 0 0 0 0 0 0 0 0 0 0 MFS0_CS0 0 P6_15 0 0 0 0 ICU0_IN1 MFS2_CS0 0 0 0 0 0 0 0 0 ICU1_IN0 MFS2_CS1 0 0 P4_06 0 0 0 0 0 0 0 ICU1_IN1 0 P4_07 PPG3_TOUT0 EINT6 0 0 ICU2_IN0 P4_08 PPG3_TOUT2 EINT7 OCU3_OTD0 ICU3_IN0 0 A 0 PPG4_TOUT0 EINT8 OCU3_OTD1 ICU3_IN1 PWM1M4 0 - DAC_L 0 OCU4_OTD0 ICU4_IN0 PWM2P4 0 0 AVCC3_DAC 0 0 PWM2M4 0 SOT3 TRACE12 0 0 0 0 SCK3 AN43 T 0 0 0 SIN3 AN44 S 182 0 0 0 AN45 S 183 0 0 0 S 184 0 0 0 185 9 0 0 PPG0_TOUT2 0 8 10 0 0 PPG1_TOUT0 0 0 0 0 PPG1_TOUT2 0 P6_16 0 0 PPG2_TOUT0 0 0 0 0 0 0 P4_09 0 0 0 0 0 0 0 PPG4_TOUT2 EINT9 0 0 0 0 0 OCU4_OTD1 ICU4_IN1 0 0 0 0 0 PWM1P5 0 0 0 0 P4_25 COM3 EINT9 0 0 0 0 P4_26 COM2 EINT10 0 TRACE13 5 0 P4_27 COM1 EINT11 AN46 T 4 VSS 0 P4_28 COM0 EINT12 S 186 3 A AVSS 0 187 7 2 A C_R 0 0 6 - DAC_R 0 0 0 MFS0_CS3 MFS4_SDA 1 AVSS 0 0 0 0 MFS0_CS1 MFS4_SCL 0 - 0 0 0 0 0 P6_26 0 MFS0_CS2 0 0 P4_10 0 0 0 0 0 0 0 0 0 P4_11 0 0 0 0 0 0 0 0 P4_12 PPG5_TOUT0 EINT10 0 0 0 0 0 0 0 0 PPG5_TOUT2 EINT11 0 0 0 0 0 0 0 0 PPG6_TOUT0 EINT12 OCU5_OTD0 ICU5_IN0 0 0 0 0 0 0 0 0 OCU5_OTD1 ICU5_IN1 PWM1M5 0 0 0 0 0 0 0 0 OCU6_OTD0 ICU6_IN0 PWM2P5 0 0 0 0 0 0 0 0 0 PWM2M5 RX1 SOT4 0 0 0 0 0 0 0 0 TX1 SCK4 AN47 0 0 0 0 0 0 0 0 SIN4 AN48 S 0 0 0 0 0 0 0 0 AN49 S 188 0 0 0 0 0 0 0 DVSS S 189 0 0 0 0 0 0 DVCC 190 0 0 0 0 0 191 0 0 0 0 192 0 0 0 S6J3200 Series 4.2 Package Dimensions Function Digit 3, 4, 5, 6, 7, 8, 9, K, L, M, N B TEQFP-216 Figure 4-18 TEQFP-208 Figure 4-19 Figure 4-20 TEQFO-256 Figure 4-21 - Note: - Same size is specified for MIN, NOM, MAX, then it should be regarded as maximum size. Document Number: 002-05682 Rev. *K Page 39 of 222 S6J3200 Series TEQFP216 4.2.1 Figure 4-18 LEQ216 Package Type TEQFP216 Package Code LEQ216 4 D D2 5 7 D1 D3 E3 E1 E E2 EXPOSED PAD 0.20 C A-B D TOP VIEW 0.10 C A-B D BOTTOM VIEW 2 GAUGE PLANE DETAIL A A A A2 10 SEATING PLANE A' A1 R1 L2 R2 11 e 0.08 C b 0.07 C A-B D 8 SIDE VIEW c b L L1 SECTION A-A' DETAIL A NOTES : DIM ENSIONS 1. ALL DIM ENSIONS ARE IN M ILLIM ETERS. SYM BOL M IN. NOM . A1 0.05 A2 1.35 0.15 1.40 D 26.00 BSC D1 24.00 BSC D2 9.90 REF D3 8.70 REF E 26.00 BSC E 1 24.00 BSC E 2 9.90 REF E 3 8.70 REF R 1 0.08 R 2 0.08 0 c 0.09 b 0.13 L 0.45 1.45 0.20 4 8 0.20 0.18 0.23 0.60 0.75 L 1 1.00 REF L 2 0.25 e M AX. 1.70 A 002-10860 *B PACKAGE OUTLINE, 216 LEAD TEQFP 0.40 BSC Document Number: 002-05682 Rev. *K 24.0X24.0X1.7 M M LEQ216 REV*B Page 40 of 222 S6J3200 Series TEQFP208 4.2.2 Figure 4-19: LET208 Package Type TEQFP208 Package Code LET208 D D1 4 D2 D3 5 7 E3 E2 E1 E EXPOSED PAD 0.20 C A-B D TOP VIEW BOTTOM VIEW 0.10 C A-B D 2 DETAIL A A A A2 A' A1 e 11 SEATING PLANE 0.08 C b 0.08 C A-B 10 PLANE c R2 b L L1 D 8 SIDE VIEW R1 L2 GAUGE SECTION A-A' DETAIL A DIMENSION SYMBOL M IN. NOM. A1 0.05 A2 1.35 0.15 1.40 D 30.00 BSC D1 28.00 BSC D2 9.90 REF D3 8.71 REF E 30.00 BSC E1 28.00 BSC E2 9.90 REF 1.45 8.71 REF E3 R1 0.08 R2 0.08 MAX. 1.70 A 0 0.20 4 8 c 0.12 b 0.17 0.22 0.27 L 0.45 0.60 0.75 L 1 L 2 e 0.20 1.00 REF 0.25 0.50 BSC 002-13651 *A PACKAGE OUTLINE, 208 LEAD TEQFP 28.0X28.0X1.7 M M LET208 REV*A Document Number: 002-05682 Rev. *K Page 41 of 222 S6J3200 Series Figure 4-20:LER208 Package Type TEQFP208 Package Code LER208 4 D D1 D2 5 7 D3 E1 E E3 E2 EXPOSED PAD 0.20 C A-B D TOP VIEW BOTTOM VIEW 0.10 C A-B D 2 DETAIL A L2 A A SEATING PLANE A' A2 e L 0.08 C 0.08 b SIDE VIEW 10 c R2 A1 11 R1 GAUGE PLANE C A-B D L1 b SECTION A-A' DETAIL A 8 DIMENSION SYMBOL M IN. NOM. A1 0.05 A2 1.35 0.15 1.40 D 30.00 BSC D1 28.00 BSC D2 9.26 REF D3 8.06 REF E 30.00 BSC E1 28.00 BSC E2 9.26 REF 1.45 8.06 REF E3 R1 0.08 R2 0.08 MAX. 1.70 A 0 0.20 4 8 c 0.12 b 0.17 0.22 0.27 L 0.45 0.60 0.75 L 1 L 2 e 0.20 1.00 REF 0.25 0.50 BSC 002-13654 *A PACKAGE OUTLINE, 208 LEAD TEQFP 28.0X28.0X1.7 M M LER208 REV*A Document Number: 002-05682 Rev. *K Page 42 of 222 S6J3200 Series 4.2.3 TEQFP256 Figure 4-21:LEL256 Package Type TEQFP256 Package Code LEL256 D D1 D2 D3 D 192 129 129 128 193 192 193 128 B E2 E3 E E1 A 256 65 65 0.20 C A-B D 64 1 0.20 H 4X e b 4X 256 1 64 A-B D EXPOSED PAD 0.07 M C A-B S D S BOTTOM VIEW TOP VIEW R1 - 0.05 S R2 A2 A H GAUGE PLANE 0.25m m c L1 SEE DETAIL A A1 0.08 C S L C SEATINGPLANE SID E VIEW D ETAIL A D IM EN SION S SYM BOL N OTES : D IM EN SION S 1. ALL D IM EN SIO N S ARE IN M ILLIM ETERS. SYM BOL M IN . N OM . M A X. M IN . N OM . M A X. A - - 1.7 0 b 0.1 3 0.1 8 0.2 3 A1 0.0 5 - 0.1 5 e A2 1.3 5 1.4 0 1.4 5 R 2 0.0 8 R1 0.0 8 2. DIM ENSIONS D1 AND E1 DO NOT INCLUD E M OLD PROTRU SION . ALLOW ABLE PROTRU SIO N IS 0.25m m PER SID E. D 1 AND E1 ARE M AXIM UM PLASTIC BODY SIZE DIM EN SION S INCLUD IN G M OLD 0.4 0 BSC. M ISM A TCH . - 0.2 0 - - D 30 .00 BSC. D1 28 .00 BSC. D2 9.90 REF. c 0.0 9 - 0.2 0 D3 8.70 REF. L 0.4 5 0.6 0 0.7 5 E 30 .00 BSC. E1 28 .00 BSC. E2 9.90 REF. E3 8.70 REF. Document Number: 002-05682 Rev. *K 0 3.5 3. D IM EN SIO N b D OES N OT INCLUD E D AM BAR PROTRU SION . ALLOW ABLE DAM BAR PROTRUSIO N SHALL N OT CAUSE THE 7 LEAD W ID TH TO EXCEED TH E M AXIM UM b D IM EN SION BY M ORE TH AN 0.08 m m . S 0.2 0 - OR THE FOOT. M INIM UM SPAC E BETW EEN PROTRU SION AND AN AD JACEN T LEAD SH ALL N OT BE LESS THAN 0.07m m . 1.0 0 REF. L 1 DAM BAR CAN NOT BE LOCATED ON THE LOW ER RAD IUS - 4. TH E TOP PA CKAGE BO D Y SIZE M AY BE SM ALLER TH AN TH E BOTTOM PACKA GE SIZE. 002-10752 *A PACKAGE OUTLINE, 256 LEAD TEQFP 28.0X28.0X1.7 M M LEL256 REV*A Page 43 of 222 S6J3200 Series 5. I/O Circuit Type 5.1 I/O Circuit Type This section explains I/O circuit types. Type A B C Circuit Analog output Analog output Pull-up control Digital output Digital output Remark - Analog output(3 V) - Audio DAC output - Analog output(3 V) - LVDS output - General-purpose I/O port - Output 2 mA, 5 mA, 10 mA or 20 mA selectable - 33 k with pull-up resistor control - 33 k with pull-down resistor control - CMOS hysteresis input - TTL input Pull-down control CMOS-hys input PSS control TTL input PSS control Document Number: 002-05682 Rev. *K Page 44 of 222 S6J3200 Series Type D Circuit Remark Pull-up control Digital output Digital output Pull-down control - General-purpose I/O port - Output 2 mA, 5 mA, 10 mA or 20 mA selectable - 33 k with pull-up resistor control - 33 k with pull-down resistor control - CMOS hysteresis input - TTL input - RSDS differential output data - General-purpose I/O port - Output 2 mA, 5 mA or 10 mA selectable - 33 k with pull-up resistor control - 33 k with pull-down resistor control - CMOS hysteresis input - TTL input CMOS-hys input PSS control TTL input PSS control Pull-up control Digital output Digital output Pull-down control CMOS-hys input Control Logic PSS control TTL input PSS control RSDS mode control E RSDS output data RSDS output enable Pull-up control Digital output Digital output Pull-down control CMOS-hys input PSS control TTL input PSS control Document Number: 002-05682 Rev. *K Page 45 of 222 S6J3200 Series Type F Circuit Pull-up control Digital output Digital output Remark - General-purpose I/O port - Output 2 mA, 5 mA, 6 mA or 10 mA selectable - 33 k with pull-up resistor control - 33 k with pull-down resistor control - CMOS hysteresis input - MediaLB level hysteresis input - External 1.2 V regulator control - Output 2 mA - General-purpose I/O port - Output 1 mA, 2 mA or 5 mA selectable - 50 k with pull-up resistor control - 50 k with pull-down resistor control - CMOS hysteresis input - Automotive hysteresis input - General-purpose I/O port with analog input - Output 1 mA, 2 mA or 5 mA selectable - 50 k with pull-up resistor control - 50 k with pull-down resistor control - CMOS hysteresis input - Automotive hysteresis input Pull-down control CMOS-hys input PSS control MediaLB-hys input PSS control G Digital output Digital output H Pull-up control Digital output Digital output Pull-down control CMOS-hys input PSS control Automotive input PSS control I Pull-up control Digital output Digital output Pull-down control CMOS-hys input PSS control Automotive input PSS control Analog input Document Number: 002-05682 Rev. *K Page 46 of 222 S6J3200 Series Type J Circuit Remark Pull-up control Digital output Digital output Pull-down control - General-purpose I/O port with analog input - Output 1 mA, 2 mA, 3 mA(I2C) or 5 mA selectable - 50 k with pull-up resistor control - 50 k with pull-down resistor control - CMOS hysteresis input - Automotive hysteresis input - TTL input - 50 k with pull-up - CMOS hysteresis input - Main oscillation I/O - JTAG_NTRST - 50 k with pull-down - TTL input - JTAG_TDI/TMS/TCK - 50 k with pull-up - TTL input - JTAG_TDO - Output 5 mA CMOS-hys input PSS control Automotive input PSS control TTL input PSS control Analog input L CMOS-hys input M X1 OSC input X0 PSS control N TTL input N2 TTL input O Digital output Digital output Document Number: 002-05682 Rev. *K Page 47 of 222 S6J3200 Series Type P Circuit Remark - Mode input - CMOS hysteresis input - CMOS hysteresis input - 50 k with pull-up - General-purpose I/O port with analog input - Output 1 mA, 2 mA, 5 mA or 30 mA selectable - 50 k with pull-up resistor control - 50 k with pull-down resistor control - CMOS hysteresis input - Automotive hysteresis input - General-purpose I/O port - Output 1 mA, 2 mA, 5 mA or 30 mA selectable - 50 k with pull-up resistor control - 50 k with pull-down resistor control - CMOS hysteresis input - Automotive hysteresis input Mode input Control Q CMOS-hys input S Pull-up control Digital output Digital output Pull-down control CMOS-hys input PSS control Automotive input PSS control Analog input T Pull-up control Digital output Digital output Pull-down control CMOS-hys input PSS control Automotive input PSS control Document Number: 002-05682 Rev. *K Page 48 of 222 S6J3200 Series Type U Circuit Pull-up control Remark - General-purpose input port with LCDC reference voltage input - 50 k with pull-up resistor control - 50 k with pull-down resistor control - CMOS hysteresis input - Automotive hysteresis input - General-purpose I/O port with analog input and LCDC Pull-down control CMOS-hys input PSS control Automotive input PSS control LCDC reference voltage input V Pull-up control Digital output Digital output Pull-down control reference voltage input - Output 1 mA, 2 mA or 5 mA selectable - 50 k with pull-up resistor control - 50 k with pull-down resistor control - CMOS hysteresis input - Automotive hysteresis input - General-purpose I/O port with analog input and LCDC CMOS-hys input PSS control Automotive input PSS control Analog input LCDC reference voltage input W Pull-up control Digital output Digital output Pull-down control COM/SEG output - Output 1 mA, 2 mA or 5 mA selectable - 50 k with pull-up resistor control - 50 k with pull-down resistor control - CMOS hysteresis input - Automotive hysteresis input CMOS-hys input PSS control Automotive input PSS control Analog input LCDC COM/SEG output Document Number: 002-05682 Rev. *K Page 49 of 222 S6J3200 Series Type X Circuit Remark Pull-up control Digital output Digital output - Sub oscillation I/O shared General-purpose I/O port - Output 1 mA, 2 mA or 5 mA selectable - 50 k with pull-up resistor control - 50 k with pull-down resistor control - CMOS hysteresis input - Automotive hysteresis input - General-purpose I/O port with LCDC COM/SEG output - Output 1 mA, 2 mA or 5 mA selectable - 50 k with pull-up resistor control - 50 k with pull-down resistor control - CMOS hysteresis input - Automotive hysteresis input - TTL input Pull-down control CMOS-hys input PSS/OSC control Automotive input PSS/OSC control OSC input PSS/OSC control Pull-up control Digital output Digital output Pull-down control CMOS-hys input PSS/OSC control Automotive input PSS/OSC control Y Pull-up control Digital output Digital output Pull-down control CMOS-hys input PSS control Automotive input PSS control TTL input PSS control LCDC COM/SEG output Document Number: 002-05682 Rev. *K Page 50 of 222 S6J3200 Series Type Z Circuit Pull-up control Digital output Digital output Pull-down control Remark - General-purpose I/O port - Output 1 mA, 2 mA or 5 mA selectable - 50 k with pull-up resistor control - 50 k with pull-down resistor control - CMOS hysteresis input - Automotive hysteresis input - TTL input CMOS-hys input PSS control Automotive input PSS control TTL input PSS control 5.2 Note Alphabets, which show the I/O circuit type, are described with the corresponding pin number in the pin assignment figure. Document Number: 002-05682 Rev. *K Page 51 of 222 S6J3200 Series 6. Port Description 6.1 Port Description List The table shows the port function of description which is supported. The port function which is not described in the table is not supported for the product. Port Name Description VCC12 +1.2-V power supply pin VCC5 +5.0-V power supply pin VCC3 +3.3-V power supply pin VCC53 +3.3 V/+5.0 V selection power supply pin VCC3_LVDS_Tx LVDS Tx power supply pin VSS GND VSS_LVDS_Tx AVCC3_DAC AVCC3_LVDS_PLL AVSS_LVDS_PLL AVCC5 AVSS LVDS Tx GND Audio DAC power supply pin LVDS PLL power supply pin LVDS PLL GND A/D converter analog power supply pin A/D converter upper limit reference voltage pin A/D converter GND DVCC SMC large current port power supply pin DVSS SMC large current port GND X1 X0 X1A X0A NMIX RSTX PSC_1 MODE C JTAG_NTRST JTAG_TDO JTAG_TDI JTAG_TCK JTAG_TMS TRACE0 TRACE1 Main clock oscillator output pin Main clock oscillator input pin Sub-clock oscillator output Sub-clock oscillator input Non-maskable interrupt input pin External reset input pin External Power Supply Control pin Mode Pin External capacity connection output pin JTAG test reset input pin JTAG test data output pin JTAG test data input pin JTAG test clock input pin JTAG test mode state input pin Trace data 0 output pin Trace data 1 output pin AVRH5 Document Number: 002-05682 Rev. *K Package Pin Number TEQFP208 TEQFP216 11, 28, 61, 11, 28, 63, 85, 122, 87, 128, 129, 123, 182, 190, 191 183 87, 104, 89, 108, 119, 115, 157, 163, 179 171 30, 43, 53, 30, 43, 55, 65, 74, 81 67, 76, 83 173, 185, 181, 193, 194, 208 202, 216 14, 27 14, 27 1, 10, 29, 1, 10, 29, 42, 42, 52, 62, 54, 64, 66, 64, 71, 73, 73, 75, 82, 80, 86, 105, 88, 109, 120, 116, 124, 130, 164, 158, 172, 180, 192, 184, 195 203 15, 26 15, 26 6 6 13 13 12 12 119 125 120 126 2, 5, 9, 121 126, 136, 146,156 125, 135, 145,155 106 107 169 170 103 114 88 113 117 108 109 110 111 112 96 97 2, 5, 9, 127 132, 142, 152,162 131, 141, 151, 161 110 111 177 178 107 118 90 117 121 112 113 114 115 116 100 101 Remark Page 52 of 222 S6J3200 Series Port Name Description TRACE2 TRACE3 TRACE_CLK TRACE_CTL ADTRG AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AN39 AN40 AN41 AN42 AN43 Trace data 2 output pin Trace data 3 output pin Trace clock Trace control A/D converter external trigger input pin ADC Analog 0 input pin ADC Analog 1 input pin ADC Analog 2 input pin ADC Analog 3 input pin ADC Analog 4 input pin ADC Analog 5 input pin ADC Analog 6 input pin ADC Analog 7 input pin ADC Analog 8 input pin ADC Analog 9 input pin ADC Analog 10 input pin ADC Analog 11 input pin ADC Analog 12 input pin ADC Analog 13 input pin ADC Analog 14 input pin ADC Analog 15 input pin ADC Analog 16 input pin ADC Analog 17 input pin ADC Analog 18 input pin ADC Analog 19 input pin ADC Analog 20 input pin ADC Analog 21 input pin ADC Analog 22 input pin ADC Analog 23 input pin ADC Analog 24 input pin ADC Analog 25 input pin ADC Analog 26 input pin ADC Analog 27 input pin ADC Analog 28 input pin ADC Analog 29 input pin ADC Analog 30 input pin ADC Analog 31 input pin ADC Analog 32 input pin ADC Analog 33 input pin ADC Analog 34 input pin ADC Analog 35 input pin ADC Analog 36 input pin ADC Analog 37 input pin ADC Analog 38 input pin ADC Analog 39 input pin ADC Analog 40 input pin ADC Analog 41 input pin ADC Analog 42 input pin ADC Analog 43 input pin Document Number: 002-05682 Rev. *K Package Pin Number TEQFP208 TEQFP216 98 102 99 103 100 104 101 105 118 122 92 90 93 91 94 92 95 96 93 97 94 98 95 99 96 100 97 101 98 102 99 103 100 104 101 105 102 106 160 166 161 167 162 168 169 170 163 171 164 172 165 173 166 174 167 175 168 176 127 133 128 134 129 135 130 136 131 137 132 138 133 139 134 140 137 143 138 144 139 145 140 146 141 147 142 148 143 149 144 150 147 153 148 154 Remark Page 53 of 222 S6J3200 Series Port Name Description AN44 AN45 AN46 AN47 AN48 AN49 TX0 TX1 TX5 TX6 RX0 RX1 RX5 RX6 ADC Analog 44 input pin ADC Analog 45 input pin ADC Analog 46 input pin ADC Analog 47 input pin ADC Analog 48 input pin ADC Analog 49 input pin CAN transmission data 0 output pin CAN transmission data 1 output pin CAN transmission data 5 output pin CAN transmission data 6 output pin CAN reception data 0 input pin CAN reception data 1 input pin CAN reception data 5 input pin CAN reception data 6 input pin EINT0 External interrupt input pin EINT1 External interrupt input pin EINT2 External interrupt input pin EINT3 External interrupt input pin EINT4 External interrupt input pin EINT5 External interrupt input pin EINT6 External interrupt input pin EINT7 External interrupt input pin EINT8 External interrupt input pin EINT9 External interrupt input pin EINT10 External interrupt input pin Document Number: 002-05682 Rev. *K Package Pin Number TEQFP208 TEQFP216 149 155 150 156 151 157 152 158 153 159 154 160 100 104 102, 154 106, 160 162, 166 168, 174 168 170, 176 99 103 101, 153 105, 159 161, 165 167, 173 167 169. 175 33, 39, 57, 33, 39, 59, 63, 96, 140, 65, 100, 146, 167, 170, 175, 178, 177,199 185, 207 40, 58, 82, 40, 60, 84, 97, 141, 101, 147, 168, 169, 176, 177, 178, 200 186,208, 41, 59, 83, 41, 61, 85, 98, 118, 102, 122, 142, 179, 148, 187, 201, 209 31, 44, 86, 31, 84, 99, 103, 123, 143, 159, 149, 165, 180, 202 188, 210 60, 100, 45, 62, 104, 144, 181, 124, 150, 203 189, 211 44, 72, 101, 46, 74, 105, 127, 147, 133, 153, 186 194, 45, 75, 89, 47, 77, 91, 102, 128, 106, 134, 148, 187, 154, 195 46, 77, 129, 48, 79, 135, 149, 160, 155, 166, 188 196 47, 76, 130, 49, 78, 92, 150, 161, 136, 156, 189 167, 197 48, 79, 90, 50, 81, 93, 131, 151, 137, 157, 162, 190 168, 198, 204 212, 51, 80, 94, 49, 78, 91, 138, 158, 132, 152, 169, 199, 191,205 213 Remark Page 54 of 222 S6J3200 Series Port Name Description EINT11 External interrupt input pin EINT12 External interrupt input pin EINT13 External interrupt input pin EINT14 External interrupt input pin EINT15 External interrupt input pin MFS0_CS0 MFS0_CS1 MFS0_CS2 MFS0_CS3 MFS2_CS0 MFS2_CS1 MFS8_CS0 MFS8_CS1 MFS8_CS2 MFS8_CS3 MFS9_CS0 MFS9_CS1 SCK0 SCK1 SCK2 SCK3 SCK4 SCK8 SCK9 SCK10 Multi-function serial ch.0 chip select 0 pin Multi-function serial ch.0 chip select 1 pin Multi-function serial ch.0 chip select 2 pin Multi-function serial ch.0 chip select 3 pin Multi-function serial ch.2 chip select 0 pin Multi-function serial ch.2 chip select 1 pin Multi-function serial ch.8 chip select 0 pin Multi-function serial ch.8 chip select 1 pin Multi-function serial ch.8 chip select 2 pin Multi-function serial ch.8 chip select 3 pin Multi-function serial ch.9 chip select 0 pin Multi-function serial ch.9 chip select 1 pin Multi-function serial ch.0 clock I/O pin Multi-function serial ch.1 clock I/O pin Multi-function serial ch.2 clock I/O pin Multi-function serial ch.3 clock I/O pin Multi-function serial ch.4 clock I/O pin Multi-function serial ch.8 clock I/O pin Multi-function serial ch.9 clock I/O pin Multi-function serial ch.10 clock I/O pin SCK11 Multi-function serial ch.11 clock I/O pin SCK12 SCK16 SCK17 Multi-function serial ch.12 clock I/O pin Multi-function serial ch.16 clock I/O pin Multi-function serial ch.17 clock I/O pin Multi-function serial ch.0 serial data input pin Multi-function serial ch.1 serial data input pin Multi-function serial ch.2 serial data input pin Multi-function serial ch.3 serial data input pin SIN0 SIN1 SIN2 SIN3 Document Number: 002-05682 Rev. *K Package Pin Number TEQFP208 TEQFP216 34, 50, 69, 34,52,71, 92, 133, 95,139,159, 153, 192, 170, 200, 206 214 35, 51, 66, 35, 53, 68, 134, 154, 96, 140, 160, 163, 193, 171, 201, 207 215 36, 54, 68, 36, 56, 70, 93, 137, 97, 143, 172, 164, 174, 182, 204 196 37, 55, 67, 37, 57, 69, 94, 138, 98, 144, 173, 165, 175, 183, 205 197 32, 38, 56, 32, 38, 58, 70, 95, 139, 72, 99, 145, 166, 176, 174, 184, 198 206 148 154 153 159 154 160 152 158 149 155 150 156 163, 191 171, 199 167, 198 175, 206 168, 199 176, 207 166, 197 174, 205 164, 192 172, 200 165, 193 173, 201 38, 91 38, 94 83, 94 85, 98 143 149 149 155 153 159 100, 180 104, 188 161, 188 167, 196 164, 192 172, 200 167, 198, 175, 206, 206 214 202 210 97 101 91 94 45, 92 47, 95 84, 95 86, 99 144 150 150 156 Remark Page 55 of 222 S6J3200 Series Port Name SIN4 SIN8 SIN9 SIN10 SIN11 SIN12 SIN16 SIN17 SOT0 SOT1 SOT2 SOT3 SOT4 SOT8 SOT9 SOT10 SOT11 SOT12 SOT16 SOT17 SCL4 (MFS4_SCL) SCL10 (MFS10_SCL) SCL12 (MFS12_SCL) SCL16 (MFS16_SCL) SCL17 (MFS17_SCL) SDA4 (MFS4_SDA) SDA10 (MFS10_SDA) SDA12 (MFS12_SDA) SDA16 (MFS16_SDA) Description Multi-function serial ch.4 serial data input pin Multi-function serial ch.8 serial data input pin Multi-function serial ch.9 serial data input pin Multi-function serial ch.10 serial data input pin Multi-function serial ch.11 serial data input pin Multi-function serial ch.12 serial data input pin Multi-function serial ch.16 serial data input pin Multi-function serial ch.17 serial data input pin Multi-function serial ch.0 serial data output pin Multi-function serial ch.1 serial data output pin Multi-function serial ch.2 serial data output pin Multi-function serial ch.3 serial data output pin Multi-function serial ch.4 serial data output pin Multi-function serial ch.8 serial data output pin Multi-function serial ch.9 serial data output pin Multi-function serial ch.10 serial data output pin Multi-function serial ch.11 serial data output pin Multi-function serial ch.12 serial data output pin Multi-function serial ch.16 serial data output pin Multi-function serial ch.17 serial data output pin Package Pin Number TEQFP208 TEQFP216 154 160 101, 181 105, 189 162, 189 168, 197 165, 193 173, 201 168, 199, 207 176, 207, 215 203 211 98 102 92 95 37, 90 37, 93 82, 93 84, 97 142 148 148 154 152 158 99, 179 103, 187 160, 187 166, 195 163, 191 171, 199 166, 197, 205 174, 205, 213 201 209 96 100 90 93 I2C ch.4 clock I/O pin 153 159 I2C ch.10 clock I/O pin 192 200 I2C ch.12 clock I/O pin 202 210 I2C ch.16 clock I/O pin 97 101 I2C ch.17 clock I/O pin 91 94 I2C ch.4 serial data I/O pin 152 158 I2C ch.10 serial data I/O pin 191 199 I2C ch.12 serial data I/O pin 201 209 I2C ch.16 serial data I/O pin 96 100 Document Number: 002-05682 Rev. *K Remark Page 56 of 222 S6J3200 Series Port Name Description SDA17 (MFS17_SDA) I2C ch.17 serial data I/O pin PPG0_TOUT0 Base timer 0 output pin PPG0_TOUT2 Base timer 1 output pin PPG1_TOUT0 Base timer 2 output pin PPG1_TOUT2 Base timer 3 output pin PPG2_TOUT0 Base timer 4 output pin PPG2_TOUT2 Base timer 5 output pin PPG3_TOUT0 Base timer 6 output pin PPG3_TOUT2 Base timer 7 output pin PPG4_TOUT0 Base timer 8 output pin PPG4_TOUT2 Base timer 9 output pin PPG5_TOUT0 Base timer 10 output pin PPG5_TOUT2 Base timer 11 output pin PPG6_TOUT0 Base timer 12 output pin PPG6_TOUT2 Base timer 13 output pin PPG7_TOUT0 Base timer 14 output pin PPG7_TOUT2 Base timer 15 output pin PPG8_TOUT0 Base timer 16 output pin PPG8_TOUT2 Base timer 17 output pin PPG9_TOUT0 Base timer 18 output pin PPG9_TOUT2 Base timer 19 output pin PPG10_TOUT0 Base timer 20 output pin PPG10_TOUT2 Base timer 21 output pin PPG11_TOUT0 Base timer 22 output pin PPG11_TOUT2 Base timer 23 output pin PPG0/1/2/3/4/5_TIN 1 Base timer 0/2/4/6/8/10 input pin Document Number: 002-05682 Rev. *K Package Pin Number TEQFP208 TEQFP216 90 39, 140, 161, 170, 199 40, 141, 162, 169, 200, 204 41,142,201, 205 143, 202, 206 144, 163, 203, 207 44, 147, 164, 174 45, 89, 148, 165, 175 32, 46, 149, 166, 176 93 39, 146, 167, 178, 207 35, 60, 67, 100, 134, 193 36, 70, 101, 137, 196 37, 63, 102, 138, 197 38, 139, 160, 198 40, 147, 168, 177, 208, 212 41,148,169, 209,213 44, 149, 170, 210, 214 45, 150, 171, 211, 215 46, 153, 172, 182 47, 91, 154, 173, 183 32, 48, 155, 174, 184 33, 49, 92, 156, 175, 185 50, 86, 93, 157, 176, 186 51, 94, 122, 158, 187 52, 74, 95, 123, 159, 188 53, 77, 96, 124, 160,189 56, 79, 97, 133, 194 57, 78, 98, 134, 195 58, 81, 99, 135, 196 59, 80, 100, 136, 197 60, 71, 101, 137, 198 61, 68, 102, 138, 199 31, 34, 70, 103, 139, 200 35, 62, 69, 104, 140, 201 36, 72, 105, 143, 204 37, 65, 106, 144, 205 38, 145, 166, 206 - 96 33, 47, 150, 167, 177 48, 84, 90, 151, 168, 178 49, 91, 118, 152, 179 50, 72, 92, 153, 180 51, 75, 154, 181 54, 77, 93, 127, 186 55, 76, 94, 128, 187 56, 79, 95, 129, 188 57, 78, 96, 130, 189 58, 69, 97, 131, 190 59, 66, 98, 132, 191 31, 34, 68, 99, 133, 192 Remark Page 57 of 222 S6J3200 Series Port Name PPG6/7/8/9/10/11_ TIN1 WOT PWM1M0 PWM1M1 PWM1M2 PWM1M3 PWM1M4 PWM1M5 PWM1P0 PWM1P1 PWM1P2 PWM1P3 PWM1P4 PWM1P5 PWM2M0 PWM2M1 PWM2M2 PWM2M3 PWM2M4 PWM2M5 PWM2P0 PWM2P1 PWM2P2 PWM2P3 PWM2P4 PWM2P5 Description Package Pin Number TEQFP208 TEQFP216 Base timer 12/14/16/18/20/22 input pin 161 167 RTC overflow output pin SMC ch.0 output pin SMC ch.1 output pin SMC ch.2 output pin SMC ch.3 output pin SMC ch.4 output pin SMC ch.5 output pin SMC ch.0 output pin SMC ch.1 output pin SMC ch.2 output pin SMC ch.3 output pin SMC ch.4 output pin SMC ch.5 output pin SMC ch.0 output pin SMC ch.1 output pin SMC ch.2 output pin SMC ch.3 output pin SMC ch.4 output pin SMC ch.5 output pin SMC ch.0 output pin SMC ch.1 output pin SMC ch.2 output pin SMC ch.3 output pin SMC ch.4 output pin SMC ch.5 output pin 161 128 132 138 142 148 152 127 131 137 141 147 151 130 134 140 144 150 154 129 133 139 143 149 153 39, 140, 161, 170, 199 40, 141, 162, 169, 200, 204 41, 142, 201, 205 143, 202, 206 144, 163, 203, 207 44, 147, 164, 174 45, 89, 148, 165, 175 32, 46, 149, 166, 176 167 134 138 144 148 154 158 133 137 143 147 153 157 136 140 146 150 156 160 135 139 145 149 155 159 OCU0_OTD0 Output compare 0 ch.0 output pin OCU0_OTD1 Output compare 0 ch.1 output pin OCU1_OTD0 Output compare 1 ch.0 output pin OCU1_OTD1 Output compare 1 ch.1 output pin OCU2_OTD0 Output compare 2 ch.0 output pin OCU2_OTD1 Output compare 2 ch.1 output pin OCU3_OTD0 Output compare 3 ch.0 output pin OCU3_OTD1 Output compare 3 ch.1 output pin OCU4_OTD0 Output compare 4 ch.0 output pin OCU4_OTD1 Output compare 4 ch.1 output pin OCU5_OTD0 Output compare 5 ch.0 output pin Document Number: 002-05682 Rev. *K 33, 47, 150, 167, 177 48, 84, 90, 151, 168, 178 49, 91, 118, 152, 179 Remark 39, 146, 167, 178, 207 40, 147, 168, 177, 208, 212 41, 148, 169, 209, 213 44, 149, 170, 210, 214 45, 150, 171, 211, 215 46, 153, 172, 182 47, 91, 154, 173, 183 32, 48, 155, 174, 184 33, 49, 92, 156, 175, 185 50, 86, 93, 157, 176, 186 51, 94, 122, 158, 187 Page 58 of 222 S6J3200 Series Port Name Description OCU5_OTD1 Output compare 5 ch.1 output pin OCU6_OTD0 Output compare 6 ch.0 output pin OCU6_OTD1 Output compare 6 ch.1 output pin OCU7_OTD0 Output compare 7 ch.0 output pin OCU7_OTD1 Output compare 7 ch.1 output pin OCU8_OTD0 Output compare 8 ch.0 output pin OCU8_OTD1 Output compare 8 ch.1 output pin OCU9_OTD0 Output compare 9 ch.0 output pin OCU9_OTD1 Output compare 9 ch.1 output pin OCU10_OTD0 Output compare 10 ch.0 output pin OCU10_OTD1 Output compare 10 ch.1 output pin OCU11_OTD0 Output compare 11 ch.0 output pin OCU11_OTD1 Output compare 11 ch.1 output pin ICU0_IN0 Input Capture 0 ch.0 input pin ICU0_IN1 Input Capture 0 ch.1 input pin ICU1_IN0 Input Capture 1 ch.0 input pin ICU1_IN1 Input Capture 1 ch.1 input pin ICU2_IN0 Input Capture 2 ch.0 input pin ICU2_IN1 Input Capture 2 ch.1 input pin ICU3_IN0 Input Capture 3 ch.0 input pin ICU3_IN1 Input Capture 3 ch.1 input pin ICU4_IN0 Input Capture 4 ch.0 input pin ICU4_IN1 Input Capture 4 ch.1 input pin ICU5_IN0 Input Capture 5 ch.0 input pin Document Number: 002-05682 Rev. *K Package Pin Number TEQFP208 TEQFP216 52, 74, 95, 50, 72, 92, 123, 159, 153, 180 188 53, 77, 96, 51, 75, 154, 124, 160, 181 189 54, 77, 93, 56, 79, 97, 127, 186 133, 194 55, 76, 94, 57, 78, 98, 128, 187 134, 195 56, 79, 95, 58, 81, 99, 129, 188 135, 196 57, 78, 96, 59, 80, 100, 130, 189 136, 197 58, 69, 97, 60, 71, 101, 131, 190 137, 198 59, 66, 98, 61, 68, 102, 132, 191 138, 199 31, 34, 70, 31, 34, 68, 103, 139, 99, 133, 192 200 35, 60, 67, 35, 62, 69, 100, 134, 104, 140, 193 201 36, 70, 101, 36, 72, 105, 137, 196 143, 204 37, 63, 102, 37, 65, 106, 138, 197 144, 205 38, 139, 38, 145, 166, 160, 198 206 39, 140, 39, 146, 167, 161, 170, 178, 207 199 40, 141, 40, 147, 168, 162, 169, 177, 208, 200, 204 212 41, 142, 41, 148, 169, 201, 205 209, 213 44, 149, 165, 143, 159, 170, 210, 202, 206 214 144, 163, 45, 150, 171, 203, 207 211, 215 44, 147, 46, 153, 172, 164, 174 182 45, 89, 148, 47, 91, 154, 165, 175 173, 183 32, 46, 149, 32, 48, 155, 166, 176 174, 184 33, 49, 92, 33, 47, 150, 156, 175, 167, 177 185 48, 84, 90, 50, 86, 93, 151, 168, 157, 176, 178 186 49, 91, 118, 51, 94, 122, 152, 179 158, 187 Remark Page 59 of 222 S6J3200 Series Port Name Description ICU5_IN1 Input Capture 5 ch.1 input pin ICU6_IN0 Input Capture 6 ch.0 input pin ICU6_IN1 Input Capture 6 ch.1 input pin ICU7_IN0 Input Capture 7 ch.0 input pin ICU7_IN1 Input Capture 7 ch.1 input pin ICU8_IN0 Input Capture 8 ch.0 input pin ICU8_IN1 Input Capture 8 ch.1 input pin ICU9_IN0 Input Capture 9 ch.0 input pin ICU9_IN1 Input Capture 9 ch.1 input pin ICU10_IN0 Input Capture 10 ch.0 input pin ICU10_IN1 Input Capture 10 ch.1 input pin ICU11_IN0 Input Capture 11 ch.0 input pin ICU11_IN1 Input Capture 11 ch.1 input pin SGA0 Sound generator ch.0 SGA output pin SGA1 Sound generator ch.1 SGA output pin SGA2 SGA3 SGO0 Sound generator ch.2 SGA output pin Sound generator ch.3 SGA output pin Sound generator ch.0 SGO output pin SGO1 Sound generator ch.1 SGO output pin SGO2 SGO3 AN0(AL0) AN1(AL1) AP0(AH0) AP1(AH1) BN0(BL0) BN1(BL1) BP0(BH0) BP1(BH1) I2S0_ECLK I2S1_ECLK I2S0_SCK I2S1_SCK I2S0_SD I2S1_SD I2S0_WS Sound generator ch.2 SGO output pin Sound generator ch.3 SGO output pin PCM PWM ch.0 output pin PCM PWM ch.1 output pin PCM PWM ch.0 output pin PCM PWM ch.1 output pin PCM PWM ch.0 output pin PCM PWM ch.1 output pin PCM PWM ch.0 output pin PCM PWM ch.1 output pin I2S external clock ch.0 input pin I2S external clock ch.1 input pin I2S continuous serial clock ch.0 pin I2S continuous serial clock ch.1 pin I2S serial data ch.0 pin I2S serial data ch.1 pin I2S word select ch.0 pin Document Number: 002-05682 Rev. *K Package Pin Number TEQFP208 TEQFP216 52, 74, 95, 50, 72, 92, 123, 159, 153, 180 188 53, 77, 96, 51, 75, 154, 124, 160, 181 189 54, 77, 93, 56, 79, 97, 127, 186 133, 194 55, 76, 94, 57, 78, 98, 128, 187 134, 195 56, 79, 95, 58, 81, 99, 129, 188 135, 196 57, 78, 96, 59, 80, 100, 130, 189 136, 197 58, 69, 97, 60, 71, 101, 131, 190 137, 198 59, 66, 98, 61, 68, 102, 132, 191 138, 199 31, 34, 70, 31, 34, 68, 103, 139, 99, 133, 192 200 35, 60, 67, 35, 62, 69, 100, 134, 104, 140, 193 201 36, 70, 101, 36, 72, 105, 137, 196 143, 204 37, 63, 102, 37, 65, 106, 138, 197 144, 205 38, 139, 38, 145, 166, 160, 198 206 90, 97, 164 93, 101, 172 91, 98, 165, 94, 102, 173, 205 213 100, 167 96, 104, 175 94, 118, 175 98, 122, 183 96, 163 92, 100, 171 92,99,166,2 95,103,174,2 06 14 93, 101, 168 97, 105, 176 95, 176 99, 123, 184 128, 175 134, 183 132, 179 138, 187 127, 174 133, 182 131, 178 137, 186 130, 177 136, 185 134, 181 140, 189 129, 176 135, 184 133, 180 139, 188 50 52 56 58 55 57 59 61 51 53 57 59 54 56 Remark Page 60 of 222 S6J3200 Series Port Name Description I2S1_WS I2S word select ch.1 pin Audio DAC external capacity connection output pin (L) Audio DAC external capacity connection output pin (R) Audio DAC output pin (L) Audio DAC output pin (R) Free-run timer ch.0/1/2/3 clock input pin Free-run timer ch.4/5/6/7 clock input pin C_L C_R DAC_L DAC_R FRT0/1/2/3_TEXT FRT4/5/6/7_TEXT FRT8/9/10/11_TEX T TIN0 TIN1 TIN2 TIN3 TIN16 TIN17 TIN18 TIN19 TIN32 TIN33 TIN34 TIN35 TIN48 TIN49 TOT0 TOT1 TOT2 TOT3 TOT16 TOT17 TOT18 TOT19 TOT32 TOT33 TOT34 TOT35 AIN8 AIN9 BIN8 BIN9 ZIN8 ZIN9 RXD0 RXD1 RXD2 RXD3 TXD0 TXD1 TXD2 Package Pin Number TEQFP208 TEQFP216 58 60 8 8 4 4 7 3 160 166 7 3 166 174 Free-run timer ch.4/5/6/7 clock input pin 95 99 Reload timer ch.0 event input pin Reload timer ch.1 event input pin Reload timer ch.2 event input pin Reload timer ch.3 event input pin Reload timer ch.16 event input pin Reload timer ch.17 event input pin Reload timer ch.18 event input pin Reload timer ch.19 event input pin Reload timer ch.32 event input pin Reload timer ch.33 event input pin Reload timer ch.34 event input pin Reload timer ch.35 event input pin Reload timer ch.48 event input pin Reload timer ch.49 event input pin Reload timer ch.0 output pin Reload timer ch.1 output pin Reload timer ch.2 output pin Reload timer ch.3 output pin Reload timer ch.16 output pin Reload timer ch.17 output pin Reload timer ch.18 output pin Reload timer ch.19 output pin Reload timer ch.32 output pin Reload timer ch.33 output pin Reload timer ch.34 output pin Reload timer ch.35 output pin Up/Down counter AIN input pin ch.8 Up/Down counter AIN input pin ch.9 Up/Down counter BIN input pin ch.8 Up/Down counter BIN input pin ch.9 Up/Down counter ZIN input pin ch.8 Up/Down counter ZIN input pin ch.9 Ethernet pin Ethernet pin Ethernet pin Ethernet pin Ethernet pin Ethernet pin Ethernet pin 35 37, 93 39, 94 41, 95 100 45, 102 47, 162 49 51, 164 55, 166 57, 168 59 159 89 34, 96 36, 97 38, 98 40, 99 101 44, 160 46, 161 48 50, 163 54, 165 56,167 58, 118 190 93, 193 90, 191 94, 196 91, 192 95, 197 48 49 50 51 44 45 46 35, 96 37, 97 39, 98 41, 99 45, 104 47, 106 49, 168 51, 170 53, 172 57, 174 59, 176 61, 123 165 91 34, 100 36, 101 38, 102 40, 103 44, 105 46, 166 48, 167 50, 169 52, 171 56, 173 58, 175 60, 122 92, 198 97, 201 93, 199 98, 204 94, 200 99, 205 50 51 52 53 46 47 48 Document Number: 002-05682 Rev. *K Remark Page 61 of 222 S6J3200 Series Package Pin Number TEQFP208 TEQFP216 47 49 58 44, 60 84 45, 86 56 58 57 59 55 57 60 62 41 41 54 56 31 31 32 32 84 86 82 84 83 85 Port Name Description TXD3 COL CRS RXER RXDV RXCLK TXER TXEN TXCLK MDC MDIO MLBCLK MLBDAT MLBSIG Ethernet pin Ethernet pin Ethernet pin Ethernet pin Ethernet pin Ethernet pin Ethernet pin Ethernet pin Ethernet pin Ethernet pin Ethernet pin MediaLB pin MediaLB pin MediaLB pin TxCLK- LVDS clock output pin 21 21 TxCLK+ LVDS clock output pin 20 20 TxDOUT0- LVDS data output pin 25 25 TxDOUT0+ LVDS data output pin 24 24 TxDOUT1- LVDS data output pin 23 23 TxDOUT1+ LVDS data output pin 22 22 TxDOUT2- LVDS data output pin 19 19 TxDOUT2+ LVDS data output pin 18 18 TxDOUT3- LVDS data output pin 17 17 TxDOUT3+ LVDS data output pin 16 16 G_SCLK0 G_SDATA0_0 G_SDATA0_1 G_SDATA0_2 G_SDATA0_3 G_SDATA1_0 G_SDATA1_1 G_SDATA1_2 G_SDATA1_3 G_SSEL0 Graphic HS-SPI clock output pin Graphic HS-SPI0 data 0 pin Graphic HS-SPI0 data 1 pin Graphic HS-SPI0 data 2 pin Graphic HS-SPI0 data 3 pin Graphic HS-SPI1 data 0 pin Graphic HS-SPI1 data 1 pin Graphic HS-SPI1 data 2 pin Graphic HS-SPI1 data 3 pin Graphic HS-SPI select 0 output pin 72 75 77 76 79 66 68 67 70 78 74 77 79 78 81 68 70 69 72 80 Document Number: 002-05682 Rev. *K Remark Described as TXOUT4M in FPD-Link Converter Described as TXOUT4P in FPD-Link Converter Described as TXOUT0M in FPD-Link Converter Described as TXOUT0P in FPD-Link Converter Described as TXOUT1M in FPD-Link Converter Described as TXOUT1P in FPD-Link Converter Described as TXOUT2M in FPD-Link Converter Described as TXOUT2P in FPD-Link Converter Described as TXOUT3M in FPD-Link Converter Described as TXOUT3P in FPD-Link Converter Page 62 of 222 S6J3200 Series Port Name Description G_SSEL1 G_CK_1 G_CS#1_1 G_CS#2_1 G_DQ0_1 G_DQ1_1 G_DQ2_1 G_DQ3_1 G_DQ4_1 G_DQ5_1 G_DQ6_1 G_DQ7_1 G_RWDS_1 G_CK_2 G_CS#1_2 G_CS#2_2 G_DQ0_2 G_DQ1_2 G_DQ2_2 G_DQ3_2 G_DQ4_2 G_DQ5_2 G_DQ6_2 G_DQ7_2 G_RWDS_2 M_SCLK0 M_SDATA0_0 M_SDATA0_1 M_SDATA0_2 M_SDATA0_3 M_SDATA1_0 M_SDATA1_1 M_SDATA1_2 M_SDATA1_3 M_SSEL0 M_SSEL1 M_CK_0 M_CS#1_0 M_CS#2_0 M_DQ0_0 M_DQ1_0 M_DQ2_0 M_DQ3_0 M_DQ4_0 M_DQ5_0 M_DQ6_0 M_DQ7_0 M_RWDS_0 Graphic HS-SPI select 1 output pin Hyper Bus 1 clock output pin Hyper Bus 1 select 1 output pin Hyper Bus 1 select 2 output pin Hyper Bus 1 Data 0 pin Hyper Bus 1 Data 1 pin Hyper Bus 1 Data 2 pin Hyper Bus 1 Data 3 pin Hyper Bus 1 Data 4 pin Hyper Bus 1 Data 5 pin Hyper Bus 1 Data 6 pin Hyper Bus 1 Data 7 pin Hyper Bus 1 RWDS pin #699 Hyper Bus 2 clock output pin Hyper Bus 2 select 1 output pin Hyper Bus 2 select 2 output pin Hyper Bus 2 Data 0 pin Hyper Bus 2 Data 1 pin Hyper Bus 2 Data 2 pin Hyper Bus 2 Data 3 pin Hyper Bus 2 Data 4 pin Hyper Bus 2 Data 5 pin Hyper Bus 2 Data 6 pin Hyper Bus 2 Data 7 pin Hyper Bus 2 RWDS pin MCU HS-SPI clock output pin MCU HS-SPI0 data 0 pin MCU HS-SPI0 data 1 pin MCU HS-SPI0 data 2 pin MCU HS-SPI0 data 3 pin MCU HS-SPI1 data 0 pin MCU HS-SPI1 data 1 pin MCU HS-SPI1 data 2 pin MCU HS-SPI1 data 3 pin MCU HS-SPI select 0 output pin MCU HS-SPI select 1 output pin MCU Hyper Bus clock output pin MCU Hyper Bus select 1 output pin MCU Hyper Bus select 2 output pin MCU Hyper Bus Data 0 pin MCU Hyper Bus Data 1 pin MCU Hyper Bus Data 2 pin MCU Hyper Bus Data 3 pin MCU Hyper Bus Data 4 pin MCU Hyper Bus Data 5 pin MCU Hyper Bus Data 6 pin MCU Hyper Bus Data 7 pin MCU Hyper Bus RWDS pin #699 LCDC Segment(Duty) Common Output Pin COM0 Document Number: 002-05682 Rev. *K Package Pin Number TEQFP208 TEQFP216 69 71 63 65 70 72 75 77 69 71 68 70 67 69 66 68 76 78 77 79 78 80 79 81 72 74 44 46 49 51 51 53 48 50 47 49 46 48 45 47 54 56 55 57 56 58 57 59 50 52 63 65 66 68 68 70 67 69 70 72 75 77 77 79 76 78 79 81 69 71 78 80 63 65 70 72 75 77 69 71 68 70 67 69 66 68 76 78 77 79 78 80 79 81 72 74 207 Remark 215 Page 63 of 222 S6J3200 Series Port Name Description SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 V0 V1 V2 V3 DSP0_CLK DSP0_CLKDSP0_CLK+ DSP0_CTRL0 DSP0_CTRL1 LCDC Segment(Duty) Common Output Pin LCDC Segment(Duty) Common Output Pin LCDC Segment(Duty) Common Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty) Output Pin LCDC Segment(Duty/Static) Output Pin LCDC Segment(Duty/Static) Output Pin LCDC Segment(Duty/Static) Output Pin LCDC Segment(Duty/Static) Output Pin LCDC Segment(Duty/Static) Output Pin LCDC Segment(Duty/Static) Output Pin LCDC Segment(Duty/Static) Output Pin LCDC Segment(Duty/Static) Output Pin LCDC Segment(Duty/Static) Output Pin LCDC Reference Voltage V0 Input Pin LCDC Reference Voltage V1 Input Pin LCDC Reference Voltage V2 Input Pin LCDC Reference Voltage V3 Input Pin Display 0 Clock output pin Display 0 RSDS Clock output pin Display 0 RSDS Clock output pin Display 0 Control output pin Display 0 Control output pin DSP0_CTRL2 Display 0 Control output pin DSP0_CTRL3 DSP0_CTRL4 Display 0 Control output pin Display 0 Control output pin COM1 COM2 COM3 Document Number: 002-05682 Rev. *K Package Pin Number TEQFP208 TEQFP216 206 214 205 213 204 212 203 202 201 200 199 198 197 196 193 192 191 190 189 188 187 186 181 180 179 178 177 176 175 174 168 167 166 165 164 163 162 161 160 159 32, 58 33 32 59, 60, 196 31, 60, 197 33, 57, 60, 82, 198 83, 199 84, 200 211 210 209 208 207 206 205 204 201 200 199 198 197 196 195 194 189 188 187 186 185 184 183 182 176 175 174 173 172 171 170 169 168 167 166 165 32, 60 33 32 61, 62, 204 31, 62, 205 33, 59, 62, 84, 206 85, 207 86, 208 Remark Page 64 of 222 S6J3200 Series Port Name Description DSP0_CTRL5 DSP0_CTRL6 DSP0_CTRL7 DSP0_CTRL8 DSP0_CTRL9 DSP0_CTRL10 DSP0_CTRL11 DSP0_DATA0_0 DSP0_DATA0_1 DSP0_DATA0_2 DSP0_DATA0_3 DSP0_DATA0_4 DSP0_DATA0_5 DSP0_DATA0_6 DSP0_DATA0_7 DSP0_DATA0_8 DSP0_DATA0_9 DSP0_DATA0_10 DSP0_DATA0_11 DSP0_DATA1_0 DSP0_DATA1_1 DSP0_DATA1_2 DSP0_DATA1_3 DSP0_DATA1_4 DSP0_DATA1_5 DSP0_DATA1_6 DSP0_DATA1_7 DSP0_DATA1_8 DSP0_DATA1_9 DSP0_DATA1_10 DSP0_DATA1_11 DSP0_DATA_D0DSP0_DATA_D0+ DSP0_DATA_D1DSP0_DATA_D1+ DSP0_DATA_D2DSP0_DATA_D2+ DSP0_DATA_D3DSP0_DATA_D3+ DSP0_DATA_D4DSP0_DATA_D4+ DSP0_DATA_D5DSP0_DATA_D5+ DSP0_DATA_D6DSP0_DATA_D6+ DSP0_DATA_D7DSP0_DATA_D7+ DSP0_DATA_D8DSP0_DATA_D8+ Display 0 Control output pin Display 0 Control output pin Display 0 Control output pin Display 0 Control output pin Display 0 Control output pin Display 0 Control output pin Display 0 Control output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Document Number: 002-05682 Rev. *K Package Pin Number TEQFP208 TEQFP216 201 209 202 210 203 211 204 212 205 213 206 214 207 215 34 34 36 36 38 38 40 40 31 31, 44 44 46 46 48 48 50 50 52 54 56 56 58 32, 58 32, 60 35 35 37 37 39 39 41 41 33 33, 45 45 47 47 49 49 51 51 53 55 57 31, 57 31, 59 33, 59 33, 61 35 35 34 34 37 37 36 36 39 39 38 38 41 41 40 40 45 44 45 47 44 46 47 49 46 48 49 51 48 50 51 53 50 52 Remark Page 65 of 222 S6J3200 Series Port Name Description DSP0_DATA_D9DSP0_DATA_D9+ DSP0_DATA_D10DSP0_DATA_D10+ DSP0_DATA_D11DSP0_DATA_D11+ DSP1_CLK DSP1_CTRL0 DSP1_CTRL1 DSP1_CTRL2 DSP1_DATA0_0 DSP1_DATA0_1 DSP1_DATA0_2 DSP1_DATA0_3 DSP1_DATA0_4 DSP1_DATA0_5 DSP1_DATA0_6 DSP1_DATA0_7 DSP1_DATA0_8 DSP1_DATA0_9 DSP1_DATA0_10 DSP1_DATA0_11 DSP1_DATA1_0 DSP1_DATA1_1 DSP1_DATA1_2 DSP1_DATA1_3 DSP1_DATA1_4 DSP1_DATA1_5 DSP1_DATA1_6 DSP1_DATA1_7 DSP1_DATA1_8 DSP1_DATA1_9 DSP1_DATA1_10 DSP1_DATA1_11 CAP0_CLK CAP0_DATA0 CAP0_DATA1 CAP0_DATA2 CAP0_DATA3 CAP0_DATA4 CAP0_DATA5 CAP0_DATA6 CAP0_DATA7 CAP0_DATA8 CAP0_DATA9 CAP0_DATA10 CAP0_DATA11 CAP0_DATA12 CAP0_DATA13 Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 0 RSDS Data output pin Display 1 Clock output pin Display 1 Control output pin Display 1 Control output pin Display 1 Control output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Display 1 Data output pin Video Capture 0 Clock input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Document Number: 002-05682 Rev. *K Package Pin Number TEQFP208 TEQFP216 55 57 54 56 57 59 56 58 59 61 58 60 199, 204 207, 212 200, 207 208, 215 201, 206 209, 214 198, 205 206, 213 203 211 201 209 199 207 197 205 193 201 191 199 189 197 187 195 181 189 179 187 177 185 175 183 202 210 200 208 198 206 196 204 192 200 190 198 188 196 186 194 180 188 178 186 176 184 174 182 59 61 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40 41 41 44 44, 46 45 45, 47 44, 46 46, 48 Remark Page 66 of 222 S6J3200 Series Port Name Description CAP0_DATA14 CAP0_DATA15 CAP0_DATA16 CAP0_DATA17 CAP0_DATA18 CAP0_DATA19 CAP0_DATA20 CAP0_DATA21 CAP0_DATA22 CAP0_DATA23 CAP0_DATA24 CAP0_DATA25 CAP0_DATA32 CAP0_DATA33 CAP0_DATA34 CAP0_DATA35 Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Video Capture 0 Data input pin Indicator PWM output pin 0 It can also obtained from INDICATOR0_1) Indicator PWM output pin (It can also obtained from INDICATOR0_0) General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port INDICATOR0_0 INDICATOR0_1 P0_00 P0_01 P0_02 P0_03 P0_04 P0_05 P0_06 P0_07 P0_08 P0_09 P0_10 P0_11 P0_12 P0_13 P0_14 P0_15 P0_16 P0_17 P0_18 P0_19 P0_26 P0_27 P0_28 P0_30 P0_31 P1_00 P1_01 P1_02 Document Number: 002-05682 Rev. *K Package Pin Number TEQFP208 TEQFP216 45, 47 47, 49 46, 48 48, 50 47 49 48 50 49 51 50 52 51 53 54 56 55 57 56 58 82 84 83 85 56, 57 58, 59 58 60 60 62 57 59 92 95 170 178 40 41 44 45 46 47 48 49 50 51 54 55 56 57 58 59 32 33 82 83 84 72 75 77 76 79 40 41 44 45 46 47 48 49 50 51 52 53 56 57 58 59 60 61 32 33 84 85 86 74 77 79 78 81 Remark Page 67 of 222 S6J3200 Series Port Name Description P1_03 P1_04 P1_05 P1_06 P1_07 P1_08 P1_09 P2_16 P2_17 P2_19 P2_22 P2_24 P2_25 P2_26 P2_27 P2_28 P2_29 P2_30 P2_31 P3_00 P3_01 P3_02 P3_03 P3_04 P3_05 P3_06 P3_07 P3_08 P3_09 P3_10 P3_11 P3_12 P3_13 P3_14 P3_15 P3_16 P3_17 P3_18 P3_19 P3_20 P3_21 P3_22 P3_23 P3_24 P3_25 P3_26 P3_27 P3_28 P3_29 General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port Document Number: 002-05682 Rev. *K Package Pin Number TEQFP208 TEQFP216 78 80 69 71 66 68 68 70 67 69 70 72 63 65 170 178 169 177 159 165 89 91 92 90 93 91 94 92 95 96 93 97 94 98 95 99 96 100 97 101 98 102 99 103 100 104 101 105 102 106 160 166 161 167 162 168 169 170 163 171 164 172 165 173 166 174 167 175 168 176 118 122 123 124 127 133 128 134 129 135 130 136 131 137 132 138 133 139 134 140 137 143 Remark Page 68 of 222 S6J3200 Series Port Name Description P3_30 P3_31 P4_00 P4_01 P4_02 P4_03 P4_04 P4_05 P4_06 P4_07 P4_08 P4_09 P4_10 P4_11 P4_12 P4_25 P4_26 P4_27 P4_28 P4_29 P4_30 P4_31 P5_00 P5_01 P5_02 P5_03 P5_04 P5_05 P5_06 P5_07 P5_08 P5_09 P5_10 P5_11 P5_12 P5_13 P5_14 P5_15 P5_16 P5_17 P5_18 P5_19 P5_20 P5_21 P5_22 P5_27 P5_28 P5_29 P5_30 General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port Document Number: 002-05682 Rev. *K Package Pin Number TEQFP208 TEQFP216 138 144 139 145 140 146 141 147 142 148 143 149 144 150 147 153 148 154 149 155 150 156 151 157 152 158 153 159 154 160 204 212 205 213 206 214 207 215 174 182 175 183 176 184 177 185 178 186 179 187 180 188 181 189 186 194 187 195 188 196 189 197 190 198 191 199 192 200 193 201 196 204 197 205 198 206 199 207 200 208 201 209 202 210 203 211 31 31 60 62 34 34 35 35 36 36 37 37 Remark Page 69 of 222 S6J3200 Series Port Name Description P5_31 P6_00 General-Purpose I/O port General-Purpose I/O port EP 6.2 Exposed Pad Package Pin Number TEQFP208 TEQFP216 38 38 39 39 - - Remark Connect the exposed pad to ground. The exposed pad is isolated with epoxy to the substrate of the die, making it an excellent path to remove heat from the IC. Remark Notes: - The port description list shows the port function of description, which is mounted and supported on the product. The function, which is not described in this table, is not supported and assured. - See the function list of the product as well. 7. Precautions and Handling Devices 7.1 Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 7.1.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Document Number: 002-05682 Rev. *K Page 70 of 222 S6J3200 Series 7.1.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 C and 30 C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125 C/24 h Document Number: 002-05682 Rev. *K Page 71 of 222 S6J3200 Series Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 M). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 7.1.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-05682 Rev. *K Page 72 of 222 S6J3200 Series 7.2 Handling Devices For Latch-Up Prevention The latch-up phenomenon may occur on a CMOS IC in the following cases: the voltage applied to an input or output pin is higher than VCC or lower than VSS; or the voltage applied between a VCC pin and a VSS pin exceeds the rating. A latch-up causes a rapid increase in the power supply current, possibly resulting in thermal damage to an element. When using the device, take sufficient care not to exceed the maximum rating. About Handling Unused Pins Leaving unused input pins open may cause permanent damage from a malfunction or latch-up. Take measures for unused pins, such as pulling up or pulling down the voltage with resistors of 2 k or higher. If there are any unused input/output pins, set them to the output state and then open them, or set them to the input state and handle them in the same way as input pins. About Power Supply Pins If the device has multiple VCC and VSS pins, the device is designed in such a way that the pins that should be at the same potential are connected to each other inside the device to prevent malfunctions such as latch-up. However, to reduce unwanted emissions, prevent malfunctions of strobe signals caused by an increase of the ground level, and observe standards on total output current, be sure to connect all the VCC and VSS pins to the power source and ground externally. Also handle all the VSS power supply pins in this way as shown in the following diagram. If there are multiple VCC or VSS systems, the device does not operate normally even within the guaranteed operating range. Figure 7-1 Pin Assignment In addition, consider connecting with low impedance from the power supply source to the VCC and VSS of this device. We recommend connecting a ceramic capacitor as a bypass capacitor between VCC and VSS, near this device. About the Crystal Oscillation Circuit Noise entering the X0 or X1 pin may cause a malfunction. Design the printed circuit board in such a way that the X0 and X1 pins, the crystal oscillator (or ceramic resonator), and a bypass capacitor to ground are located very close to the device. We recommend that the printed circuit board artwork have the X0 and X1 pins enclosed by ground. About the Mode Pin (MD) Use mode pin MD by directly connecting it to a VCC or VSS pin. To prevent noise from causing the device to accidentally enter test mode, reduce the pattern length between each mode pin and a VCC or VSS pin on the printed circuit board, and connect them with low impedance. Document Number: 002-05682 Rev. *K Page 73 of 222 S6J3200 Series Point to Note during PLL Clock Operation While a PLL clock is selected, if the oscillator breaks off or input stops, the PLL clock may continue operating with the free running frequency of the internal self-oscillator circuit. This operation is outside of the guaranteed range. Power Supply Pin Processing of an A/D Converter Even when no A/D converter is used, establish a connection such that AVCC=AVRH=VCC and AVSS=VSS. Points to Note about Using External Clocks External clocks are not supported. External direct clock input cannot be used. Power-on Sequence of the Power Supply Analog Inputs of an A/D Converter Be sure to turn on the digital power supply (VCC) before the application of the power supplies (AVCC, AVRH, and AVSS) and analog inputs (AN0 to AN63) of an A/D converter. At the power-off time, turn off the power supplies and analog inputs of the A/D converter, and then turn off the digital power supply (VCC). Perform these power-on and power-off operations without AVRH exceeding AVCC. Even when using a pin shared with an analog input as an input port, do not allow the input voltage to exceed AVCC. (Turning on or off the analog supply voltage and digital supply voltage simultaneously is not a problem.) Method to Switch off VCC12 during Power-off Sequence For revision M, P During power-off sequence, it is necessary to switch off VCC12 by driving PSC1 pin low by entering PSS mode (power domain 2 off). If VCC12 needs to be switched off by other means, RSTX needs to be asserted before switching off VCC12 to inactivate the operation of VCC12 supplied domain below the operation assurance range. For except revision M, P During power-off sequence, it is necessary to switch off VCC12 by driving PSC1 pin low by entering PSS mode (power domain 2 off). If VCC12 needs to be switched off by other means, VCC5 needs ramping down to occur LVDH1 reset before switching off VCC12 to inactivate the operation of VCC12 supplied domain below the operation assurance range. About C Pin Processing This device has a built-in voltage step-down circuit. Be sure to connect a capacitor to the C pin (refer to the pin assignment) for internal stabilization of the device. For the standard values, see "Recommended operating conditions" in the latest data sheet. Precautions on Designing a Mounting Substrate Measures against heat generation from the package must be taken for the mounting substrate to observe the absolute maximum rating (operating temperature). Design a mounting substrate with 4 or more layers. Connect the back of the package stage and the substrate pad with solder paste. Arrange thermal via holes on the substrate pad. Notes on Writing to a Register Containing a Status Flag In writing to a register containing a status flag (particularly an interrupt request flag, etc.) to control a function, it is important to take care not to accidentally clear the status flag. Therefore, before the write operation, configure the status bit such that the flag is not cleared, and then set the control bit to the desired value. Especially for control bits configured as a set of multiple bits, bit instructions cannot be used (bit instructions have only 1-bit access). In such cases, byte, half-word, or word access is used to write to the control bits and a status flag simultaneously. However, at this time, be careful not to accidentally clear bits other than the intended ones (the status flag bit in this case). Note: Bit instructions take this point into account for registers that support bit-band units, so it does not need to be a concern. You need to take care when using bit instructions for registers that do not support bit-band units. Document Number: 002-05682 Rev. *K Page 74 of 222 S6J3200 Series 8. Electric Characteristics 8.1 Absolute Maximum Rating Parameter Power supply voltage*1, *2 Analog supply voltage*1, *2 Analog reference voltage*1 Input voltage*1 Input voltage for shared ADC*1 Output voltage*1 Maximum clamp current Total maximum clamp current "L"-level maximum output current*3 Document Number: 002-05682 Rev. *K Symbol Rating Unit Remarks Min Max VCC5 VCC53 VCC3 DVCC VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS+6.0 VSS+6.0 VSS+4.0 VSS+6.0 V V V V VCC12 VSS-0.3 VSS+1.8 V AVCC5 AVCC3_DAC VCC3_LVDS_Tx AVCC3_LVDS_P LL AVRH5 VI1 VI2 VI3 VIE VSS-0.3 VSS-0.3 VSS-0.3 VSS+6.0 VSS+4.0 VSS+4.0 V V V VCC53VCC5 VCC3VCC5 DVCCVCC5 VCC12 VCC53 VCC12 VCC3 VCC12 DVCC VCC12 AVCC5 AVCC5VCC5 for DAC for LVDS VSS-0.3 VSS+4.0 V for LVDS PLL VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 V V V V V AVRH5AVCC5 5-V pins not shared SMC 5-V pins shared SMC 3-V pins 5-V/3-V pins VIA1 VSS-0.3 V 5-V pins not shared SMC VIA2 VSS-0.3 V 5-V pins shared SMC VO1 VO2 VO3 VO4 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 - VSS+6.0 VCC5+0.3 DVCC+0.3 VCC3+0.3 VCC53+0.3 VCC5+0.3 AVCC5+0.3 DVCC+0.3 AVCC5+0.3 VCC5+0.3 DVCC+0.3 VCC3+0.3 VCC53+0.3 4 20 3.5 7 10 16 30 40 8 11 |ICLAMP| |ICLAMP | IOL1 IOL2 IOL3 IOL4 IOL5 IOL6 IOL7 IOL8 V V V V mA mA mA mA mA mA mA mA mA mA 5-V pins not shared SMC*13 5-V pins shared SMC*13 3-V pins 5-V/3-V pins *12, *A *12, *A When setting is 1 mA*6, *7, *8 When setting is 2 mA*6, *7, *8, *9 When setting is 5 mA*6, *7, *8, *9 When setting is 10 mA*9 When setting is 20 mA*9 When setting is 30 mA*7 When setting is 3 mA *10 When setting is 6 mA *11 Page 75 of 222 S6J3200 Series Parameter "L"-level average output current*4 "L"-level total output current*5 "H"-level maximum output current*3 "H"-level average output current*4 "H"-level total output current*5 Power dissipation and Operation temperature Case 1 Power dissipation and Operation temperature Case 2 Power dissipation and Operation temperature Case 3 Power dissipation and Operation temperature Case 4 Power dissipation and Operation temperature Case 5 Document Number: 002-05682 Rev. *K Symbol IOLAV1 IOLAV2 IOLAV3 IOLAV4 IOLAV5 IOLAV6 IOLAV7 IOLAV8 IOL1 IOL2 IOL3 IOL4 IOH1 IOH2 IOH3 IOH4 IOH5 IOH6 IOH8 IOHAV1 IOHAV2 IOHAV3 IOHAV4 IOHAV5 IOHAV6 IOHAV8 IOH1 IOH2 IOH3 IOH4 PD TA TC PD TA TC PD TA TC PD TA TC PD TA TC Rating Min Max -40 -40 -40 -40 -40 -40 -40 -40 -40 -40 1 2 5 10 20 30 3 6 50 250 50 50 -3.5 -7 -10 -16 -30 -40 -11 -1 -2 -5 -10 -20 -30 -6 -50 -250 -50 -50 3300 +97 +144 3150 +100 +144 3000 +102 +144 2900 +105 +144 2800 +105 +144 Unit Remarks mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW oC oC mW oC oC mW oC oC mW oC oC mW oC oC When setting is 1 mA*6, *7, *8 When setting is 2 mA*6, *7, *8, *9 When setting is 5 mA*6, *7, *8, *9 When setting is 10 mA*9 When setting is 20 mA*9 When setting is 30 mA*7 When setting is 3 mA *10 When setting is 6 mA *11 *6, *10 *7 *8 *9, *11 When setting is 1 mA*6, *7, *8 When setting is 2 mA*6, *7, *8, *9 When setting is 5 mA*6, *7, *8, *9 When setting is 10 mA*9 When setting is 20 mA*9 When setting is 30 mA*7 When setting is 6 mA *11 When setting is 1 mA*6, *7, *8 When setting is 2 mA*6, *7, *8, *9 When setting is 5 mA*6, *7, *8, *9 When setting is 10 mA*9 When setting is 20 mA*9 When setting is 30 mA*7 When setting is 6 mA *11 *6, *10 *7 *8 *9, *11 Both should be satisfied. Both should be satisfied. Both should be satisfied. Both should be satisfied. Both should be satisfied. Page 76 of 222 S6J3200 Series Parameter System Thermal Resistance Symbol Theta j-a Rating Min - Max 16 Unit oC/W o Theta j-c 7.5 C/W Package Thermal Resistance oC Tstg -55 +150 Storage temperature *1: These parameters are based on the condition that VSS=AVSS=DVSS=0.0 V. Remarks The minimum value depends on the system specification of heat radiation. The described value is estimated under the condition which is specified at Operation Assurance Condition. - - *2: Take care that DVCC, AVCC5 do not exceed VCC5 at, for example, the power-on time. *3: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *4: The average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 10 ms period. The average value is the operation current x the operation ratio. *5: The total output current is defined as the maximum current value flowing through all of corresponding pins. *6: Output of 5-V pins. *7: Output of SMC pins. *8: Output of 5-V/3-V pins. *9: Output of 3-V pins. *10: Output of I2C. *11: Output of Media LB pins *12: VI or VO should never exceed the specified ratings. However, if the maximum current to/from an input is limited by a suitable external resistor, the ICLAMP rating supersedes the VI rating. *13: Take care that the output voltage does not exceed AVCC5 + 0.3 V because ADC Analog input pins (AN0-49) are internally connected to the analog elements. *A: Relevant pins: All general-purpose ports and analog input pins * * * * * * * * * Corresponding pins: all general-purpose ports Use within the operation assurance condition (See 8.2. Operation Assurance ). Use at DC voltage (current). The +B signal should always be applied by connecting a limiting resistor between the +B signal and the microcontroller. The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values at any time regardless of instantaneously or constantly when the +B signal is input. Note that when the microcontroller drive current is low, such as in the low power consumption modes, the + B input potential can increase the potential at the VCC pin via a protective diode, possibly affecting other devices. Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the power is supplied through the pin, the microcontroller may operate incompletely. Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not function in the power supply voltage. Do not leave + B input pins open. Document Number: 002-05682 Rev. *K Page 77 of 222 S6J3200 Series Example of a recommended circuit S6J3200 series WARNING: - Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: 002-05682 Rev. *K Page 78 of 222 S6J3200 Series 8.2 Operation Assurance Condition Symbol Parameter Value VCC5 Corresponding Ground VSS VCC53*1 VSS DVCC AVCC5 VCC3 DVSS AVSS VSS VCC12 VSS AVCC3_DAC VCC3_LVDS_Tx AVCC3_LVDS_PLL VCC5 VCC53*1 DVCC AVCC5 VCC3 AVCC3_DAC VCC3_LVDS_Tx AVCC3_LVDS_PLL AVSS3_DAC VSS3_LVDS_Tx AVSS3_LVDS_PLL VSS VSS DVSS AVSS VSS AVSS3_DAC VSS3_LVDS_Tx AVSS3_LVDS_PLL Smoothing capacitor*3 CS - Operating temperature TA TC - Power Supply Supply voltage Min Max 4.5 4.5 3.0 4.5 4.5 3.0 1.15*2 1.1 3.0 3.0 3.0 3.5 2.7 3.5 3.5 2.7 2.7 2.7 2.7 5.5 5.5 3.6 5.5 5.5 3.6 1.3 1.3 3.6 3.6 3.6 5.5 5.5 5.5 5.5 3.6 3.6 3.6 3.6 4.7 -40 -40 Unit V V V V V V V V V V V V V V V V V V V F +105 +144 oC oC Remarks Specified electric characteristics are assured in this range. Specified electric characteristics are NOT assured in this range. Tolerance of up to 40% See the notes below. Notes: - *1. VCC53 should be connected with either VCC5 or VCC3 on your system board because LVD does not support VCC53 itself. - - - *2. The value is only applied to the product series with revision digit A. - Note that power supplies inside "[ ]" can be turned on in arbitrary order. *3. For the connections of smoothing capacitor CS, see the following diagram. Power supply sequence is recommended as VCC5 [DVCC or AVCC5 or VCC3 or AVCC3] VCC12 [AVCC3_LVDS_PLL or VCC3_LVDS_TX] VCC5 [AVCC5 or DVCC] [VCC12 or VCC3 or AVCC3_DAC] [AVCC3_LVDS_PLL or VCC3_LVDS_TX] VCC5 AVCC5 [DVCC or VCC12 or VCC3 or AVCC3_DAC] [AVCC3_LVDS_PLL or VCC3_LVDS_TX] C Pin Connection Diagram C CS Document Number: 002-05682 Rev. *K VSS DVSS AVSS Page 79 of 222 S6J3200 Series WARNING: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. 2. Any use of semiconductor devices will be under their recommended operating condition. 3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. 4. No warranty is made with respect to any use, operating conditions or combinations not represented on this datasheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Notes: - TA: Ambient temperature (JEDEC) - TC: Case temperature (JEDEC), the maximum measured temperature of package case top. - - Both rating of TA and TC should simultaneously be satisfied as maximum operation temperature. The following condition should be satisfied in order to facilitate heat dissipation. 1. Four or more layers PCB should be used. 2. The area of PCB should be 114.3 mm x 76.2 mm or more, and the thickness should be 1.6 mm or more. (JEDEC standard) 3. One layer of middle layers at least should be used for dedicated layer to radiate heat with residual copper rate 90% or more. The layer can be used for system ground. 4. 35% or more of the die stage area which is exposed at back surface of package should be soldered to a part of 1st layer. 5. The part of 1st layer should be connected to the dedicated heat radiation layer with more than 10 thermal via holes. Figure 8-1: Example Thermal Via Holes on PCB. Notes: - Figure 8-1 is a schematic diagram showing PCB in section. - Figure 8-2, Figure 8-3, and Figure 8-4 in the following pages are recommended land patterns for each package series. Thermal via holes should closely be placed and aligned with lands. - When thermal via holes cannot be with lands, the followings are recommended as represented by Figure 8-5 which is an example for LEQ216. - - - (1). Increase pattern area size as much as possible inside the package outline. - It is recommended to connect the land pattern to the VSS-ground level (GND plan of inner layer bellow the MCU) as thermal heat sink. (2). Place thermal via holes to be with lands as close as possible. 0.25 mm a 0.30 mm in Figure 8-1, Figure 8-2, Figure 8-3, and Figure 8-4 Document Number: 002-05682 Rev. *K Page 80 of 222 S6J3200 Series Figure 8-2: Land Pattern and Thermal Via LEQ216 0.25 mm a 0.30 mm Figure 8-3: Land Pattern and Thermal Via LET208 0.25 mm a 0.30 mm Document Number: 002-05682 Rev. *K Page 81 of 222 S6J3200 Series Figure 8-4: Land Pattern and Thermal Via LER208 0.25 mm a 0.30 mm Document Number: 002-05682 Rev. *K Page 82 of 222 S6J3200 Series Figure 8-5: Optional Land Pattern 0.25 mm a 0.30 mm Document Number: 002-05682 Rev. *K Page 83 of 222 S6J3200 Series 8.3 8.3.1 DC Characteristics Port Function Characteristics (Condition: See 8.2. Operation Assurance ) Parameter Symbol Pin Name VIH1 VIH2 P4_25 to 31, P5_00 to 20, P6_20 to 26 VIH3 VIH4 VIH5 VIH6 "H" level Input voltage VIH7 P2_16, 17, 19, 22, 24 to 31, P3_00 to 31, P4_00 to 12, P6_02 to 19 P2_25, 26, P3_00, 01 RSTX NMIX VIH8 VIH9 VIH10 VIH11 VIH12 MD Conditions CMOS hysteresis input level is selected Automotive input level is selected TTL input level is selected CMOS hysteresis input level is selected Automotive input level is selected TTL input level is selected - Min 0.7xVC C53 0.8xVC C53 2.0 0.7xVC C5 0.8xVC C5 2.0 0.7xVC C5 0.7xVC C5 JTAG_NTRST JTAG_TCK JTAG_TDI JTAG_TMS P0_00 to 19, 26 to 28, 30, 31, P1_00 to 09, P5_21, 22, 27 to 31, P6_00, 01 P0_00 to 19, 30, 31, P1_00 to 09, P5_21, 22, 27 to 31, P6_00, 01 - 2.3 CMOS hysteresis input level is selected 0.7xVC P0_26 to 28 - Document Number: 002-05682 Rev. *K TTL input level is selected Value Typ - Max VCC53+0 .3 Unit V - VCC53+0 .3 V - VCC53+0 .3 V - VCC5+0. 3 V *1 - VCC5+0. 3 V *1 - VCC5+0. 3 VCC5+0. 3 VCC5+0. 3 V V V - VCC5+0. 3 V - VCC3+0. 3 V 2.0 - VCC3+0. 3 V 1.8 - VCC3+0. 3 V C3 Remarks MediaLB Page 84 of 222 S6J3200 Series Parameter Symbol VIL1 VIL2 P4_25 to 31, P5_00 to 20, P6_20 to 26 VIL3 VIL4 VIL5 VIL6 "L" level Input voltage VIL7 P2_16, 17, 19, 22, 24 to 31, P3_00 to 31, P4_00 to 12, P6_02 to 19 P2_25, 26, P3_00, 01 RSTX NMIX VIL8 VIL9 VIL10 VIL11 VIL12 Min Value Typ VSS-0.3 - VSS-0.3 - 0.5x VCC53 V VSS-0.3 - 0.8 V VSS-0.3 - 0.3x VCC5 V *1 Automotive input level is selected VSS-0.3 - 0.5x VCC5 V *1 TTL input level is selected VSS-0.3 - 0.8 V - VSS-0.3 - - VSS-0.3 - - VSS-0.3 - 0.8 V CMOS hysteresis input level is selected VSS-0.3 - 0.3x VCC3 V TTL input level is selected VSS-0.3 - 0.8 V - VSS-0.3 - 0.7 V Pin Name MD JTAG_NTRST JTAG_TCK JTAG_TDI JTAG_TMS P0_00 to 19, 26 to 28, 30, 31, P1_00 to 09, P5_21, 22, 27 to 31, P6_00, 01 P0_00 to 19, 30, 31, P1_00 to 09, P5_21, 22, 27 to 31, P6_00, 01 P0_26 to 28 Document Number: 002-05682 Rev. *K Conditions CMOS hysteresis input level is selected Automotive input level is selected TTL input level is selected CMOS hysteresis input level is selected Max 0.3x VCC53 0.3x VCC5 0.3x VCC5 Unit Remarks V V V MediaLB Page 85 of 222 S6J3200 Series Parameter Symbol Pin Name VHYS1 VHYS2 P4_25 to 31, P5_00 to 20, P6_20 to 26 VHYS3 VHYS4 VHYS5 VHYS6 Hysteresis voltage VHYS7 P2_16, 17, 19, 22, 24 to 31, P3_00 to 31, P4_00 to 12, P6_02 to 19 P2_25, 26, P3_00, 01 RSTX NMIX VHYS8 VHYS9 VHYS10 VHYS11 MD JTAG_NTRST JTAG_TCK JTAG_TDI JTAG_TMS P0_26 to 28, 30, 31, P1_00 to 09, P5_21, 22 P6_01 P0_30, 31, P1_00 to 09, P5_21, 22, P6_01 Conditions CMOS hysteresis input level is selected Automotive input level is selected TTL input level is selected CMOS hysteresis input level is selected Min - Value Typ 0.158x VCC53 P0_26 to 28 Document Number: 002-05682 Rev. *K Unit - V - 0.104x VCC53 - V - 0.032x VCC53 - V - 0.158x VCC5 - V Automotive input level is selected - 0.104x VCC5 - V TTL input level is selected - - V - - - V - - - V - - 0.032x VCC5 - V CMOS hysteresis input level is selected - 0.188x VCC3 - V TTL input level is selected - 0.164x VCC3 - V - V 0.032x VCC5 0.158x VCC5 0.158x VCC5 0.124x VCC3 *1: P3_21 to P3_31, P4_00 to P4_12 and P6_9 to P6-16 are supplied with power by DVCC. VHYS12 Max - - Remarks MediaLB Page 86 of 222 S6J3200 Series (Condition: See 8.2. Operation Assurance ) Parameter Symbol Pin Name VOH1 P4_25 to 31, P5_00 to 20, P6_20 to 26 VOH2 VOH3 VOH4 VOH5 VOH6 "H" level output voltage P2_16, 17, 22, 24 to 31, P3_00 to 31, P4_00 to 12, P6_02 to 19 VOH7 PSC_1 VOH8 JTAG_TDO VOH10 P3_21 to 31, P4_00 to 12, P6_09 to 16 VOH11 VOH12 VOH13 VOH14 P0_00 to 19, 26 to 28, 30, 31, P1_00 to 09, P5_21, 22, 27 to 31, P6_00, 01 Conditions VCC53=3.0 V IOH=-0.5 mA VCC53=3.0 V IOH=-1.0 mA VCC53=3.0 V IOH=-2.0 mA VCC5=4.5 V IOH=-1.0 mA VCC5=4.5 V IOH=-2.0 mA VCC5=4.5 V IOH=-5.0 mA VCC5=4.5 V IOH=-2.0 mA VCC5=4.5 V IOH=-5.0 mA DVCC=4.5 V IOH=-30.0 mA DVCC=4.5 V IOH=-40.0 mA VCC3=3.0 V IOH=-2.0 mA VCC3=3.0 V IOH=-5.0 mA VCC3=3.0 V IOH=-10.0 mA Min Value Typ Max Unit VCC53 - 0.5 - VCC53 V VCC53 - 0.5 - VCC53 V VCC53 - 0.5 - VCC53 V VCC5 - 0.5 - VCC5 V *1 VCC5 - 0.5 - VCC5 V *1 VCC5 - 0.5 - VCC5 V *1 VCC5 - 0.5 - VCC5 V VCC5 - 0.5 - VCC5 V DVCC - 0.5 - DVCC V SMC DVCC - 0.5 - DVCC V SMC Tj=-40oC VCC3 - 0.5 - VCC3 V VCC3 - 0.5 - VCC3 V VCC3 - 0.5 - VCC3 V VOH15 P0_00 to 19, P5_21, 22, 27 to 31, P6_00, 01 VCC3=3.0 V IOH=-20.0 mA VCC3 - 0.5 - VCC3 V VOH16 P0_26 to 28 VCC3=3.0 V IOH=-6.0 mA 2.0 - VCC3 V Document Number: 002-05682 Rev. *K Remarks MediaLB Page 87 of 222 S6J3200 Series (Condition: See 8.2. Operation Assurance ) Parameter Symbol Pin Name VOL1 P4_25 to 31, P5_00 to 20, P6_20 to 26 VOL2 VOL3 VOL4 VOL5 VOL6 "L" level output voltage P2_16, 17, 22, 24 to 31, P3_00 to 31, P4_00 to 12, P6_02 to 19 VOL7 PSC_1 VOL8 JTAG_TDO VOL9 P2_25, 26, P3_00, 01 VOL10 P3_21 to 31, P4_00 to 12, P6_09 to 16 VOL11 VOL12 VOL13 VOL14 VOL15 P0_00 to 19, 26 to 28, 30, 31, P1_00 to 09, P5_21, 22, 27 to 31, P6_00, 01 P0_00 to 19, P5_21, 22, 27 to 31, P6_00, 01 Conditions VCC53=3.0 V IOL=0.5 mA VCC53=3.0 V IOL=1.0 mA VCC53=3.0 V IOL=2.0 mA VCC5=4.5 V IOL=1.0 mA VCC5=4.5 V IOL=2.0 mA VCC5=4.5 V IOL=5.0 mA VCC5=4.5 V IOL=2.0 mA VCC5=4.5 V IOL=5.0 mA VCC5=4.5 V IOL=3.0 mA DVCC=4.5 V IOL=30.0 mA DVCC=4.5 V IOL=40.0 mA VCC3=3.0 V IOL=2.0 mA VCC3=3.0 V IOL=5.0 mA VCC3=3.0 V IOL=10.0 mA VCC3=3.0 V IOL=20.0 mA Min Value Typ Document Number: 002-05682 Rev. *K P0_26 to 28 Unit Remarks 0 - 0.4 V 0 - 0.4 V 0 - 0.4 V 0 - 0.4 V *1 0 - 0.4 V *1 0 - 0.4 V *1 0 - 0.4 V 0 - 0.4 V 0 - 0.4 V I2 C 0 - 0.55 V SMC 0 - 0.55 V SMC Tj=-40 oC 0 - 0.4 V 0 - 0.4 V 0 - 0.4 V 0 - 0.4 V - 0.4 V VCC3=3.0 V 0 IOL=6.0 mA *1: P3_21 to P3_31, P4_00 to P4_12 and P6_9 to P6-16 are supplied with power by DVCC. VOL16 Max MediaLB Page 88 of 222 S6J3200 Series (Condition: See 8.2. Operation Assurance ) Parameter Input leakage current Symbol IIL RUP1 RUP2 Pull-up resistor Pin Name P2_16, 17, 19, 22, 24 to 31, P3_00 to 31, P4_00 to 12, P4_25 to 31, P5_00 to 20, P6_02 to 31 P0_00 to 31, P1_00 to 09, P5_21, 22, 27 to 31, P6_00, 01 RSTX, NMIX P2_16, 17, 19, 22, 24 to 31, P3_00 to 31, P4_00 to 12, P4_25 to 31, P5_00 to 20, P6_02 to 31 P4_25 to 31, P5_00 to 20 RUP3 RUP4 Rdown1 Pull-down resistor P0_00 to 31, P1_00 to 09, P5_21, 22, 27 to 31, P6_00, 01 JTAG_TDI, JTAG_TMS, JTAG_TCK P2_16, 17, 19, 22, 24 to 31, P3_00 to 31, P4_00 to 12, P4_25 to 31,P5_00 to 20, P6_02 to 31 P4_25 to 31,P5_00 to 20 Rdown2 Rdown3 CIN1 Input capacitance CIN2 P0_00 to 31, P1_00 to 09, P5_21, 22, 27 to 31, P6_00, 01 JTAG_NTRST P0_00 to 31, P1_00 to 09, P2_16, 17, 19, 22, 24 to 31, P3_00 to 20, P4_25 to 31, P5_00 to 20, P5_21 22, 27 to 31, P6_00 to 08, 17 to 26 P3_21 to 31, P4_00 to 12, P6_09 to 16 Document Number: 002-05682 Rev. *K Conditions Value Unit Remarks +5 A 5-V pins 5-V/3-V pins - +10 A 3-V pins 25 50 100 k Pull-up resistor Selected Vcc53 = 4.5 V to 5.5 V 25 50 100 k 5-V pins 5-V/3-V pins Pull-up resistor Selected Vcc53 = 3.0 V to 3.6 V 40 100 200 k 5-V/3-V pins Pull-up resistor selected 17 33 66 k 3-V pins - 25 50 100 k Pull-down resistor Selected Vcc53 = 4.5 V to 5.5 V 25 50 100 k 5-V pins 5-V/3-V pins Pull-down resistor Selected Vcc53 = 3.0 V to 3.6 V 40 100 200 k 5-V/3-V pins Pull-down resistor selected 17 33 66 k 3-V pins - 25 50 100 k - - 5 15 pF - - 15 45 pF Mi n Typ Max VCC5=VCC53=DVCC= AVCC=5.5 V VSS < VI < VCC -5 - VCC3=3.6 V VSS < VI < VCC3 10 - When using SMC Page 89 of 222 S6J3200 Series (Condition: See 8.2. Operation Assurance ) Parameter High current output drive capacity Phase-to-phase deviation1 High current output drive capacity Phase-to-phase deviation2 LCD divider resistor Symbol Delta-VOH8 Delta-VOL8 RLCD COM0 to COM3 output impedance RVCOM COM0 to COM3 output impedance RVSEG LCDC leak current ILCDC *: Pin Name P3_21 to 31, P4_00 to 12, P6_09 to 16 V0 to V1, V1 to V2, V2 to V3 COMm (m=0 to 3) SEGn (n=00 to 31) V0 to V3, COMm (m=0 to 3), SEGn (n=00 to 31) Min Value Typ Max - - - - Conditions Unit Remarks 90 mV * - 90 mV * 6.25 12.5 25 k - - - 4.5 k - - - 17 k -0.5 - +0.5 A DVCC=4.5 V IOH=-30.0 mA Maximum deviation of VOH8 DVCC=4.5 V IOL= 30.0 mA Maximum deviation of VOL84 TA= + 25 C If PWM1P0/PWM1M0/PWM2P0/PWM2M0 of ch.0 is turned on simultaneously, the maximum deviation of VOH4 / VOL4 for each pin is defined. Same for other channels. Document Number: 002-05682 Rev. *K Page 90 of 222 S6J3200 Series (Condition: See 8.2. Operation Assurance ) Parameter Output Differential Voltage Output Offset Voltage Symbol Pin Name Conditions DSP0_DATAn+, DSP0_DATAnn=0 to 11 BOOST=0 ( Drivability 2mA) RL = 100 BOOST=1 ( Drivability 4mA) RL = 50 BOOST=0 ( Drivability 2mA) RL = 100 BOOST=1 ( Drivability 4mA) RL = 50 | VOD | VOS Min Value Typ Max 100 200 600 | mV | 0.5 1.2 1.5 V Unit Remarks Single Ended VRSDS N VOH VOS VOL VRSDS P Ground Level / 0V Differential +VOD (VRSDSN) - (VRSDSP) Document Number: 002-05682 Rev. *K 0V Differential -VOD Page 91 of 222 S6J3200 Series 8.3.2 Power Supply Current 8.3.2.1 Run Mode This characteristic is specified for the series with the function digit 3, 4, 5, 6, 7, 8 and 9. (Condition: See 8.2. Operation Assurance ) Symbol Pin Name ICC5 VCC5 ICC12 VCC12 Conditions Normal Operation Adder for Work Flash Programming or Erasing. CPU:240 MHz, HPM:120 MHz, GDC 2D and 3D engine:200 MHz CPU:240 MHz, HPM:120 MHz, GDC 2D engine only:200 MHz CPU:120 MHz, HPM:60 MHz, GDC: 0 MHz For TC FLASH Programming or Erasing CPU:80 MHz, HPM:40 MHz, GDC: 0 MHz For TC FLASH Programming or Erasing Adder for Work Flash Programming or Erasing. VCC3_ LVDS_Tx ILVDS AVCC3_ LVDS_PLL 50 MHz Value Typ Max 45 70 20 820 1600 700 1480 Unit TA (oC) mA mA mA mA mA mA mA 25 105 105 25 105 25 105 Remark - - 1120 mA 105 - - 1040 mA 105 - - 20 mA 105 - - 56 mA 105 *1 - 7 mA 105 - 9 mA 105 50 MHz For revision F, J For revision M, P Notes: - The output port current is not included in the specified value *1. A few mA which depends on usage for FPD-Link data transfer should be estimated for each port in an actual application, and then it should be added to the current consumption at Vcc3_LVDS_Tx. - The current consumption at Vcc3_LVDS_Tx is specified under RL=100 , CL=5 pF, f=50 MHz, and 0/1 alternation pattern output. Document Number: 002-05682 Rev. *K Page 92 of 222 S6J3200 Series This characteristic is specified for the series with the function digit B. (Condition: See 8.2. Operation Assurance ) Symbol Pin Name ICC5 VCC5 ICC12 VCC12 Conditions Normal Operation Adder for Work Flash Programming or Erasing. CPU:160 MHz, HPM:160 MHz, GDC 2D and 3D engine:160 MHz CPU:120 MHz, HPM:60 MHz, GDC: 0 MHz For TC FLASH Programming or Erasing CPU:80 MHz, HPM:40 MHz, GDC: 0 MHz For TC FLASH Programming or Erasing Adder for Work Flash Programming or Erasing. Document Number: 002-05682 Rev. *K Value Unit TA (oC) 70 20 1410 mA mA mA mA mA 25 105 105 25 105 - 1120 mA 105 - - 1040 mA 105 - - 20 mA 105 - Typ Max 45 880 - Remark - Page 93 of 222 S6J3200 Series This characteristics is specified for the series with the function digit K, L, M, and N. (Condition: See 8.2. Operation Assurance ) Symbol Pin Name ICC5 VCC5 ICC12 ILVDS VCC12 TA (oC) mA mA mA mA mA mA mA 25 105 105 25 105 25 105 1155 mA 105 - - 1075 mA 105 - - 20 mA 105 - 50 MHz - 56 mA 105 *1 50 MHz - 9 mA 105 Normal Operation Adder for Work Flash Programming or Erasing. CPU:240 MHz, HPM:120 MHz, GDC 2D and 3D engine:200 MHz CPU:240 MHz, HPM:120 MHz, GDC 2D engine only:200 MHz CPU:120 MHz, HPM:60 MHz, GDC:0 MHz For TC FLASH Programming or Erasing CPU:80 MHz, HPM:40 MHz, GDC:0 MHz For TC FLASH Programming or Erasing Adder for Work Flash Programming or Erasing. VCC3_ LVDS_Tx AVCC3_ LVDS_PLL Value Unit Conditions Typ 45 822 702 - Max 70 20 1635 1515 - Remark - Notes: - The output port current is not included in the specified value *1. A few mA which depends on usage for FPD-Link data transfer should be estimated for each port in an actual application, and then it should be added to the current consumption at Vcc3_LVDS_Tx. - The current consumption at Vcc3_LVDS_Tx is specified under RL=100 , CL=5 pF, f=50 MHz, and 0/1 alternation pattern output. Document Number: 002-05682 Rev. *K Page 94 of 222 S6J3200 Series 8.3.2.2 PSS Timer Mode Shutdown (PD6=OFF) This characteristic is specified for the series with the function digit 3, 4, 5, 6, 7, 8, 9, K, L, M, and N. (Condition: See 8.2. Operation Assurance ) Symbol ICCT5 Typ Value Max 4 MHz Crystal for Main Oscillator PD1=ON, PD4_0=ON, PD4_1=ON 350 4 MHz Crystal for Main Oscillator PD1=ON, PD4_0 or PD4_1=ON Pin Name VCC5 Unit TA (oC) 600 A 25 345 575 A 25 4 MHz Crystal for Main Oscillator PD1=ON 340 550 A 25 8 MHz Crystal for Main Oscillator PD1=ON, PD4_0=ON, PD4_1=ON 450 730 A 25 8 MHz Crystal for Main Oscillator PD1=ON, PD4_0 or PD4_1=ON 445 705 A 25 440 680 A 25 180 400 A 25 - 175 375 A 25 - 170 350 A 25 - 190 420 A 25 - 185 395 A 25 - 180 370 A 25 - 85 300 A 25 - 80 275 A 25 - 75 250 A 25 - Conditions 8 MHz Crystal for Main Oscillator PD1=ON 4 MHz External clock PD1=ON, PD4_0=ON, PD4_1=ON 4 MHz External Clock PD1=ON, PD4_0 or PD4_1=ON 4 MHz External Clock PD1=ON 8 MHz External clock PD1=ON, PD4_0=ON, PD4_1=ON 8 MHz External Clock PD1=ON, PD4_0 or PD4_1=ON 8 MHz External Clock PD1=ON 32 kHz Crystal for Sub Oscillator PD1=ON, PD4_0=ON, PD4_1=ON 32 kHz Crystal for Sub Oscillator PD1=ON, PD4_0 or PD4_1=ON 32 kHz Crystal for Sub Oscillator PD1=ON Remark CL=10 pF MCGAIN=0b00(4 MHz) CL=10 pF MCGAIN=0b00(4 MHz) CL=10 pF MCGAIN=0b00(4 MHz) CL=10 pF MCGAIN=0b01(8 MHz) CL=10 pF MCGAIN=0b01(8 MHz) CL=10 pF MCGAIN=0b01(8 MHz) Notes: - The values will be evaluated after engineering samples release. - The values have been standardized with regulator standby mode (RMSEL=1). Document Number: 002-05682 Rev. *K Page 95 of 222 S6J3200 Series This characteristic is specified for the series with the function digit B. (Condition: See 8.2. Operation Assurance ) Symbol ICCT5 Typ Value Max 4 MHz Crystal for Main Oscillator PD1=ON, PD4_0=ON, PD4_1=ON 350 4 MHz Crystal for Main Oscillator PD1=ON, PD4_0 or PD4_1=ON Pin Name VCC5 Unit TA (oC) 650 A 25 345 615 A 25 4 MHz Crystal for Main Oscillator PD1=ON 340 590 A 25 8 MHz Crystal for Main Oscillator PD1=ON, PD4_0=ON, PD4_1=ON 450 775 A 25 8 MHz Crystal for Main Oscillator PD1=ON, PD4_0 or PD4_1=ON 445 750 A 25 440 725 A 25 85 345 A 25 - 80 320 A 25 - 75 295 A 25 - Conditions 8 MHz Crystal for Main Oscillator PD1=ON 32 kHz Crystal for Sub Oscillator PD1=ON, PD4_0=ON, PD4_1=ON 32 kHz Crystal for Sub Oscillator PD1=ON, PD4_0 or PD4_1=ON 32 kHz Crystal for Sub Oscillator PD1=ON Remark CL=10 pF MCGAIN=0b00(4 MHz) CL=10 pF MCGAIN=0b00(4 MHz) CL=10 pF MCGAIN=0b00(4 MHz)CL=10 pF MCGAIN=0b01(8 MHz) CL=10 pF MCGAIN=0b01(8 MHz)CL=10 pF MCGAIN=0b01(8 MHz)- Notes: - The values will be evaluated after engineering samples release. - The values have been standardized with regulator standby mode (RMSEL=1). Document Number: 002-05682 Rev. *K Page 96 of 222 S6J3200 Series 8.3.2.3 PSS Stop Mode Shutdown This characteristic is specified for the series with the function digits 3, 4, 5, 6, 7, 8, 9, K, L, M, and N. (Condition: See 8.2. Operation Assurance ) Symbol Pin Name Conditions ICCH5 VCC5 PD1=ON, PD4_0=ON, PD4_1=ON PD1=ON, PD4_0 or PD4_1=ON PD1=ON Value Typ 65 60 55 Max 270 245 220 Unit TA (oC) A A A 25 25 25 Remark - This characteristic is specified for the series with the function digits B. (Condition: See 8.2. Operation Assurance ) Symbol Pin Name Conditions ICCH5 VCC5 PD1=ON, PD4_0=ON, PD4_1=ON PD1=ON, PD4_0 or PD4_1=ON PD1=ON Value Typ 65 60 55 Max 315 290 265 Unit TA (oC) A A A 25 25 25 Remark - Notes: - The values will be evaluated after engineering samples release. - The values have been standardized with regulator standby mode (RMSEL=1). Document Number: 002-05682 Rev. *K Page 97 of 222 S6J3200 Series AC Characteristics 8.4 8.4.1 Source Clock Timing (Condition: See 8.2. Operation Assurance ) Parameter Source oscillation clock frequency Source oscillation clock cycle time CAN PLL jitter (when locked) Internal Slow CR oscillation frequency Internal Fast CR oscillation frequency Min Value Typ Max - 3.6 - 16 MHz X0, X1 - 62.5 - 277.8 ns tPJ - - -1.5 - 1.5 ns FCRS - - 50 100 150 kHz FCRF - - 2.40 4.00 5.61 MHz Symbol Pin Name Conditions FC X0, X1 tCYL Unit Remarks Before trim After trim 3.20 4.00 4.81 MHz Notes: - The maximum/minimum values have been standardized with the main clock and PLL clock in use. - - The error of source oscillator frequency must be smaller than 3000 ppm. Enough evaluation and adjustment are recommended using oscillator on your system board. - X0 and X1 clock timing tCYL X0 CAN PLL jitter A time difference from the ideal clock is guaranteed for each cycle period within 20,000 cycles. Ideal clock Slow PLL output Fast Document Number: 002-05682 Rev. *K Page 98 of 222 S6J3200 Series 8.4.2 Sub Clock Timing (Condition: See 8.2. Operation Assurance ) Parameter Symbol Source oscillation clock frequency Source oscillation clock cycle time - FCL tLCYL Pin Name X0A, X1A X0A, X1A Min Value Typ Max - - 32.768 - kHz - - 30.52 - s Conditions Unit Remarks X0A and X1A clock timing tLCYL X0A Document Number: 002-05682 Rev. *K Page 99 of 222 S6J3200 Series 8.4.3 Internal Clock Timing This chapter shows the characteristics for internal clock timing at the current stage. In the column symbol, same clock names as described in CHAPTER 5: CLOCK SYSTEM of Platform hardware manu al are used. Corresponding functions for these clocks are described in CHAPTER 5: CLOCK CONFIGURATION of S6J3200 series hardware manual. (Condition: See 8.2. Operation Assurance ) Table 8-1: Assured Combination of Clock Frequency Max Value Combination Function digit Symbol 3, 4, 5, 6, 7, 8, 9, K, L, M, N Max *1 Max *2 Max *3 232 200 160 FSSCG0 (464) (800) (640) 200 200 200 FSSCG1 (800) (800) (800) 200 200 200 FSSCG2 (800) (800) (800) 400 400 400 FSSCG3 (800) (800) (800) 240 200 200 FPLL0 (480) (800) (800) 400 400 400 FPLL1 (800) (800) (800) 200 200 200 FPLL2 (800) (800) (800) 240 240 240 FPLL3 (480) (480) (480) FCLK_CPU0 240 200 160 FCLK_SHE 240 200 160 FCLK_FCLK 80 66.7 80 FCLK_ATB 120 100 80 FCLK_DBG 120 100 80 FCLK_HPM 120 200 160 FCLK_HPM2 60 100 80 FCLK_DMA 120 200 160 FCLK_MEMC 120 200 160 FCLK_EXTBUS 40 40 40 FCLK_SYSC1 40 40 40 FCLK_HAPP0A0 40 40 40 FCLK_HAPP0A1 40 40 40 FCLK_HAPP1B0 60 50 80 FCLK_HAPP1B1 40 40 40 FCLK_LLPBM 240 200 160 FCLK_LLPBM2 120 100 80 FCLK_LCP 60 50 80 FCLK_LCP0 40 40 40 FCLK_LCP0A 60 66.7 80 FCLK_LCP1 40 40 40 FCLK_LCP1A 60 66.7 80 FCLK_LAPP0 40 40 40 FCLK_LAPP0A 40 40 40 FCLK_LAPP1 40 40 40 FCLK_LAPP1A 40 40 40 FCLK_TRC 100 100 100 FCLK_CD1 400 400 400 FCLK_CD1A0 100 100 100 FCLK_CD1A1 100 100 100 Document Number: 002-05682 Rev. *K Function digit B Max *4 160 (640) 200 (800) 160 (640) 400 (800) 160 (640) 320 (640) 200 (800) 240 (480) 160 160 80 80 80 160 80 160 160 40 40 40 40 80 40 160 80 80 40 80 40 80 40 40 40 40 100 400 100 100 Unit Remarks MHz SSCG0 output clock MHz SSCG1 output clock MHz SSCG2 output clock MHz SSCG3 output clock MHz PLL0 output clock MHz PLL1 output clock MHz PLL2 output clock MHz PLL3 output clock MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Page 100 of 222 S6J3200 Series Symbol FCLK_CD1B0 FCLK_CD1B1 FCLK_CD2 FCLK_CD2A0 FCLK_CD2A1 FCLK_CD2B0 FCLK_CD2B1 FCLK_CD3 FCLK_CD3A0 FCLK_CD3A1 FCLK_CD3B0 FCLK_CD3B1 FCLK_CD4 FCLK_CD4A0 FCLK_CD4A1 FCLK_CD4B0 FCLK_CD4B1 FCLK_CD5 FCLK_CD5A0 FCLK_CD5A1 FCLK_CD5B0 FCLK_CD5B1 FCLK_HSSPI FCLK_SYSC0H FCLK_COMH FCLK_RAM0H FCLK_RAM1H FCLK_SYSC0P FCLK_COMP FCLK_CAN Max *1 100 100 400 400 400 400 400 200 200 200 200 200 200 200 200 200 200 240 120 120 60 60 200 60 60 60 60 60 60 40 Max Value Combination Function digit 3, 4, 5, 6, 7, 8, 9, K, L, M, N Max *2 Max *3 100 100 100 100 400 400 400 400 400 400 400 400 400 400 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 240 240 120 120 120 120 60 60 60 60 200 200 66.7 80 66.7 80 66.7 80 66.7 80 66.7 80 66.7 80 40 40 Function digit B Unit Remarks Max *4 100 100 320 320 320 320 320 160 160 160 160 160 200 200 200 200 200 240 120 120 60 60 200 80 80 80 80 80 80 40 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Notes: - *1: Maximum clock frequencies when CPU clock = 240 MHz. - For SSCG, down spread and center spread modes are supported with following conditions: For down spread mode, clock frequency setting can be up to max SSCG frequency defined in above table. For center spread mode, an appropriate clock frequency setting has to be chosen so that the modulated clock does not exceed the max SSCG frequency defined in above table. - - - 240 MHz or less is available for PLL. - - From *1 to *3, they are applied to the product series with function digit 3, 4, 5, 6, 7, 8, 9, K, L, M, and N. - Even if a combination of clock frequency is able to be configured by software, the frequency should be configured under maximum frequency described in Table 8-1. For example, 80 MHz of CLK_LCP0A seems to be configurable from both divided 240 MHz and 160 MHz of CLK_CPU. But each duty ratio of configured 80 MHz as an internal signal is different from one another. In this series, the 80 MHz from the 160 MHz divided by 2 can only be assured, but the 240 MHz divided by 3 cannot be assured from the internal timing design point of view. - - - FCLK_TRC/2 (half frequency of FCLK_TRC) comes out of the trace clock port of package external pin. *2: Maximum clock frequencies when CPU clock = 200 MHz. *3: Maximum clock frequencies when CPU clock = 160 MHz. This is also a combination of maximum clock frequencies for TC FLASH Programming or Erasing. *4: Maximum clock frequencies when CPU clock = 160 MHz for the product series with the function digit B. This is also a combination of maximum clock frequencies for TC FLASH Programming or Erasing. The frequency described in () is maximum output frequency of SSCG PLL / PLL multiplier circuit. The configurable minimum frequency of PLLn and SSCGn output is 400 MHz. Document Number: 002-05682 Rev. *K Page 101 of 222 S6J3200 Series - "Unused" means a clock source which doesn't have any supply destinations. Configure it as disable with performing at the lower clock frequency than the described maximum. - Operation assurance range Relationship between the internal clock frequency and supply voltage Power supply VCC5 [V] 5.5 Recommended guaranteed operation range 4.5 3.5 Guaranteed operation range 2 4 Frequency [MHz] Maximum frequency of each clock Frequency [MHz] Maximum frequency of each clock PLL guaranteed operation range Power supply VCC12 [V] 1.3 1.2 1.15 2 4 Note: CPU will be reset, when the power supply voltage is equal to or less than LVD setting voltage. Document Number: 002-05682 Rev. *K Page 102 of 222 S6J3200 Series - Relationship between the oscillation clock frequency and internal clock frequency Main Clock Oscillation clock frequency [MHz] - 4 Multiplied by 1 2 Internal Operation Clock Frequency PLL Clock Multiplied Multiplied Multiplied by 2 by 3 by 4 4 8 12 16 ... Multiplied by 40 Multiplied by 60 160 240 Oscillation circuit example X0 X1 R C1 C2 Note: For the configuration of an oscillation circuit, request the oscillator manufacturer to perform a circuit matching evaluation before starting design. Document Number: 002-05682 Rev. *K Page 103 of 222 S6J3200 Series AC characteristics are specified by the following measurement reference voltage values. - Input signal waveform Hysteresis input pin (Automotive) - Output signal waveform Output pin 0.8VCC5 2.4V 0.5VCC5 0.8V Hysteresis input pin (CMOS Schmitt) 0.7VCC5 0.3VCC5 0.7VCC3 0.3VCC3 Hysteresis input pin (TTL) 2.0V 0.8V DDR-HSSPI and HyperBus AC characteristics are specified with the following reference voltage regardless of input level configuration automotive, CMOS Schmitt, and TTL. - Input signal waveform Input pin (Regardless of configured input level) - Output signal waveform Output pin VIH = 0.5VCC3 VOH = 0.5VCC3 VIL = 0.5VCC3 VOL = 0.5VCC3 Document Number: 002-05682 Rev. *K Page 104 of 222 S6J3200 Series 8.4.4 Reset 8.4.4.1 Reset Input (Condition: See 8.2. Operation Assurance ) Parameter Reset input time Reset input pulse filtered Symbol Pin Name Conditions tRSTL RSTX - Value Unit Min Max 10 - s - 1 s Remarks tRSTL RSTX 0.2VCC Document Number: 002-05682 Rev. *K 0.2VCC Page 105 of 222 S6J3200 Series 8.4.4.2 Power Supply Voltage Stability Conditions For revision M, P (Condition: See 8.2. Operation Assurance ) Parameter VCC5 stability time after RSTX assertion VCC12 stability time after RSTX assertion Symbol Pin Name tFV5 VCC5 Conditions Value Unit Remarks - s VCC5>=2.7 V - s VCC12>=1.1 V Min Max 35 35 tFV12 VCC12 RSTX 0.2 VCC5 >=2.7V VCC5 tFV5 VCC12 1.1V tFV12 Note: This AC specification isn't applied except revision M, P. Document Number: 002-05682 Rev. *K Page 106 of 222 S6J3200 Series 8.4.5 Power-On Conditions 8.4.5.1 Power-On Conditions (Condition: See 8.2. Operation Assurance ) Parameter Min Value Typ Max - 2.15 2.35 2.55 V VCC5 - 2.25 2.45 2.65 V - - - - - 540 s *1 tOFF VCC5 1 - - ms *2 dV/dt VCC5 VCC5: Between 0.2 V to 2.55 V - - 6 mV/s *3 Symbol Pin Name Conditions - VCC5 - Level detection voltage Reset release voltage Level detection time Power off time Power ramp rate Unit Remarks Maximum ramp VCC5: rate guaranteed *4 |dV/dt| VCC5 Between 2.6 V 50 mV/s to not generate and 4.5 V power-on reset *1: If a power fluctuation precedes the low-voltage detection time, the detection may occur or be canceled after the supply voltage passes the detection voltage range. *2: If Vcc is held below 0.2 V for a minimum period of tOFF, power-on reset will occur. If tOFF is not satisfied, power-on reset will still occur if the power ramp rate is kept below 6 mV/s. *3: This is the power ramp rate with which power-on reset will always occur regardless of power-off time, as mentioned in *2. *4: When VCC5 is within 2.6 V - 4.5 V, and VCC5 fluctuation is below 50mV/us, the power-on reset is suppressed. Between 4.5 V 5.5 V, the power-on reset does not occur with any VCC5 fluctuation. Note: When neither *2 nor *3 can be satisfied, assert external reset (RSTX) at power-up and at any brownout event. Power off time, Power ramp rate at Power-on tOFF VCC 0.2V dV/dt 0.2V Maximum ramp rate guaranteed to not generate power-on reset 5.5V 4.5V VCC |dV/dt| |dV/dt| Document Number: 002-05682 Rev. *K 2.6V Page 107 of 222 S6J3200 Series 8.4.5.2 VCC12 Stabilization Time during Power-On / PSS to RUN Transition (Condition: See 8.2. Operation Assurance ) Parameter Symbol VCC12 stabilization time during power-on Pin Name Conditions VCC12 - Value Min Typ Max - - 14.2 Unit ms Remarks *5 0000 0.7 0001 1.4 0010 2.1 0011 2.8 0100 3.5 0101 4.2 0110 4.9 VCC12 stabilization time 0111 5.7 SYSC0_ during PSS (PD2 off) to *5 VCC12 SPECFGR: ms 1000 6.4 RUN transition (Fast-CR EX12VRSTCNT 1001 7.1 untrimmed) 1010 8.5 1011 9.9 1100 11.4 1101 12.8 1110 14.2 (default) 1111 21.3 0000 0.8 0001 1.6 0010 2.4 0011 3.3 0100 4.1 0101 4.9 0110 5.8 VCC12 stabilization time 0111 6.6 SYSC0_ during PSS (PD2 off) to *5 VCC12 SPECFGR: ms 1000 7.4 RUN transition (Fast-CR EX12VRSTCNT 1001 8.3 trimmed) 1010 9.9 1011 11.6 1100 13.3 1101 14.9 1110 16.6 (default) 1111 24.9 *5: After LVDL2 reset release during power-on sequence and PSS (PD2 off) to RUN transition, VCC12 has to rise above operation assurance range within this time. Document Number: 002-05682 Rev. *K Page 108 of 222 S6J3200 Series 8.4.6 Multi-Function Serial 8.4.6.1 UART (Asynchronous Serial Interface) Timing (SMR: MD2-0=0b000, 0b001) (1) External Clock Selected (BGR: EXT=1) (Condition: See 8.2. Operation Assurance ) Parameter Symbol Serial clock "L" pulse width SCK0 to SCK4, SCK8 to SCK12 SCK16 to SCK17 SCK0 to SCK4, SCK8 to SCK12 SCK16 to SCK17 SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 tSLSH Serial clock "H" pulse width tSHSL SCK falling time tF SCK rising time tR Pin Name Conditions (CL = 50 pF, IOL=-2 mA, IOH=2 mA), (CL=20 pF, IOL=-1 mA, IOH=1 mA) Min Value Max Unit tCLK_LCPnA*1 +10 - ns tCLK_COMP +10 - ns tCLK_LCPnA*1 +10 - ns tCLK_COMP +10 - - ns 5 ns - 5 ns Remarks *1: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12 tR SCK VIL tF tSHSL VIH VIH tSLSH VIL VIL VIH External clock selected External clock selected Document Number: 002-05682 Rev. *K Page 109 of 222 S6J3200 Series 8.4.6.2 CSIO Timing (SMR: MD2-0=0b010) (1) Normal Synchronous Transfer (SCR: SPI=0) and Mark Level "H" of Serial Clock Output (SMR: SCINV=0) (Condition: See 8.2. Operation Assurance ) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK setup time SCK Valid SIN hold time Symbol tSCYC tSLOVI tIVSHI tSHIXI Document Number: 002-05682 Rev. *K Pin Name SCK0 to SCK4, SCK8 to SCK12 SCK16 to SCK17 SCK0 to SCK4, SCK8 to SCK12, SOT0 to SOT4, SOT8 to SOT12 SCK16 to SCK17 SOT16 to SOT17 SCK0 to SCK4, SCK8 to SCK12, SIN0 to SIN4, SIN8 to SIN12 SCK16 to CK17 SIN16 to SIN17 SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 SOT0 to SOT4, SOT8 to SOT12, SOT16 to SOT17 Conditions Master Mode (CL=20 pF, IOL=-5 mA, IOH=5 mA) Value Min Max 3tCLK_LCPnA*1 - 3tCLK_LCPnA*2 - 3tCLK_COMP - 0 30 0 20*3 0 15 Unit Remarks ns ns 26.5 20*3 - ns - ns 20 0 Page 110 of 222 S6J3200 Series Parameter Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Symbol tSHSL tSLSH tSLOVE Valid SIN SCK setup time tIVSHE SCK Valid SIN hold time tSHIXE Document Number: 002-05682 Rev. *K Pin Name Conditions SCK0 to SCK4, SCK8 to SCK12 SCK16 to SCK17 SCK0 to SCK4, SCK8 to SCK12 SCK16 to SCK17 SCK0 to SCK4, SCK8 to SCK12, SOT0 to SOT4, SOT8 to SOT12, SCK16 to SCK17 SOT16 to SOT17 SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 SIN0 to SIN4, SIN8 to SIN12, SIN16 to SIN17 Value Min Max 2tCLK_LCPnA*1 - 2tCLK_LCPnA*2 - 2tCLK_COMP - 2tCLK_LCPnA*1 - 2tCLK_LCPnA*2 2tCLK_COMP Slave Mode (CL=20 pF, IOL=-5 mA, IOH=5 mA) Unit ns ns 28.5 function digit 3 to 9 K to N 25*3 - Remarks ns function digit B - ns function digit 3 to 9 K to N function digit B - ns 30 25 10 11.5 1 Page 111 of 222 S6J3200 Series Parameter Symbol SCK falling time tF SCK rising time tR Pin Name Conditions SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 Slave Mode (CL=20 pF, IOL=-5 mA, IOH=5 mA) Value Unit Min Max - 5 ns - 5 ns Remarks *1: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12 *2: n=0:Group2 of ch.0 /ch1, n=1:Group1 of ch.8 (refer to CHAPTER 11: Port Configuration in HWM) *3: Group2 of ch.0, ch1, Group1 of ch.8 (refer to CHAPTER 11: Port Configuration in HWM) Notes: - This table provides the alternate current standard for CLK synchronous mode. - - CL is the load capability value connected to the pin at the test time. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the hardware manual. tSCYC SCK VOH VOL tSLOVI SOT VOH VOL tIVSHI SIN Master mode Document Number: 002-05682 Rev. *K VIH VIL tSHIXI VIH VIL Page 112 of 222 S6J3200 Series tSLSH SCK VIH VIL tSHSL VIL VIH VIH tR tF SOT tSLOVE VOH VOL tIVSHE SIN Slave mode Document Number: 002-05682 Rev. *K VIH VIL tSHIXE VIH VIL Page 113 of 222 S6J3200 Series (2) Normal Synchronous Transfer (SCR: SPI=0) and Mark Level "L" of Serial Clock Output (SMR: SCINV=1) (Condition: See 8.2. Operation Assurance ) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK setup time SCK Valid SIN hold time Symbol tSCYC tSHOVI tIVSLI tSLIXI Serial clock "H" pulse width tSHSL Serial clock "L" pulse width tSLSH Pin Name SCK0 to SCK4, SCK8 to SCK12 SCK16 to SCK17 SCK0 to SCK4, SCK8 to SCK12 SOT0 to SOT4, SOT8 to SOT12 SCK16 to SCK17 SOT16 to SOT17 SCK0 to SCK4, SCK8 to SCK12, SIN0 to SIN4, SIN8 to SIN12, SCK16 to SCK17 SIN16 to SIN17 SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 SOT0 to SOT4, SOT8 to SOT12, SOT16 to SOT17 SCK0 to SCK4, SCK8 to SCK12 SCK16 to SCK17 Document Number: 002-05682 Rev. *K SCK0 to SCK4, SCK8 to SCK12 SCK16 to SCK17 Conditions Min Value Master Mode (CL=20 pF, IOL=-5 mA, IOH=5 mA) Slave Mode (CL=20 pF, IOL=-5 mA, IOH=5 mA) Unit 3tCLK_COMP Max - 0 30 0 20*3 0 15 26.5 - 20*3 - 20 - 0 - 2tCLK_LCPnA*1 - 2tCLK_LCPnA*2 2tCLK_COMP 2tCLK_LCPnA*1 - ns 2tCLK_LCPnA*2 2tCLK_COMP - ns 3tCLK_LCPnA*1 3tCLK_LCPnA*2 Remarks ns ns ns ns Page 114 of 222 S6J3200 Series Parameter Symbol Pin Name Conditions Min Value Max Unit 28.5 SCK SOT delay time tSHOVE SCK0 to SCK4, SCK8 to SCK12, SOT0 to SOT4, SOT8 to SOT12, 25*3 - SCK16 to SCK17 SOT16 to SOT17 Valid SIN SCK setup time SCK Valid SIN hold time tIVSLE SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 SIN0 to SIN4, SIN8 to SIN12, SIN16 to SIN17 tF SCK rising time tR function digit 3 to 9 K to N function digit B 25 Slave Mode (CL=20 pF, IOL=-5 mA, IOH=5 mA) 10 - ns 1 - ns - 5 ns - 5 ns 11.5 tSLIXE SCK falling time ns 30 Remarks SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 function digit 3 to 9 K to N function digit B *1: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12 *2: n=0:Group2 of ch.0 /ch1, n=1:Group1 of ch.8 (refer to CHAPTER 11: Port Configuration in HWM) *3: Group2 of ch.0, ch1, Group1 of ch.8 (refer to CHAPTER 11: Port Configuration in HWM) Notes: - This table provides the alternate current standard for CLK synchronous mode. - CL is the load capability value connected to the pin at the test time. - The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the hardware manual. Document Number: 002-05682 Rev. *K Page 115 of 222 S6J3200 Series tSCYC VOH SCK VOL tSHOVI VOH VOL SOT tIVSLI tSLIXI VIH VIL SIN VIH VIL Master mode tSHSL SCK VIL tR SOT VIH tSLSH VIH VIL VIL tF tSHOVE VOH VOL tIVSLE SIN VIH VIL tSLIXE VIH VIL Slave mode Document Number: 002-05682 Rev. *K Page 116 of 222 S6J3200 Series (3) SPI Supported (SCR: SPI=1), and Mark Level "H" of Serial Clock Output (SMR: SCINV=0) (Condition: See 8.2. Operation Assurance ) Parameter Serial clock cycle time SCK SOT delay time Symbol Pin Name Conditions Min Max SCK0 to SCK4, SCK8 to SCK12 3tCLK_LCPnA*1 - 3tCLK_LCPnA*2 - SCK16 to SCK17 3tCLK_COMP - SCK0 to SCK4, SCK8 to SCK12, SOT0 to SOT4, SOT8 to SOT12, 0 30 0 20*3 0 15 26.5 - 20*3 - 20 - 0 - tSCYC tSHOVI SCK16 to SCK17 SOT16 to SOT17 Valid SIN SCK setup time tIVSLI SCK0 to SCK4, SCK8 to SCK12, SIN0 to SIN4, SIN8 to SIN12, SCK16 to SCK17 SIN16 to SIN17 SCK Valid SIN hold time SOT SCK delay time tSLIXI tSOVLI SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 SIN0 to SIN4, SIN8 to SIN12, SIN16 to SIN17 SCK0 to SCK4, SCK8 to SCK12 SOT0 to SOT4, SOT8 to SOT12 SCK16 to SCK17 Document Number: 002-05682 Rev. *K Value Master Mode (CL=20 pF, IOL=-5 mA, IOH=5 mA) 2tCLK_LCPnA*1 30 2tCLK_LCPnA*2 20 2tCLK_COMP*1 15 Unit Remarks ns ns ns ns - ns - Page 117 of 222 S6J3200 Series Parameter Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Symbol Pin Name Conditions Min Max 2tCLK_LCPnA*1 - 2tCLK_LCPnA*2 - SCK16 to SCK17 2tCLK_COMP - SCK0 to SCK4, SCK8 to SCK12 2tCLK_LCPnA*1 - 2tCLK_LCPnA*2 - 2tCLK_COMP - SCK0 to SCK4, SCK8 to SCK12 tSHSL tSLSH SCK16 to SCK17 tSHOVE SCK0 to SCK4, SCK8 to SCK12, SOT0 to SOT4, SOT8 to SOT12, SCK16 to SCK17 SOT16 to SOT17 Document Number: 002-05682 Rev. *K Value Slave Mode (CL=20 pF, IOL=-5 mA, IOH=5 mA) Unit ns ns 28.5 25*3 - ns 30 Remarks function digit 3 to 9 K to N function digit B 25 Page 118 of 222 S6J3200 Series Parameter Valid SIN SCK setup time SCK Valid SIN hold time Symbol Pin Name Slave Mode (CL=20 pF, IOL=-5 mA, IOH=5 mA) tSLIXE SCK falling time tF SCK rising time tR Unit Remarks - ns function digit 3 to 9 K to N function digit B 1 - ns - 5 ns - 5 ns Min Max 10 SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 SIN0 to SIN4, SIN8 to SIN12, SIN16 to SIN17 tIVSLE Value Conditions 11.5 SCK0 to SCK4, SCK8 to SCK12 SCK16 to SCK17 SCK0 to SCK4, SCK8 to SCK12 SCK16 to SCK17 *1: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12 *2: n=0:Group2 of ch.0 /ch1, n=1:Group1 of ch.8 (refer to CHAPTER 11: Port Configuration in HWM) *3: Group2 of ch.0, ch1, Group1 of ch.8 (refer to CHAPTER 11: Port Configuration in HWM) Notes: - This table provides the alternate current standard for CLK synchronous mode. - - CL is the load capability value connected to the pin at the test time. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the hardware manual. tSCYC SCK VOH VOL tSOVLI SOT VOH VOL VOH VOL tIVSLI SIN VOL tSHOVI tSLIXI VIH VIL VIH VIL Master mode Document Number: 002-05682 Rev. *K Page 119 of 222 S6J3200 Series tSHSL tSLSH VIH SCK VIL tSHOVE VOH VOL tSLIXE VIH VIL VIH VIL * Changes when writing to the TDR register Document Number: 002-05682 Rev. *K tR VIH VIH VOH VOL tIVSLE SIN VIL tF * SOT VIL Slave mode Page 120 of 222 S6J3200 Series (4) SPI Supported (SCR: SPI=1), and Mark Level "L" of Serial Clock Output (SMR: SCINV=1) (Condition: See 8.2. Operation Assurance ) Parameter Serial clock cycle time SCK -> SOT delay time Valid SIN -> SCK setup time SCK -> Valid SIN hold time SOT -> SCK delay time Symbol Pin Name Conditions Min Max 3tCLK_LCPnA*1 - 3tCLK_LCPnA*2 - SCK16 to SCK17 3tCLK_COMP - SCK0 to SCK4, SCK8 to SCK12, SOT0 to SOT4, SOT8 to SOT12, SCK16 to SCK17 SOT16 to SOT17 0 30 0 20*3 0 15 26.5 - 20*3 - 20 - 0 - SCK0 to SCK4, SCK8 to SCK12 tSCYC tSLOVI tIVSHI tSHIXI tSOVHI Document Number: 002-05682 Rev. *K Value SCK0 to SCK4, SCK8 to SCK12, SIN0 to SIN4, SIN8 to SIN12, SCK16 to SCK17 SOT16 to SOT17 SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 SIN0 to SIN4, SIN8 to SIN12, SIN16 to SIN17 SCK0 to SCK4, SCK8 to SCK12 SOT0 to SOT4, SOT8 to SOT12 SCK16 to SCK17 SOT16 to SOT17 Master Mode (CL=20 pF, IOL=-5 mA, IOH=5 mA) 2tCLK_LCPnA*1 30 2tCLK_LCPnA*2 20 2tCLK_COMP 15 Unit Remarks ns ns ns ns ns - ns Page 121 of 222 S6J3200 Series Parameter Serial clock "H" pulse width Serial clock "L" pulse width SCK -> SOT delay time Symbol Pin Name Conditions Min Max SCK0 to SCK4, SCK8 to SCK12 2tCLK_LCPnA*1 - SCK16 to SCK17 2tCLK_COMP - 2tCLK_LCPnA*1 - 2tCLK_LCPnA*2 - 2tCLK_COMP - 2tCLK_LCPnA*2 tSHSL SCK0 to SCK4, SCK8 to SCK12 tSLSH SCK16 to SCK17 tSLOVE Value Slave Mode (CL=20 pF, IOL=-5 mA, IOH=5 mA) SCK16 to SCK17 SOT16 to SOT17 Valid SIN -> SCK setup time SCK -> Valid SIN hold time tIVSHE tSHIXE SCK falling time tF SCK rising time tR SCK0 to SCK4, SCK8 to SCK12 SCK16 to SCK17 SCK0 to SCK4, SCK8 to SCK12 SCK16 to SCK17 ns ns ns function digit 3 to 9 K to N 25*3 - 30 Remarks ns 28.5 SCK0 to SCK4, SCK8 to SCK12, SOT0 to SOT4, SOT8 to SOT12, SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 SIN0 to SIN4, SIN8 to SIN12, SIN16 to SIN17 Unit ns function digit B 25 10 ns Slave Mode (CL=20 pF, IOL=-5 mA, IOH=5 mA) - 11.5 1 function digit 3 to 9 K to N function digit B ns - 5 ns - 5 ns *1: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12 *2: n=0:Group2 of ch.0 /ch1, n=1:Group1 of ch.8 (refer to CHAPTER 11: Port Configuration in HWM) *3: Group2 of ch.0, ch1, Group1 of ch.8 (refer to CHAPTER 11: Port Configuration in HWM) Notes: - This table provides the alternate current standard for CLK synchronous mode. - - CL is the load capability value connected to the pin at the test time. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the hardware manual. Document Number: 002-05682 Rev. *K Page 122 of 222 S6J3200 Series tSCYC VOH VOH SCK VOL tSOVHI tSLOVI VOH VOL SOT VOH VOL tIVSHI tSHIXI VIH VIL SIN VIH VIL Master mode tSLSH tSHSL SCK VIL VIH VIH tF tR * SOT VOH VOL VIH tSLOV VOH VOL tSHIXE VIH VIL * Changes when writing to the TDR register Document Number: 002-05682 Rev. *K VIL E tIVSHE SIN VIL VIH VIL Slave mode Page 123 of 222 S6J3200 Series (5) Mark Level "H" of Serial Clock Output (SMR: SCINV=0) and Mark Level "H" of Serial Chip Select (SCSCR: CSLVL=1) (Condition: See 8.2. Operation Assurance ) Parameter Symbol Conditions SCSSCKsetup time tCSSI SCKSCShold time tCSHI Master mode (CL = 20 pF IOL=-5 mA, IOH=5 mA) SCS deselect time SCKSCSclock change time tCSDI tSCC Round Function Master mode (CL = 20 pF IOL=-5 mA, IOH=5 mA) Value Unit Min Max -20*1 - ns 0*2 - ns -20+5tcp*3 - ns 3tcp+0 3tcp+20 ns Remarks *1) SCSTR1.CSSU=0. tCSSI can be configured. *2) SCSTR0.CSHD=0. tCSHI can be configured. *3) SCSTR3/2.CSDS=0. tCSDI can be configured. tcp is bus clock. Ch0-4 is CLK_LCP0A. Ch8-12 is CLK_LCP1A. Ch16-17 is CLK_COMP. Document Number: 002-05682 Rev. *K Page 124 of 222 S6J3200 Series Document Number: 002-05682 Rev. *K Page 125 of 222 S6J3200 Series (6) Mark Level "L" of Serial Clock Output (SMR: SCINV=1) and Mark Level "H" of Serial Chip Select (SCSCR: CSLVL=1) (Condition: See 8.2. Operation Assurance ) Parameter Symbol Conditions SCSSCKsetup time tCSSI SCKSCShold time tCSHI Master mode (CL = 20 pF IOL=-5 mA, IOH=5 mA) SCS deselect time SCKSCSclock change time tCSDI tSCC Round Function Master mode (CL = 20 pF IOL=-5 mA, IOH=5 mA) Value Unit Min Max -20*1 - ns 0*2 - ns -20+5tcp*3 - ns 3tcp+0 3tcp+20 ns Remarks *1) SCSTR1.CSSU=0. tCSSI can be configured. *2) SCSTR0.CSHD=0. tCSHI can be configured. *3) SCSTR3/2.CSDS=0. tCSDI can be configured. tcp is bus clock. Ch0-4 is CLK_LCP0A. Ch8-12 is CLK_LCP1A. Ch16-17 is CLK_COMP. Document Number: 002-05682 Rev. *K Page 126 of 222 S6J3200 Series Document Number: 002-05682 Rev. *K Page 127 of 222 S6J3200 Series (7) Mark Level "H" of Serial Clock Output (SMR: SCINV=0) and Mark Level "L" of Serial Chip Select (SCSCR: CSLVL=0) (Condition: See 8.2. Operation Assurance ) Parameter Symbol Conditions SCSSCKsetup time tCSSI SCKSCShold time tCSHI Master mode (CL = 20 pF IOL=-5 mA, IOH=5 mA) SCS deselect time SCKSCSclock change time tCSDI tSCC Round Function Master mode (CL = 20 pF IOL=-5 mA, IOH=5 mA) Value Unit Min Max -20*1 - ns 0*2 - ns -20+5tcp*3 - ns 3tcp+0 3tcp+20 ns Remarks *1) SCSTR1.CSSU=0. tCSSI can be configured. *2) SCSTR0.CSHD=0. tCSHI can be configured. *3) SCSTR3/2.CSDS=0. tCSDI can be configured. tcp is bus clock. Ch0-4 is CLK_LCP0A. Ch8-12 is CLK_LCP1A. Ch16-17 is CLK_COMP. Document Number: 002-05682 Rev. *K Page 128 of 222 S6J3200 Series Document Number: 002-05682 Rev. *K Page 129 of 222 S6J3200 Series (8) Mark Level "L" of Serial Clock Output (SMR: SCINV=1) and Mark Level "L" of Serial Chip Select (SCSCR: CSLVL=0) (Condition: See 8.2. Operation Assurance ) Parameter Symbol Conditions SCSSCKsetup time tCSSI SCKSCShold time tCSHI Master mode (CL = 20 pF IOL=-5 mA, IOH=5 mA) SCS deselect time SCKSCSclock change time tCSDI tSCC Round Function Master mode (CL = 20 pF IOL=-5 mA, IOH=5 mA) Value Unit Min Max -20*1 - ns 0*2 - ns -20+5tcp*3 - ns 3tcp+0 3tcp+20 ns Remarks *1) SCSTR1.CSSU=0. tCSSI can be configured. *2) SCSTR0.CSHD=0. tCSHI can be configured. *3) SCSTR3/2.CSDS=0. tCSDI can be configured. tcp is bus clock. Ch0-4 is CLK_LCP0A. Ch8-12 is CLK_LCP1A. Ch16-17 is CLK_COMP. Document Number: 002-05682 Rev. *K Page 130 of 222 S6J3200 Series Document Number: 002-05682 Rev. *K Page 131 of 222 S6J3200 Series 8.4.6.3 LIN Interface (v2.1) (LIN Communication Control Interface (v2.1)) Timing (SMR: MD2-0=0b011) (1) External Clock Selected (BGR: EXT=1) (Condition: See 8.2. Operation Assurance ) Parameter Serial clock "L" pulse width Serial clock "H" pulse width Symbol Pin Name tSLSH tSHSL tF SCK rising time tR Unit Min Max SCK0 to SCK4, SCK8 to SCK12 tCLK_LCPnA*1+1 0 - ns SCK16 to SCK17 tCLK_COMP +10 - ns tCLK_LCPnA*1+1 0 - ns tCLK_COMP +10 - ns - 5 ns - 5 ns SCK0 to SCK4, SCK8 to SCK12 SCK16 to SCK17 SCK falling time Value Conditions (CL = 50 pF, IOL=-2 mA, IOH=2 mA), (CL=20 pF, IOL=-1 mA, IOH=1 mA) SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 Remarks *1: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12 tR SCK VIL tF tSHSL VIH VIH VIL tSLSH VIL VIH External clock selected Document Number: 002-05682 Rev. *K Page 132 of 222 S6J3200 Series 8.4.6.4 I2C Timing (SMR: MD2-0=0b100) (Condition: See 8.2. Operation Assurance ) Parameter Symbol SCL clock frequency fSCL Repeat "start" condition hold time SDA SCL tHDSTA Period of "L" for SCL clock Period of "H" for SCL clock tLOW tHIGH Pin Name SCL4, 10, 12, 16, and 17 SDA4, 10, 12, 16, and 17 SCL4, 10, 12, 16, and 17 SCL4, 10, 12, 16, and 17 SCL4, 10, 12, 16, and 17 SDA4, 10, 12, 16, and 17 SCL4, 10, 12, 16, and 17 SDA4, 10, 12, 16, and 17 SCL4, 10, 12, 16, and 17 SDA4, 10, 12, 16, and 17 SCL4, 10, 12, 16, and 17 SDA4, 10, 12, 16, and 17 SCL4, 10, 12, 16 and 17 Repeat "start" condition setup time SCL SDA tSUSTA Data hold time SCL SDA tHDDAT Data setup time SDA SCL tSUDAT "Stop" condition setup time SCL SDA tSUSTO Bus-free time between "stop" condition and "start" condition tBUF - Noise filter tSP - Notes: - *1: Conditions (CL = 50 pF, IOL=-2 mA, IOH=2 mA), (CL=20 pF, IOL=-1 mA, IOH=1 mA) Standard Mode Min Max Fast Mode Min Max Unit 0 100 0 400 kHz 4.0 - 0.6 - s 4.7 - 1.3 - s 4.0 - 0.6 - s 4.7 - 0.6 - s 0 3.45*1 0 0.9*2 s 250 - 100 - ns 4.0 - 0.6 - s 4.7 - 1.3 - s - ns 2tCLK_ COMP - 2tCLK_ COMP Remarks The maximum tHDDAT only has to be met if the device does not extend the "L" width (t LOW) of the SCL signal. - *2: - SCL4, 10, 12 and SDA4, 10, 12 only support the standard mode. A fast mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of "tSUDAT 250 ns". Document Number: 002-05682 Rev. *K Page 133 of 222 S6J3200 Series SDA tSUDAT tSUSTA tBUF tLOW SCL tHDSTA tHDDAT Document Number: 002-05682 Rev. *K tHIGH tHDSTA tSP tSUSTO Page 134 of 222 S6J3200 Series 8.4.7 Timer Input (Condition: See 8.2. Operation Assurance ) Parameter Symbol Input pulse width Pin Name Conditions PPG0_TIN1 to PPG11_TIN1 ICU0_IN0 to ICU11_IN0, ICU0_IN1 to ICU11_IN1 FRT0_TEXT to FRT11_TEXT TIN0 to TIN3, TIN16 to TIN19 tTWH, tTWL Min Value 4tCLK_LCPnA*1 - 100 Max Unit - ns - ns - ns - ns - ns - ns 4tCLK_LCPnA*2 - 100 4tCLK_LCPnA*2 100 4tCLK_LCPnA*3 100 4tCLK_LLPBM2 100 4tCLK_COMP 100 - TIN32 to TIN35 - TIN48 to TIN49 - Remarks 4tCLK_LCPnA*1 100 ns 4tCLK_LCPnA*1 <100 ns 4tCLK_LCPnA*2 100 ns 4tCLK_LCPnA*2 <100 ns 4tCLK_LCPnA*2 100 ns 4tCLK_LCPnA*2 <100 ns 4tCLK_LCPnA*3 100 ns 4tCLK_LCPnA*3 <100 ns 4tCLK_LLPBM2 100 ns 4tCLK_LLPBM2 <100 ns 4tCLK_COMP 100 ns 4tCLK_COMP <100 ns *1: n=0:ch.0 to ch.5, n=1:ch.6 to ch.11 *2: n=0:ch.0 to ch.7, n=1:ch.8 to ch.11 *3: n=0:ch.0 to ch.3, n=1:ch.16 to ch.19 - Timer input timing PPGx_TIN1 ICUx_IN0/1 FRTx_TEXT TINx tTIWH VIH Document Number: 002-05682 Rev. *K tTIWL VIH VIL VIL Page 135 of 222 S6J3200 Series 8.4.8 Trigger Input (Condition: See 8.2. Operation Assurance ) Parameter Input pulse width - Symbol Pin Name Conditions tTRGH, tTRGL EINT0 to EINT15 - Min 100 Value Max - Unit Remarks ns Trigger input timing tTRGH EINTx VIH tTRGL VIH VIL Document Number: 002-05682 Rev. *K VIL Page 136 of 222 S6J3200 Series 8.4.9 NMI Input (Condition: See 8.2. Operation Assurance ) Parameter Input pulse width - Symbol Pin Name Conditions tNMIL NMIX - Min 300 Value Max - Unit Remarks ns NMIX input timing tNMIL NMIX VIH VIH VIL Document Number: 002-05682 Rev. *K VIL Page 137 of 222 S6J3200 Series 8.4.10 Low-Voltage Detection 8.4.10.1 LVDL0 (Condition: See 8.2. Operation Assurance ) Parameter Min Value Typ Max - 0.9 0.95 1.0 V - - 0.925 1.025 1.125 V - - - - 30 s Pin Name Conditions - Detection Voltage Release Voltage Level Detection Time Unit Remarks *1 *2 Notes: - *1: This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. - *2: After the brown-out event where the voltage level dips below the detection threshold for less than this time, the detection may occur or be canceled. 8.4.10.2 LVDH0 Note: - LVDH0 is only used to generate power-on reset. Refer to chapter Power-On Conditions for related parameters. 8.4.10.3 LVDL1 (Condition: See 8.2. Operation Assurance ) Value Parameter Detection Voltage Release Voltage Detection Voltage Release Voltage Detection Time Pin Name - Conditions LVDL1V=10 (Default) - Unit Min Typ Max 0.92 0.97 1.02 V 0.945 1.045 1.145 V 1.02 1.07 1.12 V 1.095 1.145 1.195 V - - 30 s Guaranteed MCU Operation Range Remarks No *1 - *2 LVDL1V=11 - - Notes: - *1: This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. - *2: After the brown-out event where the voltage level dips below the detection threshold for less than this time, the detection may occur or be canceled. Document Number: 002-05682 Rev. *K Page 138 of 222 S6J3200 Series 8.4.10.4 LVDH1 (Condition: See 8.2. Operation Assurance ) Value Parameter Supply Voltage Range Detection Voltage Release Voltage Detection Voltage Release Voltage Detection Voltage Release Voltage Detection Voltage Release Voltage Detection Voltage Release Voltage Detection Voltage Release Voltage Detection Voltage Release Voltage Detection Voltage Release Voltage Detection Voltage Release Voltage Detection Time Power supply voltage regulation Pin Name Conditions VCC5 - Unit Min Typ Max 4.5 - 5.5 V 2.20 2.35 2.50 V 2.30 2.45 2.60 V 2.60 2.75 2.90 V VCC5 2.70 2.85 3.00 V VCC5 2.70 2.85 3.00 V 2.80 2.95 3.10 V 3.40 3.60 3.80 V 3.50 3.70 3.90 V 3.60 3.80 4.00 V 3.70 3.90 4.10 V 3.80 4.00 4.20 V 3.90 4.10 4.30 V 4.00 4.20 4.40 V 4.10 4.30 4.50 V 4.20 4.40 4.60 V 4.30 4.50 4.70 V 4.40 4.65 4.90 V 4.50 4.75 5.00 V VCC5 Guaranteed MCU Operation Range Remarks - LVDH1V=0000 VCC5 VCC5 LVDH1V=0001 No *1 Yes - LVDH1V=0010 VCC5 VCC5 LVDH1V=0011 VCC5 VCC5 LVDH1V=0100 VCC5 VCC5 LVDH1V=0101 VCC5 VCC5 VCC5 LVDH1V=0110 (Default) VCC5 LVDH1V=0111 VCC5 VCC5 LVDH1V=Other VCC5 - - - - 30 s *2 VCC5 - -2 - 2 V/ms *3 Notes: - *1: This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage (3.5 V). - *2: After the brown-out event where the voltage level dips below the detection threshold for less than this time, the detection may occur or be canceled. - *3: Please suppress the change of the power supply within the range of the power-supply voltage regulation to do a lowvoltage detection by detecting voltage. Document Number: 002-05682 Rev. *K Page 139 of 222 S6J3200 Series - Following power supply voltage stability conditions need to be ensured. Moreover, the EXVRSTCNT bit in the SYSC0_SPECFGR register has to be "0" for Revision other than M, P. For Revision M, P (Condition: See 8.2. Operation Assurance ) Parameter VCC5 stability time after LVDH1 low voltage detection VCC12 stability time after LVDH1 low voltage detection Symbol Pin Name tFV5 VCC5 Conditions Value Unit Remarks - s VCC5>=2.7 V - s VCC12>=1.1 V Min Max 55 55 tFV12 VCC12 For except Revision M, P (Condition: See 8.2. Operation Assurance ) Parameter Symbol Pin Name VCC12 stability time after LVDH1 low voltage detection tFV12 VCC12 Conditions Value Min Max 588 - Unit Remarks s VCC12>=1.1 V LVDH1 detect voltage >=2.7V VCC5 tFV5 PSC_1 (*) 1.1V VCC12 tFV12 *: The behavior of PSC_1 depends on the EXVRSTCNT bit regardless of revision. If the bit is set to "1", PSC_1 keeps `H' level. Document Number: 002-05682 Rev. *K Page 140 of 222 S6J3200 Series 8.4.10.5 LVDL2 (Condition: See 8.2. Operation Assurance ) Value Parameter Supply Voltage Range Detection Voltage Release Voltage Detection Voltage Release Voltage Detection Voltage Release Voltage Detection Voltage Release Voltage Detection Time Pin Name Conditions VCC12 - Unit Guaranteed MCU Operation Range Remarks - - No *1 - *2 Min Typ Max 1.1 - 1.3 V 0.72 0.77 0.82 V 0.795 0.845 0.895 V 0.82 0.87 0.92 V VCC12 0.895 0.945 0.995 V VCC12 0.92 0.97 1.02 V 0.995 1.045 1.095 V 1.02 1.07 1.12 V 1.095 1.145 1.195 V - - 30 s VCC12 VCC12 LVDL2V=00 (Default) VCC12 LVDL2V=01 LVDL2V=10 VCC12 VCC12 LVDL2V=11 VCC12 - - Notes: - *1: This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage (1.1 V). - *2: After the brown-out event where the voltage level dips below the detection threshold for less than this time, the detection may occur or be canceled. Document Number: 002-05682 Rev. *K Page 141 of 222 S6J3200 Series 8.4.10.6 LVDH2 (Condition: See 8.2. Operation Assurance ) Value Parameter Supply Voltage Range Detection Voltage Release Voltage Detection Voltage Release Voltage Detection Voltage Release Voltage Detection Time Power supply voltage regulation Pin Name Conditions VCC3 - VCC3 VCC3 LVDH2V=0000 (Default) VCC3 Unit Guaranteed MCU Operation Range Remarks - - No *1 Yes - Min Typ Max 3.0 - 3.6 V 2.2 2.35 2.5 V 2.3 2.45 2.6 V 2.6 2.75 2.9 V 2.7 2.85 3.0 V 2.7 2.85 3.0 V 2.8 2.95 3.1 V LVDH2V=0001 VCC3 VCC3 LVDH2V=0010 VCC3 - - - - 30 s - *2 VCC5 - -2 - 2 V/ms - *3 Notes: - *1: These LVD settings cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage (2.7 V). - *2: After the brown-out event where the voltage level dips below the detection threshold for less than this time, the detection may occur or be canceled. - *3: Suppress the change of the power supply within the range of the power-supply voltage regulation to do a low-voltage detection by detecting voltage. Document Number: 002-05682 Rev. *K Page 142 of 222 S6J3200 Series 8.4.11 High Current Output Slew Rate (Condition: See 8.2. Operation Assurance ) Parameter Symbol Pin Name Conditions Output rise / fall time tR2,tF2 P3_21 to 31, P4_00 to 12 - Document Number: 002-05682 Rev. *K Min Value Typ Max 15 - 100 Unit ns Remarks Load capacitance 85 pF Page 143 of 222 S6J3200 Series 8.4.12 Display Controller 8.4.12.1 Display Controller0 Timing (TTL Mode) (Condition: See 8.2. Operation Assurance ) Parameter Clock Cycle Symbol Pin Name tDC0CYC DSP0_CLK Data/Control output to DSP0_CLK time tDC0S DSP0_CLK to Data/Control valid time tDC0H Data/Control output to DSP0_CLK time tDC0S DSP0_CLK to Data/Control valid time Conditions (CL = 20 pF, IOL=-10 mA, IOH=10 mA) DSP0_DATA0_11-0 DSP0_DATA1_11-0 DSP0_CTRL4-0 (CL = 20 pF, IOL=-5 mA, IOH=5 mA) DSP0_CTRL11-0 tDC0H Value Min 15.625 20 tDCOCYC - 7.3 tDCOCYC - 5.6 tDCOCYC - 6.4 tDCOCYC - 5.0 0.8 -1.3 0.6 -5.1 tDCOCYC - 8.7 tDCOCYC - 8.4 tDCOCYC - 8.2 tDCOCYC - 5.0 0.8 -1.5 0.6 -5.1 Max - Unit Remarks ns ns *1 *2 ns - ns - ns - ns *3 *4 *5 *6 *3 *4 *5 *6 *3 *4 *5 *6 *3 *4 *5 *6 Pins in VCC3 domain If any of DSP0_ CTRL11 -0 in VCC53 domain is used Notes: - For *1, when used with DSP0_DATA* and DSP0_CTRL4-0 in VCC3 area. - - - - - - - For *2, when used with DSP0_CTRL11-0 in VCC53 area. For *3, it is targeted by the product series with function digit 3 to 9 and revision digit F. For *4, it is targeted by the product series with function digit 3 to 9 and revision digit M, P. For *5, it is targeted by the product series with function digit K to N. For *6, it is targeted by the product series with function digit B. Values valid for unshifted display clock (dsp_ClockInvert=0, dsp_ClockShift=0). The clock output delay can be adjusted. See Chapter "Graphic Subsystem" of TRM for details. t DC0CYC DSP0_CLK VOH VOH t DC0S DSP0_DATA0_11-0 DSP0_DATA1_11-0 DSP0_CTRL11-0 Document Number: 002-05682 Rev. *K t DC0H valid Page 144 of 222 S6J3200 Series 8.4.12.2 Display Controller0 Timing (RSDS) (Condition: See 8.2. Operation Assurance ) Parameter Symbol Pin Name Clock Cycle tRSCYC DSP0_CLK+ DSP0_CLK- Data output to DSP0_CLK time tRSS DSP0_CLK to Data valid time tRSH Control output to DSP0_CLK time tSPS Conditions Value 15.625 DSP0_DATA_D11~0+ DSP0_DATA_D11~0(CL = 20 pF, IOL=-4 mA, IOH=4 mA) DSP0_CTRL11~0 DSP0_CLK to Control valid time Min tSPH tRSCYC/2 - 5.0 tRSCYC/2 - 5.3 tRSCYC/2 - 5.0 tRSCYC/2 - 6.1 -0.1 -0.1 -0.1 0.5 tRSCYC - 9.1 tRSCYC - 10.1 tRSCYC - 9.0 tRSCYC - 11.4 1.1 1 1 2.1 Max - Unit Remarks ns - ns - ns - ns - ns *1 *2 *3 *4 *1 *2 *3 *4 *1 *2 *3 *4 *1 *2 *3 *4 Notes: - For *1, it is targeted by the product series with function digit 3 to 9 and revision digit F. - - - For *2, it is targeted by the product series with function digit 3 to 9 and revision digit M, P. - - Values valid for unshifted display clock (dsp_ClockInvert=0, dsp_ClockShift=0). For *3, it is targeted by the product series with function digit K to N. For *4, it is targeted by the product series with function digit B. The clock output delay can be adjusted. See the "Graphic Subsystem" chapter in the TRM for details. Document Number: 002-05682 Rev. *K Page 145 of 222 S6J3200 Series Document Number: 002-05682 Rev. *K Page 146 of 222 S6J3200 Series 8.4.12.3 Display Controller1 Timing (Condition: See 8.2. Operation Assurance ) Parameter Clock Cycle Data/Control output to DSP1_CLK time Symbol Pin Name tDC1CYC DSP1_CLK tDC1S Conditions DSP1_DATA0_11-0 DSP1_DATA1_11-0 DSP1_CTRL2-0 (CL = 20 pF, IOL=-5 mA, IOH=5 mA), Value Min 20.0 tDC1CYC - 4.3 tDC1CYC - 4.2 tDC1CYC - 4.1 -4.7 -2.4 -2.3 DSP1_CLK to tDC1H Data/Control valid time Notes: - For *1, it is targeted by the product series with function digit 3 to 9 and revision digit F. - - - - Max - Unit Remarks ns - ns - ns *1 *2 *3 *1 *2 *3 For *2, it is targeted by the product series with function digit 3 to 9 and revision digit M, P. For *3, it is targeted by the product series with function digit K to N. Values valid for unshifted display clock (dsp_ClockInvert=0, dsp_ClockShift=0). The clock output delay can be adjusted. See the "Graphic Subsystem" chapter in the TRM for details. t DC1CYC DSP1_CLK VOH VOH t DC1S DSP1_DATA0_11-0 DSP1_DATA1_11-0 DSP1_CTRL2-0 Document Number: 002-05682 Rev. *K t DC1H valid Page 147 of 222 S6J3200 Series 8.4.13 Video Capture 8.4.13.1 Video Capture Timing (Condition: See 8.2. Operation Assurance ) Parameter Clock Cycle Capture data setup time Capture data hold time Symbol Pin Name tCAP0CYC CAP0_CLK tCAP0SU CAP0_DATA35~0 tCAP0HD CAP0_DATA35~0 Conditions - Min 12.5 Value Max - Unit Remarks ns 4.0 - ns 1.0 - ns tCAP0CYC CAP0_CLK VIH VIH VIH tCAP0SU CAP0_DATA35-0 tCAP0HD valid VIH VIL Document Number: 002-05682 Rev. *K Page 148 of 222 S6J3200 Series 8.4.14 FPD-Link (LVDS) 8.4.14.1 For Revision M, P (See Figure 2-1: Option and Part Number for S6J320C.) (Condition: See 8.2. Operation Assurance ) Parameter Symbol Conditions f - CL = 5 pF (differential) delta VCM TCIP TCDT TPLLL - TC2C - - - TCSK - - - 200 ps TDSK - - - 50 ps T0 -0.235 0 +0.235 ns T1 1/7xT -0.235 1/7xT 1/7xT +0.235 ns T2 2/7xT -0.235 2/7xT 2/7xT +0.235 ns 3/7xT -0.235 3/7xT 3/7xT +0.235 ns T4 4/7xT -0.235 4/7xT 4/7xT +0.235 ns T5 5/7xT -0.235 5/7xT 5/7xT +0.235 ns T6 6/7xT -0.235 6/7xT 6/7xT +0.235 ns T0 -0.25 0 +0.25 ns T1 1/7xT -0.25 1/7xT 1/7xT +0.25 ns T2 2/7xT -0.25 2/7xT 2/7xT +0.25 ns 3/7xT -0.25 3/7xT 3/7xT +0.25 ns T4 4/7xT -0.25 4/7xT 4/7xT +0.25 ns T5 5/7xT -0.25 5/7xT 5/7xT +0.25 ns T6 6/7xT -0.25 6/7xT 6/7xT +0.25 ns VOD Differential output voltage delta VOD Common mode voltage Variation of VCM Cycle time of TXCLKP/M Duty of TXCLKP/M Internal PLL lockup time Cycle to cycle jitter Channel to Channel skew of TXOUTxP/M Skew of TXOUTxP and TXOUTxM Output pulse position for bit 0 Output pulse position for bit 1 Output pulse position for bit 2 Output pulse position for bit 3 Output pulse position for bit 4 Output pulse position for bit 5 Output pulse position for bit 6 Output pulse position for bit 0 Output pulse position for bit 1 Output pulse position for bit 2 Output pulse position for bit 3 Output pulse position for bit 4 Output pulse position for bit 5 Output pulse position for bit 6 Document Number: 002-05682 Rev. *K T3 T3 RL = 100 f = 50 MHz f = 40 MHz Max 50 390 450 505 25 1.325 1.375 25 200 10 0.11 xT/7 Unit VCM Output clock frequency Variation of VOD Value Typ 300 350 400 1.200 1.250 T 4/7xT - Min 5 210 250 295 1.075 1.125 20 - MHz mV mV mV mV V V mV ns ns ms Remarks One of three is selectable One of two is selectable Equals 1/f ns Page 149 of 222 S6J3200 Series Parameter Min Value Typ Max T0 -0.45 0 +0.45 ns T1 1/7xT -0.45 1/7xT 1/7xT +0.45 ns T2 2/7xT -0.45 2/7xT 2/7xT +0.45 ns 3/7xT - 0.45 3/7xT 3/7xT +0.45 ns T4 4/7xT -0.45 4/7xT 4/7xT +0.45 ns T5 5/7xT -0.45 5/7xT 5/7xT +0.45 ns T6 6/7xT -0.45 6/7xT 6/7xT +0.45 ns T0 -2.00 0 +2.00 ns T1 1/7xT -2.00 1/7xT 1/7xT +2.00 ns T2 2/7xT -2.00 2/7xT 2/7xT +2.00 ns 3/7xT -2.00 3/7xT 3/7xT +2.00 ns T4 4/7xT -2.00 4/7xT 4/7xT +2.00 ns T5 5/7xT -2.00 5/7xT 5/7xT +2.00 ns T6 6/7xT -2.00 6/7xT 6/7xT +2.00 ns Symbol Output pulse position for bit 0 Output pulse position for bit 1 Output pulse position for bit 2 Output pulse position for bit 3 Output pulse position for bit 4 Output pulse position for bit 5 Output pulse position for bit 6 Output pulse position for bit 0 Output pulse position for bit 1 Output pulse position for bit 2 Output pulse position for bit 3 Output pulse position for bit 4 Output pulse position for bit 5 Output pulse position for bit 6 T3 T3 Conditions f = 25 MHz f = 5 MHz Unit Remarks Notes: - All the corresponding ports of products which don't support FPD-Link should be connected to GND. AVCC3_LVDS_PLL, AVSS3_LVDS_PLL, VCC3_LVDS_Tx, VSS3_LVDS_Tx, TxDOUTn+/-, TxCLK+/-. - Channel to Channel skew of TXOUTxP/M is included in output pulse position. Document Number: 002-05682 Rev. *K Page 150 of 222 S6J3200 Series 8.4.14.2 For Revision F (See Figure 2-1: Option and Part Number for S6J320C.) (Condition: See 8.2. Operation Assurance ) Parameter Symbol Conditions f - MHz mV mV mV mV V V mV ns ns Unit CL = 5 pF (differential) delta VCM TCIP TCDT - TCSK - - - 200 ps TDSK - - - 50 ps T0 -0.25 0 +0.25 ns T1 1/7xT -0.25 1/7xT 1/7xT +0.25 ns T2 2/7xT -0.25 2/7xT 2/7xT +0.25 ns 3/7xT -0.25 3/7xT 3/7xT +0.25 ns T4 4/7xT -0.25 4/7xT 4/7xT +0.25 ns T5 5/7xT -0.25 5/7xT 5/7xT +0.25 ns T6 6/7xT -0.25 6/7xT 6/7xT +0.25 ns VOD Differential output voltage delta VOD Common mode voltage Variation of VCM Cycle time of TXCLKP/M Duty of TXCLKP/M Channel to Channel skew of TXOUTxP/M Skew of TXOUTxP and TXOUTxM Output pulse position for bit 0 Output pulse position for bit 1 Output pulse position for bit 2 Output pulse position for bit 3 Output pulse position for bit 4 Output pulse position for bit 5 Output pulse position for bit 6 Max 50 390 450 505 25 1.325 1.375 25 100 - VCM Output clock frequency Variation of VOD Value Typ 300 350 400 1.200 1.250 T 4/7xT Min 10 210 250 295 1.075 1.125 20 - T3 RL = 100 f = 50 MHz Remarks One of three is selectable One of two is selectable Equals 1/f Notes: - All the corresponding ports of products which don't support FPD-Link should be connected to GND. AVCC3_LVDS_PLL, AVSS3_LVDS_PLL, VCC3_LVDS_Tx, VSS3_LVDS_Tx, TxDOUTn+/-, TxCLK+/-. - Channel to Channel skew of TXOUTxP/M is included in output pulse position. Document Number: 002-05682 Rev. *K Page 151 of 222 S6J3200 Series Figure 8-6: LVDS AC Timing Chart TCIP TxCLK TH TxDOUT3 D3 D2 D1 TCDT = TH / (TH + TL) TL D0 D6 D5 D4 D3 D2 D1 D0 D6 TCSK TxDOUT2 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 D6 TxDOUT1 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 D6 TxDOUT0 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 D6 T0 T1 T2 T3 T4 T5 T6 Document Number: 002-05682 Rev. *K Page 152 of 222 S6J3200 Series Figure 8-7: LVDS AC Timing Chart Single End Common voltage for each data bit Tx-M Voltage [V] Delta VCM Tx-P VOD VCM Delta VOD = VOD.max - VOD.min 0 Tx-M Voltage [V] VCM Tx-P TDSK 0 Document Number: 002-05682 Rev. *K Page 153 of 222 S6J3200 Series 8.4.15 DDR-HSSPI DDR-HSSPI AC characteristics are specified with the specific reference voltage of VIL, VIH, VOL, VOH = 0.5 Vcc3 as mentioned in Section 8.4.3, regardless of automotive input-level configuration, CMOS Schmitt, and TTL. 8.4.15.1 DDR-HSSPI Interface Timing (SDR Mode) (Condition: See 8.2. Operation Assurance ) Parameter Pin Name HSSPI clock cycle tcyc G_SCLK0 M_SCLK0 20 - G_SCLK -> delayed sample clock tspcnt - 0 31.5 ns *1 - ns *1 - ns - tcyc/2 + 2 ns tcyc/2 - 3 - ns 12.00+(SS 2CD+0.5)*t cyc - ns tcyc - 2 - ns GSDATA -> G_SCLK Input setup time tisdata G_SCLK -> GSDATA Input hold time tihdata G_SCLK -> GSDATA Output delay time toddata G_SCLK -> GSDATA Output hold time tohdata GSSEL -> G_SCLK Output delay time todsel G_SDATA0_0-3 G_SDATA1_0-3 M_SDATA0_0-3 M_SDATA1_0-3 G_SDATA0_0-3 G_SDATA1_0-3 M_SDATA0_0-3 M_SDATA1_0-3 G_SDATA0_0-3 G_SDATA1_0-3 M_SDATA0_0-3 M_SDATA1_0-3 G_SDATA0_0-3 G_SDATA1_0-3 M_SDATA0_0-3 M_SDATA1_0-3 Conditions (CL = 20 pF, IOL=-10 mA, IOH=10 mA), G_SSEL0, 1 M_SSEL0, 1 G_SCLK -> GSSEL G_SSEL0, 1 tohsel M_SSEL0, 1 Output hold time Notes: - SS2CD [1:0] should be configured as 01, 10, or 11. - Value Symbol Min 10 Max - Unit ns Remarks when Quad Page Program For *1, the delay of the delay sample clock can be configured (DLP function). Document Number: 002-05682 Rev. *K Page 154 of 222 S6J3200 Series tcyc G_SCLK 0 VOH VOH tspcnt V OH Delayed sample clock V IH G_SDATA0_0-3, G_SDATA1_0-3 (input timing) VIH valid V IL G_SDATA 0_0-3, G_SDATA 1_0-3 (output timing) GSSEL 0, 1 (outputtiming) t isdata tihdata toddata V IL tohdata V OH V OH valid todsel VOL Document Number: 002-05682 Rev. *K VOL V OL tohsel V OH Page 155 of 222 S6J3200 Series 8.4.15.2 DDR-HSSPI Interface Timing (DDR Mode) (Condition: See 8.2. Operation Assurance ) Parameter Pin Name HSSPI clock cycle tcyc G_SCLK0 M_SCLK0 12.5 - ns G_SCLK -> delayed sample clock tspcnt - 0 31.5 ns *1 - ns *1 - ns - tcyc/4 + 1.5 ns Tcyc/4 1.0 - ns - ns - ns GSDATA -> G_SCLK Input setup time tisdata G_SCLK -> GSDATA Input hold time tihdata G_SCLK -> GSDATA Output delay time toddata G_SCLK -> GSDATA Output hold time tohdata GSSEL -> G_SCLK Output delay time todsel G_SDATA0_0-3 G_SDATA1_0-3 M_SDATA0_0-3 M_SDATA1_0-3 G_SDATA0_0-3 G_SDATA1_0-3 M_SDATA0_0-3 M_SDATA1_0-3 G_SDATA0_0-3 G_SDATA1_0-3 M_SDATA0_0-3 M_SDATA1_0-3 G_SDATA0_0-3 G_SDATA1_0-3 M_SDATA0_0-3 M_SDATA1_0-3 Conditions (CL = 20 pF, IOL=-10 mA, IOH=10 mA), G_SSEL0, 1 M_SSEL0, 1 G_SCLK -> GSSEL G_SSEL0, 1 tohsel M_SSEL0, 1 Output hold time Notes: - SS2CD [1:0] should be configured as 01, 10, or 11. - Value Symbol Min 15.75+(SS 2CD+0.5)*t cyc 0.75*tcyc 2.0 Max Unit Remarks For *1, the delay of the delay sample clock can be configured (DLP function). Document Number: 002-05682 Rev. *K Page 156 of 222 S6J3200 Series tcyc G_SCLK0 VOH VOH VOL tspcnt delayed sample clock VOH VOL VIH G_SDATA0_0-3, G_SDATA1_0-3 (input timing) tisdata VIH tisdata valid VIL toddata todsel VOL Document Number: 002-05682 Rev. *K tihdata valid VIL VOH valid VOL G_SDATA0_0-3, G_SDATA1_0-3 (output timing) GSSEL0, 1 (output timing) tihdata toddata tohdata tohdata valid VOH VOL tohsel VOL Page 157 of 222 S6J3200 Series 8.4.16 HyperBus HyperBus AC characteristics are specified with the specific reference voltage of VIL, VIH, VOL, VOH = 0.5Vcc3 as 8.4.3 regardless of input level configuration automotive, CMOS Schmitt, and TTL. 8.4.16.1 HyperBus Write Timing (HyperFlash) (Condition: See 8.2. Operation Assurance ) Parameter Symbol Pin Name Hyper Bus clock cycle tCKCYC G_CK M_CK CS -> CK Chip Select setup time tCSS G_CS#_1,2 M_CS#_1,2 DQ -> CK Setup time tIS G_DQ7-0 M_DQ7-0 Conditions (CL = 20 pF, IOL=-10 mA, IOH=10 mA), Remarks ns ns (A) (B) - ns (A) - ns (B) 1.25 - ns 1.25 - ns tCKCYC/2 - ns tCKCYC 3.25 tCKCYC -2.0 CK -> DQ G_DQ7-0 tIH M_DQ7-0 Hold time CK -> CS G_CS#_1,2 tCSH M_CS#_1,2 Chip select hold time Notes: - (A): The value will be targeted by the product series with revision digit A. - - Value Unit Min 12.5 10 Max - (B): The value will be targeted by the product series with after revision digit B. Hyper Bus clock cycle is always (1/FCLK_CD1)*4. Document Number: 002-05682 Rev. *K Page 158 of 222 S6J3200 Series 8.4.16.2 Hyper Bus Write Timing (HyperRAM) (Condition: See 8.2. Operation Assurance ) Parameter Hyper Bus clock cycle CS -> CK Chip Select setup time DQ -> CK Setup time CK -> DQ Hold time CK -> CS Chip select hold time RWDS-> CK Data Mask Valid Conditions Pin Name tCKCYC G_CK M_CK tCSS G_CS#_1,2 M_CS#_1,2 tCKCYC 3.25 tCKCYC 2.0 tIS G_DQ7-0 M_DQ7-0 tIH G_DQ7-0 M_DQ7-0 tCSH G_CS#_1,2 M_CS#_1,2 tDMV G_RWDS M_RWDS (CL = 20 pF, IOL=-10 mA, IOH=10 mA), CK -> RWDS G_RWDS tRIV M_RWDS Refresh Indicator Valid CK -> RWDS(Hi-z) G_RWDS tRIH M_RWDS Refresh Indicator Hold Notes: - (A): The value is targeted by the product series with revision digit A. - - - Value Symbol Unit Remarks ns ns (A) (B) - ns (A) - ns (B) 1.25 - ns 1.25 - ns tCKCYC/2 - ns 1 - ns - 6 ns 0 - ns Min 12.5 10 Max - (B): The value is targeted by the product series with after revision digit B. Hyper Bus clock cycle is always (1/FCLK_CD1)*4. When configuring the HyperBus clock cycle, take into account the HyperRAM refresh interval. Document Number: 002-05682 Rev. *K Page 159 of 222 S6J3200 Series 8.4.16.3 Hyper Bus Read Timing (HyperFlash) (Condition: See 8.2. Operation Assurance ) Parameter Symbol Pin Name Hyper Bus clock cycle tRDSCYC G_CK, G_RWDS M_CK, M_RWDS CS -> CK Chip Select setup time tCSS G_CS#_1,2 M_CS#_1,2 Conditions DQ -> CK G_DQ7-0 tIS (CL = 20 pF, M_DQ7-0 Setup time IOL=-10 mA, G_DQ7-0 CK -> DQ IOH=10 mA), tIH M_DQ7-0 Hold time CK -> CS G_CS#_1,2 tCSH M_CS#_1,2 Chip select hold time DQ-> RDS G_DQ7-0 tDSS M_DQ7-0 Setup time RDS-> DQ G_DQ7-0 tDSH M_DQ7-0 Hold time - (A): The value is targeted by the product series with revision digit A. - - - Min 12.5 Value 10 tRDSCYC 3.25 tRDSCYC -2.0 Unit Remarks ns (A) - ns (B) - ns (A) ns (B) Max - 1.25 - ns 1.25 - ns tRDSCYC / 2 - ns -0.8 -0.85 -0.8 -0.9 - ns ns (C) (C) (B): The value is targeted by the product series with after revision digit B. (C): The value is targeted by the product series with function digit 3 to 9 and revision digit H, M, P. Hyper Bus clock cycle is always (1/FCLK_CD1)*4. Document Number: 002-05682 Rev. *K Page 160 of 222 S6J3200 Series 8.4.16.4 Hyper Bus Read Timing (HyperRAM) (Condition: See 8.2. Operation Assurance ) Parameter Hyper Bus clock cycle CS -> CK Chip Select setup time DQ -> CK Setup time CK -> DQ Hold time CK -> CS Chip select hold time DQ-> RWDS (valid) Setup time Symbol tRDSCYC tCSS Pin Name Conditions G_CK, G_RWDS M_CK, M_RWDS G_CS#_1,2 M_CS#_1,2 tIS G_DQ7-0 M_DQ7-0 tIH G_DQ7-0 M_DQ7-0 tCSH G_CS#_1,2 M_CS#_1,2 tDSS G_DQ7-0 M_DQ7-0 (CL = 20 pF, IOL=-10 mA, IOH=10 mA), RWDS-> DQ (invalid) G_DQ7-0 tDSH M_DQ7-0 Hold time CK -> RWDS G_RWDS tRIV M_RWDS Refresh Indicator Valid CK -> RWDS(Hi-z) G_RWDS tRIH M_RWDS Refresh Indicator Hold Notes: - (A): The value is targeted by the product series with revision digit A. - - - - Min 12.5 Value Max - Unit Remarks ns (A) 10 - ns (B) tRDSCYC -3.25 tRDSCYC -2.0 - ns ns (A) (B) 1.25 - ns 1.25 - ns tRDSCYC /2 - ns -0.8 - -0.85 - -0.8 -0.9 - ns - 6 ns 0 - ns ns (C) (C) (B): The value is targeted by the product series with after revision digit B. (C): The value is targeted by the product series with function digit 3 to 9 and revision digit H, M, P. Hyper Bus clock cycle is always (1/FCLK_CD1)*4. When configuring the HyperBus clock cycle, take into account the HyperRAM refresh interval. Document Number: 002-05682 Rev. *K Page 161 of 222 S6J3200 Series 8.4.17 Ethernet AVB 8.4.17.1 Ethernet Receive Timing (Condition: See 8.2. Operation Assurance ) Parameter Symbol Pin Name RXCLK cylcle tRXCYC RX setup time tRXS RX hold time tRXH RXCLK RXER RXDV RXD0-3 RXER RXDV RXD0-3 Conditions - Min 40.0 Value Max - Unit Remarks ns 10.0 - ns 0 - ns tRXCYC -30ns tRXCYC RXCLK VIH VIH tRXS RXER RXDV RXD0-3 Document Number: 002-05682 Rev. *K tRXH VIH valid VIL Page 162 of 222 S6J3200 Series Ethernet Transmit Timing 8.4.17.2 (Condition: See 8.2. Operation Assurance ) Parameter TXCLK cylcle COL/CRS input setup time COL/CRS input hold time Tx delay time Symbol Pin Name tTXCYC RXCLK COL CRS tCRXS COL CRS TXER TXDV TXD0-3 tCRXH tTXD Conditions (CL = 20 pF, IOL=-5 mA, IOH=5 mA), Min 40.0 Value Max - Unit Remarks ns 12.0 - ns 0.5 - ns 0.5 25 ns tTXCYC VIH VIH VIH VIH TXCLK tCRXS tCRXH VIH COL CRS valid VIL TXER TXDV TXD0-3 Document Number: 002-05682 Rev. *K tTXD tTXD VOH valid VOL Page 163 of 222 S6J3200 Series 8.4.17.3 MDIO Timing (Condition: See 8.2. Operation Assurance ) Parameter MDC cylcle MDIO input setup time MDIO input hold time MDIO output delay time Symbol Pin Name tMDCYC MDC tMDIS MDIO tMDIH MDIO tMDOD MDIO Conditions Min 400.0 (CL = 20 pF, IOL=-5 mA, IOH=5 mA), Value Unit Max - Remarks ns 100.0 - ns 0.0 - ns 10.0 190.0 ns tMDCYC MDC VOH VOH VOH VOH VOL tMDIS tMDIH VIH MDIO (in) valid VIL tMDOD tMDOD VOH MDIO (out) valid VOL Document Number: 002-05682 Rev. *K Page 164 of 222 S6J3200 Series 8.4.18 MediaLB 8.4.18.1 MediaLB Input Timing (Condition: See 8.2. Operation Assurance ) Parameter Symbol Pin Name Conditions tmckc MLBCLK MLBCLK cycle MLBSIG, MLBDAT MLBSIG tdsmcf MLBDAT Input setup MLBSIG, MLBDAT MLBSIG tdhmcf MLBDAT Input hold Note: - CLK_HAPP1B0(internal) frequency > MLBCLK(external) frequency Min 40 Value Max - Unit Remarks ns 1.0 - ns 4.0 - ns tmckc MLBCLK VIH VIH VIL tdsmcf tdhmcf VIH MLBDAT, MLBSIG VIH valid VIL VIL Input Document Number: 002-05682 Rev. *K Page 165 of 222 S6J3200 Series 8.4.18.2 MediaLB Output Timing (Condition: See 8.2. Operation Assurance ) Parameter Symbol Pin Name Conditions Min 40 tmckc MLBCLK MLBCLK cycle MLBSIG, MLBDAT MLBSIG (CL = 20 pF, tmcfdz MLBDAT IOL=-6 mA, output stop IOH=6 mA), MLBSIG MLBSIG, MLBDAT tdout MLBDAT output delay Note: - CLK_HAPP1B0(internal) frequency > MLBCLK(external) frequency Value Max - Unit Remarks ns 26.5 - ns 0 13.5 ns tmckc - tdout tmckc MLBCLK VIH VIH tdout tmcfdz VOH MLBDAT, MLBSIG valid VOL Document Number: 002-05682 Rev. *K VOH VOL Page 166 of 222 S6J3200 Series 8.4.19 Port Noise Filter (Condition: See 8.2. Operation Assurance ) Parameter Value Symbol Pin Name Conditions Input pulse filtered - - Input pulse filtered - - 67 - ns Input pulse filtered - ALL GPIO EINT0-15 or TIN0-3, 16-19, 32-35, 48, 49 SCL4, 10, 12, 16, 17 Or SDA4, 10, 12, 16, 17 Min 67 - 240 - ns Max - Unit Remarks ns Note: - The spec guarantees that the rectangular pulse wider than min value is never removed. Document Number: 002-05682 Rev. *K Page 167 of 222 S6J3200 Series 8.4.20 JTAG (Condition: See 8.2. Operation Assurance ) Parameter Symbol TMS, TDI setup time tJTAGS TMS, TDI hold time tJTAGH TDO delay time tJTAGD JTAG_TCK Pin Name JTAG_TCK, JTAG_TMS, JTAG_TDI JTAG_TCK, JTAG_TMS, TDI JTAG_TCK, JTAG_TDO Conditions CL = 20 pF CL = 20 pF Value Min 16 Unit Max - 10 Remarks ns - ns CL = 20 pF - 25 ns VIH VIL tJTAGS tJTAGH JTAG_TMS VIH VIH JTAG_TDI VIL VIL tJTAGD JTAG_TDO VOH VOL Document Number: 002-05682 Rev. *K Page 168 of 222 S6J3200 Series 8.4.21 QPRC (Condition: See 8.2. Operation Assurance ) Parameter Symbol Pin Name "H" width of AIN "L" width of AIN tAHL tALL AIN AIN "H" width of BIN "L" width of BIN tBHL tBLL BIN BIN tAUBU BIN PC_Mode2 PC_mode3 tBUAD AIN tADBD Rising timing of BIN from "H" level of AIN Falling timing of AIN from "H" level of BIN Falling timing of BIN from "L" level of AIN Rising timing of AIN from "L" level of BIN Rising timing of AIN from "H" level of BIN Falling timing of BIN from "H" level of AIN Falling timing of AIN from "L" level of BIN Rising timing of BIN from "L" level of AIN "H" width of ZIN "L" width of ZIN Rising or falling timing of AIN/BIN from level valid timing of ZIN Level valid timing of ZIN from falling or rising timing of AIN/BIN Value Min 4tCLK_LCP1A 4tCLK_LCP1A Conditions Max Unit ns 4tCLK_LCP1A 4tCLK_LCP1A ns ns or 4tCLK_LCP1A ns PC_Mode2 PC_Mode3 or 4tCLK_LCP1A ns BIN PC_Mode2 PC_Mode3 or 4tCLK_LCP1A ns tBDAU AIN PC_Mode2 PC_Mode3 or 4tCLK_LCP1A ns 4tCLK_LCP1A ns AIN PC_Mode2 PC_Mode3 or tBUAU 4tCLK_LCP1A ns BIN PC_Mode2 PC_Mode3 or tAUBD tBDAD AIN PC_Mode2 PC_Mode3 or 4tCLK_LCP1A ns tADBU BIN PC_Mode2 PC_Mode3 or 4tCLK_LCP1A ns tZHL ZIN QCR:CGSC="0" 4tCLK_LCP1A ns tZLL ZIN QCR:CGSC="0" QCR:CGSC="1" 4tCLK_LCP1A 4tCLK_LCP1A ns ns QCR:CGSC="1" 4tCLK_LCP1A ns tZABE tABEZ Remarks AIN/BIN ZIN Note: - t is the period of peripheral clock(CLK) Document Number: 002-05682 Rev. *K Page 169 of 222 S6J3200 Series tALL tAHL AIN tAUBU tBUAD BIN tADBD tBDAU tBHL tBLL tBLL BHL BIN tBUAU tAUBD AIN tBDAD tADBU tAHL tALL tZHL ZIN tZLL Document Number: 002-05682 Rev. *K Page 170 of 222 S6J3200 Series ZIN tZABE tABEZ AIN/BIN Document Number: 002-05682 Rev. *K Page 171 of 222 S6J3200 Series 8.4.22 I2S 8.4.22.1 I2S Timing - Master mode (MSMD=1) (Condition: See 8.2. Operation Assurance ) Parameter Symbol Pin Name Conditions ECLK0/ECLK1 clock teck cycle ECLK0/ECLK1 clock ECLK0, tehw ECLK1 "H" pulse width ECLK0/ECLK1 clock telw "L" pulse width I2S clock cycle tsck (output SCK) I2S clock "H" pulse I2S0_SCK, (CL = 20 pF, tshw I2S1_SCK width IOL=-5 mA, IOH=5 mA) I2S clock "L" pulse tslw width CPOL=0, Sender delay time I2S0_SCK, SMPL=1 tdtr SCK -> SD/WS I2S1_SCK, valid I2S0_SD, I2S1_SD, Sender hold time I2S0_WS, thtr SCK -> SD/WS I2S1_WS invalid Receiver setup time I2S0_SCK, tsr SD valid -> SCK I2S1_SCK, I2S0_SD, Receiver hold time thr I2S1_SD SCK -> SD valid Notes: *1: ECKM = 1. Refer to the Resource Input Configuration chapter in Min Value Max Uni t Remarks 20 - ns 0.40* teck 0.60* teck ns 0.40* teck 0.60* teck ns 66.66 - ns 0.35* tsck 0.65* tsck ns 0.35* tsck 0.65* tsck ns - 26 ns *2 -10 - ns *2 21 - ns *2 10 - ns *2 Only relevant if external ECLK input is selected. *1 TRM for required RESSEL register settings. *2: See the I2S register description chapter in TRM for different combinations of clock polarity (CPOL), sampling point position (SMPL), polarity/pulse_width/frame_sync phase of WS (FSPL, FSLN, FSPH). Actual waveforms and relevant clock edges will change accordingly; the delay values as per above table will remain the same. t sck t shw t slw VOH VOH I2Sx_SCK VOL VOL t hdr t dtr I2Sx_SD, I2Sx_WS (output timing) VOH VOH VOL VOL t sr I2Sx_SD (input timing) Document Number: 002-05682 Rev. *K t hr VIH VIH VIL VIL Page 172 of 222 S6J3200 Series 8.4.22.2 I2S Timing - Slave mode (MSMD=0) (Condition: See 8.2. Operation Assurance ) Parameter Symbol Pin Name Conditions Min Value Max Uni t Remarks I2S clock cycle I2S0_SCK, tsck 66.66 ns I2S1_SCK (input SCK) I2S clock "H" pulse 0.40* 0.60* tshw ns tsck tsck width I2S0_SCK, I2S1_SCK 0.40* 0.60* I2S clock "L" pulse tslw ns tsck tsck width Setup time *1 tsrf 40 ns WS transition -> I2S0_SCK, (CL = 20 pF, SCK I2S1_SCK, IOL=-5 mA, I2S0_WS, Hold time IOH=5 mA) *1 I2S1_WS thrf 10 ns SCK -> WS CPOL=0, transition SMPL=0 Sender delay time I2S0_SCK, *1 tdtr 26 ns SCK -> SD valid I2S1_SCK, I2S0_SD, Sender hold time *1 thtr -10 ns I2S1_SD SCK -> SD invalid Receiver setup time I2S0_SCK, *1 tsr 21 ns SD valid -> SCK I2S1_SCK, I2S0_SD, Receiver hold time *1 thr 10 ns I2S1_SD SCK -> SD valid Note: *1: See the I2S register description chapter in the TRM for different combinations of clock polarity (CPOL), sampling point position (SMPL), polarity/pulse_width/frame_sync phase of WS (FSPL, FSLN, FSPH). Actual waveforms and relevant clock edges will change accordingly; the delay valuesbased on the table above will remain the same. Document Number: 002-05682 Rev. *K Page 173 of 222 S6J3200 Series 8.5 8.5.1 A/D Converter Electrical Characteristics (Condition: See 8.2. Operation Assurance ) Parameter - Min - Value Typ - Max 12 - - - - 12 4.0 LSB LSB *3 - AN0 to AN49 AN0 to AN49 AVRL -11.5LSB AVRH -13.5LSB - 1.9 AVRL +12.5LSB AVRH +10.5LSB LSB *4 tSMP - 0.3 - - s *1 tCMP tCNV - 0.8 1.1 - 28 - s s *1 Symbol Pin Name Resolution - Total Error Integral Non linearity Differential Non linearity Zero transition voltage Full-scale transition voltage Sampling time Compare time A/D conversion time VZT VFST - Unit Remarks bit *4 V *5 V *1 - - ns 4tCLK_LCP1A 100ns 4tCLK_LCP1A < 100ns - - 1 us - -1.0 - 1.0 A -2.0 - 2.0 A -3.0 - 3.0 A AVSS - AVRH V 4.5 - 0.0 5.5 - V V 4tCLK_LCP1A ADTRG A/D trigger input time Resumption time Analog port input current Analog input voltage Reference voltage Power supply current Variation between channels 100 - IAIN VAIN AVRH AVRL AN0 to AN17 AN18 to AN25 AN26 to AN49 AN0 to AN49 AVRH5 AVSS IA IAH AVCC - 500 1.0 900 100 A A IR IRH AVRH - 1.0 - 2.0 5.0 mA A - AN0 to AN49 - - 4.0 LSB *1: Time per channel *2: Definition of the power supply current (when VCC=AVCC=5.0 V) while the A/D converter is not operating and in stop mode *3: Total Error is a comprehensive static error that includes the linearity after trimming by software. 1LSB= (AVRH-AVRL)/4096 *4: 1LSB= (VFST-VZT)/4094 *5: 1LSB= (AVRH-AVRL)/4096 Document Number: 002-05682 Rev. *K VAVSS - VAINVAVCC AVCC AVRH *2 *2 Page 174 of 222 S6J3200 Series 8.5.2 Notes on A/D Converters About the Output Impedance of an External Circuit for Analog Input When the external impedance is too high, the analog voltage sampling time may become insufficient. In this case, we recommend attaching a capacitor (about 0.1 F) to an analog input pin. Analog input circuit model Comparator R Analog input Sampling ON C R C 12-bit A/D 3.9 k (max) 11.0 pF (max) (4.5 VAVCC5.5 V) Note: Use the numerical values provided here simply as a guide. 8.5.3 Glossary Resolution: Analog change that can be identified by an A/D converter Integral linearity error: Deviation of the straight line connecting the zero transition point ("0000 0000 0000" <--> "0000 0000 0001") and full-scale transition point ("1111 1111 1110" <--> "1111 1111 1111") from actual conversion characteristics Includes zero transition error, full-scale transition error, and non-linearity error. Differential linearity error: Deviation from the ideal value of the input voltage required for changing the output code by 1 LSB Total error: Difference between the actual value and the theoretical value. 8.5.4 Calibration Condition Calibration Condition should be the followings. AVCC=5.0 AVRH=5.0 V V TA=25C system clock frequency (CLK_LCP1A) = 10 MHz See A/D Converter Calibration in the S6J3200 hardware manual. Document Number: 002-05682 Rev. *K Page 175 of 222 S6J3200 Series Total error FFF Actual con ver FFE Digital output FFD 1.5LSB {1 LSB (N - 1) + 0.5LSB} VNT 004 (Actually-measured value) 003 Actual conversion characteristics 002 (measured value) Ideal characteristics 001 0.5LSB AVRL (AVSS) Analog input Total error of digital output N = 1LSB(Ideal value) = AVRH VNT- {1 LSB x (N-1) + 0.5LSB} 1LSB AVRH - AVRL [V] 4096 [LSB] N: A/D converter digital output value. VZT(Ideal value) = AVRL + 0.5LSB[V] VFST(Ideal value) = AVRH - 1.5LSB[V] VNT: Voltage at which the digital output changes from "(N - 1)" to "N". Document Number: 002-05682 Rev. *K Page 176 of 222 S6J3200 Series Integral linearity error Differential linearity error Ideal characteristics FFE Actual conversion characteristics FFD {1 LSB (N - 1) + VZT} 004 003 N+1 Actual conversion characteristics VFST Digital output Digital output FFF VNT (measured value) Actual conversion characteristics N N-1 V(N+1)T (measured VNT(measured value)value) 002 Ideal characteristics N-2 001 VZT (measured value) AVSS (AVRL) Analog input Integral linearity error of digital output N = Differential linearity error of digital output N = 1LSB = AVRH AVSS (AVRL) VNT- {1 LSB x (N-1) + VZT} 1LSB V(N+1) T- VNT 1LSB VFST - VZT (measured value) Actual conversion characteristics Analog input AVRH [LSB] -1 LSB [LSB] [V] 4094 VZT: Voltage for which digital output changes from "0x000" to "0x001" VFST: Voltage for which digital output changes from "0xFFE" to "0xFFF". Document Number: 002-05682 Rev. *K Page 177 of 222 S6J3200 Series 8.6 8.6.1 Audio DAC Electrical Characteristics (Condition: See 8.2. Operation Assurance ) Parameter system clock frequency sampling clock Analog output load resistance *2 Analog output load capacitance *2 capacitance Analog output single-end output range (full scale) Analog output voltage (zero) Value Typ Symbol Pin Name Conditions *1 FCLKDA0 - - 2.048 - 18.432 MHz fs - - 8 - 48 kHz - 20 - - k - - - 100 pF - 5 10 20 F RL=20 k CL=100 pF - 0.673 AVCC3_DAC - VP-P - - 0.5 AVCC3_DAC - V - -82 -72 dB 85 89 - dB 83 86 - dB 150 - 80 200 -35 -50 -40 -33 250 - dB dB dB dB dB - -13 - dB RL CL - - DAC_L DAC_R C_L C_R DAC_L DAC_R - THD+N *3 - - SNR *3 - - Dynamic range *3 - - Out-of-Band Energy Channel Separation Output impedance - - PSRR - - signal frequency: 1 kHz LPF(fc: 20 kHz) signal frequency: 1 kHz LPF(fc: 20 kHz)-- -- A-weighting filter 20 kHz to 64 fs noise 50 Hz digital input: noise 1 kHz zero noise 20 kHz digital input: full scale sine Min Unit Max Remarks Supply current AVCC3 2.2 3.2 mA _DAC normal operation Supply current AVCC3 100 A _DAC power-down DAE 650 *5 ms Startup Time *4 Notes: - *1: All parameters specified fs=44.1 kHz, system clock 256 fs and 16-bit data, RL-20 k, CL=100 pF, unless otherwise noted. - - - - *2: Refer to bellow note on RL load connection. *3: These values do not include the noise caused by the analog power supply. (Refer to 7. Use examples) *4: 10F is connected to C_L, C_R. *5: Startup time (Figure 8-8) Document Number: 002-05682 Rev. *K Page 178 of 222 S6J3200 Series Figure 8-8: Startup Time 10mV Last Volgate DAC_L/DAC_R DAE Startup Time Time [sec] Startup time can be calculated as follows. 1. Startup time (TYP) = 650[ms] (Table 5.2) 2. CCOM=10uFx(1/100) CCOM is a capacitor connected to Terminal C_L/C_R including capacitance variance. =Capacitance variance [%] 3. Startup time = Start up time (TYP)x(1) [ms] For example, CCOM=11F then = (11F-10F)/10F=10[%] So, Startup time = 650msx1+10/100 = 715[ms] Notes: - Two usages of RL load connection. - - Case1: RL is connected to AVCC3_DAC /2 (Figure 8-9) Case2: The coupling capacitance must be inserted as shown in (Figure 8-10). Figure 8-9: RL is Connected to AVCC_DAC/2 (Example) Document Number: 002-05682 Rev. *K Page 179 of 222 S6J3200 Series Figure 8-10: Coupling Capacitance (Example) Notes: - C1: more than 10 F low ESR capacitors - - - C2: 0.1 F ceramic capacitors C3, C4, C5, C6: 10 F low ESR capacitors Impedance of each power line must be as low as possible. Notes: - When DAC is not used in your system, the related pins should be - - - AVCC3_DAC=GND and AVSS=GND C_L=OPEN and C_R=OPEN DAC_L=OPEN and DAC_R=OPEN Document Number: 002-05682 Rev. *K Page 180 of 222 S6J3200 Series 8.7 Flash Memory Electrical Characteristics 8.7.1 Parameter Min Value Typ Max*3 Unit - 300 1100 ms - 800 3700 ms - 15 19 27 45 288 384 567 945 s s s s 8 kB Internal preprogramming time included 64 kB sector*1 Internal preprogramming time included System-level overhead time excluded*1 System-level overhead time excluded*1 System-level overhead time excluded*1 System-level overhead time excluded*1 - 19 384 s System-level overhead time excluded*1 - 23 483 s System-level overhead time excluded*1 - 31 651 s System-level overhead time excluded*1 - 49 1029 s System-level overhead time excluded*1 1,000/20 years 10,000/10 years 100,000/5 years - - - Temperature at write/erase time Average temperature TA=+85 degrees Celsius Sector erase time 8 bit write time 16 bit write time 32 bit write time 64 bit write time 8 bit (with ECC) write time 16 bit (with ECC) write time 32 bit (with ECC) write time 64 bit (with ECC) write time count*2 Erase / Data retention time Remarks sector*1 Notes: - *1: Guaranteed value for up to 100,000 erases - *2: Number of erases for each sector 8.7.2 Notes For revision M, P While the Flash memory is written or erased, shutdown of the external power (Vcc5 and Vcc12) is prohibited. In the application system, where Vcc5 and Vcc12 might be shut down while writing or erasing, be sure to turn the power off by using an external voltage detection function or external reset (RSTX). For external power supply voltage stability conditions please see chapter 8.4.4.2 and 8.4.10.4. For except revision M, P While the Flash memory is written or erased, shutdown of the external power (V CC5 and Vcc12) is prohibited. In the application system where VCC5 and Vcc12 might be shut down while writing or erasing, be sure to turn the power off by using an external voltage detection function. To put it concretely, after the external power supply voltage falls below the detection voltage (V DL), hold VCC5 at 2.7 V or more and Vcc12 at 1.1 V or more within the duration calculated by the following expression: Td*1 [s] + (1 / FCRF*2[MHz]) x 1029 + 25 [s] *1: See "8.4.10 Low-Voltage Detection" *2: See "8.4.1 Source Clock " Document Number: 002-05682 Rev. *K Page 181 of 222 S6J3200 Series 9. Abbreviation Abbreviation A/D converter ADC AHB AMBATM APB ATCM AXI B0TCM B1TCM BBU BDR BT BTL CAN CD CPU CR CRC CSV DAC DAP DED DMA DMAC EAM ECC ETM EXT-IRC FIQ FPU FRT GPIO HPM HW-WDT I/O I2S ICU IPCU IRC IRQ ISR JTAG LLPP LVD MCU MFS MLB Definition Remark Analog to Digital Converter Analog to Digital Converter Advanced High performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus TCM-A port Advanced eXtensible Interface TCM B0 port TCM B1 port Bit Banding Unit Boot Description Record Base Timer Bridge-Tied Load Control Area Network Clock Domain Central Processing Unit CR Oscillator Cyclic Redundancy Check Clock SuperVisor Digital Analog Converter Debug Access Port Dual Error Detection Direct Memory Access DMA Controller Exclusive Access Memory Error Correction Code Embedded Trace Macro External InteRrupt Controller Fast Interrupt Request Floating Point Unit Free-Run Timer General Purpose I/O High Performance Matrix Hardware Watchdog Timer Input or Output Inter-IC Sound Input Capture Unit Inter-Processor Communication Unit InteRrupt Controller InteRrupt Request Interrupt Service Routine Joint Test Action Group Low Latency Peripheral Port Low Voltage Detector MicroController Unit Multi-Function Serial interface Media LB Document Number: 002-05682 Rev. *K Page 182 of 222 S6J3200 Series Abbreviation NF NMI OCU OSC PCB PCBA PCM PD PLL PONR PPC PSC PSS PWM QPRC RAM RIC RLT ROM RSDS RTC RVD SCT SEC SECDED SG SHE SMC SMIX SPI SRAM SSCG SWFG SW-WDT SYSC TCFLASH TCM TCRAM TPU TSU UDC VIC VRAM WDR WDT WFG WorkFLASH Definition Remark Noise Filter Non Maskable Interrupt Output Compare Unit OSCillator Printed Circuit Board Printed Circuit Board Assembly Pulse Coded Module Power Domain Phase Locked Loop Power ON Reset Port Pin Configuration Power Supply Control Power Saving State Pulse Width Modulation Quad Position & Revolution Counter Random Access Memory Resource Input Configuration Reload Timer Read Only Memory Reduced Swing Differential Signal Real Time Clock Low Voltage Detection and Reset for RAM Retention Source Clock Timer Single Error Correction Single Error Correction and Dual Error Detection Sound Generator Secure Hardware Extension Stepper Motor Controller Sound Mixer Serial Peripheral Interface Static RAM Spread Spectrum Clock Generation Sound Waveform Generator Software Watchdog Timer System Controller FLASH connected to TCM Tightly Coupled Memory RAM connected to TCM Timing Protection Unit Time Stamp Unit Up-down Counter Vectored Interrupt Controller Video RAM Watchdog Description Record Watchdog Timer Waveform Generator Work FLASH Memory Document Number: 002-05682 Rev. *K Page 183 of 222 S6J3200 Series 10. Ordering Information Table 10-1: Order Part Number Table Part Number S6J32BAKSESE2000A S6J323CKSPSE20000 S6J323CLSPSC20000 S6J323CLUMSC20000 S6J323CLUPSC20000 S6J324CKSMSE2000A S6J324CKSPSE20000 S6J324CLSPSC20000 S6J325CKSFSE2000A S6J325CKSMSE20000 S6J325CKSPSE20000 S6J325CLSMSC20000 S6J325CLSPSC20000 S6J325CLUMSC20000 S6J325CLUPSC20000 S6J326CKSPSE20000 S6J326CLSMSC20000 S6J326CLSPSC20000 S6J327CKSMSE20000 S6J327CKSPSE20000 S6J327CLSMSC20000 S6J327CLSPSC20000 S6J327CLUMSC20000 S6J327CLUPSC20000 S6J328CKSPSE20000 S6J328CLSPSC20000 S6J328CLSPSC2D000 S6J329CKSMSE20000 Document Number: 002-05682 Rev. *K Package LER208 (208-pin plastic TEQFP) LET208 (208-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LET208 (208-pin plastic TEQFP) LET208 (208-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LET208 (208-pin plastic TEQFP) LET208 (208-pin plastic TEQFP) LET208 (208-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LET208 (208-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LET208 (208-pin plastic TEQFP) LET208 (208-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LET208 (208-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LET208 (208-pin plastic TEQFP) Page 184 of 222 S6J3200 Series Part Number S6J329CKSPSE20000 S6J329CKUMSE20000 S6J329CKUPSE20000 S6J329CLSPSC20000 S6J329CLSPSC2D000 S6J329CLUPSC20000 S6J32KEKSMSE20000 S6J32KELSMSC20000 S6J32LEKSMSE20000 S6J32LELSMSC20000 S6J32MEKSMSE20000 S6J32MELSMSC20000 S6J32NEKSMSE20000 S6J32NELSMSC20000 Package LET208 (208-pin plastic TEQFP) LET208 (208-pin plastic TEQFP) LET208 (208-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LET208 (208-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LET208 (208-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LET208 (208-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) LET208 (208-pin plastic TEQFP) LEQ216 (216-pin plastic TEQFP) *1 TEQFP-256 is for trace. It is under planning. Document Number: 002-05682 Rev. *K Page 185 of 222 S6J3200 Series 11. Errata This section describes the errata for the S6J3200 Series. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. Part Numbers Affected Part Number S6J32BAxSE S6J323CxxM/P S6J324CxSM/P S6J325CxxF/M/P S6J326CxSM/P S6J327CxxM/P S6J328CxSM/P S6J329CxxM/P S6J32KExSM S6J32LExSM S6J32MExSM S6J32NExSM S6J32B/3/4/5/6/7/8/9/K/L/M/N Qualification Status Product Status: Production Errata Summary The following table defines the errata applicability to available S6J3200 Series devices. Items MCAN wrong message transmission 1. Part Number S6J32BAxSE S6J323CxxM/P S6J324CxSM/P S6J325CxxF/M/P S6J326CxSM/P S6J327CxxM/P S6J328CxSM/P S6J329CxxM/P S6J32KExSM S6J32LExSM S6J32MExSM S6J32NExSM Fix Status Not be planned. MCAN wrong message transmission Problem Definition There is a possibility a message with an ID (arbitration field) and a format and DLC (control field) is transmitted which was not configured by the application. The message itself is syntactically correct and can be received by other nodes. The occurrence of the limitation requires a certain relationship in time between a transmission request for sending a Document Number: 002-05682 Rev. *K Page 186 of 222 S6J3200 Series message and the coincidence of noise in the 3rd bit of intermission field which is treated as the start of new message transmission (SoF). Trigger Condition Under the following conditions a message with wrong ID, format and DLC is transmitted: * M_CAN is in state "Receiver" (PSR.ACT = "10"), no pending transmission. * A new transmission is requested after sample point of 2nd bit of intermission but before the 3rd bit of Intermission is reached. * The CAN bus is sampled dominant at the third bit of Intermission which is treated as SoF (see ISO11898-1:2015 Section 10.4.2.2). Scope of Impact Under the conditions listed above it may happen, that: * The shift register is not loaded with ID, format, and DLC of the requested message. * The M_CAN will start arbitration with wrong ID, format, and DLC. * In case the ID won arbitration, a CAN message with valid CRC is transmitted. * In case this message is acknowledged, the ID stored in the Tx Event FIFO is the ID of the requested Tx message and not the ID of the message transmitted on the CAN bus * Neither an error is detected by the transmitting node nor at the receiving node. Workaround Workaround 1: This workaround avoids submitting a transmission request in the critical time window of about one bit time before the sample point of the 3rd bit of intermission field when on other pending transmission request exists: * Request a new transmission if another transmission is already pending or when the M_CAN / M_TTCAN is not in state "Receiver" (when PSR.ACT "10"). * If no pending transmission request exists, the application software needs to evaluate the Rx Interrupt flags IR.DRX, IR.RF0N, IR.RF1N which are set at the last bit of EoF when a received and accepted message gets valid. * A new transmission may be requested by writing to TXBAR once the Rx interrupt occurred and the application waited another 3 bit times before submitting its Tx request. Note the Rx interrupt is generated at the last bit of EoF which is followed by three bits of Intermission. * The application has to take care that the transmission request for the CAN Protocol Controller is activated before the critical window of the following reception is reached. A supplemental action can be applied in order to detect messages which contain wrong ID and control filed information: * A checksum covering arbitration and control fields can be added to the data field of the message to be transmitted, to detect frames transmitted with wrong arbitration and control fields. Document Number: 002-05682 Rev. *K Page 187 of 222 S6J3200 Series Workaround 2: This workaround ensures that always at least one pending Tx request exists. If that is the case, the application may launch its Tx requests at any time without suffering from the limitation. * Define a low priority message with DLC = 0 that can be sent without harm. E.g. loses arbitration against all other application messages, does not pass any acceptance filter of nodes in the same network. DLC = 0 shall reduce latency for other application messages. * Configure sufficient Tx buffers - at least two - for this message type thus that there is always another one waiting to be sent. E.g. an application that cannot react quickly enough with the time a single message of this type is sent, more than 2 Tx buffer may become necessary. * The application uses the standard interfaces of the CAN / CAN FD stack to feed these messages. * Whenever Tx confirmation is indicated for the second but last message of this type with pending Tx request, the application needs to submit at least one new Tx request. Note Tx confirmation is a standard feature in the AUTOSAR SW architecture. * Before initially leaving INIT state of the M_CAN IP by clearing CCCR.INIT bit, make sure to activate a Tx request after having cleared CCCR.CCE. This will ensure that the conditions for the occurrence of the limitation when synchronizing to the CAN bus the first time after RESET are prevented. Fix Status Not be planned. Document Number: 002-05682 Rev. *K Page 188 of 222 S6J3200 Series 12. Appendix 12.1 Application 1: JTAG tool Connection This is an application example of JTAG tool connection. See the relevant application note 002-09861 in detail. +5V0_S +5V0_S +5V0_S R R R JTAG Arm 20pin S6J3200 R R R R 112 114 116 115 JTAG_NTRST JTAG_TDI JTAG_TMS JTAG_TCK 20ohm 1 3 5 7 9 11 13 15 17 19 R 113 118 JTAG_TDO RSTX R 216pin PKG R DGND Document Number: 002-05682 Rev. *K R 2 4 6 8 10 12 14 16 18 20 Vsense nTRST TDI TMS TCK RTCK TDO nRESET Pull down Pull down VCC GND GND GND GND GND GND GND GND GND DGND DGND Page 189 of 222 S6J3200 Series 13. Major Changes Spansion Publication Number: S6J3200_DS708-00003 Page Section Revision 0.1 Revision 0.2 - Change Results - Initial release - See 11.1 Supplementary Information as described in "1.Overview 1.2. Document Definition" - See 11.1 Supplementary Information as described in "1.Overview 1.2. Document Definition" - See 11.1 Supplementary Information as described in "1.Overview 1.2. Document Definition" Revision 0.3 Revision 0.4 Revision 1.0 See 11.1 Supplementary Information as described in "1.Overview 1.2. Document Definition" NOTE: Please see "Document History" about later revised information. - - 13.1 Supplementary Information All the changes between previous and current document edition are described in this sheet. Following "ID" is a number which is owned by every change. A change which is applied to other documents of same family should have a same ID. Error Correct Page Error Page Summary Correct ID Original document code: DS708-00003-0v02-E, Previous document code: DS708-00003-0v01-E Rev. 1.0 December 26, 2014 Pin assignment 22, 23 (Relation on pin assignment) ||Function||PORT || ||MFS8_CS0||P3_08|| ||MFS9_CS0||P3_09|| ||MFS9_CS1||P3_10|| ||MFS8_CS3||P3_11|| ||MFS8_CS1||P3_12|| ||MFS8_CS2||P3_13|| I2S port name 22,23 I2S1_WS1 I2S1_SCK1 22,23 I2S1_WS I2S1_SCK #190 Ethernet port name 22,23 RDX0, RDX1, RDX2, RDX3 22,23 RXD0, RXD1, RXD2, RXD3 #191 62 Vss12: 1.15(min), 1.3(max) 1.1(min)*1, 1.3(max) - *1. The value will be for the product series with revision digit B. #169 Vcc12 power supply 62 Vss12: 1.15(min), 1.3(max) Document Number: 002-05682 Rev. *K 22, 23 (Relation on pin assignment) ||Function||PORT || ||MFS8_CS0||P3_12|| ||MFS9_CS0||P3_13|| ||MFS9_CS1||P3_14|| ||MFS8_CS3||P3_15|| ||MFS8_CS1||P3_16|| ||MFS8_CS2||P3_17|| #150 Page 190 of 222 S6J3200 Series Vcc5 current consumption Current consumption of FPD link 69 ICC12: -(typ), 1900(max) ICCT5: -(typ), 2620(max) ICCH5: -(typ), 2620(max) 68 69 ICC5 Normal operation 60mA(max) 68 69 - 68 Note: - ,,,, - Jitter of source oscillator must be smaller than 300ppm. 71 Source clock error 72 Trace clock Error Correct Page Current consumption Error Page Summary 74, 75 FCLK_TRC: 50MHz 73, 74 Internal clock frequency 75 Notes; -,,, Power On condition 79 Level detection voltage: 2.25(min) 2.45(typ) 78 2.65(max) Document Number: 002-05682 Rev. *K 74 Correct ID ICC12: 950(typ),1900(max) ICCT5: 350(typ),700(max) ICCH5: 150(typ),450(max) #170 ICC5 Normal operation 45mA(typ), #181 75mA(max) ILVDS: VCC3_LVDS_Tx,AVCC3_LVDS_PLL: #204 70mA (FPD-Link) Note: - ,,,, #178 - The error of source oscillator frequency must be smaller than 300ppm. FCLK_TRC: 100MHzNote;- FCLK_TRC/2 (half frequency of FCLK_TRC) comes out #182 of the trace clock port of package external pin. Notes; -,,, - Even if a combination of clock frequency is able to be configured by software, the frequency should be configured under maximum frequency described in Table. For example, 80MHz of CLK_LCP0A seems to be configurable from both #180 divided 240MHz and 160MHz of CLK_CPU. But each duty ratio of configured 80MHz as an internal signal is different from one another. In this series, the 80MHz from the 160MHz divided by 2 can only be assured, but the 240MHz divided by 3 cannot be assured from the internal timing design point of view. Level detection voltage: 2.15(min) 2.35(typ) 2.55(max) #138 Reset release voltage: 2.25(min) 2.45(typ) 2.65(max) Page 191 of 222 S6J3200 Series Display controller 101 AC specification Error Display controller0 Timing (TTL mode)tDC0CYC:12.5ns (min)|tDC0D|:(Remarks)tDC0V:(Remarks)Notes:- ,,,,Display controller0 Timing (RSDS)|tRSD|:- (Remarks)tSPV:(Remarks)Notes:- ,,,, Correct Page Error Page Summary 100 TCAP0CYC: 11.11ns (min) Video Capture 104 Correct ID Display controller0 Timing (TTL mode)tDC0CYC:12.5ns (min) *120ns(min) *2|tDC0D|:*3 (Remarks)tDC0V:*1, *4 (Remarks)Notes:- ,,,,- For *1, when used with DSP0_DATA* and DSP0_CTRL4-0 in VCC3 area.- For *2, when used with DSP0_DATA* and DSP0_CTRL4-0 in VCC53 area.- For *3, the value can be #187 configured and adjusted.- For *4, the value is defined as tDC0CYC - |tDC0D| and depends on adjustment of *3.Display controller0 Timing (RSDS)|tRSD|:*1 (Remarks)tSPV:*2 (Remarks)Notes:- ,,,,- For *1, the value can be configured and adjusted.- For *2, the value is defined as tDC0CYC - |tDC0D| and depends on adjustment of *1. TCAP0CYC: 12.5ns (min) 103 #188 tCAP0SU: 2ns (min) tCAP0SU: 4ns (min) Note of NC pins, LVDS pins, and 105 other no-used pin - 104 Note:- All the corresponding ports of products which don't support FPD-Link should be connected to GND.AVCC3_LVDS_PLL, AVSS3_LVDS_PLL, VCC3_LVDS_Tx, VSS3_LVDS_Tx, TxDOUTn+/-. #143 FPD-Link timing chart - 105, 106 Figure: LVDS AC characteristics (Timing chart) #183 105 Document Number: 002-05682 Rev. *K Page 192 of 222 S6J3200 Series Error Correct Page Error Page Summary Correct ID 16-1 (3 items) CS -> RDS Chip select active to RDS valid (Low): CS-> RDS(Hi-z) Chip select Inactive to RDS High-Z: CS -> CS Chip select HIGH between operation: 16-2 (4 items) CS -> CS Chip select HIGH between transaction: CS -> CS Chip select maximum LOW time: Read-Writer recovery time : CK -> CK(4th) Page open time : HyperBus AC specification 108112 16-3 (7 items) Read Initial Access Time : CS -> CK Chip select active to RDS valid (Low): CS -> RDS(Hi-Z) Chip select Inactive to RDS High-Z: CK -> DQ (Low Z) Clock to DQs Low 109Z: 112 CS -> DQ (Hi-Z) Chip select Inactive to DQs High-Z: CK -> RDS CK transition to RDS transition: CS -> CS Chip select HIGH between Operation: (Removed) #173 16-4 (8 items) CK -> CK(4th) Page open time: CS -> RWDS(Hi-Z) Chip select Inactive to RWDS High-Z: CK -> DQ (Low Z) Clock to DQs Low Z: CS -> DQ (Hi-Z) Chip select Inactive to DQs High-Z: CK -> RWDS CK transition to RWDS transition: CS -> CS Chip select HIGH between Transition: CS -> CS Chip select maximum LOW time: Read-Writer recovery time Document Number: 002-05682 Rev. *K Page 193 of 222 S6J3200 Series 108, 109 Error tCKCYC: 12.5ns(min)tCSS:3ns (min)tIS:1.25ns (min)tCSH:1.25ns (min)Notes;- ,,,, Correct Page HyperBus AC specification Error Page Summary 109 HyperBus AC specification tRDSCYC:12.5ns (min)tDSS:-0.8ns 110,111 (min)0.8ns (max)tDSH:-0.8ns (min)0.8ns (max)Notes;- ,,,, Document Number: 002-05682 Rev. *K #184 tDMV: 5.25ns (max) (A) 4ns (max) (B) 110 Notes; - ,,,, ID tCKCYC: 12.5ns(min) (A)10ns(min) (B)tCSS:3.25ns (max) (A)2ns (max) (B)tIS:5.25ns (max) (A)4ns (max) (B)tCSH:1ns (min)Notes;- ,,,,- (A): The 109,110 value will be targeted by the product series with revision digit A. - (B): The value will be targeted by the product series with revision digit B. tDMV: 0ns (min) HyperBus AC specification Correct Notes; - ,,,, - (A): The value will be targeted by the product series with revision digit A. - (B): The value will be targeted by the product series with revision digit B. #185 tRDSCYC:12.5ns (min) (A)10ns (min) (B)tDSS:-0.8ns (min)- (max)tDSH:-4.2ns (min)- (max)Notes;- ,,,,- (A): The value 111,112 will be targeted by the product series with #186 revision digit A. - (B): The value will be targeted by the product series with revision digit B. Page 194 of 222 S6J3200 Series Error Correct Page Error Page Summary Correct ID Original document code: DS708-00003-0v02-E, Previous document code: DS708-00003-0v01-E Rev. 2.0 May 20, 2015 Notes; - ,,, Note for Basic Notes; - The CLK_CPU is assigned for CPU 11 11 #194 Option - ,,, clock. The CLK_CD3A0 is assigned for Graphic clock. They are defined at the chapter of Clock Configuration. Power domain (PD): ---See the platform manual and chapter STATE TRANSITION in detail. The product series supports the power off Power domain 15 15 control of PD1, PD2 (including PD3 and #175 reset 5), and PD6. The power domain resets of PD3 and PD5 included in PD2 are not supported in the product series, and "0" is always read from the reset factor flags of them. Original document code: DS708-00003-0v03-E, Previous document code: DS708-00003-0v02-E Rev. 1.0 May 20, 2015 Display output Display output Revision B description Number of display outputs: 2 outputs simultaneously 10 Selectable from 2 x DRGB, 1 x RSDS, or 1 x LVDS (FPD-Link) Number of display outputs: Option Maximum 2 outputs simultaneously 11 Notes;- ,,,,- ,,,, Notes;- ,,,,- ,,,,- Display Output ch.0 is used for RSDS and FPD-LINK (LVDS) as well as DRGB (Digital RGB). The ch.0 of the product which doesn't support FPD- #211 LINK is used for RSDS and DRGB. Display Output ch.1 is used for DRGB only. 11 Note: - ,,, - The function digit A, B, C, and D supports Hyper SRAM. Its 3, 4, 5, and 6 doesn't support Hyper SRAM. Hyper Bus interface ch.2 on graphic 12 sub system will be embedded on product which is specified with function digit 7and 8 after revision B. Revision A only has ch.0 and 1 of Hyper Bus interface. 10 Document Number: 002-05682 Rev. *K 12 Note: - ,,, - HyperBus Interface ch.1 of the function digit 3, 4, 5, and 6 support HyperRAM after Revision B. Page 195 of 222 #210 #267 S6J3200 Series Clock Supervisor output function CR oscillation stabilization time 12 15 Error - - Correct Page CHIP ID information Error Page Summary Correct ID 12 Function digit: A, B, C, D Revision B: Chip ID: 0x10110000 JTAG ID: 0x100095CF #140 15 Clock Supervisor: See the platform manual in detail. This product series doesn't support clock #224 supervisor output port. (Related register and internal circuit is implemented.) 15 Embedded CR oscillation See the platform manual in detail. Stabilization time is as followings. - 5us for 4MHz (Fast clock) - 20us for 100kHz (Slow clock) #259 #128 15 - MOST physical channel 19 MediaLB: --MOST25 (512FS) 3 wires Maximum 15ch is available. (1ch is occupied by the system) 19 MediaLB: --MOST25 (512FS) 3 wires Maximum 15ch is available. Pin assignment IO type 23, 25 29 - 24, 27 31 (Figures are added) #141 (X0 and X1 symbol are added in fugure.) #253 59,60 IOL3,,, When setting is 5 mA*9IOLAV3,,, When setting is 5 mA*9IOL2 50mA *7IOL3 250mA *8IOH3,,, When setting is 5 61,62 mA*9IOHAV3,,, When setting is 5 mA*9IOH2 -50mA *7IOH3 -250mA *8 IOL3,,, When setting is 5 mA*6, *7, *8, *9IOLAV3,,, When setting is 5 mA*6, *7, *8, *9IOL2 250mA *7IOL3 50mA #234 *8IOH3,,, When setting is 5 mA*6, *7, *8, *9IOHAV3,,, When setting is 5 mA*6, *7, *8, *9IOH2 -250mA *7IOH3 -50mA *8 Absolute Maximum Rating 8kB Backup RAM Current 68 Consumption - 70 ICCT5: 345uA(typ),675uA(max):When shutting down 8kB Backup RAM. 450uA(typ),820uA(max):Power only supplies to Backup RAM and system controllers. When using 8MHz crystal for main oscillator. #206 445uA(typ),795uA(max):When shutting down 8kB Backup RAM. ICCH5: 145uA(typ),425uA(max):When shutting down 8kB Backup RAM. Document Number: 002-05682 Rev. *K Page 196 of 222 S6J3200 Series DC characterization of 68 PSS Current consumption Oscillator frequency range PLL/SSCG maximum frequency 68 Error Correct Page Error Page Summary 70 Notes: - ,,, 70 Notes: - ,,, - The definition of timer mode and stop mode can be seen at the chapter of STATE transition of S6J3200 hardware manual. Icc12 900(typ) 1700mA(max):CPU:160MHz, HPM:80MHz, GDC:160MHz #214 #260 Source oscillation clock frequency: X0, X1: 3.6MHz(min), 16MHz(max) Source oscillation clock frequency: X0, X1: 3.6MHz(min), 4.0MHz(max) 71 ID ICCT5: PSS Timer mode Shutdown (PD6=OFF) ICCH5: PSS Stop mode Shutdown ICCT5: Timer mode ICCH5: Stop mode Icc12 -(typ) 1700mA(max):CPU:160MHz, HPM:80MHz, GDC:160MHz Correct 73 Notes: ,,, Notes: #230 ,,, - Enough evaluation and adjustment are recommended using oscillator on your system board. 75, 76 FSSCG0:480,800(400),640,640 MHz, SSCG0 output clockFSSCG1:800(400),800(400), 800(400),800(400) MHz, SSCG1 output clockFSSCG2:800(400),800(400), 800(400),640 MHz, SSCG2 output clockFSSCG3:800,800,800,800 MHz, SSCG3 output clockFPLL0:720,800,800,640 MHz, PLL0 #208 output clockFPLL1:800,800,800,640 MHz, PLL1 output clockFPLL2:800(400),800(400),800(400), 800 MHz, PLL2 output clockFPLL3:480,480,480,480 MHz, PLL3 output clockNotes:- ,,,,- The frequency described in () is not maximum value but recommended configuration value. 74 Note: - ,,, - ,,, 76 Note: - ,,, - ,,, #219 - The configurable minimum frequency of PLLn and SSCGn output is 400MHz. 74 - 76 FCLK_CAN 40MHz(Max) 73 - Minimum PLL/SSCG frequency CAN clock frequency Document Number: 002-05682 Rev. *K #222 Page 197 of 222 S6J3200 Series Error Correct Page Error Page Summary Correct ID "Unused" clock configuration 74 Notes: ,,, ,,, 76 Notes: ,,, ,,, - "Unused" means a clock source which #229 doesn't have any supply destinations. Configure it as disable with performing at the lower clock frequency than the described maximum. Output short circuit current 104 Output short circuit current IOS: 106 (Removed) AC spec of DDRHSSPI [SDR mode] toddata: 6.5ns (max) tohdata: 3.5ns (min) todsel: 5.5ns (max) 107,108 tohsel: 4.5ns (min) [SDR mode] toddata: tcyc/2 + 2ns (max) tohdata: 2.0ns (min) todsel: -12.0ns + (SS2CD+0.5)*tcyc ns (min) tohsel: 3.5ns (min) 109, 110 [DDR mode] toddata: 6.5ns (max) todsel: 7.0ns (max) SDR/DDR Remark:tcyc -3.5nstcyc -4.5nstcyc/2107,108 (HSSPI) remark 1.5nstcyc -3.0ns #203 [DDR mode] toddata: tcyc/4 + 1.5ns (max) todsel: -15.75ns + (SS2CD+0.5)*tcyc ns (min) #164 Notes: - This is target spec. - SS2CD [1:0] should be configured as 01, 10, or 11. 109,110 (Delete) #232 ADC trigger input 119 - 121 A/D trigger input time:ADTRG 4tCLK_LCP1A ns (min) 4tCLK_LCP1A #231 100ns 100 ns (min) 4tCLK_LCP1A < 100ns ADC resumption time - 121 Resumption time: 1us(max) 119 Document Number: 002-05682 Rev. *K Page 198 of 222 #239 S6J3200 Series Error Correct Page Error Page Summary Correct ID Original document code: DS708-00003-0v04-E, Previous document code: DS708-00003-0v03-E Rev. 1.0 June 30, 2015 FPD-Link port definition 45 - 60-61 TxCLK- LVDS clock output pin: Described as TXOUT4M in FPD-Link Converter TxCLK+ LVDS clock output pin: Described as TXOUT4P in FPD-Link Converter TxDOUT0- LVDS data output pin: Described as TXOUT0M in FPD-Link Converter TxDOUT0+ LVDS data output pin: Described as TXOUT0P in FPD-Link Converter TxDOUT1- LVDS data output pin: Described as TXOUT1M in FPD-Link Converter TxDOUT1+ LVDS data output pin: #146 Described as TXOUT1P in FPD-Link Converter TxDOUT2- LVDS data output pin: Described as TXOUT2M in FPD-Link Converter TxDOUT2+ LVDS data output pin: Described as TXOUT2P in FPD-Link Converter TxDOUT3- LVDS data output pin: Described as TXOUT3M in FPD-Link Converter TxDOUT3+ LVDS data output pin: Described as TXOUT3P in FPD-Link Converter Non support port 21, 23 - 25, 27, 28, 29, (Added the Note for non-supported pin 32, 34, condition on PCB) 35, 36 Current consumption of FPD link 70 VCC3_LVDS_Tx, AVCC3_LVDS_PLL: 70 mA(max) 92 VCC3_LVDS_TX: 56mA(max) AVCC3_LVDS_PLL: 7mA(max) #246 AVcc and AVRH description 58 (AVCC0, AVCC1, AVRH0, and AVRH1) 73 (AVCC,AVRH) #250 TEQFP256 support 11 Pin count N:320 12 Pin count M:256 #272 Document Number: 002-05682 Rev. *K Page 199 of 222 #215 S6J3200 Series Error Correct Page Error Page Summary 13, 14 Notes: - ,,, - BGA is a package option under planning. ID TEQFP256 BGA320 TEQFP256 support Correct 15, 16 Notes: - ,,, - TEQFP-256 is a package option under planning. #273 17 A/D Converter: 50 channels of analog input for TEQFP216,,,24 channels of them are 19 shared with the SMC for TEQFP216/208 A/D Converter: 50 channels of analog input for TEQFP256 and TEQPF216,,,24 #274 channels of them are shared with the SMC for TEQFP256/216/208 TEQFP256 support 19 LCD Controller: TEQFP216 : 4com x 32seg TEQFP208 : 4com x 30seg ,,, 21 LCD Controller: TEQFP256 : 4com x 32seg TEQFP216 : 4com x 32seg TEQFP208 : 4com x 30seg ,,, #275 TEQFP256 support 20, 24 - 23, 38 (TEQFP256 assignment is added.) #276 Chip ID 12 Revision:B, Chip ID:0x10100010 14 Revision:B, Chip ID:Revision:C and D, Chip ID:0x10100100 #278 TEQFP256 support Document Number: 002-05682 Rev. *K Page 200 of 222 S6J3200 Series Error Correct Page Error Page Summary Correct ID Operating temperature TA: -40(min), +105(max) TC: -40(min), +144(max) Notes: - Both rating of TA and TC should simultaneously be satisfied as maximum operation temperature. - The following condition should be satisfied in order to facilitate heat dissipation. 1. 4 or more layers PCB should be used. 2. The area of PCB should be 114.3 mm x 76.2 mm or more, and the thickness #283 should be 1.6 mm or more. (JEDEC standard) 3. 1 layer of middle layers at least should be used for dedicated layer to radiate heat with residual copper rate 90% or more. The layer can be used for system ground. 4. 35~50% of the die stage area which is exposed at back surface of package should be soldered to a part of 1st layer. 5. The part of 1st layer should be connected to the dedicated heat radiation layer with more than 10 thermal via holes. Main and sub oscillator is available. - A wide range of 3.6 - 16MHz is #311 available for main oscillator (Inside Figure 2-1: Option and Part Number) #313 C: Support MCAN 3.0.1. D: Support MCAN 3.2. Case Temperature issue 64, 65 Operating temperature TA: -40(min), +105(max) 80, 81 Main clock frequency 15 Main and sub oscillator is available. - A wide range of 3.6 - 4MHz is available for main oscillator 17 Revision description 11 - 12 CPU Clock Maximum 11 200MHz (CPU Clock of function digit A, B, C, and D) 13 160MHz (CPU Clock of function digit A, B, C, and D) 39 Note:- Same size is specified for MIN, NOM, MAX, then it should be regarded as #315 maximum size. Maximum gap between package 24 and board - Document Number: 002-05682 Rev. *K Page 201 of 222 #314 S6J3200 Series Error Correct Page Error Page Summary Correct ID Power dissipation and Operation temperature Case 1, PD - 3300 mW, TA -40 +97 degC, Both should be satisfied. TC -40 +144 degC, Power dissipation and Operation temperature Case 2, PD - 3150 mW, TA -40 +100 degC, Both should be satisfied. TC -40 +144 degC, Power dissipation and Operation temperature Case 3, PD - 3000 mW TA -40 +102 degC, Both should be satisfied. TC -40 +144 degC, Power dissipation and Operation 62 temperature - 77, 78 Power dissipation and Operation temperature Case 4, PD - 2900 mW, TA -40 +105 degC, Both should be satisfied. TC -40 +144 degC, Power dissipation and Operation temperature Case 5, PD - 2800 mW, TA -40 +105 degC, Both should be satisfied. TC -40 +144 degC, System Thermal Resistance, Theta j-a - 16 degC/W, The minimum value depends on the system specification of heat radiation. The described value is estimated under the condition which is specified at Operation Assurance Condition. Package Thermal Resistance, Theta j-c - 7.5 degC/W, Document Number: 002-05682 Rev. *K Page 202 of 222 #317 S6J3200 Series Error Correct Page Error Page Summary HyperBus GPO Remark 18 HyperBus ,,, 21 Chip Select Output 11 - 13 12 Notes: ,,, - SCL4, 10, 12 and SDA4, 10, 12 of I2C is not supported yet, and will be enhanced after Revision B. 13 Revision B description Correct ID HyperBus ,,, GPO signal can only be used for "Internal Control example by GPO" in this product, #345 that is, it can select using HyperBus of PF or using HyperBus of Graphic Sub System. (Part Number is added to show Chip Select Output of MFS) Notes: ,,, - Multi-function serial interface of the function digit 3, 4, 5, 6, 7, and 8 support SCL4, 10, 12 and SDA4, 10, 12 of I2C after Revision D. To configure Lock or Unlock for both MPUXn_UNLOCK and MPUHn_UNLOCK, - Lock: 0x112ABB56 - Unlock: 0xACCABB56 0-wait-cycle: 80MHz or less. 1-wait-cycle: 160MHz or less. 2-wait-cycle: more than 160MHz. The maximum frequency should be referred in datasheet. #346 #349 MPU lock and unlock value 16 - 18 Flash Access Speed 17 1-wait-cycle with 80-160MHz. 2-wait-cycle with 160-240MHz. 19 Oscillator error 73 - The error of source oscillator frequency must be smaller than 300ppm. 97 - The error of source oscillator frequency #360 must be smaller than 3000ppm. Input leakage current:IIL:P2_16, 17, 19, 22, 24 to 31, P3_00 to 31, P4_00 to 12, P6_02 to 31 Input capacitance:CIN1:P0_00 to 31, P1_00 89 to 09, P2_16, 17, 19, 22, 24 to 31, P3_00 to 20, P5_21, 22, 27 to 31, P6_00 to 08, 17 to 26 Input leakage current:IIL:P2_16, 17, 19, 22, 24 to 31, P3_00 to 31, P4_00 to 12, P4_25 to 31, P5_00 to 20, P6_02 to 31 Input capacitance:P0_00 to 31, P1_00 to #363 09, P2_16, 17, 19, 22, 24 to 31, P3_00 to 20, P4_25 to 31, P5_00 to 20, P5_21, 22, 27 to 31, P6_00 to 08, 17 to 26 Input leakage current,Pull-up resistor,Pull-down 69 resistor and Input capacitance for P4_25 to P4_31 #351 #357 CLK_HPM Frequency 16 1 wait cycle is necessary to read at over 180MHz (target). 18 See the platform manual in detail. 1 wait cycle is necessary for RAM read at over 160MHz. #366 No need to insert wait cycles for RAM write. nSRST description 15 - INITX - SRSTX - nSTRST 17 - INITX - SRSTX (and nSRST pin) Document Number: 002-05682 Rev. *K Page 203 of 222 #367 S6J3200 Series Error Correct Page Error Page Summary Correct ID Multi-functional Serial (MFS):,,, 20 Multi-functional Serial (MFS):CTS/RTS is not mounted (hardware flow control is not #373 supported for this series.) Pin assignment and pin list should be separately 20 instead of the red characters - 24-37 (The figure of pin assignment are added) #374 DDR-HSSPI DDR 110 Mode Note: ,,, - SS2CD [1:0] should be configured as 01, 10, or 10. 140 Notes: ,,, - SS2CD [1:0] should be configured as 01, 10, or 11. Hardware flow control 18 #376 Notes:- *1: Target maximum clock 100 frequencies when CPU clock = 240MHz- ,,, Notes:- *1: Target maximum clock frequencies when CPU clock = 240MHz 232MHz or less is available for SSCG #380 Down Spread. - 240MHz or less is available for PLL.- ,,, Input Pulse Width 120 Port Noise Filter: Width for input removal: All GPIO: 25ns(max) 151 *: Input pulse width less than at least 25nm is removed when Port noise filter is enabled. Port Noise Filter: Width for input removal: All GPIO: 67ns(max) *: Input pulse width less than at least Typ #382 25ns to Max 67ns is removed when Port noise filter is enabled. *: Input pulse width 100ns or more is recommended to be effective. TYPO in 216 pin assign P0_26 0 P0_27 0 P0_28 0 24-30 ("0"s are removed) P0_26 P0_27 P0_28 #384 - 14 Function Digit: 3,4,5,6,7,8 E and F: Chip ID: 0x10100101, JTAG ID: 0x1000C5CF --Function Digit: A,B,C,D E and F: Chip ID: 0x10110001, JTAG ID: 0x100095CF #409 - 124 (LVDL0 spec is added.) #410 (Old value) 138, 140 (New values are added in the table) #411 (Old value) 142145 (New values are added in the table) #412 Oscillator Error Issue CHIP ID 76 21,22 12 RVD Detection/Release 99 Voltage DDH-HSSPI AC 109, Specification 110 HyperBus AC Specification 111114 Document Number: 002-05682 Rev. *K Page 204 of 222 S6J3200 Series 72 Unsupport Partial 15 Wakeup Error Correct Page Power Supply Current Error Page Summary ID - 92-96 Power Domain (PD): ,,, 17 (New table is added, and the value of Icc12, Icc5, Icct5, and Icch5 are #413 improved.) Power Domain (PD): ,,,This series doesn't #416 support partial wakeup for PD6. VSS12: 1.15*1 1.1*1 80 #417 VSS12: 1.15 1.1*1 Vcc12 power supply limit Correct 64 Notes: - *1. The value will be for the product series with revision digit B. - ,,, Notes: - *1. The value is only applied to the product series with revision digit A. - ,,, VOD:210, 300, 390 mV250, 350, 450 mV295, 400, 505 mVVCM:1.075, 1.200, 1.325 V1.125, 1.250, 1.375 V #418 81-84 (Land pattern of thermal via hole is added.) #429 80 Notes: -,,, - Power supply sequence is #431 recommended as VCC5 -> [DVCC or AVCC5 or VCC3 or AVCC3] -> VCC12 -> [AVCC3_LVDS_PLL or VCC3_LVDS_TX] FPD-Link DC Spec 106 VOD:270, 300, 340 mV310, 350, 400 mV360, 400, 450 mVVCM:1.120, 1.150, 135 1.175 V1.170, 1.200, 1.225 V1.220, 1.250, 1.280 V Land Pattern for Thermal Via 65 - Power On Sequence 64 Recommendation Document Number: 002-05682 Rev. *K Page 205 of 222 S6J3200 Series Internal Clock Timing for FSSCG0-3 and FPLL0-3 75, 76 Correct Page Error Page Summary Error FSSCG0 480 800(400) 640 640 FSSCG1 800(400) 800(400) 800(400) 800(400) FSSCG2 800(400) 800(400) 800(400) 640 FSSCG3 800 800 800 800 FPLL0 720 800 800 640 FPLL1 800 800 800 640 FPLL2 800(400) 800(400) 800(400) 800 FPLL3 480 480 480 480 Notes: ,,, - The frequency described in () is not maximum value but recommended configuration value. Correct ID FSSCG0 232(480) 200(800) 160(640) 160(640) FSSCG1 200(800) 200(800) 200(800) 200(800) FSSCG2 200(800) 200(800) 200(800) 160(640) FSSCG3 200(800) 200(800) 200(800) 200(800) FPLL0 240(720) 200(800) 200(800) 160(640) FPLL1 400(800) 400(800) 400(800) 99, 100 320(640) FPLL2 200(800) 200(800) 200(800) 200(800) FPLL3 240(480) 240(480) 240(480) 240(480) #432 Notes: ,,, - The frequency described in () is maximum output frequency of SSCG PLL / PLL multiplier circuit. VIH spec(TTL level) for JTAGpins 65 VIH9: 2.0(Min) 85 VIH9: 2.3(Min) #437 VIH of Media LB port 65 VIH12: 1.7(V) 85 VIH12: 1.8(V) #438 Original document code: DS708-00003-1v0-E, Previous document code: DS708-00003-0v04-E Rev. 1.0 September 30, 2015 Resource clock frequency 9 Resource clock frequency : 40MHz (Max) 8 Resource clock frequency : Option : See #465 AC specification on the datasheet Description for up/down counter 10, 20 Up/Down Counter 9, 19 Quad Position & Revolution Counter(Up/Down Counter) Display output 13 Notes: ,,, - Display Output ch.0 is used for RSDS and FPD-LINK (LVDS) as well as DRGB (Digital RGB). The 12 ch.0 of the product which doesn't support FPD-LINK is used for RSDS and DRGB. Display Output ch.1 is used for DRGB only. Document Number: 002-05682 Rev. *K #530 Notes: ,,, - Display Output ch.0 is used for RSDS and FPD-LINK (LVDS) as well as DRGB (Digital RGB). The ch.0 of the product which doesn't support FPD-LINK is used #452 for RSDS and DRGB. - Display Output ch.1 is used for FPDLINK (LVDS) and DRGB (Digital RGB). The ch.1 of the product which doesn't support FPD-LINK is used for DRGB only. Page 206 of 222 S6J3200 Series Error Correct Page Error Page Summary Correct ID Relationship SYSC0_SYSIDR and ChipID 14 ID is specified for each function digit and revision which is defined at Figure 2-1. 13 ID is specified for each function digit and revision which is defined at Figure 2-1. Chip ID can be read from SYSC0_SYSIDR. #471 For SYSC0_SYSIDR, see the TraveoTM Platform hardware manual. Typo in trace buffer size 17 4kB Embedded Trace Buffer 16 4k Word Embedded Trace Buffer #528 MFS: ,,, 19 MFS: ,,, WUCR function is not supported for this product. #284 CS port availability 20 MFS:Chip select function of CSIO is not supported yet and will be enhanced with next revision. 19 MFS:The availability of chip select function can be seen at Function Digit Table. #448 Not support CS input - 19 Chip Select Input is not supported. #467 WUCR function 20 20 Usage for I2S ch1 20 - I2S0 only supports the output of sound sources. - I2S1 supports both the input and the output. - ,,, 19 - I2S0 can output sound sources which are processed by Sound System. - I2S1 can input sound sources which are processed by Sound System. #529 - ,,, See the "Sound System Configuration" of S6J3200 hardware manual in detail. Imporvement of descritption for I2C Note all pins do not necessarily support I2C, but the pins which have the dedicated 19 I/O characteristics only support it. Note - Not all pins support I2C. Only pins which have the I2C I/O characteristics #531 support it. 20 Reference for DDR High Speed 20 SPI & CAN-FD - Reference information for GPO 21 GPO signal can only be used for "Internal Control example by GPO" in this product, that is, it can select 20 using HyperBus of PF or using HyperBus of Graphic Sub System. Delete unnecessary description for Graphic subsystem 21 Order replacement of RGB pins. Document Number: 002-05682 Rev. *K 19, 20 20 (Added "See the platform manual in detail" for CAN-FD & DDR High Speed #532 SPI) GPO signal can only be used for "Internal Control example by GPO" in this product, that is, it can select using HyperBus of PF or using HyperBus #533 of Graphic Sub System. See the "HyperBus Interface Port Configuration" of S6J3200 hardware manual in detail. (Deleted) #534 Page 207 of 222 S6J3200 Series Error Correct Page Error Page Summary Correct ID Direct Memory Access Interface, MAC Filtering Block -VLAN tag, IEEE 1588 and IEEE 802.1AS Support, MAC PFC Priority 21 Based Pause Frame Support, and 802.1Qav Support - Credit Based Shaping (Delete) Improvement of description for Pin 23 Assignment Alphabets with pin numbers are signs specify I/O circuit type. 22 The characters next to the pin number in the pin assignment drawing specify the #535 I/O circuit type. (figure added) Regarding "red" character in Pin Assignment 23-38 The pins which are described in "red" character are not supported, and will be enhanced with next revision products. 23-35 The pins which are described in "red" character are not supported product with #524 revision A and C. 76 Maximum clamp current:*A (Remarks) 75 Total maximum clamp current:*A (Remarks) Maximum clamp current:*12, *A (Remarks) Total maximum clamp current:*12, *A (Remarks) #503 Input voltage:VI2:VCC5+0.3(Max) ,,, Input voltage:VIE:VCC5+0.3(Max) Input voltage:VI2:DVCC+0.3(Max) ,,, Input voltage:VIE:VCC53+0.3(Max) #518 Delete Ethernet restriction for product Note for Input voltage and Max clamp current 22 TYPO in Absolute 76 Maximum Rating Note for Input voltage and Max clamp current Power supply sequence 75 78 - 77 80 Power supply sequence is recommended as VCC5 -> [DVCC or AVCC5 or VCC3 or 79 AVCC3] -> VCC12 -> [AVCC3_LVDS_PLL or VCC3_LVDS_TX] #516 *12: VI or VO should never exceed the specified ratings. However, if the maximum current to/from an input is #470 limited by a suitable external resistor, the ICLAMP rating supersedes the VI rating. Power supply sequence is recommended as VCC5 -> [DVCC or AVCC5 or VCC3 or AVCC3] -> VCC12 -> [AVCC3_LVDS_PLL or #474 VCC3_LVDS_TX]. Note that power supplies inside "[]" can be turned on in arbitrary order. VIH/VIL characteristics for 85, 86 I/O of DVCC - 84, 85 (Added the "*1" for note of some characteristics and the description) #439 DS 8.3.1 Port Function Characteristics 86 VIL10(Max) 0.3xVcc5 85 VIL10(Max) 0.3xVcc3 #453 VOH characteristic for I/O of MediaLB 87 VOH16:VCC3-0.5(Min) 86 VOH16:2.0(Min) #441 Document Number: 002-05682 Rev. *K Page 208 of 222 S6J3200 Series Error Correct Page Error Page Summary Correct ID VOH/L4, VOH/L5, VOH/L6 characteristics for 87, 88 I/O of VCC5 and DVCC - 86, 87 (Added the "*1" for note of some characteristics and the description) #442 VOL4, VOL5 characteristics VOL4:0.55(Max) VOL5:0.55(Max) 87 VOL4:0.4(Max) VOL5:0.4(Max) #443 88 Pull-up/Pull-down resistor for 5V/3V 89 pins (P4_25 to 31, P5_00 to 20) PUP2:P2_16, 17, 19, 22, 24 to 31, P3_00 to 31, P4_00 to 12, P6_02 to 31:Pull-up registor selected,,,Pdown2:P2_16, 17, 19, 88 22, 24 to 31, P3_00 to 31, P4_00 to 12, P6_02 to 31:Pull-down registor selected PUP2:P2_16, 17, 19, 22, 24 to 31, P3_00 to 31, P4_00 to 12, P4_25 to 31, P5_00 to 20, P6_02 to 31:Pull-up registor selected Vcc53 = 4.5V to #430 5.5V,,,Pdown2:P2_16, 17, 19, 22, 24 to 31, P3_00 to 31, P4_00 to 12, P4_25 to 31, P5_00 to 20, P6_02 to 31:Pull-down registor selected Vcc53 = 4.5V to 5.5V Typo in condition of IIL characterisistics for 3V I/O VCC3=3.3 V VSS < VI < VCC3 88 VCC3=3.6 V VSS < VI < VCC3 CIN1:P3_21 to 31, P4_00 to 12, P6_09 to 16 88 CIN2:P3_21 to 31, P4_00 to 12, P6_09 to #445 16 88 Pull-up resistor:RUP2:P4_25 to 31, P5_00 to 20:Pull-up resistor Selected Vcc53 = 3.0V to 3.6V:40(Min):100(Typ):200(Max):k:5V/3 V pins ,,, #501 Pull-down resistor:Rdown1:P4_25 to 31,P5_00 to 20:Pull-down resistor Selected Vcc53 = 3.0V to 3.6V:40(Min):100(Typ):200(Max):k:5V/3 V pins 89 Typo in symbol for 89 input capacitance Pull-up/Pull-down resistor for 5V/3V 89 pins - FPD-Link DC Spec 92 - 91 DS 8.3.2.1 Run Mode 93 (Icc5 is only defined) 92 Maximu clock frequency of SSCG3 99 FSSCG3:200(800), 200(800), 200(800), 200(800) 98 Document Number: 002-05682 Rev. *K #444 Note: - ,,, - The current consumption at Vcc3_LVDS_Tx is specified under RL=100 , CL=5 pF, f=50 MHz, and 0/1 alternation pattern output. (Current values related CPU operation should be specified as Icc12) FSSCG3:400(800), 400(800), 400(800), 400(800) Page 209 of 222 #433 #454 #458 S6J3200 Series SSCG Max Frequency Error 99, 100, 131134, 138, 140,142 -150, 159 100 Notes: - *1: Target maximum clock frequencies when CPU clock = 240MHz - 232MHz or less is available for SSCG Down Spread. - 240MHz or less is available for PLL. Correct Page Delete "Taget spec" Error Page Summary Correct ID 98, 99, 100, 131134, 138, (Deleted explanation for target spec) 140, 142150, 159 99 #504 Notes: - *1: Target maximum clock frequencies when CPU clock = 240MHz #487 - 232MHz or less is available for SSCG Down Spered on/off. - 240MHz or less is available for PLL. Notes:,,,- *3: Target maximum clock frequencies when CPU clock = 160MHz. This is also a combination of maximum clock frequencies for TC FLASH Programming or Erasing.- From *1 to *3, they are applied to the product series with function digit 3, 4, 5, 6, 7, and 8.- *4: #406 Target maximum clock frequencies when CPU clock = 160MHz for the product series with the function digit A, B, C, and D. This is also a combination of maximum clock frequencies for TC FLASH Programming or Erasing. Internal Clock Timing 100 Notes:,,,- *3: Target maximum clock frequencies when CPU clock = 160MHzFrom *1 to *3, they are not applied to the product series with function digit A, B, C, 100 and D. - *4: Target maximum clock frequencies when CPU clock = 160MHz for the product series with thefunction digit A, B, C, and D. Level detection hysteresis width 105 Level detection hysteresis width 104 (Delete) #457 Default Value of LVDL1 126 LVDL1V=01(Default),,, LVDL1V=10 125 LVDL1V=01,,, LVDL1V=10(Default) #502 131 ( - Updated the min/max value in |tDC0D| and tDC0V. - Added the new definition for DSP0_CTRL11-0 of tDC0V. - Update the #347 note for *2 and delete the note for *4. Updated figure for definition of tDC0V.) Display AC specification 131 - Document Number: 002-05682 Rev. *K Page 210 of 222 S6J3200 Series Error Correct Page Error Page Summary Correct ID Display AC specification 132 - 132 ( - Updated the min/max value for |tRSD|, tRSV, tSPD, tSPV. - Delete the note for #506 *2. - Updated figure for definition of tSPV and tRSV.) Display AC specification 133 - 133 ( - Updated the min/max value for tDC1D, tDC1V and delete the remarks for tDC1V. #505 - Updated figure for definition of tDC1V.) FPD-Link Output Clock Frequency 135 Output clock frequency: 1MHz(min),50MHz(max) 135 Output clock frequency: (min),50MHz(max) Add "TxCLK+/-" in case of don't 135 support FPD-Link Note: - All the corresponding ports of products which don't support FPD-Link should be connected to GND. AVCC3_LVDS_PLL, AVSS3_LVDS_PLL, VCC3_LVDS_Tx, VSS3_LVDS_Tx, TxDOUTn+/-. 135 Note: - All the corresponding ports of products which don't support FPD-Link should be connected to GND. #525 AVCC3_LVDS_PLL, AVSS3_LVDS_PLL, VCC3_LVDS_Tx, VSS3_LVDS_Tx, TxDOUTn+/-, TxCLK+/-. DDRHSSPI (SDR) clock cycle for 138 Quad Page Program - 138 HSSPI clock cycle:20(Min):when Quad Page Program #484 HyperBus AC specification RDS> DQ (valid) Setup time ,,, RDS> DQ (invalid)Hold time 144 RDS> DQ Setup time ,,, RDS> DQ Hold time #519 153 8.5.4 Calibration ConditionCalibration Condition A/D Converter should be calibrated under the following condition.AVCC=5.0V AVRH=5.0V Ta=25 system clock frequency (CLK_LCP1A)= 10MHz See A/D Converter Calibration on the S6J3200 hardware manual. #358 ADC Software Trimming 144 153 - Document Number: 002-05682 Rev. *K #522 Page 211 of 222 S6J3200 Series Document History Document Title: S6J3200 Series 32-bit Microcontroller TraveoTM Family Document Number: 002-05682 Revision ECN Orig. of Submission Change Date Description of Change Migrated to Cypress and assigned document number 002-05682. ** - NNAS 09/30/2015 No change to document contents or format. *A 5234352 NNAS 04/22/2016 Updated formatting 2. Function List 2.1 Function List [Improve] Corrected the number of CRC unit. (1unit -> 4unit) 2. Function List 2.2.1 Basic Option 2.2.2 ID [Improve] Updated the "Option and Part Number", "Function Digit table" and "ID" table for adding new revision and improving readability. 2. Function List 2.2.2 ID [Improve] Added the value of Platform ID in SYSC0_SYSPFIDR 3. Product Description 3.2 Product Description [Enhancement] Added support for center spread mode with limited condition 3. Product Description 3.2 Product Description [Improve] Added the description for "MK_CEER" of security 3. Product Description 3.2 Product Description [Improve] Added the description for hot swap function of I2C *B 5340908 NNAS 07/08/2016 3. Product Description 3.2 Product Description [Improve] Added the explanation for function of PSC1. 3. Product Description 3.2 Product Description [Improve] Added the explanation for reset of EX5VRST. 3. Product Description 3.2 Product Description [Improve] Added the information of main oscillation stabilization wait time. 3. Product Description 3.2 Product Description [Improve] Added the register information (HYPERBUSIn_IEN) for clarifying "not support". of "Interrupt Enable Register" 3. Product Description 3.2 Product Description [Improve] Corrected the number of I2C support ports for MFS. 3. Product Description 3.2 Product Description [Improve] Corrected the revision digit information for Ethernet AVB. 3. Product Description 3.2 Product Description [Improve] Corrected the stabilization time for embedded CR oscillation. 3. Product Description 3.2 Product Description [Improve] For convenience to understand power domain definition. Document Number: 002-05682 Rev. *K Page 212 of 222 S6J3200 Series Revision ECN Orig. of Submission Change Date Description of Change 3.Product Description 3.2 Product Description [Improve] Deleted the unnecessary description for PPU of I2S 4. Package and Pin Assignment 4.1 Pin Assignment [Improve] Added the part number information for figure 4-8 and 4-15 4. Package and Pin Assignment 4.1.1 TEQFP-216 Pin Assignment [Improve] Added the "M_CK_0" for TEQFP-216 Pin Assignment 4. Package and Pin Assignment 4.1.2 TEQPF-208 Pin Assignment [Improve] Corrected part number in figure title. (S6J32xCL -> S6J32xCK) 4. Package and Pin Assignment 4.1.3 TEQPF-256 Pin Assignment [Improve] Corrected the IO-circuit type for pin.217 to 256 6. Port Description 6.1 Port Description List [Improve] Added the supplementary information for I2C pin name of SCL, SDA. 7. Precautions and Handling Devices 7.2 Handling Devices [Improve] Deleted the obsolete description about power ramp rate ("About the Power-on Time") 7. Precautions and Handling Devices 7.2 Handling Devices [Improve] Removed duplicated description 7. Precautions and Handling Devices 7.2. Handling Devices [Limitation] Added description of how to turn off VCC12 during power off sequence. 8. Electric Characteristics 8.1 Absolute Maximum Rating [Improve] Deleted "total maximum clamp current" for special spec. 8. Electric Characteristics 8.1 Absolute Maximum Rating [Limitation] Added the condition to "Analog pin input voltage" 8. Electric Characteristics 8.2 Operation Assurance Condition [Improve] clarified the rate of die stage area which is exposed at back surface of package for heat dissipation. 8. Electric Characteristics 8.3.1 Port Function Characteristics [Improve] Remarks of VOH5 is modified. 8. Electric Characteristics 8.3.2.1 Run Mode [Improve] Added information. "50 MHz" into AVCC3_LVDS_PLL. 8. Electric Characteristics 8.3.2.2 PSS Timer Mode Shutdown (PD6=OFF) [Enhance] PD4 shutdown support [Improve] Added remarks in osc mode spec 8. Electric Characteristics 8.4.1 Source Clock Timing [Improve] Corrected the min value of source oscillation clock cycle time. 8.Electric Characteristics 8.4.3 Internal Clock Timing [Enhancement] Added support for center spread mode with limited condition 8. Electric Characteristics 8.4.3 Internal Clock Timing Document Number: 002-05682 Rev. *K Page 213 of 222 S6J3200 Series Revision ECN Orig. of Submission Change Date Description of Change [Enhance] The series of port reference voltage level VIL/VIH/VOL/VOH for HyperBus AC specification is defined. 8. Electric Characteristics 8.4.3 Internal Clock Timing [Improve] Corrected the maximum output frequency of SSCG0 and PLL0 8. Electric Characteristics 8.4.4 Reset Input [Improve] Improved readability for width for reset input removal. 8 Electric Characteristics 8.4.5 Power-On Conditions [Enhancement] Reduced Power off time to 1ms [Limitation] Defined Power ramp rate requirement for 1)when tOFF is satisfied 2)tOFF is not satisfied [Limitation] Increased Level detection time to 540us 8.Electric Characteristics 8.4.5.2 VCC12 Stabilization Time during Power-On / PSS to RUN Transition [Limitation] Added VCC12 stabilization time requirement for power-up sequence and PSS to RUN transition 8. Electric Characteristics 8.4.6.2 CSIO Timing (SMR:MD2-0=0b010) [Improve] Corrected min value of Serial clock "H" pulse width and Serial clock "L" pulse width 8. Electric Characteristics 8.4.6.2 CSIO Timing (SMR:MD2-0=0b010) [Limitation] Changed AC spec of MFS CSIO mode 8.Electric Characteristics 8.4.6.2 CSIO Timing (SMR:MD2-0=0b010) [Improve] Added CS output AC timing. 8. Electric Characteristics 8.4.6.4 I2C Timing (SMR:MD2-0=0b100) [Improve] Corrected the name of "High-Speed Mode" to "Fast Mode". 8. Electric Characteristics 8.4.7 Timer Input [Improve]Clock definition of remarks is modified 8. Electric Characteristics 8.4.8 Trigger Input [Improve] Definition of RXx pin and limitation of stop mode is deleted. 8. Electric Characteristics 8.4.10 Low-Voltage Detection [Limitation] Corrected release voltage for LVDL0, LVDH0 and LVDL1 8 Electric Characteristics 8.4.10 Low-Voltage Detection [Limitation] Add note that this LVDL0 cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage [Improve] Removed LVDH0 table due to duplication with 8.4.5 Power-On Conditions [Limitation] Add note that this LVDL1 cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage with any setting [Limitation] Add note that this LVDH1 cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage for some of the settings [Limitation] Add note that this LVDL2 cannot be used to reliably generate a reset before Document Number: 002-05682 Rev. *K Page 214 of 222 S6J3200 Series Revision ECN Orig. of Submission Change Date Description of Change voltage dips below minimum guaranteed MCU operation voltage with any setting [Limitation] Add note that this LVDH2 cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage for some of the settings 8. Electric Characteristics 8.4.10.3 LVDL1 [Improve] Deleted the useless configuration of LVDL1. (LVDL1V=01) 8.Electric Characteristics 8.4.10.6 LVDH2 [Improve] Typ value of release voltage at conditions of LVDH2V=0001 changes 2.75V to 2.85V. 8. Electric Characteristics 8.4.11 High Current Output Slew Rate [Improve] Corrected the typo in figure. (VOL8, VOH8 -> VOL, VOH) 8. Electric Characteristics 8.4.12.2 Display Controller0 Timing (RSDS) [Improve] Delete unnecessary characteristics 8. Electric Characteristics 8.4.14 FPD-link [Improve] Corrected unit. "Ohm" -> "ohm" [Improve] Corrected remarks on "Common mode voltage". "One of three" -> "One of two" [Improve] Added missing information. "5 pF (differential)" [Improve] Corrected format. "25MHz" -> "25 MHz", "4/7" -> "4 / 7". [Improve] Added cycle to cycle jitter spec. [Improve] Added information. "Equals 1/f" into TCIP. [Improve] Corrected max time in "Cycle time of TXCLKP/M". [Improve] Added other frequency spec into "Output pulse position". [Limitation] Added PLL lock-up time. [Improve] Separately added specs for revision H. 8. Electric Characteristics 8.4.14. FPD-Link (LVDS) [Limitation] Specified minimum output frequency 5MHz. 8. Electric Characteristics 8.4.16 HyperBus [Enhance] Enhanced AC spec Hyper Bus read timing and corrected timing chart 8. Electric Characteristics 8.4.16 HyperBus [Enhance] The series of port reference voltage level VIL/VIH/VOL/VOH for HyperBus AC specification is defined. 8. Electric Characteristics 8.4.16 HyperBus [Improve] Added a note for clarifying the HyperBus clock cycle and source. 8. Electric Characteristics 8.4.16 HyperBus [Improve] Corrected the revision digit information. 8. Electric Characteristics 8.4.19 Port Noise Filter [Improve] Change the description of filter specification and note for GPIO [Improve] Added the filter specification for EINT, TIN [Improve] Added the filter specification for SCL, SDA of I2C 9. Abbreviation [Improve] Added the word "QPRC" to abbreviation. Document Number: 002-05682 Rev. *K Page 215 of 222 S6J3200 Series Revision ECN Orig. of Submission Change Date Description of Change 10. Ordering Information [Improve] Updated "Order Part Number Table" 11. Appendix 11.1 Application 1: JTAG tool connection [Improve] Figure of JTAG tool connection as an application example is added. 2. Function List 2.2.1.1 S6J320C [Improve] Added new function digit 9 to Function digit table 2. Function List 2.2.1.1 S6J320C [Improve] Updated the Revision information 2. Function List 2.2.1.2 S6J320A [Improve] Corrected the Revision information (Digit:G -> Digit:E) 2. Function List 2.2.2 ID [Improve] Added the ID information for revision J, K, L, and M 4. Package and Pin Assignment 4.2 Package Dimensions [Limitation] Updated PKG figure and changed parameter of symbol b, c and ddd for LEQ216 [Improve] Updated PKG figure for LET208 and LER208 *C 5515119 NNAS 11/10/2016 7. Precautions and Handling Devices 7.2 Handling Devices [Limitation] Added the "Method to Switch off VCC12 during Power-off Sequence" for except revision M 8. Electric Characteristics 8.3.2.1 Run Mode [Limitation] Changed the power supply current of "AVcc3_LVDS_PLL" for after revision H. 8. Electric Characteristics 8.4.4.2 Power supply voltage stability conditions [Limitation] Added the power supply voltage stability conditions for revision M 8. Electric Characteristics 8.4.10.4 LVDH1 [Limitation] Added the note for power supply voltage stability conditions 8. Electric Characteristics 8.4.14 FPD-Link (LVDS) [Improve] Added the revision information for AC specification table 8. Electric Characteristics 8.7.2 Notes [Limitation] Added the note for shutdown of external power 2. Function List 2.2.1.1 S6J320C [Limitation] Sub clock stabilization time *D 5638486 NNAS 02/22/2017 2. Function List 2.2.2 ID [Improve] Added the IPIdentifier information for graphic subsystem 4. Package and Pin Assignment 4.1 Pin Assignment [Improve] Added "S6J329" for PKG figure information Document Number: 002-05682 Rev. *K Page 216 of 222 S6J3200 Series Revision ECN Orig. of Submission Change Date Description of Change 4. Package and Pin Assignment 4.2 Package Dimensions [Improve] Corrected "A1" value of LEQ216, LET208, LER208 (0.00(MIN)-0.20(MAX) -> 0.05(MIN)-0.15(MAX)) [Improve] Added figure for 256 pin PKG 6. Port Description 6.1 Port Description List [Improve] Exposed pad connection recommendation 7. Precautions and Handling Devices 7.2 Handling Devices [Improve] Corrected the typo in "Method to Switch off VCC12 during Power-off Sequence" (RTSX -> RSTX) 8. Electric Characteristics 8.2 Operation Assurance Condition [Improve] Exposed pad connection recommendation 8. Electric Characteristics 8.2 Operation Assurance Condition [Limitation] Added the note about the connection of Vcc53. 8. Electric Characteristics 8.3.1 Port Function Characteristics [Improve] Corrected the VOH/VOL drive capacity when VCC53=3.0V. 8. Electric Characteristics 8.3.2 Power Supply Current [Improve] Add revision E and J to 'Remarks' of AVCC3_LVDS_PLL. 8.Electric Characteristics 8.3.2.2 PSS Timer Mode Shutdown (PD6=OFF) [Enhance] Added external clock mode spec 8. Electric Characteristics 8.3.2 Power Supply Current [Improve] Added note of regulator mode for measurement condition to 8.3.2.2 PSS Timer Mode Shutdown (PD6=OFF) and 8.3.2.3 PSS Stop Mode Shutdown. 8.Electric Characteristics 8.4.6.2 CSIO Timing (SMR: MD2-0=0b010) [Improve] Corrected the min. value of tSCYC [Improve] Corrected the min. value of tSOVLI and tSOVHI [Improve] Remove the Remarks for tSYSC, tSHSL and tSLSH 8. Electric Characteristics 8.4.10.4 LVDH1 [Limitation] Added more setting needed for power supply voltage stability conditions 8. Electric Characteristics 8.4.10.5 LVDL2 [Improve] Corrected the typo in Max release voltage of "LVDL2V=01" condition. (9.995 > 0.995) 8. Electric Characteristics 8.4.12 Display Controller [Improve] Corrected the min. value of Clock Cycle for DSP0_CLK in 8.4.12.1 Display Controller0 Timing (TTL Mode). [Improve] Corrected the min. value of Clock Cycle for DSP0_CLK+/- in 8.4.12.2 Display Controller0 Timing (RSDS). 8.Electric Characteristics 8.4.15 DDR-HSSPI [Enhance] Add description for reference voltage of VIL, VIH, VOL and VOH 8. Electric Characteristics 8.4.15.2 DDR-HSSPI Interface Timing (DDR Mode) [Improve] Corrected timing chart of "G_SDATA0_0-3", "GSDATA1_0-3" and "GSSEL0,1" for DDR mode. Document Number: 002-05682 Rev. *K Page 217 of 222 S6J3200 Series Revision ECN Orig. of Submission Change Date Description of Change 8. Electric Characteristics 8.4.16 HyperBus [Enhance] Added note with regard to HyperRAM refresh interval in 8.4.16.2 Hyper Bus Write Timing (HyperRAM). [Enhance] Added note with regard to HyperRAM refresh interval in 8.4.16.4 Hyper Bus Read Timing (HyperRAM). 8.Electric Characteristics 8.4.20 JTAG [Enhance] Add JTAG AC specifications 8.Electric Characteristics 8.4.21 QPRC [Enhance] Add AC specification for QPRC 8.Electric Characteristics 8.4.22 I2S [Improve] Add AC specification for I2S 10. Ordering Information [Improve] Updated "Ordering Information" *E 5690647 RUPA 04/18/2017 Updated Cypress logo. Updated Copyright. 1. Overview 1.1 Document Definition Table 1-1 [Improve] Added the "Document Code" information for Application note 2.Function List 2.1 Function List [Enhance] Updated Description and Remark for System-RAM size enhance 2. Function List 2.2.1 Basic Option Figure 2-1 [Improve] Updated "Revision version" information 2.Function List 2.2.1.1 S6J320C Note [Improve] Updated revision digit information 2.Function List 2.2.1.3 S6J320E [Enhance] Added the Basic option information for S6J320E Series 2.Function 2.2.2 ID [Improve] Updated function digit information *F 5879435 HNIS 09/19/2017 2.Function List 2.2.2 ID [Enhance] Added the ID information of Function Digit K, L, M, N for S6J320E Series 3. Product Description 2. Product Description [Improve] Added the description for INITX 3. Product Description 3.2 Product Description Table 3-1. [Limitation] Add limitation of FPD-Link converter. 4. Package and Pin Assignment 4.1 Pin Assignment [Enhance] Added the figure of pin assignment for S6J320E Series 4. Package and Pin Assignment 4.2 Package Dimensions [Enhance] Added the Function Digit information for S6J320E Series 5. I/O Circuit Type 5.1 I/O Circuit Type [Improve] Corrected typo of pull-up/down resistance value in I/O circuit Type E Document Number: 002-05682 Rev. *K Page 218 of 222 S6J3200 Series Revision ECN Orig. of Submission Change Date Description of Change 7. Precautions and Handling Devices 7.2 Handling Devices About C Pin Processing [Improve] Deleted typo about other series product information. 8.Electric Characteristics 8.2 Operation Assurance Condition [Enhance] Added two Power supply sequence 8. Electric Characteristics 8.3.2 Power Supply Current [Enhance] Added the power supply current for S6J320E Series 8.Electric Characteristics 8.3.2.1 Run Mode [Improve] Updated function digit information 8.Electric Characteristics 8.3.2.2 PSS Timer Mode Shutdown (PD6=OFF) [Improve] Updated function digit information 8. Electric Characteristics 8.4.3 Internal Clock Timing Table 8-1 [Enhance] Added the Function Digit K, L, M, N for S6J320E Series 8.Electric Characteristics 8.4.3 Internal Clock Timing [Improve] Updated function digit information 8.Electric Characteristics 8.4.6.2 CSIO Timing (SMR: MD2-0=0b010) [Improve] Updated function digit information 8. Electric Characteristics 8.4.6 Multi-Function Serial [Enhance] Added the Function Digit K, L, M, N for S6J320E Series 8.Electric Characteristics 8.4.16.3 Hyper Bus Read Timing (HyperFlash) [Improve] Updated function digit information 10. Ordering Information [Enhance] Updated "Order Part Number" 4. Package and Pin Assignment 4.1.1 TEQFP-216 Pin Assignment [Improve] Added "S6J329CLxx" for title of figure 4-2 of pin assignment. 4. Package and Pin Assignment 4.1.2 TEQPF-208 Pin Assignment [Improve] Added "S6J329CKxx" for title of figure 4-10 of pin assignment. *G 5986519 HNIS 12/07/2017 7. Precautions and Handling Devices 7.2 Handling Devices Power Supply Pin Processing of an A/D Converter [Improve] Removed "AVRL" 7. Precautions and Handling Devices 7.2 Handling Devices Power-on Sequence of the Power Supply Analog Inputs of an A/D Converter [Improve] Changed from "AVRL" to "AVSS" 8.Electric Characteristics 8.4.4.2 Power supply voltage stability conditions [Improved] Improved timing chart 8.Electric Characteristics 8.5 A/D Converter [Improve] Removed "AVRL5" from Pin Name of Reference voltage AVRL(Symbol) *H 6054035 HNIS 02/01/2018 8.Electric Characteristics 8.4.12 Display Controller [Improve] Change spec of display controller timing. *I 6195638 ATSE 05/31/2018 2.Function List 2.2.1.1 S6J320A [Enhance] Added revision P to Figure 2-1 Document Number: 002-05682 Rev. *K Page 219 of 222 S6J3200 Series Revision ECN Orig. of Submission Change Date Description of Change [Enhance] Added remark 1), 2) of revision to Figure 2-1 [Improve] Removed the description of limitation of revision F from Notes 2.Function List 2.2.1.2 S6J320A [Improve] Removed option Digit U and Pin count Digit L from Figure 2-2 [Improve] Removed function Digit A,C,D from Table 2-3 2.Function List 2.2.1.3 S6J320E [Improve] Removed option Digit U from Figure 2-3 2.Function List 2.2.2 ID [Enhance] Added Revision P of Function Digit 3,4,5,6,7,8,9 to table [Improve] Removed Function Digit A,C,D from table [Improve] Removed Option U of Function Digit B,K,L,M,N from table 3. Product Description 3.2 Product Description [Enhance] Added revision P to FPD-Link Converter of Table 3-1 [Improve] Removed "Note: -The description of the preliminary documentation will be changed without any notification." 4. Package and Pin Assignment 4.1 Pin Assignment [Improve] Removed Function Digit A,C,D from table [Improve] Removed TEQFP-216 of Function Digit B from table 4. Package and Pin Assignment 4.1.1 TEQFP-216 Pin Assignment [Improve] Removed Figure 4-9:TEQFP-216 (S6J32xALxx) 6. Port Description 6.1 Port Description List [Improve] Revised Description of G_SSEL0, G_SSEL1, M_SSEL0, M_SSEL1 from "HS-SPIx select" to "HS-SPI select x" 7. Precautions and Handling Devices 7.2 Handling Devices [Enhance] Added revision P to "Method to Switch off VCC12 during Power-off Sequence" 8. Electric Characteristics 8.3.1 Port Function Characteristics [Enhance] Added Hysteresis voltage (VHYS1-12) 8. Electric Characteristics 8.3.2.1 Run Mode [Enhance] Added revision P to Remark of "ILVDS" [Improve] Removed function digit A,C,D from title 8. Electric Characteristics 8.3.2.2 PSS Timer Mode Shutdown (PD6=OFF) [Improve] Removed function digit A,C,D from title 8. Electric Characteristics 8.3.2.3 PSS Stop Mode Shutdown [Improve] Removed function digit A,C,D from title 8. Electric Characteristics 8.4.3 Internal Clock Timing [Improve] Removed function digit A,C,D from Notes: 8. Electric Characteristics 8.4.4.2 Power Supply voltage stability conditions [Enhance] Added revision P title and Notes: 8. Electric Characteristics 8.4.6.2 CSIO Timing (SMR: MD2-0=0b010) [Improve] Removed function digit A,C,D from Remark Document Number: 002-05682 Rev. *K Page 220 of 222 S6J3200 Series Revision ECN Orig. of Submission Change Date Description of Change 8. Electric Characteristics 8.4.10.4 LVDH1 [Enhance] Added revision P to Note and title of tFV5, tFV12 8. Electric Characteristics 8.4.12.1 Display Controller0 Timing (TTL Mode) [Enhance] Added revision P to Notes: [Improve] Removed function digit A,C,D from Note 8. Electric Characteristics 8.4.12.2 Display Controller0 Timing (RSDS) [Enhance] Added revision P to Notes: [Improve] Removed function digit A,C,D from Notes: 8. Electric Characteristics 8.4.12.3 Display Controller1 Timing [Enhance] Added revision P to Notes: 8. Electric Characteristics 8.4.14.1 For Revision M [Enhance] Added revision P title and Notes: 8. Electric Characteristics 8.4.16.3 Hyper Bus Read Timing (HyperFlash) [Enhance] Revised revision G to revision H, M, P of (C) 8. Electric Characteristics 8.4.16.4 Hyper Bus Read Timing (HyperRAM) [Enhance] Revised after revision G to revision H, M, P of (C) 8. Electric Characteristics 8.7.2 Notes [Enhance] Added revision P to Notes 10. Ordering Information [Improve] Removed S6J32BALSExC2000x, S6J32DAKSExE2000x, S6J32DALSExC2000x and added S6J32K/L/M/N devices [Enhance] Added revision P devices [Enhance] Added option U devices [Improve] Defined ordering options for all devices *J 6269495 ATSE 08/01/2018 11. Errata [Improve] Added Errata chapter as new chapter 8. Electric Characteristics 8.4.1 Source Clock Timing [Enhance] CAN PLL jitter *K 6530775 ATSE 04/04/2019 8. Electric Characteristics 8.4.15.1 DDR-HSSPI [Improve] Revised timing figure. 10. Ordering Information Table 10 1: Order Part Number Table [Improve] Removed S6J323CKSMSE2000A, S6J323CLSMSC2000A, S6J324CLSMSC20000, S6J326CKSMSE20000, S6J328CKSMSE2000A, S6J328CLSMSC2000A, S6J329CLSMSC2000A [Enhance] Added S6J328CLSPSC2D000, S6J329CLSPSC2D000 Document Number: 002-05682 Rev. *K Page 221 of 222 S6J3200 Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC(R) Solutions Products cypress.com/arm PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU Automotive cypress.com/automotive Cypress Developer Community Clocks & Buffers cypress.com/clocks Interface cypress.com/interface Internet of Things cypress.com/iot Memory cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless Arm(R) Cortex(R) Microcontrollers Community | Projects | Videos | Blogs | Training | Components Technical Support cypress.com/support Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. (c) Cypress Semiconductor Corporation, 2015-2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). 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"High-Risk Device" means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices. "Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i) Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-05682 Rev. *K April 4, 2019 Page 222 of 222