FEATURES FUNCTIONAL BLOCK DIAGRAMS SPI interface with error detection Includes CRC, invalid read/write address, and SCLK count error detection Supports burst mode and daisy-chain mode Industry-standard SPI Mode 0 and SPI Mode 3 interface compatible Round robin mode allows switching times comparable with a parallel interface General-purpose digital outputs to control other devices, such as parallel switches from Analog Devices, Inc. 4 typical on resistance at 25C 0.5 typical on-resistance flatness at 25C 0.2 typical on-resistance match between channels at 25C VSS to VDD analog signal range Fully specified at 15 V, 5 V, and +12 V Power-up sequence of VDD, VSS, and GND before applying VL and digital/analog inputs 1.8 V logic compatibility with 2.7 V VL 3.3 V 24-lead LFCSP package ADGS1408 S1 D S8 SPI INTERFACE SCLK SDI CNV SDO 16791-001 GPO1 GPO2 GPO3 GPO4 CS RESET/VL Figure 1. ADGS1408 Functional Block Diagram ADGS1409 S1A DA S4A S1B APPLICATIONS DB S4B Automated test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communications systems Relay replacement GPO1 GPO2 GPO3 GPO4 GPO5 SPI INTERFACE SCLK SDI CS RESET/VL CNV SDO 16791-002 Data Sheet SPI Interface, 4 RON, 15 V/+12 V/5 V, 1.8 V Logic Control, 8:1/Dual 4:1 Muxes ADGS1408/ADGS1409 Figure 2. ADGS1409 Functional Block Diagram GENERAL DESCRIPTION The ADGS1408/ADGS1409 are analog multiplexers comprising eight single channels and four differential channels, respectively. A serial peripheral interface (SPI) controls the switches. The SPI interface has robust error detection features such as cyclic redundancy check (CRC) error detection, invalid read/write address detection, and SCLK count error detection. It is possible to daisy-chain multiple ADGS1408/ADGS1409 devices together. Daisy-chain mode enables the configuration of multiple devices with a minimal amount of digital lines. The ADGS1408/ADGS1409 can also operate in burst mode to decrease the time between SPI commands. iCMOS construction ensures ultra low power dissipation, making the devices ideally suited for portable and battery-powered instruments. supplies. In the off condition, signal levels up to the supplies are blocked. The on-resistance profile is flat over the full analog input range, which ensures linearity and low distortion when switching audio signals. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. SPI interface removes the need for parallel conversion, logic traces, and reduces GPIO channel count. Daisy-chain mode removes additional logic traces when multiple devices are used. CRC error detection, invalid read/write address detection, and SCLK count error detection ensure a robust digital interface. CRC and error detection capabilities allow the use of the ADGS1408/ADGS1409 in safety critical systems. Minimal distortion. Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADGS1408/ADGS1409 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Software Reset ............................................................................. 24 Applications ....................................................................................... 1 Daisy-Chain Mode ..................................................................... 24 Functional Block Diagrams ............................................................. 1 Power-On Reset .......................................................................... 25 General Description ......................................................................... 1 Round Robin Mode.................................................................... 26 Product Highlights ........................................................................... 1 General-Purpose Outputs (GPOs) .......................................... 27 Revision History ............................................................................... 2 Applications Information .............................................................. 28 Specifications..................................................................................... 3 Digital Input Buffers .................................................................. 28 15 V Dual Supply ....................................................................... 3 Power Supply Rails ..................................................................... 28 5 V Dual Supply ......................................................................... 5 Power Supply Recommendations............................................. 28 12 V Single Supply ........................................................................ 7 Power Supply Sequencing ......................................................... 28 Continuous Current per Channel, Sx or Dx ............................. 9 Register Summaries ........................................................................ 29 Timing Characteristics .............................................................. 10 Register Details ............................................................................... 30 Absolute Maximum Ratings.......................................................... 12 Switch Data Register .................................................................. 30 Thermal Resistance .................................................................... 12 Error Configuration Register.................................................... 31 ESD Caution ................................................................................ 12 Error Flags Register .................................................................... 31 Pin Configurations and Function Descriptions ......................... 13 Burst Enable Register ................................................................. 32 Typical Performance Characteristics ........................................... 15 Round Robin Enable Register................................................... 32 Test Circuits ..................................................................................... 19 Round Robin Channel Configuration Register ..................... 32 Terminology .................................................................................... 22 CNV Edge Select Register ......................................................... 33 Theory of Operation ...................................................................... 23 Software Reset Register ............................................................. 33 Address Mode ............................................................................. 23 Outline Dimensions ....................................................................... 34 Error Detection Features ........................................................... 23 Ordering Guide .......................................................................... 34 Clearing the Error Flags Register ............................................. 24 Burst Mode .................................................................................. 24 REVISION HISTORY 6/2018--Revision 0: Initial Version Rev. 0 | Page 2 of 34 Data Sheet ADGS1408/ADGS1409 SPECIFICATIONS 15 V DUAL SUPPLY VDD = +15 V 10%, VSS = -15 V 10%, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) +25C 4 4.7 0.2 0.78 0.5 0.72 0.04 0.2 0.04 0.45 0.1 1.5 -40C to +85C High Impedance Output Capacitance GPOx Output Voltage High, VOH Low, VOL Timing tON (GPO) tOFF (GPO) Break-Before-Make Time Delay, tD Unit Test Conditions/Comments VDD to VSS V typ max typ VS = 10 V, IS = -10 mA, see Figure 32 VDD = +13.5 V, VSS = -13.5 V VS = 10 V, IS = -10 mA 5.7 6.7 0.85 1.1 0.77 0.92 0.6 5.0 2.0 30.0 3.0 30.0 DIGITAL OUTPUTS SDO Output Voltage Low, VOL High Impedance Leakage Current -40C to +125C Low, VINL Input Current, IINL or IINH 0.001 Digital Input Capacitance, CIN 4 VDD = +16.5 V, VSS = -16.5 V VS = 10 V, VD = 10 V, see Figure 35 VS = 10 V, VD = 10 V, see Figure 35 VS = VD = 10 V, see Figure 31 V max V max A typ 0.1 A max pF typ VL - 0.2 V 0.2 V min V max ISOURCE = 100 A ISINK = 100 A ns typ ns max ns typ ns max ns typ CL = 15 pF, see Figure 43 4 DIGITAL INPUTS Input Voltage High, VINH nA typ nA max nA typ nA max nA typ nA max VS = 10 V, IS = -10 mA 0.4 0.2 0.001 95 115 15 20 50 max typ max 115 115 25 25 35 ns min 2 1.35 0.8 0.8 V min V min V max V max A typ A max pF typ 0.1 Rev. 0 | Page 3 of 34 ISINK = 5 mA ISINK = 1 mA VOUT = VGND or VL CL = 15 pF, see Figure 43 CL = 15 pF, see Figure 44 3.3 V < VL 5.5 V 2.7 V VL 3.3 V 3.3 V < VL 5.5 V 2.7 V VL 3.3 V VIN = VGND or VL ADGS1408/ADGS1409 Parameter DYNAMIC CHARACTERISTICS1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Data Sheet +25C -40C to +85C -40C to +125C Unit Test Conditions/Comments 145 185 120 220 245 ns typ ns max ns typ RL = 100 , CL = 35 pF VS = 10 V, see Figure 40 RL = 100 , CL = 35 pF 165 185 200 ns max VS = 10 V, see Figure 41 ns typ RL = 100 , CL = 35 pF 175 195 ns max VS = 10 V, see Figure 41 20 RL = 100 , CL = 35 pF VS1 = VS2 = 10 V, see Figure 39 VS = 0 V, RS = 0 , CL = 1 nF, see Figure 42 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 33 RL = 110 , 15 V p-p, f = 20 Hz to 20 kHz, see Figure 36 RL = 50 , CL = 5 pF, see Figure 37 125 155 Break-Before-Make Time Delay, tD Charge Injection, QINJ -50 ns typ ns min pC typ Off Isolation -64 dB typ Channel to Channel Crosstalk -70 dB typ Total Harmonic Distortion + Noise 0.025 % typ -3 dB Bandwidth ADGS1408 ADGS1409 Insertion Loss 60 115 0.24 MHz typ MHz typ dB typ 14 pF typ 80 40 pF typ pF typ 135 90 pF typ pF typ 0.002 A typ A max A typ A max A typ A max CS (Off ) CD (Off ) ADGS1408 ADGS1409 CD (On), CS (On) ADGS1408 ADGS1409 POWER REQUIREMENTS IDD 40 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 26 and Figure 27 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz 1 220 380 270 440 VDD = +16.5 V, VSS = -16.5 V All switches open S8/S4A closed, VL = 5.5 V S8/S4A closed, VL = 2.7 V IL Inactive 6.3 8.0 Inactive, SCLK = 1 MHz SCLK = 50 MHz Inactive, SDI = 1 MHz SDI = 25 MHz Active at 50 MHz 14 7 390 210 15 7.5 230 120 1.8 2.1 0.7 1.0 Rev. 0 | Page 4 of 34 A typ A max A typ A typ A typ A typ A typ A typ A typ A typ mA typ mA max mA typ mA max Digital inputs = 0 V or VL CS = VL and SDI = 0 V or VL, VL = 5 V CS = VL and SDI = 0 V or VL, VL = 3 V CS = VL and SDI = 0 V or VL, VL = 5 V CS = VL and SDI = 0 V or VL, VL = 3 V CS and SCLK = 0 V or VL, VL = 5 V CS and SCLK = 0 V or VL, VL = 3 V CS and SCLK = 0 V or VL, VL = 5 V CS and SCLK = 0 V or VL, VL = 3 V Digital inputs toggle between 0 V and VL, VL = 5.5 V E E E E E E E E Digital inputs toggle between 0 V and VL, VL = 2.7 V Data Sheet Parameter ISS ADGS1408/ADGS1409 +25C 0.002 -40C to +85C 1 4.5 16.5 VDD/VSS 1 -40C to +125C Unit A typ A max V min V max Test Conditions/Comments Digital inputs = 0 V or VL GND = 0 V GND = 0 V Guaranteed by design; not subject to production test. 5 V DUAL SUPPLY VDD = +5 V 10%, VSS = -5 V 10%, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) +25C -40C to +85C Unit VDD to VSS V typ 7.4 9 0.3 10.5 12 max typ 0.78 1.5 2.5 0.91 1.1 2.5 2.8 max typ max 0.02 0.2 0.02 0.45 0.04 0.3 0.6 5.0 0.8 20.0 1.1 22.0 DIGITAL OUTPUTS SDO Output Voltage Low, VOL High Impedance Leakage Current -40C to +125C 0.4 0.2 0.001 0.1 High Impedance Output Capacitance GPOx Output Voltage High, VOH Low, VOL Timing tON (GPO) tOFF (GPO) Break-Before-Make Time Delay, tD 4 VL - 0.2 V 0.2 95 115 15 20 50 115 115 25 25 35 Rev. 0 | Page 5 of 34 nA typ nA max nA typ nA max nA typ nA max Test Conditions/Comments VS = 4.5 V, IS = -10 mA, see Figure 32 VDD = +4.5 V, VSS = -4.5 V VS = 4.5 V, IS = -10 mA VS = 4.5 V, IS = -10 mA VDD = +5.5 V, VSS = -5.5 V VS = 4.5 V, VD = 4.5 V, Figure 35 VS = 4.5 V, VD = 4.5 V, see Figure 35 VS = VD = 4.5 V, see Figure 31 V max V max A typ A max pF typ ISINK = 5 mA ISINK = 1 mA VOUT = VGND or VL V min V max ISOURCE = 100 A ISINK = 100 A ns typ ns max ns typ ns max ns typ ns min CL = 15 pF, see Figure 43 CL = 15 pF, see Figure 43 CL = 15 pF, see Figure 44 ADGS1408/ADGS1409 Parameter DIGITAL INPUTS Input Voltage High, VINH Data Sheet +25C -40C to +85C Low, VINL Input Current, IINL or IINH -40C to +125C Unit Test Conditions/Comments 2 1.35 0.8 0.8 V min V min V max V max A typ A max pF typ 3.3 V < VL 5.5 V 2.7 V VL 3.3 V 3.3 V < VL 5.5 V 2.7 V VL 3.3 V VIN = VGND or VL RL = 100 , CL = 35 pF VS = 3 V, see Figure 40 RL = 100 , CL = 35 pF VS = 3 V, see Figure 41 RL = 100 , CL = 35 pF VS = 3 V, see Figure 41 RL = 100 , CL = 35 pF VS1 = VS2 = 3 V, see Figure 39 VS = 0 V, RS = 0 , CL = 1 nF, see Figure 42 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 33 RL = 110 , 5 V p-p, f = 20 Hz to 20 kHz, see Figure 36 RL = 50 , CL = 5 pF, see Figure 37 0.001 0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 Transition Time, tTRANSITION 4 Break-Before-Make Time Delay, tD 320 440 265 365 245 330 95 Charge Injection, QINJ -10 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation -64 dB typ Channel to Channel Crosstalk -70 dB typ Total Harmonic Distortion + Noise 0.06 % typ -3 dB Bandwidth ADGS1408 ADGS1409 Insertion Loss 40 80 0.5 MHz typ MHz typ dB typ 20 pF typ 130 65 pF typ pF typ 180 120 pF typ pF typ 0.002 A typ VDD = +5.5 V, VSS = -5.5 V Digital inputs = 0 V or VL, VL = 5.5 V A max A typ A max S8/S4A closed, VL = 2.7 V tON (EN) tOFF (EN) 515 570 425 470 370 400 55 CS (Off ) CD (Off ) ADGS1408 ADGS1409 CD (On), CS (On) ADGS1408 ADGS1409 POWER REQUIREMENTS IDD RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 26 and Figure 27 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz 1 14 20 Rev. 0 | Page 6 of 34 Data Sheet Parameter IL Inactive Inactive, SCLK = 1 MHz SCLK = 50 MHz Inactive, SDI = 1 MHz SDI = 25 MHz Active at 50 MHz ADGS1408/ADGS1409 +25C -40C to +85C -40C to +125C Unit Test Conditions/Comments 14 A typ A max A typ Digital inputs = 0 V or VL 8.0 7 A typ 390 A typ 210 A typ 15 7.5 230 120 1.8 A typ A typ A typ A typ mA typ 6.3 2.1 0.7 1.0 ISS 0.002 1.0 4.5 16.5 VDD/VSS 1 mA max mA typ mA max A typ A max V min V max CS = VL and SDI = 0 V or VL, VL = 5V CS = VL and SDI = 0 V or VL, VL = 3V CS = VL and SDI = 0 V or VL, VL = 5V CS = VL and SDI = 0 V or VL, VL = 3V CS and SCLK = 0 V or VL, VL = 5 V CS and SCLK = 0 V or VL, VL = 3 V CS and SCLK = 0 V or VL, VL = 5 V CS and SCLK = 0 V or VL, VL = 3 V Digital inputs toggle between 0 V and VL, VL = 5.5 V E E E E E E E E Digital inputs toggle between 0 V and VL, VL = 2.7 V Digital inputs = 0 V or VL GND = 0 V GND = 0 V Guaranteed by design; not subject to production test. 12 V SINGLE SUPPLY VDD = 12 V 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT (ON) +25C -40C to +85C -40C to +125C Unit 0 V to VDD V typ 6.7 VS = 0 V to 10 V, IS = -10 mA, see Figure 32 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = -10 mA 8.7 0.2 10.2 11.7 max typ 0.82 1.5 2.5 0.85 1.1 VS = 0 V to 10 V, IS = -10 mA 2.5 2.8 max typ max nA typ VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V, see Figure 35 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) 0.04 0.2 0.04 0.6 Drain Off Leakage, ID (Off ) 0.45 0.06 0.44 1.0 37.0 1.3 32.0 Channel On Leakage, ID (On), IS (On) Test Conditions/Comments 5.0 Rev. 0 | Page 7 of 34 nA max nA typ nA max nA typ nA max VS = 1 V/10 V, VD = 10 V/1 V, see Figure 35 VS = VD = 1 V/10 V, see Figure 31 ADGS1408/ADGS1409 Parameter DIGITAL OUTPUTS SDO Output Voltage Low, VOL High Impedance Leakage Current Data Sheet +25C -40C to +85C -40C to +125C Unit Test Conditions/Comments 0.4 0.2 V max V max A typ A max pF typ ISINK = 5 mA ISINK = 1 mA VOUT = VGND or VL V min V max ISOURCE = 100 A ISINK = 100 A ns typ ns max ns typ ns max ns typ ns min CL = 15 pF, see Figure 43 0.001 0.1 High Impedance Output Capacitance GPOx Output Voltage High, VOH Low, VOL Timing tON (GPO) tOFF (GPO) Break-Before-Make Time Delay, tD 4 VL - 0.2 V 0.2 95 115 15 20 50 115 115 25 25 35 DIGITAL INPUTS Input Voltage High, VINH 2 1.35 0.8 0.8 Low, VINL Input Current, IINL or IINH 0.001 0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD 4 210 280 195 250 145 185 90 340 385 295 325 215 240 50 Charge Injection, QINJ -12 CL = 15 pF, see Figure 44 V min V min V max V max A typ A max pF typ 3.3 V < VL 5.5 V 2.7 V VL 3.3 V 3.3 V < VL 5.5 V 2.7 V VL 3.3 V VIN = VGND or VL ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ RL = 100 , CL = 35 pF VS = 8 V, see Figure 40 RL = 100 , CL = 35 pF VS = 8 V, see Figure 41 RL = 100 , CL = 35 pF VS = 8 V, see Figure 41 RL = 100 , CL = 35 pF VS1 = VS2 = 8 V, see Figure 39 VS = 6 V, RS = 0 , CL = 1 nF, see Figure 42 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 33 RL = 50 , CL = 5 pF, see Figure 37 Off Isolation -64 dB typ Channel to Channel Crosstalk -70 dB typ ADGS1408 ADGS1409 Insertion Loss 36 72 0.5 MHz typ MHz typ dB typ CS (Off ) CD (Off ) ADGS1408 ADGS1409 20 pF typ 120 60 pF typ pF typ -3 dB Bandwidth Rev. 0 | Page 8 of 34 CL = 15 pF, see Figure 43 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 26 and Figure 27 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz Data Sheet Parameter CD (On), CS (On) ADGS1408 ADGS1409 POWER REQUIREMENTS IDD ADGS1408/ADGS1409 +25C -40C to +85C -40C to +125C Unit 170 110 pF typ pF typ 0.002 A typ A max A typ A max A typ A max 1 220 380 270 440 Test Conditions/Comments VS = 6 V, f = 1 MHz VDD = 13.2 V All switches open S8/S4A closed, VL = 5.5 V S8/S4A closed, VL = 2.7 V IL Inactive 6.3 14 A typ A max A typ 7 A typ 390 A typ 210 A typ 15 7.5 230 120 1.8 A typ A typ A typ A typ mA typ 8.0 Inactive, SCLK = 1 MHz SCLK = 50 MHz Inactive, SDI = 1 MHz SDI = 25 MHz Active at 50 MHz 2.1 mA max mA typ 0.7 1.0 5 20 VDD 1 mA max V min V max Digital inputs = 0 V or VL CS = VL and SDI = 0 V or VL, VL = 5 V CS = VL and SDI = 0 V or VL, VL = 3 V CS = VL and SDI = 0 V or VL, VL = 5 V CS = VL and SDI = 0 V or VL, VL = 3 V CS and SCLK = 0 V or VL, VL = 5 V CS and SCLK = 0 V or VL, VL = 3 V CS and SCLK = 0 V or VL, VL = 5 V CS and SCLK = 0 V or VL, VL = 3 V Digital inputs toggle between 0 V and VL, VL = 5.5 V E E E E E E E E Digital inputs toggle between 0 V and VL, VL = 2.7 V GND = 0 V, VSS = 0 V GND = 0 V, VSS = 0 V Guaranteed by design; not subject to production test. CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx Table 4. ADGS1408, One Channel On Parameter CONTINUOUS CURRENT, Sx OR D1 VDD = 15 V, VSS = -15 V (JA = 58.4C/W) VDD = 12 V, VSS = 0 V (JA = 58.4C/W) VDD = 5 V, VSS = -5 V (JA = 58.4C/W) 1 25C 85C 125C Unit 304.9 259.7 247.2 133.6 122.7 119.3 48.9 48 47.6 mA max mA max mA max 25C 85C 125C Unit 229.6 194.7 185.2 114.3 103 99.6 47.2 45.7 45.2 mA max mA max mA max Sx refers to the S1 to S8 pins. Table 5. ADGS1409, Two Channels On Parameter CONTINUOUS CURRENT, Sx OR Dx1 VDD = 15 V, VSS = -15 V (JA = 58.4C/W) VDD = 12 V, VSS = 0 V (JA = 58.4C/W) VDD = 5 V, VSS = -5 V (JA = 58.4C/W 1 Sx refers to the S1A to S4A and S1B to S4B pins, and Dx refers to the DA and DB pins. Rev. 0 | Page 9 of 34 ADGS1408/ADGS1409 Data Sheet TIMING CHARACTERISTICS VL = 2.7 V to 5.5 V, GND = 0 V, and all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization, not production tested. Table 6. Parameter TIMING CHARACTERISTICS t1 t2 t3 t4 t5 t6 t7 t8 t91 t10 t11 t12 t13 1 Limit Unit Test Conditions/Comments 20 8 8 10 6 8 10 20 20 20 20 8 8 ns min ns min ns min ns min ns min ns min ns min ns max ns max ns max ns min ns min ns min SCLK or CNV period SCLK or CNV high pulse width SCLK or CNV low pulse width CS falling edge to SCLK or CNV active edge Data setup time Data hold time SCLK or CNV active edge to CS rising edge CS falling edge to SDO data available SCLK falling edge to SDO data available CS rising edge to SDO returns to high impedance CS high time between SPI commands CS falling edge to SCLK/CNV becomes stable CS rising edge to SCLK/CNV becomes stable Measured with the 1 k pull-up resistor to VL and 20 pF load. t9 determines the maximum SCLK frequency when SDO is used. Timing Diagrams t1 SCLK t4 t2 t3 t7 CS t5 SDI R/W t6 A6 A5 D2 D1 D0 t10 t9 0 0 1 D2 D1 D0 16791-102 SDO t8 Figure 3. Address Mode Timing Diagram Rev. 0 | Page 10 of 34 Data Sheet ADGS1408/ADGS1409 t1 SCLK t2 t3 t4 t7 CS D7 SDI t6 D6 D0 D7 INPUT BYTE FOR DEVICE N t9 SDO 0 0 0 D1 D0 INPUT BYTE FOR DEVICE N + 1 D7 ZERO BYTE t8 D6 D6 D1 t10 D0 16791-103 t5 INPUT BYTE FOR DEVICE N Figure 4. Daisy-Chain Timing Diagram t11 CS t13 16791-004 SCLK OR CNV t12 Figure 5. SCLK or CNV and CS Timing Relationship t4 CS t2 t3 t7 CNV t9 t1 S1 S2 Figure 6. Round Robin Timing Diagram Rev. 0 | Page 11 of 34 S(LAST) 16791-005 SDO MUX CHANNEL t10 RESYNC ADGS1408/ADGS1409 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 7. Parameter VDD to VSS VDD to GND VSS to GND VL to GND For VDD 5.5V For VDD > 5.5V SDO GPOx Analog Inputs1 Digital Inputs1 Peak Current, Sx or Dx Pins2 Continuous Current, Sx or Dx2, 3 Operating Temperature Range Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature, Pb-Free Rating 35 V -0.3 V to +25 V +0.3 V to -25 V -0.3 V to VDD + 0.3 V -0.3 V to +6 V -0.3 V to +6 V -0.3 V to VL + 0.3 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first -0.3 V to +6 V 497 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% -40C to +125C -65C to +150C 150C 260(+0/-5)C Only one absolute maximum rating can be applied at any one time. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. Table 8. Thermal Resistance Package Type CP-24-172 1 2 JA 58.4 JCB1 17.2 JT 2.2 Unit C/W JCB is the junction to the bottom of the case value. Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board with four thermal vias. See JEDEC JESD51. ESD CAUTION 1 Overvoltages at the digital Sx and Dx pins are clamped by internal diodes. Limit current to the maximum ratings given. 2 Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins. 3 See Table 4 and Table 5. Rev. 0 | Page 12 of 34 Data Sheet ADGS1408/ADGS1409 20 SDO 19 GPO1 21 CS 22 SCLK 23 SDI 24 GPO2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VSS 1 18 V DD 17 S5 S1 2 S2 3 ADGS1408 16 CNV GND 4 TOP VIEW (Not to Scale) 15 S6 14 RESET/VL 13 S7 S8 12 NIC 11 D 10 NIC 9 S4 7 GPO4 8 GPO3 6 NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO THE SUBSTRATE, VSS. 2. NIC = NOT INTERNALLY CONNECTED. 16791-007 S3 5 Figure 7. ADGS1408 Pin Configuration Table 9. ADGS1408 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9, 11 10 12 13 14 Mnemonic VSS S1 S2 GND S3 GPO3 S4 GPO4 NIC D S8 S7 RESET/VL 15 16 17 18 19 20 S6 CNV S5 VDD GPO1 SDO 21 22 23 24 CS SCLK SDI GPO2 EPAD Description Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground. Source Terminal 1. This pin can be an input or output. Source Terminal 2. This pin can be an input or output. Ground (0 V) Reference. Source Terminal 3. This pin can be an input or output. General-Purpose Output 3. This pin is a digital output. Source Terminal 4. This pin can be an input or output. General-Purpose Output 4. This pin is a digital output. Not Internally Connected. Drain Terminal. This pin can be an input or output. Source Terminal 8. This pin can be an input or output. Source Terminal 7. This pin can be an input or output. RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply. Pull the RESET/VL pin low to complete a hardware reset. After a reset, all switches open, and the appropriate registers are set to their default. Source Terminal 6. This pin can be an input or output. Convert Digital Input. When in round robin mode, the CNV pin is used to cycle through the selected channels. Source Terminal 5. This pin can be an input or output. Most Positive Power Supply Potential. General-Purpose Output 1. This pin is a digital output. Serial Data Output. This pin can be used for daisy chaining a number of these devices together or for reading back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of SCLK. Pull this open-drain output to VL with an external resistor. Active Low Control Input. CS is the frame synchronization signal for the input data. Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz. Serial Data Input. Data is captured on the positive edge of the serial clock input. General-Purpose Output 2. This pin is a digital output. Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS. Rev. 0 | Page 13 of 34 20 SDO 19 GPO1 22 SCLK 21 CS 23 SDI Data Sheet 24 GPO2 ADGS1408/ADGS1409 18 V DD 17 S1B VSS 1 S1A 2 S2A 3 ADGS1409 16 CNV GND 4 TOP VIEW (Not to Scale) 15 S2B S3A 5 14 RESET/VL GPO3 6 NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO THE SUBSTRATE, VSS. 16791-008 S4B 12 GPO5 11 DB 10 DA 9 S4A 7 GPO4 8 13 S3B Figure 8. ADGS1409 Pin Configuration Table 10. ADGS1409 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mnemonic VSS S1A S2A GND S3A GPO3 S4A GPO4 DA DB GPO5 S4B S3B RESET/VL 15 16 17 18 19 20 S2B CNV S1B VDD GPO1 SDO 21 22 23 24 CS SCLK SDI GPO2 EPAD Description Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground. Source Terminal 1A. This pin can be an input or output. Source Terminal 2A. This pin can be an input or output. Ground (0 V) Reference. Source Terminal 3A. This pin can be an input or output. General-Purpose Output 3. This pin is a digital output. Source Terminal 4A. This pin can be an input or output. General-Purpose Output 4. This pin is a digital output. Drain Terminal A. This pin can be an input or output. Drain Terminal B. This pin can be an input or output. General-Purpose Output 5. This pin is a digital output. Source Terminal 4B. This pin can be an input or output. Source Terminal 3B. This pin can be an input or output. RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply. Pull the RESET/VL pin low to complete a hardware reset. After a reset, all switches open, and the appropriate registers are set to their default. Source Terminal 2B. This pin can be an input or output. Convert Digital Input. When in round robin mode, the CNV pin is used to cycle through the selected channels. Source Terminal 1B. This pin can be an input or output. Most Positive Power Supply Potential. General-Purpose Output 1. This pin is a digital output. Serial Data Output. This pin can be used for daisy chaining a number of these devices together or for reading back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of SCLK. Pull this open-drain output to VL with an external resistor. Active Low Control Input. CS is the frame synchronization signal for the input data. Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz. Serial Data Input. Data is captured on the positive edge of the serial clock input. General-Purpose Output 2. This pin is a digital output. Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS. Rev. 0 | Page 14 of 34 Data Sheet ADGS1408/ADGS1409 TYPICAL PERFORMANCE CHARACTERISTICS 7 VDD = +15V VSS = -15V TA = 25C 6 ON RESISTANCE () 4 3 2 1 0 -16.5 VDD VDD VDD VDD VDD = +15V, VSS = -15V = +13.5V, VSS = -13.5V = +12V, VSS = -12V = +10V, VSS = -10V = +16.5V, VSS = -16.5V -12.5 -8.5 -4.5 5 4 3 2 1 -0.5 3.5 7.5 11.5 15.5 SOURCE OR DRAIN VOLTAGE (V) 0 -15 16791-006 ON RESISTANCE () 5 TA TA TA TA = +25C = +85C = -40C = +125C -10 -5 0 5 10 15 SOURCE OR DRAIN VOLTAGE (V) Figure 9. On Resistance vs. VS or VD for Various Dual Supplies 16791-108 6 Figure 12. On Resistance vs. VS or VD for Various Temperatures, 15 V Dual Supply 9 12 VDD = +5V VSS = -5V TA = 25C 8 10 5 4 3 2 1 0 -7 VDD VDD VDD VDD -6 = +7V, VSS = -7V = +5.5V, VSS = -5.5V = +5V, VSS = -5V = +4.5V, VSS = -4.5V -5 -4 -3 -2 -1 0 1 2 3 4 5 7 6 4 0 -5 TA TA TA TA = +25C = +85C = -40C = +125C -4 -3 -2 -1 0 1 2 3 4 5 SOURCE OR DRAIN VOLTAGE (V) Figure 10. On Resistance vs. VS or VD for Various Dual Supplies Figure 13. On Resistance vs. VS or VD for Various Temperatures, 5 V Dual Supply 13 10 TA = 25C VSS = 0V 12 VDD = 12V VSS = 0V 9 11 8 ON RESISTANCE () 9 8 7 6 5 4 VDD VDD VDD VDD VDD 2 1 0 1 = 12V = 13.2V = 10.8V = 8V = 5V 2 3 6 5 4 3 2 TA TA TA TA 1 4 5 6 7 8 9 10 11 12 13 SOURCE OR DRAIN VOLTAGE (V) 0 16791-107 3 7 0 = +25C = +85C = -40C = +125C 2 4 6 8 10 12 SOURCE OR DRAIN VOLTAGE (V) Figure 11. On Resistance vs. VS or VD for Various Single Supplies Figure 14. On Resistance vs. VS or VD for Various Temperatures, 12 V Single Supply Rev. 0 | Page 15 of 34 16791-010 10 ON RESISTANCE () 6 2 SOURCE OR DRAIN VOLTAGE (V) 0 8 16791-009 ON RESISTANCE () 6 16791-036 ON RESISTANCE () 7 ADGS1408/ADGS1409 1.0 IS (OFF) +- ID (OFF) +- IS (OFF) -+ ID (OFF) -+ ID, IS (ON) ++ ID, IS (ON) - - 0.6 0.4 18 VDD = +15V VSS = -15V VBIAS = +10V/-10V 14 0.2 0 -0.2 -0.4 -0.6 10 8 6 4 0 10 20 30 40 50 60 70 80 14 IS (OFF) +- ID (OFF) +- IS (OFF) -+ ID (OFF) -+ ID, IS (ON) ++ ID, IS (ON) - - 10 40 60 80 100 120 TEMPERATURE (C) Figure 18. Leakage Current vs. Temperature, 12 V Single Supply 200 VDD = +15V VSS = -15V VBIAS = +10V/-10V TA = 25C 150 CHARGE INJECTION (pC) 12 20 0 04861-013 -2 16791-011 0 -1.0 Figure 15. Leakage Current vs. Temperature, 15 V Dual Supply 8 6 4 2 0 100 50 VDD = +5V VSS = -5V 0 VDD = +12V VSS = 0V -50 -100 VDD = +15V VSS = -15V 20 40 60 80 100 120 TEMPERATURE (C) -200 -15 16791-012 0 IS (OFF) +- ID (OFF) +- IS (OFF) -+ ID (OFF) -+ ID, IS (ON) ++ ID, IS (ON) - - 9 8 7 -5 0 5 10 15 V S (V) Figure 16. Leakage Current vs. Temperature, 15 V Dual Supply 10 -10 16791-014 -150 -2 Figure 19. Charge Injection vs. Source Voltage (VS) 400 VDD = +5V VSS = -5V VBIAS = +4.5V/-4.5V 15V DS 12V SS 5.5V DS 350 300 tTRANSITION (ns) 6 5 4 3 2 250 200 150 100 1 -1 0 20 40 60 80 100 120 TEMPERATURE (C) Figure 17. Leakage Current vs. Temperature, 5 V Dual Supply 0 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 120 16791-120 50 0 16791-015 LEAKAGE CURRENT (nA) VDD = 12V VSS = 0V VBIAS = 1V/10V 2 TEMPERATURE (C) LEAKAGE CURRENT (nA) 12 -0.8 -4 IS (OFF) +- ID (OFF) +- IS (OFF) -+ ID (OFF) -+ ID, IS (ON) ++ ID, IS (ON) - - 16 LEAKAGE CURRENT (nA) 0.8 LEAKAGE CURRENT (nA) Data Sheet Figure 20. Transition Time vs. Temperature for Single Supply (SS) and Dual Supply (DS) Rev. 0 | Page 16 of 34 Data Sheet 0 0 VDD = +15V VSS = -15V TA = 25C -20 NO DECOUPLING 100nF DECOUPLING CAP 10uF + 100nF DECOUPLING CAP -10 -20 -30 -40 -60 -80 VDD = +15V VSS = -15V TA = 25C -40 ACPSRR (dB) OFF ISOLATION (dB) ADGS1408/ADGS1409 -50 -60 -70 -80 -100 -90 -100 -120 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 21. Off Isolation vs. Frequency, 15 V Dual Supply 0 -120 100 10k 100k FREQUENCY (Hz) 1M 10M Figure 24. AC Power Supply Rejection Ratio (ACPSRR) vs. Frequency, 15 V Dual Supply 0.10 VDD = +15V VSS = -15V TA = 25C -20 1k 16791-124 1k 16791-121 -110 -140 LOAD = 110 TA = 25C 0.09 0.08 0.07 THD + N (%) CROSSTALK (dB) -40 -60 -80 -100 VDD = +5V, VSS = -5V, VS = +5V p-p 0.06 0.05 0.04 0.03 VDD = +15V, VSS = -15V, VS = +15V p-p 0.02 -120 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 0 10 16791-122 1k 100 Figure 22. ADGS1408 Crosstalk vs. Frequency, 15 V Dual Supply 0 0 -0.5 -1.0 -40 -60 BANDWIDTH (dB) ADJACENT CHANNELS NON-ADJACENT CHANNELS -80 -1.5 -2.0 -2.5 -100 -3.0 -140 -3.5 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 23. ADGS1409 Crosstalk vs. Frequency, 15 V Dual Supply VDD = +15V VSS = -15V TA = 25C -4.0 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M 16791-019 -120 16791-123 CROSSTALK (dB) 100k 10k Figure 25. THD + N vs. Frequency VDD = +15V VSS = -15V TA = 25C -20 1k FREQUENCY (Hz) 16791-032 0.01 -140 Figure 26. ADGS1408 Insertion Loss vs. Frequency, 15 V Dual Supply Rev. 0 | Page 17 of 34 ADGS1408/ADGS1409 Data Sheet 250 0 15V -0.5 200 +12V -1.5 IDD (A) -2.0 TA = 25C ADGS1408 WITH S8 SELECTED 100 -2.5 -3.0 50 VDD = +15V VSS = -15V TA = 25C -4.0 100 5V 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 0 16791-031 -3.5 150 2.7 3.0 3.5 4.0 4.5 5.0 5.5 VL (V) 16791-129 BANDWIDTH (dB) -1.0 Figure 29. IDD vs. VL Figure 27. ADGS1409 Insertion Loss vs. Frequency, 15 V Dual Supply 2.0 450 1.5 400 TA = 25C 350 300 IL (uA) 0.5 0 -0.5 250 200 150 -1.0 100 -2.0 0 1 2 3 4 5 6 TIME (s) 7 8 50 9 0 VL = 5V VL = 3V 1 10 20 30 40 SCLK FREQUENCY (MHz) Figure 30. IL vs. SCLK Frequency when CS is High Figure 28. Digital Feedthrough Rev. 0 | Page 18 of 34 50 16791-126 SCLK = 2.5MHz SCLK IDLE VDD = +15V VSS = -15V TA = 25C -1.5 16791-128 VOUT (mV) 1.0 Data Sheet ADGS1408/ADGS1409 TEST CIRCUITS Dx VS VD 16791-024 Sx Sx A (ON) ID (OFF) Dx A VS 16791-028 IS (OFF) D VD Figure 31. On Leakage Figure 35. Off Leakage VDD 0.1F VSS VDD VSS 0.1F AUDIO PRECISION RS IDS Sx VS V p-p V1 Dx Dx RON = V1/IDS Figure 36. THD + Noise Figure 32. On Resistance VDD VSS VOUT VDD 0.1F 0.1F NETWORK ANALYZER 16791-029 S VOUT RL 110 GND 16791-025 Sx VDD VSS 0.1F 0.1F VSS VDD NETWORK ANALYZER VSS S1 RL 50 D S2 Sx RL 50 50 VS Dx GND VOUT VS 16791-026 CHANNEL TO CHANNEL CROSSTALK = 20 log V RL OUT 50 GND INSERTION LOSS = 20 log VOUT WITH SWITCH VS WITHOUT SWITCH 16791-030 VS Figure 37. -3 dB Bandwidth Figure 33. Channel to Channel Crosstalk VSS VSS NETWORK ANALYZER 0.1F 0.1F VDD NETWORK ANALYZER VSS Sx 50 RL 50 VDD VSS VS 50 VS VOUT Dx VOUT RL 50 GND INTERNAL BIAS S1 RL 50 VOUT OFF ISOLATION = 20 log VS 16791-027 ACPSRR = 20 log GND D1 VOUT VS NOTES 1. BOARD AND COMPONENT EFFECTS ARE NOT DE-EMBEDDED FROM THE ACPSRR MEASUREMENT. Figure 34. Off Isolation Figure 38. ACPSRR Rev. 0 | Page 19 of 34 NC 16791-141 VDD ADGS1408/ADGS1409 Data Sheet VDD VSS VDD VSS SCLK S1 0V VS S2 TO S7 S8 VS1 = VS8 80% 80% ADGS14081 OUTPUT OUTPUT D 100 1SIMILAR 35pF 16791-143 GND tD CONNECTION FOR THE ADGS1409. Figure 39. Break-Before-Make Time Delay, tD VDD VSS VDD VSS SCLK ADGS14081 S1 50% 50% VS1 S2 TO S7 VS8 90% D RL 100 GND CL 35pF VOUT 10% tTRANSITION 1SIMILAR tTRANSITION CONNECTION FOR THE THE ADGS1409. 16791-144 S8 Figure 40. Transition Time, tTRANSITION VDD VSS VDD VSS SCLK ADGS14081 S1 50% 50% VS1 S2 TO S8 90% GND RL 100 CL 35pF VOUT 10% tOFF (EN) 1 SIMILAR tON (EN) CONNECTION FOR THE ADGS1409. 16791-145 D Figure 41. Switching Times, tON (EN) and tOFF (EN) 3V SCLK RS VDD VSS VDD VSS Sx Dx QINJ = CL x VOUT INPUT LOGIC V OUT SWITCH OFF SWITCH ON Figure 42. Charge Injection, QINJ Rev. 0 | Page 20 of 34 GND 16791-132 VOUT V OUT CL 1nF VS Data Sheet ADGS1408/ADGS1409 VDD VSS VDD VSS SCLK ADGS14081 GPOx CL 15pF 50% 50% VGPO 90% GND 10% tON (GPO) 16791-146 tOFF (GPO) 1SIMILAR CONNECTION FOR THE ADGS1409. Figure 43. GPOx Timing, tON (GPO) and tOFF (GPO) VGPO2 80% 80% VSS VDD VSS 0V 80% GPO1 80% ADGS14081 0V CL 15pF GPO2 tD (GPO) tD (GPO) GND CL 15pF TIME DELAY BETWEEN GPO1 TURNING OFF AND GPO2 TURNING ON 1SIMILAR CONNECTION FOR THE ADGS1409. Figure 44. GPOx Break-Before-Make Time Delay, tD (GPO) Rev. 0 | Page 21 of 34 VGPO1 VGPO2 16791-147 VGPO1 VDD ADGS1408/ADGS1409 Data Sheet TERMINOLOGY CD (On), CS (On) CD (on) and CS (on) are the on switch capacitances, which are measured with reference to ground. IDD IDD is the positive supply current. ISS ISS is the negative supply current. VD, VS VD and VS are the analog voltages on Terminal Dx and Terminal Sx, respectively. RON RON is the ohmic resistance between Terminal Dx and Terminal Sx. RON RON is the difference between the RON of any two channels. RFLAT (ON) RFLAT (ON) is flatness defined as the difference between the maximum and minimum value of on resistance values measured over the specified analog signal range. IS (Off) IS (off) is the source leakage current with the switch off. CIN CIN is the digital input capacitance. tON tON is the delay between applying the digital control input and the output switching on. tOFF tOFF is the delay between applying the digital control input and the output switching off. Off Isolation Off isolation is a measure of unwanted signal coupling through an off switch. Charge Injection Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. Crosstalk Crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. ID (Off) ID (off) is the drain leakage current with the switch off. IS (On), ID (On) IS (on) and ID (on) are the channel leakage currents with the switch on. -3 dB Bandwidth Bandwidth is the frequency at which the output is attenuated by 3 dB. VINL VINL is the maximum input voltage for Logic 0. On Response On response is the frequency response of the on switch. VINH VINH is the minimum input voltage for Logic 1. IINL, IINH IINL and IINH are the low and high input currents of the digital inputs. CD (Off) CD (off) is the off switch drain capacitance, which is measured with reference to ground. CS (Off) CS (off) is the off switch source capacitance, which is measured with reference to ground. Insertion Loss Insertion loss is the loss due to the on resistance of the switch. Total Harmonic Distortion + Noise (THD + N) THD + N is the ratio of the harmonic amplitude plus noise of the signal to the fundamental. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR is the ratio of the amplitude of signal on the output to the amplitude of the modulation. ACPSRR is a measure of the ability of the devices to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. Rev. 0 | Page 22 of 34 Data Sheet ADGS1408/ADGS1409 THEORY OF OPERATION The target register address of an SPI command is determined on the eighth SCLK rising edge. Data from this register propagates out on SDO from the 9th to the 16th SCLK falling edge during SPI reads. A register write occurs on the 16th SCLK rising edge during SPI writes. The ADGS1408/ADGS1409 are a set of serially controlled analog multiplexers comprising eight single channels and four differential channels, respectively, with error detection features. SPI Mode 0 and SPI Mode 3 can be used with the devices. The devices operate with SCLK frequencies up to 50 MHz. The default mode for the ADGS1408/ADGS1409 is address mode, in which the registers of the device are accessed by a 16-bit SPI command bounded by CS. The SPI command becomes 24-bit if the user enables CRC error detection. Other error detection features include SCLK count error and invalid read/write error. If any of these SPI interface errors occur, they are detectable by reading the error flags register. The ADGS1408/ADGS1409 can also operate in two other modes, namely burst mode and daisy-chain mode. During any SPI command, SDO sends out eight alignment bits on the first eight SCLK falling edges. The alignment bits observed at SDO are 0x25. ERROR DETECTION FEATURES Protocol and communication errors on the SPI interface are detectable. There are three detectable errors: incorrect SCLK error detection, invalid read and write address error detection, and CRC error detection. Each error has a corresponding enable bit in the error configuration register. In addition, there is an error flag bit for each error in the error flags register. The interface pins of the ADGS1408/ADGS1409 are CS, SCLK, SDI, and SDO. Hold CS low when using the SPI interface. Data is captured on SDI on the rising edge of SCLK, and data is propagated out on SDO on the falling edge of SCLK. SDO has an open-drain output. Connect a pull-up to this output. When not pulled low by the ADGS1408/ADGS1409, SDO is in a high impedance state. CRC Error Detection The CRC error detection feature extends a valid SPI frame by eight SCLK cycles. These eight extra cycles are needed to send the CRC byte for that SPI frame. The CRC byte is calculated by the SPI block using the 16-bit payload: the R/W bit, Register Address Bits[6:0], and Register Data Bits[7:0]. The CRC polynomial used in the SPI block is x8 + x2 + x1 + 1 with a seed value of 0. For a timing diagram with CRC enabled, see Figure 46. Register writes occur at the 24th SCLK rising edge with CRC error checking enabled. ADDRESS MODE Address mode is the default mode for the ADGS1408/ADGS1409 on power-up. A single SPI frame in address mode is bounded by a CS falling edge and the succeeding CS rising edge. An SPI frame is comprised of 16 SCLK cycles. The timing diagram for address mode is shown in Figure 45. The first SDI bit indicates if the SPI command is a read or write command. When the first bit is set to 0, a write command is issued, and if the first bit is set to 1, a read command is issued. The next seven bits determine the target register address. The remaining eight bits provide the data to the addressed register. The last eight bits are ignored during a read command, because during these clock cycles, SDO propagates out the data contained in the addressed register. During an SPI write, the microcontroller/CPU provides the CRC byte through SDI. The SPI block checks the CRC byte just before the 24th SCLK rising edge. On this same edge, the register write is prevented if an incorrect CRC byte is received by the SPI interface. In the case of the incorrect CRC byte being detected, the CRC error flag is asserted in the error flags register. During an SPI read, the CRC byte is provided to the microcontroller through SDO. The CRC error detection feature is disabled by default and can be configured by the user through the error configuration register. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 CS SDI SDO 0 0 1 0 0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 16791-133 SCLK Figure 45. Address Mode Timing Diagram 1 2 8 9 10 16 17 18 19 20 21 22 23 24 R/W A6 A0 D7 D6 D0 C7 C6 C5 C4 C3 C2 C1 C0 CS SDI SDO 0 0 1 D7 D6 D0 C7 C6 C5 Figure 46. Timing Diagram with CRC Enabled Rev. 0 | Page 23 of 34 C4 C3 C2 C1 C0 16791-134 SCLK ADGS1408/ADGS1409 Data Sheet SCLK Count Error Detection BURST MODE SCLK count error detection allows the user to detect if an incorrect number of SCLK cycles are sent by the microcontroller/ CPU. When in address mode, with CRC disabled, 16 SCLK cycles are expected. If 16 SCLK cycles are not detected, the SCLK count error flag asserts in the error flags register. When fewer than 16 SCLK cycles are received by the device, a write to the register map never occurs. When the ADGS1408/ADGS1409 receive more than 16 SCLK cycles, a write to the memory map still occurs at the 16th SCLK rising edge, and the flag asserts in the error flags register. With CRC enabled, the expected number of SCLK cycles is 24. SCLK count error detection is enabled by default and can be configured by the user through the error configuration register. The SPI interface can accept consecutive SPI commands without the need to deassert the CS line, which is called burst mode. Burst mode is enabled through the burst enable register. This mode uses the same 16-bit command to communicate with the device. In addition, the response of the device at SDO is still aligned with the corresponding SPI command. Figure 47 shows an example of SDI and SDO during burst mode. The invalid read/write address and CRC error checking functions operate similarly during burst mode as they do during address mode. However, SCLK count error detection operates in a slightly different manner. The total number of SCLK cycles within a given CS frame are counted, and if the total is not a multiple of 16, or a multiple of 24 when CRC is enabled, the SCLK count error flag asserts. Invalid Read/Write Address Error Detection An invalid read/write address error detects when a nonexistent register address is a target for a read or write. In addition, this error asserts when a write to a read only register is attempted. The invalid read/write address error flag asserts in the error flags register when an invalid read/write address error occurs. The invalid read/write address error is detected on the ninth SCLK rising edge, which means a write to the register never occurs when an invalid address is targeted. Invalid read/write address error detection is enabled by default and can be disabled by the user through the error configuration register. SDI COMMAND0[15:0] COMMAND1[15:0] COMMAND2[15:0] COMMAND3[15:0] SDO RESPONSE0[15:0] RESPONSE1[15:0] RESPONSE2[15:0] RESPONSE3[15:0] Figure 47. Burst Mode Frame SOFTWARE RESET When in address mode, the user can initiate a software reset. To initiate a software reset, write two consecutive SPI commands, namely 0xA3 followed by 0x05, targeting Register 0x0B. After a software reset, all register values are set to default. CLEARING THE ERROR FLAGS REGISTER DAISY-CHAIN MODE To clear the error flags register, write the special 16-bit SPI frame, 0x6CA9, to the device. This SPI command does not trigger the invalid read/write address error. When CRC is enabled, the user must also send the correct CRC byte for a successful error clear command. At the 16th or 24th SCLK rising edge, the error flags register resets to 0. The connection of several ADGS1408/ADGS1409 devices in a daisy-chain configuration is possible, and Figure 48 shows this setup. All devices share the same CS and SCLK line, whereas the SDO of a device forms a connection to the SDI of the next device, creating a shift register. In daisy-chain mode, SDO is an eightcycle delayed version of SDI. When in daisy-chain mode, all commands target the switch data register. Therefore, it is not possible to make configuration changes while in daisy-chain mode. ADGS1408 ADGS1408 DEVICE 1 DEVICE 2 S1 S1 D D VL S8 CNV SPI INTERFACE 16791-135 CS SDO S8 CNV SPI INTERFACE 16791-050 SDI SCLK CS SDO RESET/VL Figure 48. Two ADGS1408 Devices Connected in a Daisy-Chain Configuration Rev. 0 | Page 24 of 34 Data Sheet ADGS1408/ADGS1409 The ADGS1408/ADGS1409 can only enter daisy-chain mode when in address mode by sending the 16-bit SPI command, 0x2500 (see Figure 49). When the ADGS1408/ADGS1409 receive this command, the SDO of the device sends out the same command because the alignment bits at SDO are 0x25, which allows multiple daisy-connected devices to enter daisychain mode in a single SPI frame. A hardware reset is required to exit daisy-chain mode. An SCLK rising edge reads in data on SDI while data is propagated out of SDO on an SCLK falling edge. The expected number of SCLK cycles must be a multiple of eight before CS goes high. When the expected number of SCLK cycles is not a multiple of eight, the SPI interface sends the last eight bits received to the switch data register. POWER-ON RESET The digital section of the ADGS1408/ADGS1409 goes through an initialization phase during VL power-up. This initialization also occurs after a hardware or software reset. After VL power-up or a reset, ensure a minimum of 120 s from the time of power-up or reset before any SPI command is issued. Ensure that VL does not drop out during the 120 s initialization phase because it may result in incorrect operation of the ADGS1408/ADGS1409. For the timing diagram of a typical daisy-chain SPI frame, see Figure 50. When CS goes high, Device 1 writes Command 0, Bits[7:0] to its switch data register, Device 2 writes Command 1, Bits[7:0] to its switches, and so on. The SPI block uses the last eight bits it received through SDI to update the switches. After entering daisy-chain mode, the first eight bits sent out by SDO on each device in the chain are 0x00. When CS goes high, the internal shift register value does not reset back to zero. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 CS SDI SDO 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 16791-037 SCLK 0 Figure 49. SPI Command to Enter Daisy-Chain Mode SDI COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0] COMMAND0[7:0] DEVICE 1 SDO 8'h00 COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0] DEVICE 2 SDO2 8'h00 8'h00 COMMAND3[7:0] COMMAND2[7:0] DEVICE 3 SDO3 8'h00 8'h00 8'h00 COMMAND3[7:0] DEVICE 4 NOTES 1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY. 16791-038 CS Figure 50. Example of an SPI Frame Where Four ADGS1408/ADGS1409 Devices Connect in Daisy-Chain Mode Rev. 0 | Page 25 of 34 ADGS1408/ADGS1409 Data Sheet After configuration completes, the round robin enable register allows the ADGS1408/ADGS1409 to enter round robin mode. When in round robin mode, the SPI is no longer used to switch between channels. Instead, to switch from one channel to another, ensure that a digital signal is present on the CNV pin while CS is pulled low. ROUND ROBIN MODE Round robin mode allows the ADGS1408/ADGS1409 to cycle through the channels faster by reducing the overhead needed from the digital interface to switch from one channel to the next. The round robin configuration register selects which channels are to be included in a cycle, and the CNV edge select register selects on which edge of CNV the ADGS1408/ADGS1409 switch to the next channel in the sequence. At the end of the channel cycle, a resync pulse appears on SDO to inform the user that the current cycle ended; then, SDO loops back to the start of the sequence of channels. Figure 51 shows an example of the round robin mode interface, and Figure 52 shows the CNV signal of the analog-to-digital converter (ADC) being used in conjunction with the ADGS1408 in round robin mode. To exit round robin mode, either perform a hardware reset or send the following two 16-bit addressable mode SPI frames: 0xA318, followed by 0xE3B4. These frames are the only SPI commands recognized by the SPI interface while in round robin mode. Round robin mode is significantly faster than addressable mode to cycle through channels because it removes the 16-bit overhead required to change input channel. In addition, round robin mode removes the need for SCLK to be running, which reduces the digital current consumption, IL. The maximum CNV frequency is bound by the transition time of the device along with the required settling time for the application. ROUND ROBIN CYCLE CS CNV MUX CHANNEL X S1 S2 S(LAST) 16791-154 RESYNC SDO Figure 51. Round Robin Mode Interface Example tCYC VIO S1 S2 S3 SDI D ADGS1408 IN7 S8 IN AD7980 SDO CNV CNV ACQUISITION CNV tACQ tCONV SCK ACQUISITION CONVERSION CS SDI SCK CONVERT GPO GPO CLK 1 SCK 2 3 14 15 16 DATA IN DIGITAL HOST tDIS tEN SDO MUX CHANNEL D15 N D14 D13 N+1 Figure 52. Example of the CNV Signal of an ADC Cycling Through Channels in the ADGS1408 Rev. 0 | Page 26 of 34 D1 D0 N+2 16791-155 IN0 IN1 IN2 Data Sheet ADGS1408/ADGS1409 or low. When the device is in round robin mode, the GPOs are driven low. The logic low level is GND, and VL sets the logic high level. Figure 53 shows how the ADGS1408 can be used to control another device, which in this example is the ADG758. GENERAL-PURPOSE OUTPUTS (GPOs) The ADGS1408 has four GPOs, and the ADGS1409 has five GPOs. These digital outputs allow the control of other devices using the ADGS1408/ADGS1409. The GPOs are controlled from the SW_DATA register where they can be either set high ADGS1408 ADG758 S1 S1 D S8 S8 SDO CNV D SPI INTERFACE GPO1 GPO2 1 OF 8 DECODER GPO3 GPO4 A0 A1 A2 EN 16791-156 SDI SCLK CS RESET/VL Figure 53. ADGS1408 Device Controlling the ADG758 Rev. 0 | Page 27 of 34 ADGS1408/ADGS1409 Data Sheet APPLICATIONS INFORMATION There are input buffers present on the digital input pins (CS, SCLK, and SDI). These buffers are active at all times; as a result, there is current drawn from the VL supply if SCLK or SDI are toggling, regardless of whether CS is active. For typical values of this current draw, refer to the Specifications section and Figure 30. (LDOs), ADP7118 and ADP7182 (positive and negative LDOs, respectively), that can be used to reduce the output ripple of the ADP5070 in ultralow noise sensitive applications. The ADM7160 can be used to generate the VL voltage required to power digital circuitry within the ADGS1408/ADGS1409. +16.5V +5V INPUT To guarantee correct operation of the ADGS1408/ADGS1409, 0.1 F decoupling capacitors are required. The voltage range that can be supplied to VL is from 2.7 V to 5.5 V. The device is fully specified at 15 V, 5 V, and +12 V analog supply voltage ranges. POWER SUPPLY RECOMMENDATIONS Analog Devices has a wide range of power management products to meet the requirements of most high performance signal chains. An example of a bipolar power solution is shown in Figure 54. The ADP5070 dual switching regulator generates a positive and negative supply rail for the ADGS1408/ADGS1409, an amplifier, and/or a precision converter in a typical signal chain. Also shown in Figure 54 are two optional low dropout regulators +3.3V ADP7118 +15V ADP7182 -15V LDO POWER SUPPLY RAILS The ADGS1408/ADGS1409 can operate with bipolar supplies between 4.5 V and 16.5 V. The supplies on VDD and VSS do not need to be symmetrical; however, the VDD to VSS range must not exceed 33 V. The ADGS1408/ADGS1409 can also operate with single supplies between 5 V and 20 V with VSS connected to GND. ADM7160 ADP5070 LDO -16.5V LDO 16791-142 DIGITAL INPUT BUFFERS . Figure 54. Bipolar Power Solution Table 11. Recommended Power Management Devices Product ADP5070 ADM7160 ADP7118 ADP7182 Description 1 A/0.6 A, dc-to-dc switching regulator with independent positive and negative outputs 5.5 V, 200 mA, ultralow noise, linear regulator 20 V, 200 mA, low noise, CMOS LDO linear regulator -28 V, -200 mA, low noise, LDO linear regulator POWER SUPPLY SEQUENCING Take care to ensure correct power supply sequencing. Incorrect power supply sequencing can result in the device being subjected to stresses beyond the maximum ratings listed in Table 7. Ensure that the analog power supplies (VDD and VSS) and ground (GND) are present before applying VL, the digital inputs, and the analog inputs. Failure to adhere to this sequence may result in damage to the device. Rev. 0 | Page 28 of 34 Data Sheet ADGS1408/ADGS1409 REGISTER SUMMARIES Table 12. ADGS1408 Register Summary Reg. 0x01 0x02 0x03 0x05 0x06 0x07 0x09 0x0B Name Bit 7 SW_DATA GPO4 ERR_CONFIG ERR_FLAGS BURST_EN ROUND_ROBIN_EN RROBIN_CHANNEL_CONFIG S8_EN CNV_EDGE_SEL SOFT_RESETB Bit 6 GPO3 S7_EN Bit 5 Bit 4 GPO2 GPO1 Reserved Reserved S6_EN Bit 3 A2 Bit 2 A1 RW_ERR_EN RW_ERR_FLAG Reserved Reserved S5_EN S4_EN S3_EN Reserved SOFT_RESETB Bit 1 Bit 0 A0 EN SCLK_ERR_EN CRC_ERR_EN SCLK_ERR_FLAG CRC_ERR_FLAG BURST_MODE_EN ROUND_ROBIN_EN S2_EN S1_EN CNV_EDGE_SEL Default 0x00 0x06 0x00 0x00 0x00 0xFF 0x00 0x00 RW R/W R/W R R/W R/W R/W R/W R/W Default 0x00 0x06 0x00 0x00 0x00 0x0F 0x00 0x00 RW R/W R/W R R/W R/W R/W R/W R/W Table 13. ADGS1409 Register Summary Reg. 0x01 0x02 0x03 0x05 0x06 0x07 0x09 0x0B Name SW_DATA ERR_CONFIG ERR_FLAGS BURST_EN ROUND_ROBIN_EN RROBIN_CHANNEL_CONFIG CNV_EDGE_SEL SOFT_RESETB Bit 7 GPO5 Bit 6 GPO4 Bit 5 Bit 4 GPO3 GPO2 Reserved Reserved Reserved Bit 3 GPO1 Bit 2 A1 RW_ERR_EN RW_ERR_FLAG Reserved Reserved S4_EN S3_EN Reserved SOFT_RESETB Rev. 0 | Page 29 of 34 Bit 1 A0 SCLK_ERR_EN SCLK_ERR_FLAG S2_EN Bit 0 EN CRC_ERR_EN CRC_ERR_FLAG BURST_MODE_EN ROUND_ROBIN_EN S1_EN CNV_EDGE_SEL ADGS1408/ADGS1409 Data Sheet REGISTER DETAILS SWITCH DATA REGISTER Address: 0x01, Reset: 0x00, Name: SW_DATA The switch data register controls the status of the eight switches of the ADGS1408/ADGS1409, as well as the general-purpose digital outputs. Use the ADGS1408/ADGS1409 truth tables in conjunction with the bit descriptions. Table 14. Bit Descriptions for SW_DATA, ADGS1408 Bit(s) 7 6 5 4 3 2 1 0 Bit Name GPO4 GPO3 GPO2 GPO1 A2 A1 A0 EN Settings Description Enable bit for GPO4. Enable bit for GPO3. Enable bit for GPO2. Enable bit for GPO1. Enable bit for A2. Enable bit for A1. Enable bit for A0. Enable bit for ADGS1408. ADGS1408 disabled. ADGS1408 enabled. 0 1 Default 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W R/W R/W R/W Default 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 15. Bit Descriptions for SW_DATA, ADGS1409 Bit(s) 7 6 5 4 3 2 1 0 Bit Name GPO5 GPO4 GPO3 GPO2 GPO1 A1 A0 EN Settings Description Enable bit for GPO5. Enable bit for GPO4. Enable bit for GPO3. Enable bit for GPO2. Enable bit for GPO1. Enable bit for A1. Enable bit for A0. Enable bit for ADGS1409. ADGS1409 disabled. ADGS1409 enabled. 0 1 Table 16. ADGS1408 Truth Table1 A2 X 0 0 0 0 1 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 X means don't care. Table 17. ADGS1409 Truth Table1 A1 X 0 0 1 1 1 A0 X 0 1 0 1 EN 0 1 1 1 1 On Switch Pair None S1 S2 S3 S4 X means don't care. Rev. 0 | Page 30 of 34 On Switch None S1 S2 S3 S4 S5 S6 S7 S8 Data Sheet ADGS1408/ADGS1409 ERROR CONFIGURATION REGISTER Address: 0x02, Reset: 0x06, Name: ERR_CONFIG The error configuration register allows the user to enable and disable the relevant error features as required. Table 18. Bit Descriptions for ERR_CONFIG Bit(s) [7:3] 2 Bit Name Reserved RW_ERR_EN Settings 0 1 1 SCLK_ERR_EN 0 1 0 CRC_ERR_EN 0 1 Description These bits are reserved. Set these bits to 0. Enable bit for detecting an invalid read/write address. Disabled. Enabled. Enable bit for detecting the correct number of SCLK cycles in an SPI frame. 16 SCLK cycles are expected when CRC is disabled and burst mode is disabled. 24 SCLK cycles are expected when CRC is enabled and burst mode is disabled. A multiple of 16 SCLK cycles is expected when CRC is disabled and burst mode is enabled. A multiple of 24 SCLK cycles is expected when CRC is enabled and burst mode is enabled. Disabled. Enabled. Enable bit for CRC error detection. SPI frames are 24 bits wide when enabled. Disabled. Enabled. Default 0x0 0x1 Access R R/W 0x1 R/W 0x0 R/W ERROR FLAGS REGISTER Address: 0x03, Reset: 0x00, Name: ERR_FLAGS The error flags register allows the user to determine if an error occurred. To clear the error flags register, write the special 16-bit SPI command, 0x6CA9, to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, the user must include the correct CRC byte during the SPI write for the clear error flags register command to succeed. Table 19. Bit Descriptions for ERR_FLAGS Bit(s) [7:3] 2 Bit Name Reserved RW_ERR_FLAG Settings 0 1 1 SCLK_ERR_FLAG 0 1 0 CRC_ERR_FLAG 0 1 Description These bits are reserved. Set these bits to 0. Error flag for invalid read/write address. The error flag asserts during an SPI read if the target address does not exist. The error flag also asserts when the target address of an SPI write does not exist or is read only. No error. Error. Error flag for the detection of the correct number of SCLK cycles in an SPI frame. No error. Error. Error flag that determines if a CRC error occurred during a register write. No error. Error. Rev. 0 | Page 31 of 34 Default 0x0 0x0 Access R R 0x0 R 0x0 R ADGS1408/ADGS1409 Data Sheet BURST ENABLE REGISTER Address: 0x05, Reset: 0x00, Name: BURST_EN The burst enable register allows the user to enable or disable burst mode. When enabled, the user can send multiple consecutive SPI commands without deasserting CS. Table 20. Bit Descriptions for BURST_EN Bit(s) [7:1] 0 Bit Name Reserved BURST_MODE_EN Settings 0 1 Description These bits are reserved. Set these bits to 0. Burst mode enable bit. Disabled. Enabled. Default 0x0 0x0 Access R R/W ROUND ROBIN ENABLE REGISTER Address: 0x06, Reset: 0x00, Name: ROUND_ROBIN_EN The round robin register allows the user to enable or disable round robin mode. When enabled, the user can cycle through the channels enabled in the round robin configuration register by presenting the relevant edge on the CNV pin. Table 21. Bit Descriptions for ROUND_ROBIN_EN Bit(s) [7:1] 0 Bit Name Reserved ROUND_ROBIN_EN Settings 0 1 Description These bits are reserved. Set these bits to 0. Round robin mode enable bit. Disabled. Enabled. Default 0x0 0x0 Access R R/W ROUND ROBIN CHANNEL CONFIGURATION REGISTER Address: 0x07, Reset: 0xFF (ADGS1408), 0x0F (ADGS1409), Name: RROBIN_CHANNEL_CONFIG The round robin channel configuration register controls which channels are included in a cycle during round robin mode. During round robin mode, the channels are cycled through in ascending order. Table 22. Bit Descriptions for RROBIN_CHANNEL_CONFIG, ADGS1408 Bit(s) 7 Bit Name S8_EN Settings 0 1 6 S7_EN 0 1 5 S6_EN 0 1 4 S5_EN 0 1 3 S4_EN 0 1 2 S3_EN 0 1 Description Enable bit for S8. S8 disabled during round robin mode. S8 enabled during round robin mode. Enable bit for S7. S7 disabled during round robin mode. S7 enabled during round robin mode. Enable bit for S6. S6 disabled during round robin mode. S6 enabled during round robin mode. Enable bit for S5. S5 disabled during round robin mode. S5 enabled during round robin mode. Enable bit for S4. S4 disabled during round robin mode. S4 enabled during round robin mode. Enable bit for S3. S3 disabled during round robin mode. S3 enabled during round robin mode. Rev. 0 | Page 32 of 34 Default 0x1 Access R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W Data Sheet Bit(s) 1 Bit Name S2_EN ADGS1408/ADGS1409 Settings 0 1 0 S1_EN 0 1 Description Enable bit for S2. S2 disabled during round robin mode. S2 enabled during round robin mode. Enable bit for S1. S1 disabled during round robin mode. S1 enabled during round robin mode. Default 0x1 Access R/W 0x1 R/W Default 0x0 0x1 Access R R/W 0x1 R/W 0x1 R/W 0x1 R/W Table 23. Bit Descriptions for RROBIN_CHANNEL_CONFIG, ADGS1409 Bit(s) [7:4] 3 Bit Name Reserved S4_EN Settings 0 1 2 S3_EN 0 1 1 S2_EN 0 1 0 S1_EN 0 1 Description These bits are reserved. Set these bits to 0. Enable bit for S4. S4 disabled during round robin mode. S4 enabled during round robin mode. Enable bit for S3. S3 disabled during round robin mode. S3 enabled during round robin mode. Enable bit for S2. S2 disabled during round robin mode. S2 enabled during round robin mode. Enable bit for S1. S1 disabled during round robin mode. S1 enabled during round robin mode. CNV EDGE SELECT REGISTER Address: 0x06, Reset: 0x00, Name: CNV_EDGE_SEL The CNV edge select register allows the user to select the active edge of the CNV pin when the device is in round robin mode. Table 24. Bit Descriptions for CNV_EDGE_SEL Bit(s) [7:1] 0 Bit Name Reserved CNV_EDGE_SEL Settings 0 1 Description These bits are reserved. Set these bits to 0. CNV active edge select bit. Falling edge of CNV is the active edge. Rising edge of CNV is the active edge. Default 0x0 0x0 Access R R/W SOFTWARE RESET REGISTER Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB Use the software reset register to perform a software reset. Write 0xA3 followed by 0x05 consecutively to this register, and the registers of the device reset to their default state. Table 25. Bit Descriptions for SOFT_RESETB Bit(s) [7:0] Bit Name SOFT_RESETB Settings Description To perform a software reset, consecutively write 0xA3 followed by 0x05 to this register. Rev. 0 | Page 33 of 34 Default 0x0 Access R ADGS1408/ADGS1409 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.25 0.18 1 0.50 BSC 2.70 2.60 SQ 2.50 EXPOSED PAD 13 TOP VIEW 1.00 0.95 0.90 6 12 7 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PKG-004677 0.50 0.40 0.30 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 24 19 18 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8. 02-09-2017-A PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 55. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body and 0.95 mm Package Height (CP-24-17) Dimensions shown in millimeters ORDERING GUIDE Model1 ADGS1408BCPZ ADGS1408BCPZ-RL7 ADGS1409BCPZ ADGS1409BCPZ-RL7 EVAL-ADGS1408SDZ EVAL-ADGS1409SDZ 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP] 24-Lead Lead Frame Chip Scale Package [LFCSP] 24-Lead Lead Frame Chip Scale Package [LFCSP] 24-Lead Lead Frame Chip Scale Package [LFCSP] ADGS1408 Evaluation Board ADGS1409 Evaluation Board Z = RoHS Compliant Part. (c)2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16791-0-6/18(0) Rev. 0 | Page 34 of 34 Package Option CP-24-17 CP-24-17 CP-24-17 CP-24-17