INCH-POUND MIL-M-38510/210E 27 March 2006 SUPERSEDING MIL-M-38510/210D 16 May 1986 MILITARY SPECIFICATION MICROCIRCUIT, DIGITAL, 16,384 BIT SCHOTTKY, BIPOLAR, PROGRAMMABLE READ-ONLY MEMORY (PROM), MONOLITHIC SILICON Inactive for new design after 24 July 1995 This specification is approved for use by all Departments and Agencies of the Department of Defense. The requirements for acquiring the product herein shall consist of this specification sheet and MIL-PRF 38535. 1. SCOPE 1.1 Scope. This specification covers the detail requirements for monolithic silicon, programmable read-only memory (PROM) microcircuits which employ thin film nichrome (NiCr) resistors, platinum-silicide, tungsten (W), titanium-tungsten (TiW) or zapped vertical emitter as the fusible link or programming element. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, (see 6.4). 1.2 Part or Identifying Number (PIN). The PIN is in accordance with MIL-PRF-38535, and as specified herein. 1.2.1 Device types. The device types are as follows: Device type 01 02 03 04 05 Circuit 2048 words/8 bits per word PROM with uncommitted collector 2048 words/8 bits per word PROM with active pull-up and a third high-impedance state output 2048 words/8 bits per word PROM with uncommitted collector 2048 words/8 bits per word PROM with active pull-up And a third high-impedance state output 4096 words/4 bits per word PROM with active pull-up and a third high-impedance state output Access times (ns) 100, 50 100, 50 55, 30 55, 30 80, 40 1.2.2 Device class. The device class is the product assurance level as defined in MIL-PRF-38535. 1.2.3 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter J K R L 3 Descriptive designator GDIP1-T24 or CDIP2-T24 GDFP2-F24 or CDFP3-F24 GDIP1-T20 or CDIP2-T20 GDIP3-T24 or CDIP4-T24 CQCC1-N28 Terminals 24 24 20 24 28 Package style Dual-in-line Flat pack Dual-in-line Dual-in-line Square leadless chip carrier Comments, suggestions, or questions on this document should be addressed to: Commander, Defense Supply Center Columbus, ATTN: DSCC-VAS, P. O. Box 3990, Columbus, OH 43218-3990, or emailed to mailto:memory@dla.mil . Since contact information can change, you may want to verify the currency of this address information using the ASSIST Online database at http://assist.daps.dla.mil AMSC N/A FSC 5962 MIL-M-38510/210E 1.3 Absolute maximum ratings. Supply voltage range ............................................................................. Input voltage range ................................................................................ Storage temperature range .................................................................... Lead temperature (soldering, 10 seconds).............................................. Thermal resistance, junction to case (JC): 1/ Cases J, L, and R.............................................................................. Case K ............................................................................................. Case 3 .............................................................................................. Output voltage range............................................................................... Output sink current.................................................................................. Maximum power dissipation (PD) 3/ ....................................................... Maximum,unction temperature (TJ) 4/ .................................................... -0.5 V dc to +7.0 V dc -1.5 V dc at -10 mA to +5.5 V dc -65C to +150C +300C 40C/W maximum 60C/W maximum 0.08C/W maximum 2/ -0.5 V dc to +VCC 100 mA 1.02 W +175C 1.4 Recommended operating conditions. Supply voltage ....................................................................................... +4.5 V dc minimum to +5.5 V dc maximum Minimum high-level input voltage (VIH) ................................................... 2.0 V dc Maximum low-level input voltage (VIL) .................................................... 0.8 V dc Normalized fanout (each output) .......................................................... 8 mA 5/ Case operating temperature range (TC) .................................................. -55 C to +125 C 2. APPLICABLE DOCUMENTS 2.1 General. The documents listed in this section are specified in sections 3, 4, or 5 of this specification. This section does not include documents cited in other sections of this specification or recommended for additional information or as examples. While every effort has been made to ensure the completeness of this list, document users are cautioned that they must meet all specified requirements of documents cited in sections 3, 4, or 5 of this specification, whether or not they are listed. 2.2 Government documents. 2.2.1 Specifications and Standards. The following specifications and standards form a part of this specification to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATIONS MIL-PRF-38535 - Integrated Circuits (Microcircuits) Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard for Microelectronics. Interface Standard Electronic Component Case Outline ______ 1/ 2/ 3/ 4/ Heat sinking is recommended to reduce the junction temperature. When a thermal resistance value is included in MIL-STD-1835, it shall supersede the value stated herein. Must withstand the added PD due to short circuit test (e.g. IOS). Maximum junction temperature shall not be exceeded except for allowable short circuit duration burn-in screening conditions per method 5004 of MIL-STD-883. 5/ 16 mA for circuits A, B, D, F, H, and I devices. 2 MIL-M-38510/210E (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.3 Order of precedence. In the event of a conflict between the text of this specification and the references cited herein, the text of this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Qualification. Microcircuits furnished under this specification shall be products that are manufactured by a manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturers list before contract award (see 4.3 and 6.3). 3.2 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.3 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein. 3.3.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.3.2 Truth table 3.3.2.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered itme drawing shall be as specified on figure 2. When required in groups A, B, or C (see 4.4), the devices shall be programmed by the manufacturer prior to test in a checkerboard pattern (a minimum of 50 percent of the total number of bits programmed) or to any altered item drawing pattern which includes at least 25 percent of the total number of bits programmed. 3.3.2.2 Programmed devices. The truth table for programmed devices shall be as specified by the altered item drawing. 3.3.3 Functional block diagram. The functional block diagram shall be as specified on figure 3. 3.3.4 Case outlines. The case outlines shall be as specified in 1.2.3. 3.4 Lead material and finish. The lead material and finish shall be in accordance with MIL-PRF-38535 (see 6.6). 3.5 Electrical performance characteristics. The electrical performance characteristics are as specified in table I, and apply over the full recommended case operating temperature range, unless otherwise specified. 3.6 Electrical test requirements. The electrical test requirements shall be as specified in table II, and where applicable, the altered item drawing. The electrical tests for each subgroup are described in table III. 3.7 Marking. Marking shall be in accordance with MIL-PRF-38535. 3 MIL-M-38510/210E TABLE I. Electrical performance characteristics. Test Symbol High-level output voltage VOH Low-level output voltage VOL Input clamp voltage VIC Maximum collector cut-off current High-impedance (off-state) output high current High-impedance (off-state) output low current High-level input current ICEX IIH Low-level input current IIL Short circuit output current Supply current IOS Propagation delay time, high-to-low level logic, address to output Propagation delay time, low-to-high level logic, address to output Propagation delay time, high-to-low level logic, enable to output Propagation delay time, low-to-high level logic, enable to output tPHL1 IOHZ IOLZ ICC tPLH1 Conditions 1/ -55C TC +125C VCC = 4.5 V; IOH = -2 mA; VIH = 2.0 V; VIL = 0.8 V VCC = 4.5 V; IOL = 8 mA; 2/ VIH = 2.0 V; VIL = 0.8 V VCC = 4.5 V; IIN = -10 mA; TC = 25C VCC = 5.5 V; VO = 5.2 V VCC = 5.5 V; V0 = 5.2 V VCC = 5.5 V; V0 = 0.5 V VCC = 5.5 V; VIN = 5.5 V VCC = 5.5 V; VIN = 0.5 V VCC = 5.5 V; V0 = 0.0 V 3/ VCC = 5.5 V; VIN = 0; outputs = open VCC = 4.5 V and 5.5 V; CL = 30 pF (see figure 4) tPHL2 tPLH2 Device type 02,04,05 Limits Min Max 2.4 01,02 03,04,05 0.5 V 01,02 03,04,05 -1.5 V 01,03 100 A 02,04,05 100 A 02,04,05 -100 A 01,02 03,04,05 01,02 03,04,05 02,04,05 50 A -250 A -100 mA 01,02 03,04,05 185 mA 01,02 03,04 05 01,02 03,04 05 01,02 03,04 05 01,02 03,04 05 100 55 80 100 55 80 50 30 40 50 30 40 ns -10 1/ Complete terminal conditions shall be specified in table III. 2/ IOL = 16 mA for circuits A, B, D, F, H, I, and J. 3/ Not more than one output shall be grounded at one time. Output shall be at high logic level prior to test. 4 Unit V ns ns ns MIL-M-38510/210E TABLE II. Electrical test requirements. Subgroups (see table III) 1/, 2/, 3/ Class S Class B devices devices 1 1 MIL-PRF-38535 test requirements Interim electrical parameters Final electrical test parameters for unprogrammed devices Final electrical test parameters for programmed devices Group A test requirements Group B end-point electrical parameters subgroup 5 Group C end-point electrical parameters Group D test requirements 1*, 2, 3, 7*, 8 1*, 2, 3, 7* 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 7, 8 1*, 2, 3, 7*, 8 1*, 2, 3, 7*, 8, 9, 1, 2, 3, 7, 8 9, 10, 11 N/A 1, 2, 3, 7, 8 1, 2, 3, 7, 8 1/ * PDA applies to subgroups 1 and 7. 2/ Any or all subgroups may be combined when using high-speed testers. 3/ Subgroups 7 and 8 shall consist of verifying the pattern specified. 3.8 Processing options. Since the PROM is an unprogrammed memory capable of being programmed by either the manufacturer or the user to result in a wide variety of configurations, two processing options are provided for selection in the contract, using an altered item drawing. 3.8.1 Unprogrammed PROM delivered to the user. All testing shall be verified through group A testing as defined in 3.3.2.1, table II, and table III. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. 3.8.2 Maunufacturer-programmed PROM delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to delivery. 3.9 Microcircuit group assignment. The devices covered by this specification shall be in microcircuit group number 14 (see Appendix A MIL-PRF-38535.) 5 MIL-M-38510/210E 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not effect the form, fit, or function as described herein. 4.2 Screening. Screening shall be in accordance with MIL-PRF-38535 and shall be conducted on all devices prior to qualification and quality conformance inspection. The following additional criteria shall apply: a. The burn-in test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document control by the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD883. b. Interim and final electrical test parameters shall be as specified in table II, except interim electrical parameters test prior to burn-in is optional at the discretion of the manufacturer. c. Additional screening for space level product shall be as specified in MIL-PRF-38535, appendix B. d. Class B devices processed to an altered item drawing may be programmed either before or after burn-in at the manufacturer's discretion. The required electrical testing shall include, as a minimum, the final electrical tests for programmed devices as specified in table II herein. Class S devices processed by the manufacturer to an altered item drawing shall be programmed prior to burnin. 4.3 Qualification inspection. Qualification inspection shall be in accordance with MIL-PRF-38535. 4.4 Technology Conformance inspection (TCI). Technology conformance inspection shall be in accordance with MIL-PRF-38535 and as specified herein for groups A, B, C, and D inspections (see 4.4.1 through 4.4.4). 4.4.1 Group A inspection. Group A inspection shall be in accordance with table III of MIL-PRF-38535 and as follows: a. Electrical test requirements shall be as specified in table II herein. b. Subgroups 4, 5, and 6 shall be omitted. c. For unprogrammed devices, a sample shall be be selected to satisfy programmability requirements prior to performing subgroups 9, 10, and 11. Twelve devices shall be submitted to programming (see 3.3.2.1). If more than 2 devices fail to program, the lot shall be rejected, At the manufacturer's option, the sample may be increased to 24 total devices with no more than 4 total device failures allowed. d. For unprogrammed devices, 10 devices from the programmability sample shall be submitted to the requirements of group A, subgroups 9, 10, and 11. If more than two total devices fail in all three subgroups, the lot shall be rejected. At the manufacturer's option, the sample may be increased to 20 total devices with no more that 4 total device failures allowed. 6 MIL-M-38510/210E 4.4.2 Group C inspection. Group C inspection shall be in accordance with table IV of MIL-PRF-38535 and as follows: a. End-point electrical parameters shall be as specified in table II herein. b. The steady-state life test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burnin test circuit shall be maintained under document control by the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MILSTD-883. c. For qualification, at least 50 percent of the sample selected for testing in subgroup 1 shall be programmed (see 3.3.2). For quality conformance inspection, the programmability sample (see 4.4.1c) shall be included in the subgroup 1 tests. 4.4.3 Group D inspection. Group D inspection shall be in accordance with table V of MIL-PRF-38535. Endpoint electrical parameters shall be as specified in table II herein. 4.5 Methods of inspection. Methods of inspection shall be specified and as follows: 4.5.1 Voltage and current. All voltages given are referenced to the microcircuit ground terminal. Currents given are conventional and positive when flowing into the referenced terminal. 4.6 Programming procedure identification. The programming procedure to be utilized shall be identified by the manufacturer's circuit designator. The circuit designator is cross referenced in 6.5 herein with the manufacturer's symbol. 7 MIL-M-38510/210E 4.7 Programming procedure for circuit A. The programming characteristics of table IVA and the following procedures shall be used for programming the device. a. Connect the device in the electrical configuration for programming. The waveforms on figure 5A and the programming characteristics of table IVA shall apply to these procedures. b. Address the PROM with the binary address of the selected word to be programmed. Address inputs are TTL compatible. An open circuit shall not be used to address the PROM. c. Apply VPL voltage to VCC. d. Bring the CE X inputs high and the CEX inputs low to disable the device. The chip enables are TTL compatible. An open circuit shall not be used to disable the device. e. Disable the programming circuitry by applying a voltage of VOPD to the outputs of the PROM. f. Raise VCC to VPH with rise time less than or equal to tTLH. g. After a delay equal to or greater than tD1, apply only one pulse with amplitude of VOPE and duration of tP to the output selected for programming. Note that the PROM is supplied with fuses intact, which generates an output high. Programming a fuse will cause the output to go low. h. Lower VCC to VPL following a delay of tD2 from programming enable pulse applied to an output. i. Enable the PROM for verification by applying VIL to CE X and VIH to CEX. j. Apply VPHV to VCC and verify bit is programmed. k. Repeat 4.7a through 4.7j for all other bits to be programmed in the PROM. l. If any bit does not verify as programmed, it shall be considered a programming reject. 4.8 Programming procedure for circuit B. The programming characteristics of table IVB and the following procedures shall be used for programming the device. a. Connect the device in the electrical configuration for programming. The waveforms on figure 5B and the programming characteristics of table IVB shall apply to these procedures. b. Apply VIH CE 1 and the binary address of the PROM word to be programmed. Raise VCC to VCCP. c. After a tD delay, apply only one VOP to the output to be programmed high. Apply VOP to one output at a time. d. After a tD delay, a pulse CE 1 to a VIL level for a duration of tP. e. After tP and a tD delay, remove VOP from the programmed output. f. Other bits in the same word may be programmed sequentially while the VCC input is at the VCCP level by applying VOP pulses to each output to be programmed and pulsing CE 1 to the VIL level, allowing for proper delays between VOP and CE 1. g. Repeat 4.8b through 4.8e for all bits to be programmed. h. To verify programming, lower VCCP to VCC. Connect a 10 k resistor between each output and VCC. Apply VIL to CE 1 input. The programmed outputs should remain in the high state and the unprogrammed outputs should go to the low level. 8 MIL-M-38510/210E i. If any bit does not verify as programmed, it shall be considered a programming reject. 4.9 Programming procedures for circuit C, device types 02 and 04. The programming characteristics of table IVC and the following procedures shall be used for programming device types 02 and 04. a. Connect the device in the electrical configuration for programming. The waveforms on figure 5C, device types 02 and 04, and the programming characteristics of table IVC, device types 02 and 04, shall apply to these procedures. b. Terminate all device outputs with a 10 k resistor to VCC. Apply VIH to CE1. c. Address the PROM with the binary address of the selected word to be programmed. Raise VCC to VCCP. d. After a tD delay (10 s), apply only one VOUT pulse to the output to be programmed. Program one output at a time. e. After a tD delay (10 s), pulse CE 1 input to logic "0" for a duration of tP. f. After a tD delay (10 s), remove the VOUT pulse from the programmed output. (Programming a fuse will cause the output to go to a high-level logic in the verify mode.) g. Other bits in the same word may be programmed sequentially while the VCC input is at the VCCP level by applying VOUT pulses to each output to be programmed allowing a delay to tD between pulses as shown on figure 5C. h. Repeat 4.9b through 4.9g for all other bits to be programmed. i. To verify programming, after tD (10 s) delay, lower VCC to VCCH and apply a logic "0" level to CE 1 input. The programmed output should remain in the "1" state. Again, lower VCC to VCCL and verify that the programmed output remains in the "1" state. j. If any bit does not verify as programmed, it shall be considered a programming reject. 4.10 Programming procedures for circuit C, device type 05. The programming characteristics of table IVC, device type 05, and the following procedures shall be used for programming the device. a. Connect the device in the electrical configuration for programming. The output pins shall be terminated with a 10 k resistor to GND and bypass VCC to GND with a 0.01 F capacitor. The waveforms on figure 5C, device type 05, and the programming characteristics of table IVC, device type 05, shall apply to these procedures. b. Disable the device by applying VIH to CE 2 input and VIL to CE 1. The chip enable pins are TTL compatible. c. Apply VIL to all other pins. d. Address the PROM with the binary address of the selected word to be programmed and reset TP = 5 s. Address inputs are TTL compatible. e. After a delay of TD1, raise the VCC pin to VCCP. f. After a delay of TD2, raise the corresponding output pin to VOPF. g. After a delay of TD3, lower CE 2 to VIL for a duration of TP and simultaneously lower the output to VIL and wait TD4. 9 MIL-M-38510/210E h. Return the CE 2 to VIH. i. Wait TD5 and lower VCC to VCCV. j. Wait TD6 and lower CE 2 to VIL for the duration to TV. k. A properly blown fuse will read VOL and unblown fuse will read VOH. 1. If the fuse is blown, go to n. 2. If the fuse is unblown, go to 1. l. If TP is less than 30 s, increment TP by 5 s and go to e. If TP is 5 s go to m. m. If TP is 30 s, the device is a reject. n. After a delay of TD7, select the next output or address to be programmed. o. Repeat steps 4.10d through 4.10k until all required addresses are programmed. p. To verify the program keep VCC pin at VCCV. Apply VIL to CE 2. The programmed fuse will go to the low level and unblown fuse shall remain in the high level. 4.11 Programming procedures for circuit D. The programming characteristics on table IVD, and the following procedures shall be used for programming the device. a. Connect the device in the electrical configuration for programming. The waveforms on figure 5D and the programming characteristics of table IVD shall apply to these procedures. b. Select the word to be programmed by applying the appropriate voltages to the address pins as well as the required voltages to chip enable pins to select the device. c. Apply the proper power, VCC = 6.5 V, GND = 0 V. d. Verify that the bit to be programmed is in the "0" logic state. e. Enable the chip for programming by application of the chip enable voltage, VP(CE1) = 21.0 V to CE 1 (pin 20). CE2 and CE3 should be left high. f. Apply IOP programming current ramp to the output to be programmed. The other outputs shall be left open. Only one output may be programmed at a time. During the rise of the current ramp, the required current will be achieved to program the junction. As programming occurs a drop in voltage can be sensed at the output of the device. Upon detection of VPS, the current shall be held for thap and then shut off. g. Verify that the programmed bit is in the "1" logic state. Lower VP(CE1) to 0 V and read the output. Note: The PROM is supplied with fuses generating a low-level logic output. Programming a fuse will cause the output to go to a high-level logic in the verify mode. h. Lower VCC to 0 V. The power supply duty cycle shall be equal to or less than 50 percent. i. If the bit verifies as not having been programmed at VCC = 6.5 V, then repeat the programming ramp sequence up to 15 times until the bit is programmed. If after 16 programming attempts, the bit does not program, then the device shall be considered a reject. 10 MIL-M-38510/210E j. If the bit verifies as having been programmed at VCC = 6.5 V, then one of the following two conditions shall be followed: (1) If the current required to program was less than IOP(max), then proceed to step 1. (2) If the current required to program was equal to or greater than IOP(max), then the device shall be considered a reject and no further attempts at programming other bits shall be attempted. k. Repeat 4.11a through 4.11j for all other bits to be programmed. l. If any bit does not verify as programmed, it shall be considered a programming reject. 4.12 Programming procedures for circuit E. The programming characteristics for this device have been discontinued. 4.13 Programming procedures for circuit F. The programming characteristics on table IVF and the following procedures shall be used for programming the devices: a. Connect the device in the electrical configuration for programming. The waveforms on figure 5F and the programming characteristics of table IVF shall apply to these procedures. b. Raise VCC to 5.5 V. c. Address the PROM with binary address of the selected word to be programmed. Address inputs are TTL compatible. d. Disable the chip by applying VIH to the CE inputs and VIL to the CE inputs. The chip enable inputs are TTL compatible. e. Apply the VPP pulse to the programming pin CE 1. In order to insure that the output transistor is OFF before increasing voltage on the output pin, the program pins voltage pulse shall precede the output pins programming pulse by TD1 and leave after the programming pins programming pulse by TD2 (see figure 5F). f. Apply one VOUT pulse with duration of tP to the output selected for programming. The outputs shall be programmed one output at a time, since internal decoding circuitry is capable of sinking only one unit of programming current at a time. Note: The PROM is supplied with fuses generating a high-level logic output. Programming a fuse will cause the output to go to a low-level logic in the verify mode. g. Other bits in the same word may be programmed sequentially by applying VOUT pulses to each output to be programmed. h. Repeat 4.13b through 4.13g for all other bits to be programmed. i. Enable the chip by applying VIL to the CE inputs and VIH to the CE inputs, and verify the program. Verification may check for a low output by requiring the device to sink 12 mA at VCC = 4.2 V and 0.2 mA at VCC = 6.2 V at TC = 25C. j. If any bit does not verify as programmed, it shall be considered a programming reject. 11 MIL-M-38510/210E 4.14 Programming procedures for circuit G. The programming characteristics on table IVG and the following procedures shall be used for programming the devices: a. Connect the device in the electrical configuration for programming. The waveforms on figure 5G and the programming characteristics of table IVG shall apply to these procedures. b. Select the desired word by applying high or low levels to the appropriate address inputs. Disable the device by applying a high level to one or more `active low' chip Enable inputs. NOTE: Address and Enable inputs must be driven with TTL logic levels during programming and verification. c. Increase VCC from nominal to VCCP (10.5 0.5 V) with a slew rate limit of IRR (1.0 to 10.0 V/s). Since VCC is the source of the current required to program the fuse as well as the ICC for the device at the programming voltage, it must be capable of supplying 750 mA at 11.0 V. d. Select the output where a logical high is desired by raising that output voltage to VOP (10.5 0.5 V). Limit the slew rates to IRR (1.0 to 10.0 V/s). This voltage change may occur simultaneously with the VCC increase to VCCP, but must not precede it. It is critical that only one output at a time be programmed since the internal circuits can only supply programming current to one bit at a time. Outputs not being programmed must be left open or connected to a high impedance source of 20 k minimum (remember that the outputs of the device are disabled at this time). e. Enable the device by taking the chip Enable(s) to a low level. This is done with a pulse PWE for 10 s. The 10 s duration refers to the time that the circuit (device) is enabled. Normal input levels are used and rise and fall times are not critical. f. Verify that the bit has been programmed by first removing the programming voltage from the output and then reducing VCC to 5.0 V (0.25 V). The device must be Enabled to sense the state of the outputs. During verification, the loading of the output must be within specified IOL and IOH limits. g. If the device is not to be tested for VOH over the entire temperature range subsequent to programming, the verification of step 4.14f is to be performed at a VCC level of 4.0 V (0.2 V). VOH, during the 4 V verification, must be at least 2.0 V. The 4 V VCC verification assures minimum VOH levels over the entire temperature range. h. Repeat 4.14b through 4.14f for each bit to be programmed to a high level. If the procedure is performed on an automatic programmer, the duty cycle of VCC at the programming voltage must be limited to a maximum of 25 percent. This is necessary to minimize device junction temperatures. After all selected bits are programmed, the entire contents of the memory should be verified. i. If any bit does not verify as programmed, it shall be considered a programming reject. 12 MIL-M-38510/210E 4.15 Programming procedures for circuit H. The programming characteristics of table IVH and the following procedures shall be used for programming the device. a. Connect the device in the electrical configuration for programming. The waveforms on figure 5H and the programming characteristics of table IVH shall apply to these procedures. b. Address the word to be programmed, apply 5 V to VCC and active levels to all chip Enable inputs. c. Verify the status of a bit location by checking the output level. d. Decrease VCC to 0 V. e. For bit locations that do not require programming, skip steps 4.15f through 4.15l. f. Increase VCC to VCC(pr) with a minimum current capability of 250 mA. g. Apply VS(pr) to all chip Enable inputs. II 25 mA. Active-high enables may be left high. h. Connect all outputs, except the one to be programmed, to VIL. Only one bit is to be programmed at a time. i. Apply the output programming pulse for 20 s. Minimum current capability of the programming supply should be 250 mA. j. After terminating the output pulse, disconnect all outputs from VIL conditions. k. Reduce the voltage at CE input to VIL. l. Decrease VCC to 0 V. m. Return to 4.15e until all outputs in the word have been programmed. n. Repeat 4.15c through 4.15l for each word in memory. o. Verify programming of every word after all words have been programmed using VCC values of 4.5 V and 5.5 V. p. If any bit does not verify as programmed, it shall be considered a programming reject. 4.16 Programming procedures for circuit I. The programming characteristics in table IVI and the following procedures shall be used for programming the device: a. Connect the device in the electrical configuration for programming. The waveforms on figure 5I and the programming characteristics of table IVI shall apply to these procedures. b. Terminate all outputs with a 300 resistor to VONP. Apply VIHP to the CE 2, CE3, and CE4 inputs and VILP to the CE 1 inputs. c. Address the PROM with the binary address of the selected word to be programmed. Raise VCC to VCCP. d. After a delay of t1, apply only one VOP pulse with a duration of tP, t2 and d(VOP)/dt to the output selected for programming. After a delay of t2 and d(VOP)/dt, pulse CE 2 from VIHP to VCEP for the duration of tP, 2d(VCE)/dt, and t3; CE 2 is then to go to VILP level. e. To verify programming after CE 1 has been set to VILP, lower VCC to VCCL after a delay of t4. The programmed output should remain in the logic `1' state. 13 MIL-M-38510/210E f. The outputs should be programmed one output at a time, since the internal decoding circuitry is capable of sinking only one unit of programming current at a time. Note that the PROM is supplied with fuses generating a low-level logic output. Programming a fuse will cause the output to go to a high level logic in the verify mode. g. Repeat 4.16b through 4.16f for all other bits to be programmed. h. If any bit does not verify as programmed, it shall be considered a programming reject. 4.17 Programming procedures for circuit J. The programming characteristics in table IVJ and the following procedures shall be used for programming the device: a. Connect the device in the electrical configuration for programming. The waveforms on figure 5J and the programming characteristics of table IVJ shall apply to these procedures. b. Address the PROM with the binary address of the selected word to be programmed. Address inputs are TTL compatible. An open circuit should not be used to address the PROM. c. Disable the chip by applying input high (VIH) to the CS input. CS input must remain at VIH for programming. The chip select is TTL compatible. An open circuit should not be used to disable the chip. d. Disable the programming circuitry by applying an Output Voltage Disable of less than VOPD to the output of the PROM. The output may be left open to achieve the disable. e. Raise VCC to VPH with rise time equal to tr. f. After a delay equal to or greater than td, apply a pulse with amplitude of VOPE and duration of tP to the output selected for programming. Note that the PROM is supplied with fuses intact generating an output high. Programming a fuse will cause the output to go low in the verify mode. g. Other bits in the same word may be programmed while the VCC input is raised to VPH by applying output enable pulses to each output which is to be programmed. The output enable pulses must be separated by a minimum interval of td. h. Lower VCC to 4.5 V following a delay of td from the last programming enable pulse applied to an output. i. Enable the PROM for verification by applying a logic "0" (VIL) to the CS input. j. Repeat 4.17a through 4.17i for all other bit to be programmed in the PROM. k. If any bit does not verify as programmed, it shall be considered a programming reject. 14 MIL-M-38510/210E Device type Case outline Terminal number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 01, 02, 03, 04 J, K, and L 16 O7 17 18 19 20 O8 CE3 CE2 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 GND O4 O5 O6 21 22 23 24 CE 1 A10 A9 A8 VCC 25 26 27 28 ------------- 05 R Terminal symbol A8 A7 A6 A5 A4 A3 A2 A1 A0 GND O4 O3 O2 O1 CE 2 NC A7 A6 A5 A4 A3 A2 A1 A0 NC O1 O2 O3 GND NC CE 1 A11 A10 A9 VCC O4 ------------- NC CE3 CE2 ------------- FIGURE 1. Terminal connections. 15 02 and 04 3 O5 O6 O7 O8 CE 1 A10 A9 A8 VCC MIL-M-38510/210E Device types 01, 02, 03, and 04 WORD NO. NA NA 6/ CE 1 L H 6/ CE2 6/ ADDRESS DATA CE3 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O8 O7 O6 O5 O4 O3 O2 O1 H X H X X X X X X X X X X X X X X X X X X X X X 5/ 5/ 5/ 5/ 5/ 5/ 5/ 5/ X X OC OC OC OC OC OC OC OC Device type 05 WORD NO. NA NA 6/ CE 1 L H 6/ CE 2 L X ADDRESS DATA A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O4 O3 O2 X X X X X X X X X X X X X X X X X X X X X X X X 5/ 5/ 5/ 5/ OC OC OC OC NOTES: 1. NA = Not applicable. 2. X = Input may be high level, low level, or open circuit. 3. OC = Open circuit (high resistance output). 4. Program readout can only be accomplished with enable input at low level. 5. The outputs for an unprogrammed device shall be high for circuits A, C, (device type 05), E, F, and J and low for circuits B, C (device types 02, 04), D, G, and I. 6. Enable inputs are ANDED. FIGURE 2. Truth table (unprogrammed). 16 O1 MIL-M-38510/210E Device types 01 and 02 Circuit A FIGURE 3. Functional block diagrams. 17 MIL-M-38510/210E Device type 05 Circuit A FIGURE 3. Functional block diagrams - Continued. 18 MIL-M-38510/210E Device types 01 and 02 Circuit B FIGURE 3. Functional block diagram - Continued. 19 MIL-M-38510/210E Device types 01, 02, and 04 Circuit C FIGURE 3. Functional block diagrams - Continued. 20 MIL-M-38510/210E Device type 05 Circuit C FIGURE 3. Functional block diagrams - Continued 21 MIL-M-38510/210E Device types 02, 03, and 04 Circuit D FIGURE 3. Functional block diagrams - Continued. 22 MIL-M-38510/210E Device type 02 Circuits F and I FIGURE 3. Functional block diagrams - Continued. 23 MIL-M-38510/210E Device type 01 Circuit G FIGURE 3. Functional block diagrams - Continued. 24 MIL-M-38510/210E Device type 02 Circuit G FIGURE 3. Functional block diagrams - Continued. 25 MIL-M-38510/210E Device types 02 and 04 Circuit H FIGURE 3. Functional block diagram - Continued. 26 MIL-M-38510/210E Device type 02 Circuit J FIGURE 3. Functional block diagrams - Continued. 27 MIL-M-38510/210E Device types 01, 02, 03, and 04 NOTES: 1. Test table for devices programmed in accordance with an altered item drawing may be replaced by the equivalent tests which apply to the specific program configuration for the resulting read-only memory 2. CL = 30 pF minimum, including jig and probe capacitance, R1 =330 25%, and R2 = 680 20%. 3. Outputs may be under load simultaneously. FIGURE 4. Switching time test circuit. 28 MIL-M-38510/210E Device type 05 NOTES: 1. Test table for devices programmed in accordance with an altered item drawing may be replaced by the equivalent tests which apply to the specific program configuration for the resulting read-only memory 2. CL = 30 pF minimum, including jig and probe capacitance, R1 =330 25%, and R2 = 680 20%. 3. Outputs may be under load simultaneously. FIGURE 4. Switching time test circuit - Continued. 29 MIL-M-38510/210E NOTE: 1. All other waveform characteristics shall be as specified in table IVA. FIGURE 5A. Programming voltage waveforms during programming for circuit A. 30 MIL-M-38510/210E FIGURE 5B. Programming voltage waveforms during programming for circuit B. NOTE: All other waveforms characteristics shall be as specified in table IVC. FIGURE 5C. Programming voltage waveforms during programming for circuit C, device types 02 and 04. 31 MIL-M-38510/210E *Current clamp or voltage clamp will be needed. FIGURE 5C. Programming voltage waveforms during programming for circuit C, device type 05 - Continued. 32 MIL-M-38510/210E FIGURE 5D. Programming voltage waveforms during programming for circuit D. 33 MIL-M-38510/210E FIGURE 5E. Programming waveforms for circuit E have been discontinued. NOTES: 1. Output load is 0.2 mA and 12 mA during 7.0 V and 4.0 V check, respectively. 2. All other waveform characteristics shall be as specified in table IVF. FIGURE 5F Programming voltage waveforms during programming for circuit F. 34 MIL-M-38510/210E FIGURE 5G. Programming voltage waveforms during programming for circuit G. 35 MIL-M-38510/210E FIGURE 5H. Programming voltage waveforms during programming for circuit H. 36 MIL-M-38510/210E NOTES: 1. All delays between edges are specified from completion of the first edge, not midpoints. 2. Delays t1, t2, t3, and t4 must be greater than 100 ns; maximum delays of 1 s are recommended to minimize heating during programming. 3. During tV the output being programmed is switched to the load R and verified. 4. Outputs not being programmed are connected to VONP through resistor which provides output current limiting. FIGURE 5I. Programming voltage waveforms during programming for circuit I. 37 MIL-M-38510/210E FIGURE 5J. Programming voltage waveforms during programming for circuit J. 38 TABLE III. Group A inspection for device types 01 and 03. Terminal conditions: (Outputs not designated are open or resistive coupled to GND or voltage. Inputs not designated are high 2.0 V or 0.8 V. Subgroup Symbol 1 TC=+25C VIC VOL 39 IIH ICEX ICC See footnotes at end of table. 9 10 11 01 02 03 3/ 3/ 3/ 5.2V 5.2V 5.2V 12 13 14 15 16 17 18 19 GND 04 05 06 07 08 CE3 CE2 GND " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " 20 CE 21 22 23 A10 A9 A8 -10mA -10mA -10mA -10mA 3/ 3/ 3/ 3/ 3/ 2.0V " " " " " " " 0.8V " " " " " " " 2/ " " " " " " " 2/ " " " " " " " -10mA 2/ " " " " " " " 0.5V 0.5V 0.5V 0.5V 0.5V 0.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 0.5V 0.5V Measured terminal VCC Test limits Min Unit Max 1 -10mA 2.0V " " " " " " " 24 4.5V 5.2V 5.2V 5.2V 5.2V 5.2V GND GND GND GND 4.5V " " " " " " " " " " " " " " " " " " " " " 5.5V " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " A7 A6 A5 A4 A3 A2 A1 A0 CE3 CE2 CE1 A10 A9 A8 01 02 03 04 05 06 07 08 A7 A6 A5 A4 A3 A2 A1 A0 CE3 CE2 CE1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CE3 CE2 CE1 A10 A9 A8 01 02 03 04 05 06 07 08 VCC -1.0 " " " " " " " " " " " " " -1.5 " " " " " " " " " " " " " 0.5 " " " " " " " -250 " " " " " " " " " " " " " 50 " " " " " " " " " " " " " 100 " " " " " " " 185 V " " " " " " " " " " " " " " " " " " " " " A " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " mA MIL-M-38510/210E IIL MIL- Cases 1 2 3 4 5 6 7 8 STDJ,K 883 Test A7 A6 A5 A4 A3 A2 A1 A0 method no. 1 -10mA 2 -10mA 3 -10mA 4 -10mA 5 -10mA 6 -10mA 7 -10mA 8 -10mA 9 10 11 12 13 14 3007 15 1/ 2/ 2/ 2/ 2/ 2/ 2/ 2/ 1/ 2/ " " " " " " " " " 16 " 17 " " " " " " " " " " " " " " " " " 18 " 19 " " " " " " " " " 20 " " " " " " " " " 21 " " " " " " " " " 22 " " " " " " " " 3009 23 0.5V " 24 0.5V " 25 0.5V " 26 0.5V " 27 0.5V " 28 0.5V " 29 0.5V " 30 0.5V " 31 " 32 " 33 " 34 " 35 " 36 3010 37 5.5V " 38 5.5V " 39 5.5V " 40 5.5V " 41 5.5V " 42 5.5V " 43 5.5V " 44 5.5V " 45 " 46 " 47 " 48 " 49 " 50 51 52 53 54 55 56 57 58 3005 59 GND GND GND GND GND GND GND GND TABLE III. Group A inspection for device types 01 and 03 - Continued. Terminal conditions: (Outputs not designated are open or resistive coupled to GND or voltage. Inputs not designated are high 2.0 V or 0.8 V. Subgroup Symbol MILCases 1 2 3 4 5 6 7 8 9 STDJ,K 883 Test A7 A6 A5 A4 A3 A2 A1 A0 01 method no. 2 Same tests, terminal conditions, and limits as for subgroup 1, except TC = +125C. 3 Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55C. Funct4/ 7 60 4/ 4/ 4/ 4/ 4/ 4/ 4/ 4/ 4/ TC=+25C ional tests 8 Same tests, terminal conditions, and limits as for subgroup 7, except TC = +125C and -55C. 61 5/ 5/ 5/ 5/ 5/ 5/ 5/ 5/ 6/ tPHL1 GALPAT 9 Fig. 4 62 5/ 5/ 5/ 5/ 5/ 5/ 5/ 5/ " TC=+25C tPLH1 63 tPHL2 Sequen8/ 8/ 8/ 8/ 8/ 8/ 8/ 8/ " tial 64 tPLH2 8/ 8/ 8/ 8/ 8/ 8/ 8/ 8/ " Fig. 4 10 Same tests, terminal conditions, and limits as for subgroup 9, except TC = +125C 11 Same tests, terminal conditions, and limits as for subgroup 10, except TC = -55C 10 11 12 13 14 15 16 17 18 19 02 03 GND 04 05 06 07 08 CE3 CE2 20 CE 21 22 23 24 A10 A9 A8 VCC Measured terminal Test limits Min Unit Max 1 4/ 4/ GND 4/ 4/ 4/ 4/ 4/ 4/ 4/ 4/ 4/ 4/ 4/ 4/ Outputs 4/ 6/ " " " 6/ " " " GND " " " 6/ " " " 6/ " " " 6/ " " " 6/ " " " 6/ " " " 5.5V 5.5V 8/ 8/ 5.5V 5.5V 8/ 8/ GND GND 8/ 8/ 5/ 5/ 8/ 8/ 5/ 5/ 8/ 8/ 5/ 5/ 8/ 8/ 5/ 5/ 8/ 8/ Outputs " " " 7/ 7/ 9/ 9/ ns " " " See footnotes at end of table. MIL-M-38510/210E 40 TABLE III. Group A inspection for device types 02 and 04. Outputs not designated are open or resistive coupled to GND or voltage. Terminal conditions: Inputs not designated are high 2.0 V or 0.8 V. Subgroup Symbol 1 TC=+25C VIC VOL 41 IIL IIH 3 4 5 6 7 8 9 11 12 13 16 17 18 19 20 22 23 24 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 GND O4 O5 O6 O7 O8 CE3 CE2 -10mA -10mA -10mA -10mA -10mA -10mA -10mA 1/ 2/ " " " " " " " 2/ 12/ 15/ 16/ 17/ " " " " " 2/ " " " " " " " 2/ 15/ 16/ 17/ " " " " " " 2/ 13/ " " " " " " " 2/ 15/ 16/ 17/ " " " " " " 2/ " " " " " " " 2/ 15/ 16/ 17/ " " " " " " 2/ " " " " " " " 2/ 15/ 16/ 17/ " " " " " " 2/ " " " " " " " 2/ 15/ 16/ 17/ " " " " " " 2/ " " " " " " " 2/ 15/ 16/ 17/ 18/ " " " " " 0.5V 0.5V 0.5V 0.5V 0.5V 0.5V 0.5V 5.5V See footnotes at end of table. 14 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 3/ 3/ 3/ -2mA -2mA -2mA GND " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " CE 25 26 27 21 22 23 24 A10 A9 A8 VCC -10mA -10mA -10mA -10mA 3/ 3/ 3/ 3/ 3/ -2mA -2mA -2mA -2mA -2mA 2.0V " " " " " " " " " " " " " " " Measured terminal Test limits Min Unit Max 1 -10mA 2.0V " " " " " " " " " " " " " " " 28 0.8V " " " " " " " " " " " " " " " -10mA 2/ 2/ 13/ 2/ 13/ " " " " " " " " " " " " " " " " " " " " " 2/ 15/ 2/ 15/ 2/ 15/ 16/ 17/ 16/ 17/ 16/ 17/ " " " " " " " " " " " " " " " " " " 0.5V 0.5V 0.5V 0.5V 0.5V 0.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 4.5V " " " " " " " " " " " " " " " " " " " " " " " " " " " " " 5.5V " " " " " " " " " " " " " " " " " " " " " " " " " " " A7 A6 A5 A4 A3 A2 A1 A0 CE3 CE2 CE1 A10 A9 A8 O1 O2 O3 O4 O5 O6 O7 O8 O1 O2 O3 O4 O5 O6 O7 O8 A7 A6 A5 A4 A3 A2 A1 A0 CE3 CE2 CE1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CE3 CE2 CE1 A10 A9 A8 -1.5 " " " " " " " " " " " " " 0.5 " " " " " " " 2.4 " " " " " " " -1.0 " " " " " " " " " " " " " -250 " " " " " " " " " " " " " 50 " " " " " " " " " " " " " V " " " " " " " " " " " " " " " " " " " " " " " " " " " " " A " " " " " " " " " " " " " " " " " " " " " " " " " " " MIL-M-38510/210E VOH MILCase 2 STD3 883 Cases 1 method J,K,L Test A7 no. 1 -10mA 2 3 4 5 6 7 8 9 10 11 12 13 14 3007 15 1/ 2/ " " 16 " " 17 " " 18 " " 19 " " 20 " " 21 " " 22 3006 23 2/ 14/ " 15/ 16/ 24 17/ " 25 " " 26 " " 27 " " 28 " " 29 " " 30 3009 31 0.5V " 32 " 33 " 34 " 35 " 36 " 37 " 38 " 39 " 40 " 41 " 42 " 43 " 44 3010 45 5.5V " 46 " 47 " 48 " 49 " 50 " 51 " 52 " 53 " 54 " 55 " 56 " 57 " 58 TABLE III. Group A inspection for device types 02 and 04 - Continued. Outputs not designated are open or resistive coupled to GND or voltage. Terminal conditions: Inputs not designated are high 2.0 V or 0.8 V. Subgroup Symbol See footnotes at end of table. 11 12 13 14 16 17 18 19 20 22 23 24 25 26 27 28 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 O1 O2 O3 GND O4 O5 O6 O7 O8 CE3 CE2 A10 A9 A8 VCC 5.2V 5.2V 5.2V 0.5V 0.5V 0.5V GND GND GND GND " " " " " " " " " " " " " " " " " " " " " " " " GND 0.5V " " " " " " " " " " " " " " " 4.5V " " " " " " " 0.5V " " " " " " " " " " " " " " " 4.5V " " " " " " " 5.2V 5.2V 5.2V 5.2V 5.2V 0.5V 0.5V 0.5V 0.5V 0.5V GND GND GND GND CE Measured terminal Test limits Min Unit Max 1 4.5V 5.5V " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " 0.5V 2/ 15/ 2/ 15/ 2/ 15/ 16/ 17/ 16/ 17/ 16/ 17/ " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " GND GND GND GND " O1 O2 O3 O4 O5 O6 O7 O8 O1 O2 O3 O4 O5 O6 O7 O8 O1 O2 O3 O4 O5 O6 O7 O8 VCC -10 " " " " " " " 100 " " " " " " " -100 " " " " " " " -100 " " " " " " " 185 4/ 4/ 4/ GND 4/ 4/ 4/ 4/ 4/ 4/ 4/ 4/ 4/ 4/ 4/ 4/ Outputs 4/ 6/ " " " 6/ " " " 6/ " " " GND " " " 6/ " " " 6/ " " " 6/ " " " 6/ " " " 6/ " " " 5.5V 5.5V 8/ 8/ 5.5V 5.5V 8/ 8/ GND GND 8/ 8/ 5/ 5/ 8/ 8/ 5/ 5/ 8/ 8/ 5/ 5/ 8/ 8/ 5/ 5/ 8/ 8/ Outputs " " " 7/ 7/ 9/ 9/ A " " " " " " " " " " " " " " " mA " " " " " " " " ns " " " MIL-M-38510/210E 42 MILCase 2 3 4 5 6 7 8 9 STD3 883 Cases 1 2 3 4 5 6 7 8 method J,K,L Test A7 A6 A5 A4 A3 A2 A1 A0 no. 1 IOHZ 59 60 TC=+25C 61 62 63 64 65 66 IOLZ 67 68 69 70 71 72 73 74 IOS 3011 2/ 15/ 2/ 15/ 17/ 2/ 2/ 15/ 18/ 2/ 75 14/ 2/ 2/ 15/ 2/ 15/ " 15/ 16/ 12/ 16/ 16/ 17/ 16/ 17/ 16/ 17/ 15/ 16/ 16/ 17/ 15/ 16/ 76 17/ 17/ " " " " " 17/ " 77 " " " " " " " " " 78 " " " " " " " " " 79 " " " " " " " " " 80 " " " " " " " " " 81 " " " " " " " " " 82 3005 83 GND GND GND GND GND GND GND GND ICC 2 Same tests, terminal conditions, and limits as for subgroup 1, except TC = +125C. 3 Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55C. Funct4/ 7 84 4/ 4/ 4/ 4/ 4/ 4/ 4/ 4/ ional TC=+25C tests 8 Same tests, terminal conditions, and limits as for subgroup 7, except TC = +125C and -55C. GALPAT 5/ 5/ 5/ 5/ 5/ 5/ 5/ 85 5/ tPHL1 9 Fig. 4 86 tPLH1 5/ 5/ 5/ 5/ 5/ 5/ 5/ 5/ TC=+25C Sequen87 tPHL2 8/ 8/ 8/ 8/ 8/ 8/ 8/ 8/ tPLH2 8/ 8/ 8/ 8/ 8/ 8/ 8/ 8/ tial 88 Fig. 4 10 Same tests, terminal conditions, and limits as for subgroup 9, except TC = +125C. 11 Same tests, terminal conditions, and limits as for subgroup 10, except TC = -55C. TABLE III. Group A inspection for device type 05. Outputs not designated are open or resistive coupled to GND or voltage. Terminal conditions: Inputs not designated are high 2.0 V or 0.8 V. Subgroup 1 TC=+25C Symbol VIC VOL VOH 43 IIH See footnotes at end of table. 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 -10mA -10mA -10mA -10mA -10mA -10mA -10mA -10mA 2/ " " " " " " " 2/ 19/ " " " 2/ " " " 2/ 19/ " " " 2/ " " " 2/ 19/ " " " 2/ " " " 2/ 19/ " " " 2/ " " " 2/ 19/ " " " 2/ " " " 2/ 19/ " " " 2/ " " " 2/ 19/ " " " 2/ " " " 0.5V 0.5V 0.5V 0.5V 0.5V 0.5V 0.5V 0.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 10 GND GND " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " 11 O4 12 O3 13 O2 14 O1 15 CE 16 2 CE 17 A11 18 A10 19 A9 -10mA -10mA -10mA -10mA 3/ 3/ 3/ 3/ -2mA -2mA -2mA -2mA 0.8V " " " " " " " 20 VCC Measured terminal 4.5V " " " " " " " " " " " " " " " " " " " " " 5.5V " " " " " " " " " " " " " " " " " " " " " " " " " " " A8 A7 A6 A5 A4 A3 A2 A1 A0 CE2 CE1 A11 A10 A9 O4 O3 O2 O1 O4 O3 O2 O1 A8 A7 A6 A5 A4 A3 A2 A1 A0 CE2 CE1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CE2 CE1 A11 A10 A9 Test limits Min Max Unit -1.5 " " " " " " " " " " " " " 0.5 " " " V " " " " " " " " " " " " " " " " " " " " " A " " " " " " " " " " " " " " " " " " " " " " " " " " " 1 0.8V " " " " " " " 2/ " " " " " " " 2/ " " " " " " " -10mA 2/ " " " " " " " 0.5V 0.5V 0.5V 0.5V 0.5V 5.5V 5.5V 5.5V 5.5V 5.5V 2.4 " " " -1.0 " " " " " " " " " " " " " -250 " " " " " " " " " " " " " 50 " " " " " " " " " " " " " MIL-M-38510/210E IIL MILCase R 1 STD- Test no. A8 883 method 1 -10mA 2 3 4 5 6 7 8 9 10 11 12 13 14 3007 15 1/ 2/ " " 16 " 17 " " 18 " 3006 19 2/ " " 20 " " 21 " 22 " 3009 23 0.5V " 24 " 25 " 26 " 27 " 28 " 29 " 30 " 31 " 32 " 33 " 34 " 35 " 36 3010 37 5.5V " 38 " 39 " 40 " 41 " 42 " 43 " 44 " 45 " 46 " 47 " 48 " 49 " 50 TABLE III. Group A inspection for device type 05 - Continued. Outputs not designated are open or resistive coupled to GND or voltage. Terminal conditions: Inputs not designated are high 2.0 V or 0.8 V. Subgroup Symbol 9 A0 10 GND 11 O4 12 O3 13 O2 14 O1 5.2V 15 CE 16 2 CE 17 A11 18 A10 19 A9 20 VCC Measured terminal O4 O3 O2 O1 O4 O3 O2 O1 O4 O3 O2 O1 VCC Test limits Min Max Unit 100 " " " -100 " " " -100 " " " 185 A " " " " " " " mA " " " " 1 2/ " " " GND GND " " " " " " " " " " " " 4/ GND 4/ 4/ 4/ 4/ 4/ 4/ 4/ 4/ 4/ 4/ Outputs 4/ 5/ 5/ 8/ 8/ GND " " " 6/ " " " 6/ " " " 6/ " " " 6/ " " " GND GND 8/ 8/ GND GND 8/ 8/ 5/ 5/ 8/ 8/ 5/ 5/ 8/ 8/ 5/ 5/ 8/ 8/ 5/ 5/ 8/ 8/ Outputs " " " 80 80 40 40 5.2V 5.2V 5.2V 0.5V 0.5V 0.5V 0.5V GND GND GND GND 4.5V " " " " " " " 0.5V " " " GND 0.5V " " " GND 2/ " " " GND 2/ " " " GND 2/ " " " GND 5.5V " " " " " " " " " " " " 4.5V " " " " " -10 " " " ns " " " MIL-M-38510/210E 44 MILCase R 1 2 3 4 5 6 7 8 STD-883 Test A8 A7 A6 A5 A4 A3 A2 A1 method no. 1 IOHZ 51 52 TC=+25C 53 54 IOLZ 55 56 57 58 IOS 3011 59 2/ 2/ 2/ 2/ 2/ 2/ 2/ 2/ " " " " " " " " " 60 " 61 " " " " " " " " " 62 " " " " " " " " ICC 3005 63 GND GND GND GND GND GND GND GND 2 Same tests, terminal conditions, and limits as for subgroup 1, except TC = +125C. 3 Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55C. Funct4/ 7 64 4/ 4/ 4/ 4/ 4/ 4/ 4/ 4/ ional TC=+25C tests 8 Same tests, terminal conditions, and limits as for subgroup 7, except TC = +125C and TC = -55C. GALPAT 5/ 5/ 5/ 5/ 5/ 5/ 5/ 65 5/ tPHL1 9 Fig. 4 66 tPLH1 5/ 5/ 5/ 5/ 5/ 5/ 5/ 5/ TC=+25C Sequen67 tPHL2 8/ 8/ 8/ 8/ 8/ 8/ 8/ 8/ tPLH2 8/ 8/ 8/ 8/ 8/ 8/ 8/ 8/ tial 68 Fig. 4 10 Same tests, terminal conditions, and limits as for subgroup 9, except TC = +125C. 11 Same tests, terminal conditions, and limits as for subgroup 9, except TC = -55C. MIL-M-38510/210E 1/ For unprogrammed devices, apply 13.0 V on pin 1(A7) and pin 2 (A6), for device types 01 and 02, and on pin 1 (A8) for device type 05 for circuit A devices. 2/ For programmed devices, select an appropriate address to acquire the desired output state. VIH = 2.0 V, VIL = 0.8 V. 3/ IOL = 8 mA for circuits C and G. IOL = 16 mA for circuits A, B, D, F, H, I, and J. 4/ The functional tests shall verify that no fuses are blown for unprogrammed devices or that the altered item drawing pattern exists for programmed devices (see table II and 3.3.2.1). All bits shall be tested. Terminal conditions shall be as follows: a. Inputs: H = 2.4 V, L = 0.4 V b. Outputs: Output voltage shall be: H 1.5 V and L 1.5 V. c. The functional tests shall be performed with VCC = 4.5 V and VCC = 5.5 V. 5/ GALPAT (programmed PROM). This program will test all bits in the array, the addressing and interaction between bits for ac performance, tPHL1 and tPLH1. Each bit in the pattern is fixed by being programmed with an "H" or "L". Description: 1. Word 0 is read. 2. Word 1 is read. 3. Word 0 is read. 4. Word 2 is read. 5. Word 0 is read. 6. The reading procedure continues back and forth between word 0 and the next higher numbered word until word 2047 or 4095 is reached, then increments to the next word and reads back and forth as in step 1 through 7 and shall include all words. 2 7. Pass execution time = (n + n) x cycle time. n = 2048 or 4096. 8. The GALPAT tests shall be performed with VCC = 4.5 V and 5.5 V. 6/ The outputs are loaded per figure 4. 7/ tPHL1, tPLH1 = 100 ns for device types 01 and 02 and 55 ns for device types 03 and 04. 8/ Sequential test (programmed PROM). This program will test all bits in the array for tPHL2 and tPLH2. Description: 1. Each word in the pattern is tested from the enable lines to the output lines for recovery. 2. Word 0 is addressed. Enable line is pulled HI to LO and LO to HI. tPHL2 and tPLH2 are read. 3. Word 1 is addressed. Same enable sequence as above. 4. The reading procedure continues until word 2047 or 4095 is reached. 5. Pass execution time = 2048 x cycle time (or 4096 x cycle time). 6. The sequential tests shall be performed with VCC = 4.5 V and 5.5 V. 9/ tPHL2, tPLH2 = 50 ns for device types 01 and 02 and 30 ns for device types 03 and 04. 10/ For uprogrammed devices, apply 13 V on pin 8 (A0) for circuit I devices. 11/ For unprogrammed devices, 12.0 V on pin 6 (A2) and 0.0 V on pin 5 (A3) for circuit F devices. 12/ For unprogrammed devices, apply 13 V on pin 2 (A6) for circuit I devices. 45 MIL-M-38510/210E 13/ For unprogrammed devices, apply 10 V to pin 4 (A4), apply VOH to pin 21 (A10), and apply VOL to pin 23 (A8) for circuit H. 14/ For unprogrammed devices, apply 10.5 V on pin 1 (A7) for circuit B devices.. 15/ For unprogrammed devices, apply 10.5 V to pin 3 (A5), apply 0 V to pins 4, 5, 6, 7, 8 (A4, A3, A2, A1, A0), and apply 3 V to pins 1, 2, 21, 22, 23, (A7, A6, A10, A9, A8) for circuit G devices. 16/ For unprogrammed devices type 02 (82S191), with date codes before 8626. apply 10.0 V on pin 6 (A2); apply 5.0 V to all other addresses for circuit C devices. 17/ For unprogrammed device types 02 (with date codes 8626 or later) and 04 (82S191A), apply 10.0 V on A4; apply 5.0 V on A0, A1, A2, A3 and A6; and apply 0.5 V on A5, A7, A8, A9 and A10 for circuit C devices. 18/ For unprogrammed devices, apply 12.0 V on pin 8 (A0) for circuit D devices. 19/ For unprogrammed device type 05, apply 15.0 V to pin 4 (A5); apply 0.0 V to pins 5, 9 (A4, A0); apply 4.5 V to pins 3, 6, 7, 8 (A6, A3, A2, A1) for circuit C devices. 46 MIL-M-38510/210E TABLE IVA. Programming characteristics for circuit A. Parameter Address input voltage 2/ Programming Voltage to VCC low Program verify Verify voltage Programming input low current at VPH Programming voltage (VCC) transition time Programming delay Programming pulse width Programming duty cycle Output voltage Enable Disable Symbol Unit Limits 1/ Min Recommended Max VIH VIL VPH 3/ VPL VPHV VR 4/ 2.4 0.0 10.75 0.0 ---4.5 5.0 0.4 11.0 0.0 5.5 ---- 5.0 0.5 11.25 1.5 ---5.5 V V V " " " IILP ---- -300 -600 A tTLH tTHL tD1 tD2 tP 5/ PDC 1 1 10 1 90 ---- 5 5 10 5 100 30 10 10 20 5 110 60 s s s s s % VOPE 6/ VOPD 10.5 0.0 10.5 5.0 11.0 5.5 V V During the programming the chip must be disabled for proper operation. 1/ TA = +25C. 2/ No inputs should be left open for VIH. 3/ VPH source must be capable of supplying one ampere. 4/ It is recommended that post programming dual verification be made at V minR and V max R. 5/ Note step j in programming procedure. 6/ VOPE source must be capable of supplying 10 mA minimum. 47 MIL-M-38510/210E TABLE IVB. Programming characteristics for circuit B. Parameter Symbol Limits Conditions 1/ Unit Min Recommended Max VCCP 10.5 11.0 11.5 V IOP 20 25 30 mA VOUT 10.5 11.0 11.5 V tP 9 10 11 s 0 1 1 5 10 10 s V/s ICCP 800 900 1,000 mA Low VCC for verification VCCL 3.9 4.0 4.1 V High VCC for verification VCCH 5.8 6.0 6.2 V VIH 2.4 5.0 5.5 V VIL 0.0 0.4 0.8 V ---- 25 50 % VCC required during programming VOUT current limit during programming Output programming voltage Pulse width of programming voltage Programming delay VCCP or VOUT transition time VCCP current Address input voltage Maximum duty cycle during automatic programming of program pin and output pin tD tTLH D.C. Rise time of VCC or VOUT tP/ tC 1/ TC = +25C. 48 MIL-M-38510/210E TABLE IVC. Programming characteristics for circuit C, device types 02 and 04. Parameter Programming voltage to VCC Verificaiton upper limit Verificaiton lower limit Verify threshold Programming supply current Input voltage, high level "1" Input voltage, low level "0" Input current Input current Output programming voltage Output programming current Programming voltage transition time Symbol Limits Conditions 1/ Unit Min Recommended Max 8.5 8.75 9.0 V VCCH 5.3 5.5 5.7 V VCCL VS 3/ 4.3 1.4 4.5 1.5 4.7 1.6 V V 300 450 mA VIH 2.4 5.5 V VIL 0 0.4 0.8 V 16 17 50 -500 18 A A V 180 200 220 mA 50 s 500 s VCCP 2/ ICCP IIH IIL VOUT 4/ IOUT ICCP = 375 75 mA Transient or steady-state VCCP = +8.75 0.25 V VIH = +5.5 V VIL = +0.4 V IOUT = 200 20 mA; Transient or steady-state VOUT = 17 V 1 V tTLH 10 CE programming pulse width tP 300 Pulse sequence delay tD 10 400 1/ TC = +25C. 2/ Bypass VCC to GND with a 0.01 F capacitor to reduce voltage spikes. 3/ VS is the sensing threshold of the PROM output voltage for a programmed bit. It normally constitutes the reference voltage applied to a comparator circuit to verify a successful fusing attempt. 4/ Care should be taken to insure the 17 V 1 V output voltage is maintained during the entire fusing cycle. The recommended supply is a constant current source clamped at the specified voltage limit. 49 s MIL-M-38510/210E TABLE IVC. Programming characteristics for circuit C, device type 05 - Continued. Parameter Symbol Limits Conditions 1/ Unit Min Recommended Max 8.5 8.75 9.0 V 4.75 5.0 5.25 V IIH = 50 A 2.4 3.0 5.5 V IIL = 500 A 0.0 0.0 0.5 V IOPF VOPF1 VOPF = 17.5 0.5 V IOPF = 300 25 mA 150 17.0 185 17.5 220 18.0 mA V VOPF2 IOPF = 300 25 mA 20.0 22.0 V VOH 2.4 5.25 V Output voltage low VOL 0.0 0.45 V VCC delay time TD1 50% to 10% VCCP 10 10 25 s VOUT delay time TD2 90% VCCP to 10% VOFF 1.0 1.0 5.0 s TD3 - TD8 See figure 5C 1.0 1.0 10 s VCC rise time TR1 0 % to 100% 4.0 7.0 8.0 s VOUT rise time TR2 10% to 90% 3.0 10 17 s VCC fall time TF1 100% to 0% 2.0 4.0 10 s VOUT fall time TF2 100% to 0% 4.0 7.0 20 s CE 2 programming pulse width 4/ TP 10% to 10% 5.0 10 30 s CE 2 verify pulse width 4/ TV 10% to 10% 5.0 5.0 10 s Clock pulse width (CK) TWC 50% to 50% 0.5 0.75 1.0 s Programming voltage to VCC 2/ Verify voltage VCCP Input voltage, high level "1" Input voltage, low level "0" Forced output current Forced output voltage (program) 3/ Forced output voltage (program) 3/ Output voltage high VIH VIL Pulse sequence delays ICCP = 425 75 mA Transient or steady-state VCCV 1/ TC = +25C. 2/ If the overall program/verify cycle exceeds the recommended value, a 25% duty cycle must be used for VCCP. 3/ VOPF supply should regulate to 0.25 V at IOPF. Maximum slew rate for VOPF should be 1.0 V/s. 4/ CE 2 rise time slew rate should be 1.0 V/ns maximum. CE 2 fall time slew rate should be 10.0 V/ns maximum. 50 MIL-M-38510/210E TABLE IVD. Programming characteristics for circuit D. Parameter Symbol Limits Conditions 1/ Unit Min Recommended Max Power supply voltage VCC 6.4 6.5 6.6 Power supply rise time 2/ tr(VCC) 0.2 2.0 s Power supply fall time 2/ tf(VCC) 0.2 2.0 s VCC on time 3/ VCC off time tON tOFF 4/ Duty cycle for VCC tdRBP Fuse read time tW Delay to VCC off Delay to read after programming Chip select programming voltage Chip select program current limit Input voltage low See programming Time diagram 50 tON/(tOFF + tON) Read delay before programming Initial check 5/ td(VCC) 5/ tdRAP 5/ V Programming verification % 3.0 s 1.0 s 1.0 s 3.0 s VCSP 20.0 20.0 22.0 V ICSP 175 180 185 mA VIL 0.0 0.0 0.4 V Input voltage high VIH 2.4 5.0 5.0 V Delay to chip deselect tdCS Chip select pulse rise time Delay to chip select time trCS Chip select pulse fall time 1.0 s 3.0 4.0 s tdAP 0.2 1.0 s tfCS 0.1 0.1 See footnotes at end of table. 51 1.0 s MIL-M-38510/210E TABLE IVD. Programming characteristics for circuit D - Continued. Ramp characteristics Parameter Symbol Limits Conditions 1/ Min Programming current linear point Output programming current limits Output programming voltage limit Current slew rate Recommended Max 10 20 mA 155 160 165 mA 24 25 26 V 0.9 1.0 1.1 mA/s IOPLP IOP(MAX) Apply current ramp to selected output VOP(MAX) SRIOP Constant after linear point Unit Blow sense voltage VPS 0.7 Delay to programming ramp Time to reach linear point Program sense inhibit tdBP 2.0 3.0 tLP 0.2 1.0 10 s tss 2.0 3.0 10 s Time to program fuse ttp 3.0 150 s 1.5 1.6 s 0.1 0.2 s Programming ramp hold time Programming ramp fall time 2/ thAP After fuse programs tfIOP 1.4 V s 1/ TC = +25C 2/ Rise and fall times are from 10% to 90%. 3/ Total time VCC is on to program fuse is equal to or greater than the sum of all the specified delays, pulse widths and rise/fall times. 4/ tOFF is equal to or greater than tON. 5/ Proceed to next address after read strobe indicates programmed cell. TABLE IVE. Programming characteristics for circuit E - Discontinued. 52 MIL-M-38510/210E TABLE IVF. Programming characteristics for circuit F . Parameter VCC required during programming Rise time of program pulse to data out or program pin Programming voltage on program pin Output programming voltage Programming pin pulse width ( CE ) Pulse width of programming voltage Required current limit of power supply feeding program pin and output during program Required time delay between disabling memory output and application of output programming pulse Required time delay between removal of programming pulse and enabling memory output Output current during verification Symbol Maximum duty cycle during automatic programming of program pin and output pin Unit Min Recommended Max VCCP 5.4 5.5 5.6 V tTLH 0.34 0.40 0.46 V/s VPP 32.5 33 33.5 V VOUT 25.5 26 26.5 V ---- 100 180 s 1 40 s VPP = 33 V, VOUT = 26 V, VCC = 5.5 V 240 ---- mA Measured at 10% levels 70 90 s tPP Chip disabled, VCC = 5.5 V tp IL TD1 TD2 IOLV1 80 100 Chip enabled, VCC = 4.0 V Chip enabled, VCC = 7.0 V ns 11 12 13 mA 0.19 0.2 0.21 mA VIH 2.4 5.0 5.5 V VIL 0.0 0.4 0.8 V ---- ---- 25 % IOLV2 Address input voltage Limits Conditions 1/ D.C. tp/tc 1/ TC = 25C 53 MIL-M-38510/210E TABLE IVG. Programming characteristics for circuit G . Parameter Symbol Required VCC for programming ICC during programming VCCP Required output voltage for programming Output current while programming Rate of voltage change of VCC or output Programming pulse width (enabled) Required VCC for verification Maximum duty cycle for VCC at VCCP Address set-up time VOP ICCP IOP Limits Conditions 1/ Unit Min Recommended Max 10.0 10.5 11.0 V 750 mA 11.0 V 20 mA 10.0 V/s VCC = 11 V 10.0 10.5 VOUT = 11 V IRR 1.0 PWE 9 10 11 s VCCV 3.8 4.0 4.2 V 25 25 % MDC t1 2/ 100 ns 5 s VCCP set-up time t2 VCCP hold time t5 100 ns VOP set-up time t3 100 ns VOP hold time t4 100 ns 1/ TC = +25C. 2/ VCCP setup time may be greater than 0 if VCCP rises at the same rate or faster than VOP. 54 MIL-M-38510/210E TABLE IVH. Programming characteristics for circuit H . Parameters 1/ Symbol Min Nom Max Unit Steady-state supply voltage VCC 4.75 5 5.25 V Input voltage VIH 3 4 5 V VIL 0 0 0.5 V 0 0 0.5 V Voltage all outputs except the one to be programmed Supply voltage level to program a bit VCC(pr) 5.75 6 6.25 V Select or enable level to program a bit VS(pr) 9.75 10 11 V Output level during interval t5 VO(PR) 15.75 16 16.25 V Low 4.4 4.5 4.6 V High 5.4 5.5 5.6 V Time for VCC to settle and to verify need to program t1 0 5 10 s Timing from VCC = 6 V until chip select (enable) is at 10 V Timing from chip select (enable) high to start or program ramp Ramp time, output program pulse t2 5 5 10 s t3 0.1 5 10 s t4 10 15 20 s Duration of output program pulse t5 15 20 20 s Time from end of program pulse to chip select (enable) low Time from chip select (enable) low to VCC = 0 V t6 5 5 10 s t7 0.1 5 5 s Time for cooling between bits t8 30 50 100 s Time for cooling between words t9 30 50 Supply voltage during verification (see step 0) 1/ TC = +25C. 55 s MIL-M-38510/210E TABLE IVI. Programming characteristics for circuit I . Parameter Symbol Limits Conditions 1/ Min Recommended Unit Max VCC during programming VCCP 5.0 5.5 V High level input voltage during programming Low level input voltage during programming Chip enable voltage during programming Output voltage during programming Voltage on outputs not to be programmed Current on outputs not to be programmed Rate of output voltage change Rate of chip enable voltage change Programming period VIHP 2.4 5.5 V VILP 0.0 0.45 V 14.5 15.5 V VOP 19.5 20.5 V VONP 0 VCCP + 0.3 20 V mA 20 250 V/s 100 1000 V/s tp 50 100 s VCCL 4.5 5.0 s VCC during programming verification VCEP CE 1 pin IONP d(VOP)/dt d(VCE)/dt CE 1 pin 1/ TC = +25C. 56 MIL-M-38510/210E TABLE IVJ. Programming characteristics for circuit J . Limits 1/ Parameters Symbol Min Recommended Max Unit VIH 2.4 5.0 5.0 V VIL 0.0 0.4 0.8 V VPH 11.75 12.0 12.25 V VPL 4.5 4.5 5.5 V ICCP 600 600 650 mA tr 1.0 1.0 10 s tf 1.0 1.0 10 s Programming delay td 10 10 100 s Programming pulse width tP 100 1000 s Programming duty cycle DC ---- 50 90 % Output voltage enable VOPE 10.0 10.5 11.0 V Output voltage disable 3/ VOPD 4.5 5.0 5.5 V Address input voltage 2/ Programming/verify voltage to VCC Programming voltage current limit with VPH applied Voltage rise and fall time 1/ TC = +25C. 2/ Address and chip select shall not be left open for VIH. 3/ Disable condition shall be met with output open circuit. 57 MIL-M-38510/210E 5. PACKAGING 5.1 Packaging requirements. For acquisition purposes, the packaging requirements shall be as specified in the contract or order (see 6.2). When packaging of materiel is to be performed by DoD or in-house contractor personnel, these personnel need to contact the responsible packaging activity to ascertain packaging requirements. Packaging requirements are maintained by the Inventory Control Point's packaging activity within the Military Service or Defense Agency, or within the military service's system command. Packaging data retrieval is available from the managing Military Department's or Defense Agency's automated packaging files, CD-ROM products, or by contacting the responsible packaging activity. 6. NOTES (This section contains information of a general or explanatory nature which may be helpful, but is not mandatory.) 6.1 Intended use. Microcircuits conforming to this specification are intended for logistic support of existing equipment. 6.2 Acquisition requirements. Acquisition documents should specify the following: a. Title, number, and date of the specification. b. PIN and compliance identifier, if applicable (see 1.2). c. Requirements for delivery of one copy of the conformance inspection data pertinent to the device inspection lot to be supplied with each shipment by the device manufacturer, if applicable. d. Requirements for certificate of compliance, if applicable. e. Requirements for notification of change of product or process to contracting activity in addition to notification to the qualifying activity, if applicable. f. Requirements for failure analysis (including required test condition of method 5003 of MIL-STD-883), corrective action, and reporting of results, if applicable. g. Requirements for product assurance options. h. Requirements for special lead lengths, or lead forming, if applicable. Unless otherwise specified, these requirements will not apply to direct purchase by or direct shipment to the Government. i. Requirement for programming the device, including processing option. The device may be programmed pre- or post-burn-in, if applicable. j. Requirements for "JAN" marking. k. Packaging Requirements (see 5.1) 6.3 Qualification. With respect to products requiring qualification, awards will be made only for products which are, at the time of award of contract, qualified for inclusion in Qualified Manufacturers List QML-38535 whether or not such products have actually been so listed by that date. The attention of the contractors is called to these requirements, and manufacturers are urged to arrange to have the products that they propose to offer to the Federal Government tested for qualification in order that they may be eligible to be awarded contracts or purchase orders for the products covered by this specification. Information pertaining to qualification of products may be obtained from DSCC-VQ, 3990 E. Broad Street, Columbus, Ohio 43218-3990. 58 MIL-M-38510/210E 6.4 Superseding information. The requirements of MIL-M-38510 have been superseded to take advantage of the available Qualified Manufacturer Listing (QML) system provided by MIL-PRF-38535. Previous references to MIL-M38510 in this document have been replaced by appropriate references to MIL-PRF-38535. All technical requirements now consist of this specification and MIL-PRF-38535. The MIL-M-38510 specification sheet number and PIN have been retained to avoid adversely impacting existing government logistics systems and contractor's parts lists. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535, MIL-HDBK-1331, and as follows: GND ............................................ VIN ............................................... VIC ................................................ IIN ................................................. Ground zero voltage potential. Voltage level at an input terminal Input clamp voltage Current flowing into an input terminal 6.6 Logistic support. Lead materials and finishes (see 3.4) are interchangeable. Unless otherwise specified, microcircuits acquired for Government logistic support will be acquired to device class B (see 1.2.2), lead material and finish C (see 3.4). Longer length leads and lead forming should not affect the part number. It is intended that spare devices for logistic support be acquired in the unprogrammed condition (see 3.8.1) and programmed by the maintenance activity, except where use quantities for devices with a specific program or pattern justify stocking of preprogrammed devices. 6.7 Substitutability. The cross-reference information below is presented for the convenience of users. Microcircuits covered by this specification will functionally replace the listed generic-industry type. Generic-industry microcircuit types may not have equivalent operational performance characteristics across military temperature ranges or reliability factors equivalent to MIL-M-38510 device types and may have slight physical variations in relation to case size. The presence of this information should not be deemed as permitting substitution of generic-industry types for MIL-M-38510 types or as a waiver of any of the provisions of MIL-PRF-38535. Military device type 01 1/ 01 1/ 01 1/ 01 1/ 02 1/ 02 1/ 02, 04 02 1/ 02 1/ 02 1/ 02, 04 1/ 02 1/ 02 1/ 03 1/ 04, 02 1/ 05 1/ 05 1/ 1/ 2/ Generic-industry Type 76160 / Harris 53S1680/Monolithic Memories 82S190/Signetics Corp. 77S190/National 76161/Harris 53S1681 / Monolithic Memories 82S191A/Signetics Corp. 3636/Intel 29681/Raytheon 77S191/National 28S166A/Texas Instruments 27S191/Advanced Micro Devices Circuit Designator A B C G A B C E F G H I 76161/Motorola 93Z510/Fairchild 93Z511/Fairchild 76165/Harris 82HS195/Signetics Corp. J D D A C This generic-industry type is no longer manufactured. Zapped vertical emitter. 59 Fusible Links NiCr TiW NiCr TiW/W NiCr TiW NiCr Polysilicon NiCr TiW/W TiW Platinum silicide NiCr ZVE 2/ ZVE NiCr ZVE CAGE Number 34371 50364 18324 27014 34371 50364 18324 34649 07933 27014 01295 34335 04713 07263 07263 34371 18324 MIL-M-38510/210E 6.8 Change from previous issue. Marginal notations are not used in this revision to identify changes with respect to the previous issue, due to the extensiveness of the changes. Custodians: Army - CR Navy - EC Air Force - 11 DLA - CC Preparing activity: DLA - CC Review activities: Army - SM, MI Navy - AS, CG, MC, SH TD Air Force - 03, 19, 99 (Project 5962-2006-003) NOTE: The activities listed above were interested in this document as of the date of this document. Since organization and responsibilities can change, you should verify the currency of the information above using the ASSIST Online database at http://assist.daps.dla.mil. 60