74F193SCX - Fairchild Semiconductor

April 1988

Revised September 2000

74F193 Up/Down Binary Counter with Separ ate Up/Down Clocks

74F193

Up/Down Binary Coun ter with Separate Up/Dow n Clocks

General Description

The 74F193 is an up/down modulo-16 binary counter. Sep-

arate Count Up and Count Down Clocks are used, and in

either counting mode the circuits operate synchronously.

The outpu ts change stat e synchrono usly with the LOW-to-

HIGH transitions on the clock inputs. Separate Terminal

Count Up and Terminal Count Down ou tputs are provided

that are u sed as the clock s for subsequen t stages withou t

extra logic, thus simplifying multi-stage counter designs.

Individual preset inputs allow the circuit to be used as a

programmable counter. Both the Parallel Load (PL) and t h e

Master Reset (MR) inputs asynchronously override the

clocks.

Ordering Code:

Devices also available in Ta pe and Reel. Speci fy by appe nding suffix let te r “X” to the ord ering co de.

Note 1: Device not availabl e in Tape and R eel.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F193SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

74F193SJ

(Note 1) M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74F193PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F193

Unit Loading/Fan Out

Functional Description

The 74F193 is a 4-bit binary synchronous up/down (revers-

ible) counter. It contains four edge-triggered flip-flops, with

internal gating and steering logic to provide master reset,

individual preset, count up and count down operations.

A LOW-to-HIGH tra nsition on the CP inpu t to each flip-flo p

causes the output to change state. Synchronous switching,

as opposed to ripple counting, is achieved by driving the

stee ring gate s of all st ages from a com mon Coun t Up line

and a com mon Count Down line, thereby c ausing all state

changes to be initiated simultaneously. A LOW-to-HIGH

transition on th e Count Up input will a dvance the count by

one; a similar transition on the Count Down input will

decreas e the count by on e. While counting with one clock

input, the other should be held HIGH, as indicated in the

Function Table.

The Terminal Count Up (TCU) and Terminal Count Down

(TCD) outputs are normally HIGH. When the circuit has

reached the maximum count state 15, the next HIGH-to-

LOW transition of the Count Up Clock will cause TCU to go

LOW. TCU will s tay LOW until CPU goes H I GH aga i n, th us

effectively repeating the Count Up Clock, but delayed by

two gate delays. Similarly, the TCD output will go LOW

when the circuit is in the zero state and the Count Down

Clock goes LOW. Since the TC outputs repeat the clock

wavef orms, they can be us ed as the clock input si gnals to

the next higher order circuit in a multistage counter.

TCU = Q0 • Q1 • Q2 • Q3 • CPU

TCD = Q0• Q1 • Q2 • Q3 • CPD

The 74F193 has an asynchronous parallel load capability

permitting the counter to be preset. When the Parallel Load

(PL) and the Mast er Reset (MR) inputs ar e LOW, informa-

tion present on the Parallel Data input (P0–P3) is loaded

into the counter and appears on the outputs regardless of

the conditions of the clock inputs. A HIGH signal on the

Master Reset input will disable the preset gates, override

both clock inputs, and latch each Q output in the LOW

state . If one of t he clock inp uts is LOW du ring and aft er a

reset or load operation, the next LOW-to-HIGH transition of

that clock will be interprete d as a legitimate signal and will

be co unted.

Function Table

H = HIGH Voltage Lev el

L = LOW Voltage Level

X = Immaterial



= LOW-to-HIGH Clock Transition

State Diagram

Pin Names Description U.L. Input IIH/IIL

HIGH/LOW Output IOH/IOL

CPUCount Up Clock Input (Active Rising Edge) 1.0/3.0 20 µA/−1.8 mA

CPDCount Down Clock Input (Active Rising Edge) 1.0/3.0 20 µA/−1.8 mA

MR Asynchronous Master Reset Input (Active HIGH) 1.0/1.0 20 µA/−0.6 mA

PL Asynchronous Parallel Load Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA

P0–P3Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA

Q0–Q3Flip-Flop Outputs 50/33.3 −1 mA/20 mA

TCDTerminal Count Down (Borrow) Output (Active LOW) 50/33.3 −1 mA/20 mA

TCUTer minal Count Up (Carr y) Outp ut (A ctive LOW) 50/33.3 −1 mA/20 mA

MR PL CPUCPDMode

H X X X Reset (Asyn.)

L L X X Preset (Asyn.)

L H H H No Change



H Count Up

LHH



Count Down

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74F193

Logic Diagram

Please note that this diagram is provided only for the understandi ng of logic operations and should not be used to estimate propagation delays.

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74F193

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions

Note 2: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation

under th es e conditi ons is not im plied.

Note 3: Eith er v oltage lim it or c urrent limit is sufficien t to prot ect inputs .

DC Electrical Characteristi cs

Stora ge Temper atu re −65°C to +150°C

Ambient Temperature under Bias −55°C to +125°C

Junct ion Temper atu re und er Bias −55°C to +150°C

VCC Pin Potential to Ground Pin −0.5V to +7.0V

Input Voltage (Note 3) −0.5V to +7.0V

Input Current (Note 3) −30 mA to +5.0 mA

Voltage Applied to Output

in HIGH State (with VCC = 0V)

Standard Output −0.5V to VCC

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated IOL (mA)

Free Air Ambient Temperature 0°C to +70°C

Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units VCC Conditions

VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal

VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

VOH Output HIGH 10% VCC 2.5 VMin

IOH = −1 mA

Voltage 5% VCC 2.7 IOH = −1 mA

VOL Output LOW Voltage 10% VCC 0.5 V Min IOL = 20 mA

IIH Input HIGH 5.0 Max VIN = 2.7V

Current

IBVI Input HIGH Current 100 µAMaxV

IN = 7.0V

Breakdown Test 7.0

ICEX Output HIGH 50 µAMaxV

OUT = VCC

Leakage Current

VID Input Leakage 4.75 V 0.0 IID = 1.9 µA

Test All Other Pins Grounded

IOD Output Leakage 3.75 µA0.0

VIOD = 150 mV

Circuit Current All Other Pins Grounded

IIL Input LOW Current −0.6 mA Max VIN = 0.5V (MR, PL, Pn)

−1.8 VIN = 0.5V (CPu, CPD)

IOS Output Short-Circuit Current −60 −150 mA Max VOUT = 0V

ICC Power Supply Current 38 55 mA Max

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74F193

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

A = 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF

Min Typ Max Min Max

fMAX Maximum Count Frequency 100 125 90 MHz

tPLH Propagation Delay 4.0 7.0 9.0 4.0 10.0 nstPHL CPU or CPD to 3.5 6.0 8.0 3.5 9.0

TCU or TCD

tPLH Propagation Delay 4.0 6.5 8.5 4.0 9.5 ns

tPHL CPU or CPD to Qn 5.5 9.5 12.5 5.5 13.5

tPLH Propagation Delay 3.0 4.5 7.0 3.0 8.0 ns

tPHL Pn to Qn 6.0 11.0 14.5 6.0 15.5

tPLH Propagation Delay 5.0 8.5 11.0 5.0 12.0 ns

tPHL PL to Qn 5.5 10.0 13.0 5.5 14.0

tPHL Propagation Delay 5.5 11.0 14.5 5.5 15.5

MR to Qn

tPLH Propagation Delay 6.0 10.5 13.5 6.0 14.5

MR to TCU

tPHL Propagation Delay 6.0 11.5 14.5 6.0 15.5

MR to TCD

tPLH Propagation Delay 7.0 12.0 15.5 7.0 16.5 ns

tPHL PL to TCU or TCD 7.0 11.5 14.5 7.0 15.5

tPLH Propagation Delay 7.0 11.5 14.5 7.0 15.5 ns

tPHL Pn to TCU or TCD 6.5 11.0 14.0 6.5 15.0

Symbol Parameter

TA = +25°CT

A = 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V

MinMaxMinMax

tS(H) Setup Time, HIGH or LOW 4.5 5.0

tS(L) Pn to PL 4.5 5.0

tH(H) Hold Time, HIGH or LOW 2.0 2.0

tH(L) Pn to PL 2.0 2.0

tW(L) PL Pulse Width, LOW 6.0 6.0 ns

tW(L) CPU or CPD 5.0 5.0 ns

Pulse Width, LOW

tW(L) CPU or CPD

Pulse Width, LOW 10.0 10.0 ns

(Change of Direction)

tW(H) MR Pulse Width, HIGH 6.0 6.0 ns

tREC Recovery Time 6.0 6.0 ns

PL to CPU or CPD

tREC Recovery Time 4.0 4.0 ns

MR to CPU or CPD

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74F193

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

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74F193

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74F193 Up/Down Binary Counter with Separate Up/Down Clocks

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

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to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a lif e supp ort

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device or system, or to affect its safety or effectiveness.