1
40V General Purpose Precision Operational Amplifier
ISL28177
The ISL28177 is an OP07 replacement featuring low input
offset voltage, low input bias current, and competitive noise
and AC performance. The ESD ratings are best among
competitive parts at 5kV HBM, 300V MM, and 2.2kV CDM. The
amplifier operates over the 6V (±3V) to 40V (±20V) range.
Applications include precision active filters, medical and
analytical instrumentation, precision power supply controls,
and industrial sensors.
The ISL28177 is available in the SOT23-5 and SOIC-8
packages and operates over the extended temperature range
to -40°C to +125°C.
Features
• Wide Supply Range . . . . . . . . . . . . . . . . 6V (±3V) to 40V (±20V)
• Low Input Offset Voltage . . . . . . . . . . . . . . . . . . . . 150µV, Max
• Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . . . .1nA, Max
• Low Noise . . . . . . . . . . . . . . . . . . . . . . . . . . .9.5nV/√Hz @ 1kHz
• Gain Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600kHz
• Exceptional ESD Performance . . . . . . . . . 5kV HBM, 300V MM,
2.2kV CDM
• Operating Temperature Range. . . . . . . . . . .-40°C to +125°C
•Packages
- ISL28177 (Single) . . . . . . . . . . . . . . . . . . . SOT23-5, SOIC-8
Applications
• Precision Active Filters
• Medical and Analytical Instrumentation
• Precision Power Supply Controls
• Industrial Sensors
FIGURE 1. TYPICAL APPLICATION FIGURE 2. INPUT NOISE PERFORMANCE
-
+
OUTPUT
V+
R1
V-
R2
C1
C2
SALLEN-KEY LOW PASS FILTER (10kHz)
VIN
1.84k 4.93k
3.3nF
8.2nF
0.1 1 10 100 1k 10k 100k
INPUT NOISE VOLTAGE (nV/√Hz)
FREQUENCY (Hz)
INPUT NOISE CURRENT (pA/√Hz)
1
10
100
1000
10000
1
10
100
1000
10000
VS = ±18V
INPUT NOISE CURRENT
INPUT NOISE VOLTAGE
April 5, 2012
FN7859.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL28177
2FN7859.2
April 5, 2012
Ordering Information
PART NUMBER
(Note 2, 3) PART MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL28177FBZ 28177 FBZ -40 to +125 8 Ld SOIC M8.15E
ISL28177FBZ-T13 (Note 1) 28177 FBZ -40 to +125 8 Ld SOIC M8.15E
ISL28177FBZ-T7 (Note 1) 28177 FBZ -40 to +125 8 Ld SOIC M8.15E
ISL28177FBZ-T7A (Note 1) 28177 FBZ -40 to +125 8 Ld SOIC M8.15E
Coming Soon
ISL28177FHZ
TBD -40 to +125 SOT23-5 P5.064A
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28177. For more information on MSL please see techbrief TB363.
Pin Configurations
ISL28177
(8 LD SOIC)
TOP VIEW
ISL28177
(5 LD SOT-23)
TOP VIEW
Pin Descriptions
ISL28177
(8 LD SOIC)
ISL28177
(5 LD SOT-23) PIN NAME EQUIVALENT CIRCUIT DESCRIPTION
3 3 IN+ Circuit 1 Amplifier non-inverting input
4 2 V- Circuit 3 Negative power supply
2 4 IN- Circuit 1 Amplifier inverting input
7 5 V+ Circuit 3 Positive power supply
61V
OUT Circuit 2 Amplifier output
1, 5, 8 - NC - No internal connection
NC
IN-
IN+
V -
1
2
3
4
8
7
6
5
NC
V+
VOUT
NC
+
-
OUT
V-
IN+
V+
IN-
1
2
3
5
4
CIRCUIT 2
CIRCUIT 1
V+
V-
CIRCUIT 3
CAPACITIVELY
COUPLED
ESD CLAMP
IN-
V+
V-
IN+
500Ω500ΩV+
V-
OUT
ISL28177
3FN7859.2
April 5, 2012
Absolute Maximum Ratings Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V
Maximum Differential Input Voltage . . . . . . . 44V or V- - 0.5V to V+ + 0.5V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . 44V or V- - 0.5V to V+ + 0.5V
Min/Max Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Output Short-Circuit Duration (1 output at a time) . . . . . . . . . . . . . . Indefinite
ESD Ratings
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 5kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per CDM-22CI0ID) . . . . . . . . . . . . . .2.2kV
Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)
5 Ld SOT-23 Package (Notes 4, 5) . . . . . . . . TBD TBD
8 Ld SOIC Package (Notes 4, 5) . . . . . . . . . . 125 73
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-40°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . .6V (±3V) to 40V (±20V)
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications VS = ±5V to ±15V, RL = Open, VCM = 0V, TA = +25°C, unless otherwise specified. Boldface limits apply over the
operating temperature range, -40°C to +125°C.
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 6) TYP
MAX
(Note 6) UNIT
VOS Input Offset Voltage 150 µV
-40°C to +85°C 250 µV
-40°C to +125°C 350 µV
TCVOS Input Offset Voltage Temperature
Coefficient
-40°C to +125°C 0.5 1.4 µV/°C
ΔVOS/Time Long Term VOS Stability 0.4 µV/mo
IBInput Bias Current 0.2 1 nA
-40°C to +125°C 1nA
IOS Input Offset Current 0.2 1 nA
-40°C to +125°C 1nA
eNInput Noise Voltage f = 0.1Hz to 10Hz 0.38 µVP-P
Input Noise Voltage Density f = 10Hz 13 nV/√Hz
Input Noise Voltage Density f = 100Hz 9.6 nV/√Hz
Input Noise Voltage Density f = 1kHz 9.5 nV/√Hz
iNInput Noise Current Density f = 1kHz 87 fA/√Hz
VCMIR Common Mode Input Voltage Range Guaranteed by CMRR test V- +2 V+ -2 V
CMRR Common Mode Rejection Ratio VCM = V- +2V to V+ - 2V 120 140 dB
120 dB
PSRR Power Supply Rejection Ratio VS = ±3V to ±20V 115 130 dB
115 dB
VOL Output Voltage Low,
VOUT to V-
RL = 2kΩ1.2 1.25 V
RL = 2kΩ, -40°C to +125°C 1.3 V
VOH Output Voltage High,
V+ to VOUT
RL = 2kΩ1.2 1.25 V
RL = 2kΩ, -40°C to +125°C 1.3 V
SR Slew Rate RL = 2kΩ, CL = 100pF 0.2 V/µs
GBWP Gain Bandwidth Product RL = 100kΩ, CL = 60pF 600 kHz
AVOL Large Signal Gain VOUT = ±3V to ±13V, RL = 10kΩ120 140 dB
120 dB
ISL28177
4FN7859.2
April 5, 2012
ISSupply Current 1.18 1.4 mA
1.7 mA
VSSupply Voltage ±3V ±20V V
ISC Short Circuit Current 30 mA
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Electrical Specifications VS = ±5V to ±15V, RL = Open, VCM = 0V, TA = +25°C, unless otherwise specified. Boldface limits apply over the
operating temperature range, -40°C to +125°C. (Continued)
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 6) TYP
MAX
(Note 6) UNIT
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified.
FIGURE 3. INPUT OFFSET VOLTAGE (VOS) vs TEMPERATURE FIGURE 4. POWER SUPPLY CURRENT (IS) vs TEMPERATURE
FIGURE 5. POSITIVE INPUT BIAS CURRENT (IIB+) vs TEMPERATURE FIGURE 6. NEGATIVE INPUT BIAS CURRENT (IIB-) vs TEMPERATURE
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
V
OS
(µV)
-100
-80
-60
-40
-20
0
20
40
60
80
100 VS = ±15V
TEMPERATURE (°C)
-40-20 0 20406080100120
IS (mA)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VS = ±15V
TEMPERATURE (°C)
-40-20 0 20406080100120
IBIAS+ (nA)
-500
-400
-300
-200
-100
0
100
200
300
400
500 VS = ±15V
TEMPERATURE (°C)
-40-20 0 20406080100120
IBIAS- (nA)
-500
-400
-300
-200
-100
0
100
200
300
400
500 VS = ±15V
ISL28177
5FN7859.2
April 5, 2012
FIGURE 7. POSITIVE OUTPUT VOLTAGE (VOH) vs TEMPERATURE FIGURE 8. POSITIVE OUTPUT VOLTAGE (VOL) vs TEMPERATURE
FIGURE 9. POSITIVE OUTPUT VOLTAGE (VOUT) vs OUTPUT CURRENT
(IOUT) vs TEMPERATURE
FIGURE 10. UNITY GAIN FREQUENCY RESPONSE vs RL
FIGURE 11. OPEN LOOP GAIN-PHASE vs FREQUENCY FIGURE 12. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
TEMPERATURE (°C)
-40-20 0 20406080100120
VOH (V)
13.5
13.6
13.7
13.8
13.9
14.0
14.1
14.2
14.3
14.4
14.5
VS = ±15V
RL = 2k
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
VOL (V)
VS = ±15V
RL = 2k
-14.5
-14.4
-14.3
-14.2
-14.1
-14.0
-13.9
-13.8
-13.7
-13.6
-13.5
-15
-10
-5
0
0 1020304050607080
0
5
10
15
V
OL
(V)
CURRENT (mA)
-55°C
-40°C
0°C
+25°C
+150°C
+125°C
+75°C
VS = ±15V
AV = 2
VIN = ±7.5V-DC
RF = RG = 100k
V
OH
(V)
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
10 100 1k 10k 100k 1M 10M
RL = 100
CL = 4pF
AV = +1
VS = ±15V
VOUT = 50mVP-P
RL = 499
RL = 1k
RL = 10k
RL = 100k
RL = ∞
GAIN (dB), PHASE (°)
FREQUENCY (Hz)
-40
-20
0
20
40
60
80
100
120
140
160
180
0.01 0.1 1 10 100 1k 10k 100k 1M 10M 100M
VS = ±15V
RL = 1MΩ
SIMULATION
GAIN
PHASE
-10
0
10
20
30
40
50
60
70
GAIN (dB)
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M
ACL = 1
ACL = 10
ACL = 1001
VS = ±15V
CL = 4pF
VOUT = 50mVP-P
RL = OPEN
ACL = 101
RF = 0, RG = ∞
RF = 100kΩ, RG = 100
RF = 100kΩ, RG = 1k
RF = 100kΩ, RG = 11kΩ
ISL28177
6FN7859.2
April 5, 2012
FIGURE 13. UNITY GAIN FREQUENCY RESPONSE vs CLFIGURE 14. OVERSHOOT vs LOAD CAPACITANCE
FIGURE 15. INPUT NOISE VOLTAGE AND CURRENT SPECTRAL DENSITY FIGURE 16. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz
FIGURE 17. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 18. SMALL SIGNAL TRANSIENT RESPONSE
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M
-10
-8
-6
-4
-2
0
2
4
6
8
RL = 10k
AV = +1
VS = ±15V
VOUT = 50mVP-P
CL = 2200pF
CL = 4pF
CL = 1000pF
CL = 4700pF
CL = 10nF
CL = 22nF
OVERSHOOT (%)
LOAD CAPACITANCE (nF)
0
10
20
30
40
50
60
70
0.001 0.01 0.1 1 10 100
+OVERSHOOT
-OVERSHOOT
V
S
= ±15V
V
OUT
= 50mV
P-P
RL= 10k
AV = 1
0.1 1 10 100 1k 10k 100k
INPUT NOISE VOLTAGE (nV/√Hz)
FREQUENCY (Hz)
INPUT NOISE CURRENT (pA/√Hz)
1
10
100
1000
10000
1
10
100
1000
10000
VS = ±18V
INPUT NOISE CURRENT
INPUT NOISE VOLTAGE
INPUT NOISE VOLTAGE (nV)
012345678910
TIME (s)
-500
-400
-300
-200
-100
0
100
200
300
400
500
VS = ±18V
AV = 10k
VOUT (V)
TIME (µs)
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
0 100 200 300 400 500 600 700 800 900 1k
VS = ±15V
AV = 1
RL = 2k AND 10k
CL = 4pF
VOUT (mV)
TIME (µs)
-40
-30
-20
-10
0
10
20
30
40
012345678910
AV = 1
RL = 2k AND 10k
CL = 4pF
VS = ±15V
VS = ±5V
ISL28177
7FN7859.2
April 5, 2012
Applications Information
Functional Description
The ISL28177 is a low noise op amp fabricated in a 40V
complementary bipolar DI process designed for general purpose
low power applications. It utilizes a super-beta NPN input stage
with input bias current cancellation for low input bias current and
low input noise voltage. A complimentary bipolar output stage
enables high capacitive load drive without external
compensation.
Operating Voltage Range
The ISL28177 is designed to operate over the 6V (±3V) to 40V
(±20V) range. The common mode input voltage range extends to
2V from each rail, and the output voltage swings to 1.3V of
each rail.
Input Performance
The super-beta NPN input pair reduces input bias current while
maintaining good frequency response, low input bias current and
low noise. Input bias cancellation circuits provide additional bias
current reduction to <1nA, and excellent temperature
stabilization and low TCVOS.
Input ESD Diode Protection
The input terminals (IN+ and IN-) have internal ESD protection
diodes to the positive and negative supply rails, series connected
500Ω current limiting resistors and an anti-parallel diode pair
across the inputs (Figure 21).
The series resistors limit the high feed-through currents that can
occur in pulse applications when the input dv/dt exceeds the
0.2V/µs slew rate of the amplifier. Without the series resistors, the
input can forward-bias the anti-parallel diodes causing current to
flow to the output, resulting in severe distortion and possible diode
failure. Figure 17 provides an example of distortion free large signal
response using a 10VP-P input pulse with an input rise time of <1ns.
The series resistors enable the input differential voltage to be equal
to the maximum power supply voltage (40V) without damage.
In applications where one or both amplifier input terminals are at
risk of exposure to high voltages beyond the power supply rails,
current limiting resistors may be needed at the input terminal to
limit the current through the power supply ESD diodes to
20mA max.
Output Current Limiting
The output current is internally limited to approximately ±30mA
at +25°C and can withstand a short circuit to either rail as long
as the power dissipation limits are not exceeded. Continuous
operation under these conditions may degrade long term
reliability.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL28177 is immune to output phase reversal.
FIGURE 19. POSITIVE OUTPUT OVERLOAD RESPONSE TIME FIGURE 20. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
-2
0
2
4
6
8
10
12
14
16
-280
-240
-200
-160
-120
-80
-40
0
40
80
0 40 80 120 160 200 240 280 320 360 400
OUTPUT (V)
INPUT (mV)
TIME (µs)
VS = ±15V
AV = 100
VIN = 200mVP-P
OVERDRIVE = 1V
RL = 10k
INPUT
OUTPUT
-16
-14
-12
-10
-8
-6
-4
-2
0
2
-80
-40
0
40
80
120
160
200
240
280
0 40 80 120 160 200 240 280 320 360 400
OUTPUT (V)
INPUT (mV)
TIME (µs)
VS = ±15V
AV = 100
VIN = 200mVP-P
OVERDRIVE = 1V
RL = 10k
INPUT
OUTPUT
FIGURE 21. INPUT ESD DIODE CURRENT LIMITING
-
+RL
VIN
VOUT
V+
V-
500Ω
500Ω
ISL28177
8FN7859.2
April 5, 2012
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperature under certain load and power supply conditions. It is
therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
where:
•PD
MAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
•PD
MAX for each amplifier can be calculated using Equation 2:
where:
•T
MAX = Maximum ambient temperature
•θJA = Thermal resistance of the package
•PD
MAX = Maximum power dissipation of 1 amplifier
•V
S = Total supply voltage
•I
qMAX = Maximum quiescent supply current of 1 amplifier
•V
OUTMAX = Maximum output voltage swing of the application
ISL28177 SPICE Model
Figure 22 shows the SPICE model schematic and Figure 23 shows
the net list for the SPICE model. The model is a simplified version
of the actual device and simulates important AC and DC
parameters. AC parameters incorporated into the model are: 1/f
and flatband noise voltage, Slew Rate, CMRR, Gain and Phase. The
DC parameters are, VOS, IOS, total supply current and output
voltage swing. The model uses typical parameters given in the
“Electrical Specifications” table beginning on page 3. The AVOL is
adjusted for 140dB with the dominant pole at 0.075Hz. The CMRR
is set 145dB, fcm = 500kHz. The input stage models the actual
device to present an accurate AC representation. The model is
configured for ambient temperature of +25°C.
Figures 24 through 37 show the characterization vs simulation
results for the Noise Voltage, Closed Loop Gain vs Frequency,
Small Signal 0.1V Step, Large Signal 5V Step Response, Open
Loop Gain Phase, CMRR, Unity Gain Frequency Response vs CL
and Output Voltage Swing for ±15V supplies.
LICENSE STATEMENT
The information in this SPICE model is protected under the
United States copyright laws. Intersil Corporation hereby grants
users of this macro-model hereto referred to as “Licensee”, a
nonexclusive, nontransferable license to use this model as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the macro-model,
in whole, in part, or in modified form, to anyone outside the
Licensee’s company. The Licensee may modify the macro-model
to suit his/her specific applications, and the Licensee may make
copies of this macro-model for use within their company only.
This macro-model is provided “AS IS, WHERE IS, AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral, incidental,
or consequential damages in connection with or arising out of
the use of this macro-model. Intersil reserves the right to make
changes to the product and the macro-model without prior
notice.
TJMAX TMAX θJAxPDMAXTOTAL
+= (EQ. 1)
P
DMAX VSIqMAX VS
( - VOUTMAX)VOUTMAX
RL
----------------------------
×+×=(EQ. 2)
ISL28177
9FN7859.2
April 5, 2012
2ND GAIN STAGE
2ND POLE STAGE
NOISE STAGE
REF VOLTAGE
COMMON MODE
GAIN STAGE
WITH ZERO
CORRECTION CURRENT
SOURCES
OUTPUT STAGE
INPUT STAGE 1ST GAIN STAGE MID SUPPLY
20
V++
V--
V++
16
V--
15
17
12
7
Vc
Vin-
6
22
Vin+
8
1
2
3
14
19
21
VCM
11
13
Vmid
18
10
23
24
VOUT
25
9
5
V+
4
In+
V-
0
0
0
0
0
0
DX
D3
ISY
1.18e-3
ISY
1.18e-3
Q2
SuperB
C2
2e-12
+
-
G12
GAIN = 1.11e-2
+
-
G12
R5
1
R5
1
DX
D10
R14
1989.49546
R10
1
R10
1
R13
1989.49546
C9
10e-12
IEE
200e-6
C8
10e-12
R16
1989.49546
R1
5e11
R12
1
R3
4.45e3
DX
D9
+
-
G13
GAIN = 1.11e-2
G13
V6
0.18
C5
1e-9
C5
1e-9
V2
1.71.7
+
-
G3
GAIN = 4.712E-3
+
-
G3
GAIN = 4.712E-3
V1 0.07
V1
IEE1
96e-6
DX
D5
DX
D5
DX
D7D7
C3
2e-12
V7
0.18
-
+
+
-
En
-
+
+
-
C1
1.2e-12
-
++
-
EOS
GAIN = 1E-9
-
++
-
EOS
+
-
G2
GAIN = 0.06
+
-
G2
GAIN = 0.06
R9
1
R9
1
R19
5000
R2
5e11
V5
1.7
V5
+
-
G9
GAIN = 502.64e-6
+
-
G9
R8
2122.196e6
L1
318.31927e-6
L1
318.31927e-6
C4
1e-9
R7
2122.196e6
+
-
G1
GAIN = 0.06
+
-
G1
+
-
G5
GAIN = 0.1e-6
+
-
G5
GAIN = 0.1e-6
DN
D1
+
-
G6
GAIN = 0.1e-6
+
-
G6
GAIN = 0.1e-6
Q1
SuperB
Q4
Cascode
Q4
DX
D2
DX
-
+
+
-
E2
GAIN = 1
-
+
+
-
E2
VOS
150E-6
DX
D6D6
R11
1
+
-
G14
GAIN = 1.11e-2
G14
+
-
G8
GAIN = 502.64e-6
G8
IOS
1e-9
+
-
G4
GAIN = 4.712E-3
+
-
G4
V3
1.7
V3
1.7
DX
D8
R18
9E1
Q3
Mirror
Q3
Mirror
+
-
G10
GAIN = 502.64e-6
+
-
G10
R6
1
R6
1
DY
D12D12
C7
10e-12
DX
D4D4
R15
1989.49546
L2
318.31927e-6318.31927e-6
R4
4.45e3
V4
1.7
V4
DY
D11D11
C6
10e-12
+
-
G7
GAIN = 502.64e-6
G7 R17
9E1
-
+
+
-
E1
GAIN = 1
E1
+
-
G11
GAIN = 1.11e-2
-
G11
Q5
Cascode
Q5
FIGURE 22. SPICE MODEL SCHEMATIC
ISL28177
10 FN7859.2
April 5, 2012
*ISL28177 Macromodel
**Revision History:
*Revision A, LaFontaine December 14, 2011
*Model for Noise, quiescent supply currents,
*CMRR 145dB, fcm=500kHz, AVOL 140dB
*f=0.075Hz SR = 0.2V/us, GBWP 600kHz,
*2nd pole 8Mhz, output voltage clamp
*and short ckt current limit.
*
*Copyright 2011 by Intersil Corporation
*Refer to data sheet "LICENSE
*STATEMENT", Use of this model indicates
*your acceptance with the terms and
*provisions in the License Statement.
*
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performanc e
*characteristics under a wide range of
*external circuit configurations using
*compatible simulation platforms - such as
*iSim PE.
*
*Device performance features supported by
*this model
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances
*Open loop gain and phase
*Closed loop bandwidth and frequency
*response
*Loading effects on closed loop frequency
*response
*Input noise terms including 1/f effects
*Slew rate
*Input and Output Headroom limits to I/O
*voltage swing
*Supply current at nominal specified supply
*voltages
**
*Device performance features NOT
*supported by this model:
*Harmonic distortion effects
*Disable operation (if any)
*Thermal effects and/or over temperature
*parameter variation
*Limited performance variation vs. supply
*voltage is modeled
*Part to part performance variation due to
*normal process parameter spread
*Any performance difference arising from
*different packaging
* source
:
*+input
* | -input
* | | +Vsupply
* | | | -Vsupply
* | | | | output
* | | | | |
.subckt ISL28177 Vin+ Vin- V+ V- VOUT
* source ISL28177_SPICEMODEL
*
*Voltage Noise
E_En IN+ VIN+ 2 0 1
D_D1 1 2 DN
V_V1 1 0 0.07
R_R19 2 0 5000
*
*Input Stage
I_IOS IN+ VIN- DC 1e-9
C_C1 IN+ VIN- 1.2e-12
C_C2 0 VIN- 2e-12
C_C3 0 IN+ 2e-12
R_R1 VCM VIN- 5e11
R_R2 IN+ VCM 5e11
R_R3 6 V++ 4.45e3
R_R4 7 V++ 4.45e3
Q_Q1 4 VIN- 3 SuperB
Q_Q2 5 10 3 SuperB
Q_Q3 V-- 3 9 Mirror
Q_Q4 6 8 4 Cascode
Q_Q5 7 8 5 Cascode
I_IEE 3 V-- DC 200e-6
I_IEE1 V++ 8 DC 96e-6
D_D2 8 9 DX
E_EOS 10 11 VC VMID 1E-9
V_VOS 11 IN+ 30E-6
*
*1st Gain Stage
G_G1 V++ 13 6 7 0.06
G_G2 V-- 13 6 7 0.06
R_R5 13 V++ 1
R_R6 V-- 13 1
V_V2 12 13 1.7
V_V3 13 14 1.7
D_D3 12 V++ DX
D_D4 V-- 14 DX
*
*2nd Gain Stage
G_G3 V++ 15 13 VMID 4.712E-3
G_G4 V-- 15 13 VMID 4.712E-3
R_R7 15 V++ 2122.196e6
R_R8 V-- 15 2122.196e6
V_V4 16 15 1.7
V_V5 15 17 1.7
D_D5 16 V++ DX
D_D6 V-- 17 DX
C_C4 15 V++ 1e-9
C_C5 V-- 15 1e-9
*
*Mid supply Ref
R_R9 VMID V++ 1
R_R10 V-- VMID 1
E_E1 V++ 0 V+ 0 1
E_E2 V-- 0 V- 0 1
I_ISY V+ V- DC 1.18e-3
*
*Common Mode Gain Stage with Zero
G_G5 V++ VC VCM VMID 0.1e-6
G_G6 V-- VC VCM VMID 0.1e-6
R_R11 VC 18 1
R_R12 19 VC 1
L_L1 18 V++ 318.31927e-6
L_L2 19 V-- 318.31927e-6
*
*2nd Pole Stage
G_G7 V++ 20 15 VMID 502.64e-6
G_G8 V-- 20 15 VMID 502.64e-6
G_G9 V++ 21 20 VMID 502.64e-6
G_G10 V-- 21 20 VMID 502.64e-6
R_R13 20 V++ 1989.49546
R_R14 V-- 20 1989.49546
R_R15 21 V++ 1989.49546
R_R16 V-- 21 1989.49546
C_C6 20 V++ 10e-12
C_C7 V-- 20 10e-12
C_C8 21 V++ 10e-12
C_C9 V-- 21 10e-12
*
*Output Stage with Correction Current
Sources
G_G11 VOUT V++ V++ 21 1.11e-2
G_G12 V-- VOUT 21 V-- 1.11e-2
G_G13 22 V-- VOUT 21 1.11e-2
G_G14 25 V-- 21 VOUT 1.11e-2
D_D7 21 23 DX
D_D8 24 21 DX
D_D9 V++ 22 DX
D_D10 V++ 25 DX
D_D11 V-- 22 DY
D_D12 V-- 25 DY
V_V6 23 VOUT 0.18
V_V7 VOUT 24 0.18
R_R17 VOUT V++ 9E1
R_R18 V-- VOUT 9E1
*
.model SuperB npn
+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50
+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12
+ kf=0 af=0
.model Cascode npn
+ is=502E-18 bf=150 va=300 ik=17E-3
+rb=140 re=0.011 rc=900 cje=0.2E-12
+cjc=0.16E-12f kf=0 af=0
.model Mirror pnp
+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185
+ re=0.101 rc=180 cje=1.34E-12
+ cjc=0.44E-12
+ kf=0 af=0
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends subckt ISL28177
FIGURE 23. SPICE NET LIST
ISL28177
11 FN7859.2
April 5, 2012
Characterization vs Simulation Results
FIGURE 24. CHARACTERIZED INPUT NOISE VOLTAGE FIGURE 25. SIMULATED INPUT NOISE VOLTAGE
FIGURE 26. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY FIGURE 27. SIMULATED CLOSED LOOP GAIN vs FREQUENCY
FIGURE 28. CHARACTERIZED SMALL SIGNAL TRANSIENT
RESPONSE vs RL, VS= ±0.9V, ±2.5V
FIGURE 29. SIMULATED SMALL SIGNAL TRANSIENT
RESPONSE VS = ±15V
0.1 1 10 100 1k 10k 100k
INPUT NOISE VOLTAGE (nV/√Hz)
FREQUENCY (Hz)
INPUT NOISE CURRENT (pA/√Hz)
1
10
100
1000
10000
1
10
100
1000
10000
VS = ±18V
INPUT NOISE VOLTAGE
INPUT NOISE CURRENT
0.1 1 10 100 1k 10k 100k
FREQUENCY (Hz)
1
10
100
1000
10000
INPUT NOISE VOLTAGE
VS = ±15V
INPUT NOISE VOLTAGE (nV/√Hz)
-10
0
10
20
30
40
50
60
70
GAIN (dB)
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M
ACL = 1
ACL = 10
ACL = 1001
VS = ±15V
CL = 4pF
VOUT = 50mVP-P
RL = OPEN
ACL = 101
RF = 0, RG = ∞
RF = 100kΩ, RG = 100
RF = 100kΩ, RG = 1k
RF = 100kΩ, RG = 11kΩ
-10
0
10
20
30
40
50
60
70
GAIN (dB)
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M
ACL = 1
ACL = 10
ACL = 1001
VS = ±15V
CL = 4pF
VOUT = 50mVP-P
RL = OPEN
ACL = 101
RF = 100kΩ, RG = 11kΩ
RF = 100kΩ, RG = 1k
RF = 100kΩ, RG = 100
RF = 0, RG = ∞
V
OUT
(mV)
TIME (µs)
-40
-30
-20
-10
0
10
20
30
40
012345678910
AV = 1
RL = 2k AND 10k
CL = 4pF
VS = ±5V
VS = ±15V
V
OUT
(mV)
TIME (µs)
-40
-30
-20
-10
0
10
20
30
40
012345678910
AV = 1
RL = 10k
CL = 4pF
ISL28177
12 FN7859.2
April 5, 2012
FIGURE 30. CHARACTERIZED LARGE SIGNAL TRANSIENT
RESPONSE vs RL, VS=±15V
FIGURE 31. SIMULATED LARGE SIGNAL TRANSIENT
RESPONSE, VS=±14V
FIGURE 32. SIMULATED (DESIGN) OPEN-LOOP GAIN, PHASE vs
FREQUENCY
FIGURE 33. SIMULATED (SPICE) OPEN-LOOP GAIN, PHASE vs
FREQUENCY
FIGURE 34. CHARACTERIZEDUNITY GAIN
FREQUENCY RESPONSE vs CL
FIGURE 35. SIMULATED UNITY GAIN FREQUENCY RESPONSE vs CL
Characterization vs Simulation Results (Continued)
V
OUT
(V)
TIME (µs)
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
0 100 200 300 400 500 600 700 800 900 1k
VS = ±15V
AV = 1
RL = 2k AND 10k
CL = 4pF
V
OUT
(V)
TIME (µs)
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
0 100 200 300 400 500 600 700 800 900 1k
VS = ±15V
AV = 1
RL = 2k AND 10k
CL = 4pF
GAIN (dB), PHASE (°)
FREQUENCY (Hz)
-40
-20
0
20
40
60
80
100
120
140
160
180
0.01 0.1 1 10 100 1k 10k 100k 1M 10M 100M
VS = ±15V
RL = 1MΩ
SIMULATION
GAIN
PHASE
GAIN (dB), PHASE (°)
FREQUENCY (Hz)
-40
-20
0
20
40
60
80
100
120
140
160
180
0.01 0.1 1 10 100 1k 10k 100k 1M 10M 100M
VS = ±15V
RL = 1MΩ
SIMULATION
GAIN
PHASE
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M
-10
-8
-6
-4
-2
0
2
4
6
8
RL = 10k
AV = +1
VS = ±15V
VOUT = 50mVP-P
CL = 2200pF
CL = 4pF
CL = 1000pF
CL = 4700pF
CL = 10nF
CL = 22nF
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M
-10
-8
-6
-4
-2
0
4
6
8
10
CL = 2200pF
CL = 4pF
CL = 1000pF
CL = 4700pF
CL = 10nF
CL = 22nF
2
ISL28177
13
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7859.2
April 5, 2012
For additional products, see www.intersil.com/product_tree
.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL28177
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/sear
FIGURE 36. SIMULATED (SPICE) CMRR FIGURE 37. SIMULATED OUTPUT VOLTAGE SWING ±15V
Characterization vs Simulation Results (Continued)
0.01 0.1 1.0 10 100 1k 10k 100k 1M 10M 100M 1G
0
40
80
120
160
200
CMRR (dB)
FREQUENCY (Hz)
-15
-10
-5
0
5
10
15
00.2 0.4 0.6 0.8 1.0
TIME (ms)
13.79V
-13.8V
VOLTAGE (V)
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE REVISION CHANGE
March 29, 2012 FN7859.2 Changed Note 1 in “Ordering Information” on page 2 from:
“Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.”
to:
“Please refer to TB347 for details on reel specifications.”
Listed out tape and reel parts individually in “Ordering Information” on page 2 (ISL28177FBZ-T13,
ISL28177FBZ-T7, ISL28177FBZ-T7A)
January 5, 2012 FN7859.1 Added SPICE model to data sheet.
Added ESD Ratings to description on page 1.
October 31, 2011 FN7859.0 Initial Release
ISL28177
14 FN7859.2
April 5, 2012
Package Outline Drawing (M8.15E)
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
Unless otherwise specified, tolerance : Decimal ± 0.05
The pin #1 identifier may be either a mold or mark feature.
Interlead flash or protrusions shall not exceed 0.25mm per side.
Dimension does not include interlead flash or protrusions.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "A"
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
A
B
4
4
0.25 AMC B
C
0.10 C
5
ID MARK
PIN NO.1
(0.35) x 45°
SEATING PLANE
GAUGE PLANE
0.25
(5.40)
(1.50)
4.90 ± 0.10
3.90 ± 0.10
1.27 0.43 ± 0.076
0.63 ±0.23
4° ± 4°
DETAIL "A" 0.22 ± 0.03
0.175 ± 0.075
1.45 ± 0.1
1.75 MAX
(1.27) (0.60)
6.0 ± 0.20
Reference to JEDEC MS-012.
6.
SIDE VIEW “B”
ISL28177
15 FN7859.2
April 5, 2012
Package Outline Drawing
P5.064A
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
Dimension is exclusive of mold flash, protrusions or gate burrs.
This dimension is measured at Datum “H”.
Package conforms to JEDEC MO-178AA.
Foot length is measured at reference to gauge plane.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
6.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
INDEX AREA
PIN 1
SEATING PLANE
GAUGE
0.45±0.1
(2 PLCS)
10° TYP
4
1.90
0.40 ±0.05
2.90
0.95
1.60
2.80
0.05-0.15
1.14 ±0.15
0.20 CA-B DM
(1.20)
(0.60)
(0.95)
(2.40)
0.10 C
0.08-0.20
SEE DETAIL X
1.45 MAX
(0.60)
0-3°
C
B
A
D
3
3
3
0.20 C
(1.90)
2x
0.15 C
2x
D
0.15 C
2x
A-B
(0.25)
H
5
2
4
5
5
END VIEW
PLANE
