ECP5TM Evaluation Board User Guide FPGA-EB-02017-1.0 July 2018 ECP5TM Evaluation Board User Guide Contents Acronyms in This Document .................................................................................................................................................5 1. Introduction ..................................................................................................................................................................6 1.1. ECP5 Evaluation Board ........................................................................................................................................6 1.2. Features ...............................................................................................................................................................8 1.3. ECP5 Device .........................................................................................................................................................8 2. Applying Power to the Board ........................................................................................................................................9 3. Programming and I2C ..................................................................................................................................................10 3.1. JTAG Download Interface ..................................................................................................................................10 3.2. Alternate JTAG Download Interface ..................................................................................................................10 3.3. JTAG to MSPI Pass-through Interface ................................................................................................................11 3.4. Other JTAG Configuration Pins ..........................................................................................................................11 3.5. Configuration Modes.........................................................................................................................................11 4. ECP5 Clock Sources .....................................................................................................................................................12 5. Headers and Test Connections ...................................................................................................................................13 5.1. Versa Headers ...................................................................................................................................................13 5.2. Arduino Board GPIO Headers ............................................................................................................................15 5.3. Raspberry Pi Board GPIO Header ......................................................................................................................17 5.4. GPIO Headers ....................................................................................................................................................18 5.5. Microphone Expansion Header .........................................................................................................................21 5.6. PMOD Header ...................................................................................................................................................21 5.7. JTAG Header ......................................................................................................................................................22 5.8. Parallel Configuration Header ...........................................................................................................................22 6. Control Buses - I2C, I3C, UART, and SPI........................................................................................................................23 6.1. I2C and I3C Topology ..........................................................................................................................................23 6.2. UART Topology ..................................................................................................................................................24 6.3. SPI Topology ......................................................................................................................................................24 6.3.1. SPI Configuration ..........................................................................................................................................24 6.3.2. SPI Flash Access .............................................................................................................................................25 7. LEDs and Switches ......................................................................................................................................................26 7.1. DIP Switch..........................................................................................................................................................26 7.2. Configuration Mode Switch...............................................................................................................................26 7.3. General Purpose Push Buttons..........................................................................................................................26 7.4. General Purpose LEDs .......................................................................................................................................27 7.5. Indicator LEDs ....................................................................................................................................................27 8. Software Requirements ..............................................................................................................................................28 9. Storage and Handling..................................................................................................................................................28 10. Ordering Information ..............................................................................................................................................28 References ..........................................................................................................................................................................29 Lattice Semiconductor Documents .................................................................................................................................29 Technical Support Assistance...............................................................................................................................................30 Appendix A. ECP5 Evaluation Board Schematics ................................................................................................................31 Appendix B. ECP5 Evaluation Board Bill of Materials .........................................................................................................43 Revision History ...................................................................................................................................................................49 (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide Figures Figure 1.1. Top View of ECP5 Evaluation Board.................................................................................................................... 6 Figure 1.2. Bottom View of ECP5 Evaluation Board ............................................................................................................. 7 Figure 1.3. Top View of ECP5 Evaluation Board - Jumper Locations.................................................................................... 7 Figure 2.1. Board Power Supply............................................................................................................................................ 9 Figure 3.1. Configuration and I2C Architecture ................................................................................................................... 10 Figure 6.1. I2C Architecture, I3C, and UART Options ........................................................................................................... 24 Figure 6.2. SPI Interface ...................................................................................................................................................... 25 Figure A. 1. Title Page ......................................................................................................................................................... 31 Figure A. 2. Block Diagram .................................................................................................................................................. 32 Figure A. 3. USB Interface ................................................................................................................................................... 33 Figure A. 4 Arduino Header (BANK2) .................................................................................................................................. 34 Figure A. 5. Raspberry Pi Header (BANK3) .......................................................................................................................... 35 Figure A. 6. SERDES SMA .................................................................................................................................................... 36 Figure A. 7. IO Breakout (BANK0, BANK1, BANK6) ............................................................................................................. 37 Figure A. 8. IO Breakout (BANK7, Differential Pairs) .......................................................................................................... 38 Figure A. 9. Configuration ................................................................................................................................................... 39 Figure A. 10. Power Decoupling and LEDs .......................................................................................................................... 40 Figure A. 11.Power Hookup ................................................................................................................................................ 41 Figure A. 12. Power Regulators .......................................................................................................................................... 42 Tables Table 2.1. ECP5 VCCIO Supply Options ................................................................................................................................. 9 Table 3.1. JTAG Connections .............................................................................................................................................. 10 Table 3.2. Other JTAG Signals ............................................................................................................................................. 11 Table 3.3. CFGMDN Mode Settings .................................................................................................................................... 11 Table 4.1. Clock Sources ..................................................................................................................................................... 12 Table 5.1. Versa J39 Header Pin Connections..................................................................................................................... 13 Table 5.2. Versa J40 Header Pin Connections..................................................................................................................... 14 Table 5.3. Arduino J6 Pin Connections ............................................................................................................................... 15 Table 5.4. Arduino J3 Pin Connections ............................................................................................................................... 15 Table 5.5. Arduino J7 Pin Connections ............................................................................................................................... 16 Table 5.6. Arduino J4 Pin Connections ............................................................................................................................... 16 Table 5.7. Raspberry Pi JP8 Header Pin Connections ......................................................................................................... 17 Table 5.8. J5 Header Pin Connections................................................................................................................................. 18 Table 5.9. J8 Header Pin Connections................................................................................................................................. 19 Table 5.10. J32 Header Pin Connections ............................................................................................................................ 19 Table 5.11. J33 Header Pin Connections ............................................................................................................................ 20 Table 5.12. J30 Header Pin Connections ............................................................................................................................ 21 Table 5.13. J31 Header Pin Connections ............................................................................................................................ 21 Table 5.14. J1 Header Pin Connections............................................................................................................................... 22 Table 5.15. J38 Header Pin Connections ............................................................................................................................ 22 Table 6.1. I2C Global Bus Connections ................................................................................................................................ 23 Table 6.2. ECP5 SPI Connections......................................................................................................................................... 25 Table 7.1. Eight-Position DIP Switch Signals ....................................................................................................................... 26 Table 7.2. CFGMDN Switch Signals ..................................................................................................................................... 26 Table 7.3. Push Button Switch Signals ................................................................................................................................ 26 Table 7.4. General Purpose LED Signals.............................................................................................................................. 27 (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 3 ECP5TM Evaluation Board User Guide Table 7.5. Various LED Signals ............................................................................................................................................27 Table 10.1. Ordering Information .......................................................................................................................................28 (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 4 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide Acronyms in This Document A list of acronyms used in this document. Acronym Definition ASC Analog Sense and Control caBGA Chip Array Ball Grid Array CMOS Complementary Metal-Oxide Semiconductor DIP Dual Inline Package DNI Do Not Install ESD Electro Static Discharge FPGA Field Programmable Logic Array FTDI Future Technology Devices International GDDR Graphics Double Data Rate GPIO General Purpose Input/Output I2C Inter-Integrated Circuit I3C Improved Inter-Integrated Circuit JTAG Joint Test Action Group LVDS Low-Voltage Differential Signaling MDP Mobile Development Platform PMOD Peripheral Module SCM Serial Configuration Mode SPCM Slave Parallel Configuration Mode SPI Serial Peripheral Interface UART Universal Asynchronous Receiver Transmitter USB Universal Serial Bus (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 5 ECP5TM Evaluation Board User Guide 1. Introduction The Lattice Semiconductor ECP5TM Evaluation Board allows designers to investigate and experiment with the features of the ECP5-5G Field Programmable Gate Array (FPGA). The features of the ECP5 Evaluation Board can assist engineers with the rapid prototyping and testing of their specific designs. The ECP5 Evaluation Board is part of the ECP5 Evaluation Kit, which includes the following: ECP5 Evaluation Board pre-loaded with the demo design Mini USB cable Quick Start Guide The contents of this user guide include top-level functional descriptions of the various portions of the development board, descriptions of the on-board headers, diodes and switches and a complete set of schematics. 1.1. ECP5 Evaluation Board The ECP5 Evaluation Board features the ECP5-5G FPGA in the 381-ball caBGA package (LFE5UM5G-85F-8BG381) and the ability to expand the usability of the ECP5 with Arduino, Raspberry Pi, PMOD, MCD, and Versa headers, along with access to all SERDES channels. Over 170 I/Os and 20 differential pairs are available for user-defined applications. Figure 1.1 shows the top view of the ECP5 Evaluation Board. Figure 1.2 shows the bottom view of the board. Figure 1.3 shows the jumper locations. SERDES Test SMA Connectors (J9-J26) Parallel Config Header (J38) Versa Expansion Connectors (J39, J40) SPI Flash Configuration Memory (U4) mini USB Programming (J2) JTAG Interface (J1) CFG Switches (SW1) Input Switches (SW5) ECP5-5G Device (U3) GPIO Headers (J5, J8) Output LEDs (D5-D12) Input Push Buttons (SW2, SW3, SW4) Prototype Area Microphone Board/ GPIO Header (J30) PMOD/GPIO Header (J31) GPIO Headers (J32, J33) 12 V DC Power Input (J37) Figure 1.1. Top View of ECP5 Evaluation Board (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 6 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide Raspberry Pi Header (JP8) FTDI Interface Chip (U1) Arduino Header (J3, J4, J6, J7) Figure 1.2. Bottom View of ECP5 Evaluation Board FTDI Reset (JP1) FTDI Osc Connect (JP2) SERDES Osc Reset (JP9) Arduino Supplies (JP3, JP4, JP5) Raspberry Pi Supplies (JP6, JP7) VCCIO0 Supply VCCIO7 Supply Flash Chip Selection Selection Selection (JP18) (JP10) (JP11) Figure 1.3. Top View of ECP5 Evaluation Board - Jumper Locations (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 7 ECP5TM Evaluation Board User Guide 1.2. Features ECP5-5G FPGA (LFE5UM5G-85F-8BG381) General Purpose Input/Output (GPIO) breakout with Arduino, Raspberry Pi, Versa, PMOD, and MDC board interconnect 178 General purpose I/Os, 20 differential pair I/Os with on board termination, 4 5G SERDES channels USB-B connection for device programming and Inter-Integrated Circuit (I2C) utility and ability to support Improved Inter-Integrated Circuit (I3C) On-board Boot Flash - 128 Mbit Serial Peripheral Interface (SPI) Flash, with Quad read feature 8 input DIP switches, 3 push buttons and 8 LEDs for demo purposes Lattice Diamond(R) programming support Multiple reference clock sources Caution: The ECP5 Evaluation Board contains ESD-sensitive components. ESD safe practices should be followed while handling and using the development board. 1.3. ECP5 Device The ECP5 Evaluation Board features the ECP5-5G in a 381-ball caBGA package. This ECP5-5G device, also referred to as LFE5UM5G-85F-8BG381, features 84,000 LUTs and 3744 kbits of embedded block RAM. This device offers a variety of features and programmability. For more information on the capabilities of ECP5TM, see ECP5 and ECP5-5G Family Data Sheet (FPGA-DS-02012). (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 8 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide 2. Applying Power to the Board The ECP5 Evaluation Board has most of its power supplied by onboard regulators powered by an external 12 V power. In addition, the USB connection supplies 5 V to some components, and off board supplies can be used to supply the Raspberry Pi and Arduino headers. Jumpers or resistor installation/removal can be used to achieve several different power supply configurations. Refer to Appendix A. ECP5 Evaluation Board Schematics to see the details of these power supply options. Figure 2.1 shows the high-level power supply architecture of the board. Table 2.1 shows the voltage options available for the various VCCIO supplies. VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO6 (See Table VCCIO7 VCCIO8 2.1) Jumpers and Resistors VCC_CORE (+1.2v) 12V In (J37) ECP5 (U3) +1.5V Regulator +2.5V (U7, U8) +3.3V Versa Header (J39, J40) VCCHTX0 VCCHTX1 Regulator VCCA_SERDES0 (U5, U6) VCCA_SERDES1 VCCA0 VCCA1 ECP5 SERDES +12.0V FTDI (U1) +3.3V_RASP Rasp berry Pi Header (JP8) Ard uino Header (J3, J4, J6, J7) +3.3V_AR USB 5V In (J2) VBUS_5V Figure 2.1. Board Power Supply Table 2.1. ECP5 VCCIO Supply Options VCCIO Bank Selection +3.3V +2.5V +3.3V_AR +3.3V_RASP +1.5V VCC_CORE(+1.2V) VCCIO0 Jumper (JP 10) Default Selectable N/A N/A Selectable Selectable VCCIO1 Resistors Selectable Default N/A N/A N/A N/A VCCIO2 Resistors Default Selectable Selectable N/A N/A N/A VCCIO3 Resistors Default Selectable N/A Selectable N/A N/A VCCIO6 Resistors Default Selectable N/A N/A N/A N/A VCCIO7 Jumper (JP 11) Default Selectable N/A N/A Selectable Selectable VCCIO8 Resistors Default Selectable N/A N/A N/A N/A Warning: Only one option should be enabled for each ECP5 device I/O Bank. The implementation of these options can be found in Figure A. 11. (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 9 ECP5TM Evaluation Board User Guide 3. Programming and I2C The JTAG/SPI programming architecture and I2C interface of the ECP5 Evaluation Board is shown in Figure 3.1. Figure 3.1. Configuration and I2C Architecture 3.1. JTAG Download Interface The ECP5 Evaluation Board has a built-in download controller for programming the ECP5-5G device. It uses an FT2232H Future Technology Devices International (FTDI) part to convert USB to JTAG. To use the built-in download cable, connect the USB cable from the mini USB to your PC, that is, with Diamond programming software installed. A mini USB to USB-A cable is included in the ECP5 Evaluation Kit. The USB hub on the PC detects the cable of the USB function on Port 0, making the built-in cable available for use with the Diamond programming software. 3.2. Alternate JTAG Download Interface J1 is an 8-pin standalone JTAG header used with an external Lattice download cable that is available separately, when the FTDI part is disabled from the JTAG chain after setting the JP1 jumper. A USB download cable can be attached to the board using J1 to interface with the ECP5-5G. For details on the connection between the USB download cable and J1, refer to Programming Cable User's Guide (FPGA-UG-02042). J1 can also be used as test point when USB to JTAG is working. Additionally, you can enable the JTAG access path through the Raspberry Pi header (JP8) for customer applications. This is done by connecting the JP8 header to the J1 header through some onboard resistors. The JTAG connections between J1 and JP8 are listed in Table 3.1. Table 3.1. JTAG Connections J1 Pin Number JTAG Signal Name ECP5-5G Ball Location for JTAG Raspberry Pi Header (JP8) Pin Number J1 to JP8 Isolation (Assembly) Raspberry Pi GPIO 1 VCCIO8 -- -- -- -- 2 TDO V4 10 R39 (DNI) IO15 3 TDI R5 11 R40 (DNI) IO17 4 -- -- -- -- -- 5 -- -- -- -- -- 6 TMS U5 12 R41 (DNI) IO18 7 GND -- -- -- -- 8 TCK T5 8 R38 (DNI) IO14 (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 10 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide 3.3. JTAG to MSPI Pass-through Interface The download controller can also access the JTAG to MSPI pass-through circuit that allows the slave SPI Flash to be erased, programmed, and read with Diamond Programmer. 3.4. Other JTAG Configuration Pins The ECP5 Evaluation Board provides test points for other JTAG configuration pins as shown in Table 3.2. Table 3.2. Other JTAG Signals Signal Name ECP5-5G Ball Location Test Point PROGRAMN W3 TP21 INITN V3 TP20 DONE Y3 TP22 For more information on ECP5 JTAG and SPI programming, refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGATN-02039). 3.5. Configuration Modes The ECP5 can be configured in Master SPI, Slave SPI, SCM, JTAG, and SPCM modes. These modes can be selected using the CFGMDN switches provided on the board (detailed in the DIP Switch section and ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039). Table 3.3 below details the CFGMDN settings that are used to select individual configuration modes. Table 3.3. CFGMDN Mode Settings Configuration Mode SSPI MSPI Bus Size Options Clock CFGMDN2 CFGMDN1 CFGMDN0 1 -- CCLK 0 0 1 1 Serial (SPI_Serial 2 Dual (SPI_Dual) 4 Quad (SPI_Quad) MCLK 0 1 0 1, 2, 4 Dual-Boot 1, 2, 4 Multi-Boot SCM (Slave_Serial) 1 -- CCLK 1 0 1 SPCM (Slave_Parallel) 8 -- CCLK 1 1 1 (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 11 ECP5TM Evaluation Board User Guide 4. ECP5 Clock Sources The ECP5 Evaluation Board has three options for the ECP5-5G clock sources: 12 MHz from U1 FTDI Chip 200 MHz SERDES clock from X2 Differential Oscillator. For different user applications, the X2 footprint accepts commonly-available devices of different frequencies. X5 oscillator for LVDS source sync clock. X5 is not populated by default. For convenience, a 50 MHz device is specified in the ECP5 Evaluation Board Bill of Materials section, Item 127. Other frequency devices may be mounted as desired. The 12 MHz clock from the FT2232H FTDI device requires JP2 to be installed to connect the 12 MHz clock signal to the ECP5 device I/O. JP1 should not be installed to enable U1. Table 4.1. Clock Sources Clock Frequency Signal Name ECP5 Ball Location Clock Source Comments 12 MHz 12 MHz A10 U1 JP2 installed. JP1 removed. 200 MHz 200 MHz/200 MHz_n Y19/ W20 X2 JP9 added to disable. 50 MHz 50 MHz_OSC B11 X5 (DNI) 50 MHz_OSC_EN (C11) to enable/disable. (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 12 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide 5. Headers and Test Connections This section describes the ECP5 Evaluation Board headers and test connections. 5.1. Versa Headers The board provides two headers - J39 and J40 which can be used for expansion or as general purpose I/O connections. Table 5.1. Versa J39 Header Pin Connections J39 Pin Number Signal Name ECP5-5G-85 Ball 1 GND -- 2 NC -- 3 EXPCON_2V5* -- 4 D15 D15 5 B15 B15 6 C15 C15 7 B13 B13 8 B20 B20 9 D11 D11 10 E11 E11 11 B12 B12 12 C12 C12 13 D12 D12 14 E12 E12 15 C13 C13 16 D13 D13 17 E13 E13 18 A14 A14 19 A9 A9 20 B10 B10 21 5VIN -- 22 GND -- 23 EXPCON_2V5* -- 24 GND -- 25 +3.3V -- 26 GND -- 27 +3.3V -- 28 GND -- 29 E7 -- 30 GND -- 31 A11 A11 32 GND -- 33 A19 A19 34 GND -- 35 EXPCON_3V3* -- (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 13 ECP5TM Evaluation Board User Guide J39 Pin Number Signal Name ECP5-5G-85 Ball 36 GND -- 37 EXPCON_3V3* -- 38 GND -- 39 EXPCON_3V3* -- 40 GND -- *Note: Signal is connected to power source through removable resistor. Table 5.2. Versa J40 Header Pin Connections J40 Pin Number Signal Name ECP5-5G-85 Ball 1 K2 K2 2 GND -- 3 A15 A15 4 F1 F1 5 H2 H2 6 G1 G1 7 J4 J4 8 J5 J5 9 J3 J3 10 K3 K3 11 L4 L4 12 L5 L5 13 M4 M4 14 N5 N5 15 N4 N4 16 P5 P5 17 N3 N3 18 M3 M3 19 GND -- 20 EXPCON_3V3* -- 21 K5 K5 22 GND -- 23 M5 M5 24 GND -- 25 L3 L3 26 GND -- 27 N2 N2 28 M1 M1 29 L2 L2 30 GND -- 31 L1 L1 32 N1 N1 33 C14 C14 (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 14 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide J40 Pin Number Signal Name ECP5-5G-85 Ball 34 GND -- 35 P1 P1 36 E14 E14 37 D14 D14 38 CARDSEL#* -- 39 K4 K4 40 GND -- *Note: Signal is connected to power source through removable resistor. 5.2. Arduino Board GPIO Headers The board provides four headers - J3, J4, J6 and J7 for Arduino Zero board adaption or as general purpose I/O connections. Table 5.3. Arduino J6 Pin Connections J6 Pin Number Signal Name Arduino ZERO Board Signal ECP5-5G-85 Ball 1 AR_IO8 ~8 K16 -- 2 AR_IO9 ~9 J16 -- 3 AR_SS_IO10 ~10 H17 -- 4 AR_MOSI_IO11 ~11 J17 -- 5 AR_MISO_IO12 ~12 H18 -- 6 AR_SCK_IO13 ~13 H16 -- 7 GND GND -- -- 8 AR_AREF AREF G18 AR_AREF connection to AREF through R27, DNI by default. 9 AR_SDA SDA G16 Optional connection to SDA0 through R26, DNI by default. 10 AR_SCL SCL F17 Optional connection to SCL0 through R25, DNI by default. Comments Table 5.4. Arduino J3 Pin Connections J3 Pin Number Signal Name Arduino ZERO Board Signal ECP5-5G-85 Ball 1 AR_IO0 RX <- 0 F19 -- 2 AR_IO1 TX -> 1 F20 -- 3 AR_IO2 2 E20 -- 4 AR_IO3 ~3 E19 -- 5 AR_IO4 ~4 D19 -- 6 AR_IO5 ~5 D20 -- 7 AR_IO6 ~6 C20 -- 8 AR_IO7 7 K17 -- Comments (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 15 ECP5TM Evaluation Board User Guide Table 5.5. Arduino J7 Pin Connections J7 Pin Number Signal Name Arduino ZERO Board Signal ECP5-5G-85 Ball 1 AR_IO14 ATN C18 -- 2 NC IOREF -- -- 3 AR_RESET RESET D17 Pin D17 should be set high by default. Avoid Arduino ZERO board in Reset status when connected. 4 +3.3V_AR 3.3 V -- Jumper to 3.3 V power supply from Arduino ZERO board 5 VBUS_5V 5V -- Jumper to 5 V USB power 6 GND GND -- -- 7 GND GND -- -- 8 +12.0V VIN -- Jumper to +12.0V power supply from Arduino ZERO board Comments Table 5.6. Arduino J4 Pin Connections J4 Pin Number Signal Name Arduino ZERO Board Signal ECP5-5G-85 Ball 1 AR_AD0 A0 F18 Used as GPIO in digital mode 2 AR_AD1 A1 E17 Used as GPIO in digital mode 3 AR_AD2 A2 E18 Used as GPIO in digital mode 4 AR_AD3 A3 D18 Used as GPIO in digital mode 5 AR_AD4 A4 F16 Used as GPIO in digital mode 6 AR_AD5 A5 E16 Used as GPIO in digital mode Comments Note: For Table 5.3, Table 5.4, Table 5.5, and Table 5.6, if jumper to VBUS_5V is installed, 5 V power can be supplied from either the Arduino board or the ECP5 Evaluation Board. With jumper removed, both boards need their own 5 V power. (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 16 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide 5.3. Raspberry Pi Board GPIO Header The ECP5 Evaluation Board provides a 40-pin receptacle which is compatible with the GPIO header of Raspberry Pi 2/3 serial models, or can be used for general purpose I/Os. Table 5.7. Raspberry Pi JP8 Header Pin Connections JP8 Pin Number Signal Name 1 ECP5-5G-85 Ball 1 +3.3V_RASP 2 RASP_5V 2 -- 3 RASP_IO02 T17 4 RASP_5V 2 -- 5 RASP_IO03 U16 6 GND -- 7 RASP_IO04 U17 8 RASP_IO14 P18 9 GND -- 10 RASP_IO15 N20 11 RASP_IO17 N19 12 RASP_IO18 T16 13 RASP_IO27 M18 14 GND -- 15 RASP_IO22 N17 16 RASP_IO23 P17 -- 1 17 3.3V_RASP -- 18 RASP_IO24 M17 19 RASP_IO10 U20 20 GND -- 21 RASP_IO09 T19 22 RASP_IO25 N18 23 RASP_IO11 R20 24 RASP_IO08 U19 25 GND -- 26 RASP_IO07 R18 27 RASP_ID_SD L18 28 RASP_ID_SC L17 29 RASP_IO05 U18 30 GND -- 31 RASP_IO06 T18 32 RASP_IO12 T20 33 RASP_IO13 P20 34 GND -- 35 RASP_IO19 R17 36 RASP_IO16 P19 37 RASP_IO26 N16 38 RASP_IO20 P16 (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 17 ECP5TM Evaluation Board User Guide JP8 Pin Number Signal Name ECP5-5G-85 Ball 39 GND -- 40 RASP_IO21 R16 Notes: 1. 3.3 V power is supplied from Raspberry Pi board. 2. 5 V power can come from either the Raspberry Pi board or the ECP Evaluation Board (via USB) when jumper JP7 is installed. When jumper JP7 is not installed, both boards need their own 5 V power. 5.4. GPIO Headers There are two types of general purpose I/O headers: simple general purpose headers, and differential general purpose headers. The differential headers have associated termination resistors for each differential I/O pair. Table 5.8. J5 Header Pin Connections J5 Pin Number Signal Name ECP5-5G-85 Ball Differential Pair 1 VCCIO2 -- -- 2 VCCIO2 -- -- 3 H20 H20 H20/G19 4 G19 G19 H20/G19 5 GND -- -- 6 GND -- -- 7 K18 K18 K18/J18 8 J18 J18 K18/J18 9 GND -- -- 10 GND -- -- 11 K19 K19 K19/J19 12 J19 J19 K19/J19 13 GND -- -- 14 GND -- -- 15 K20 K20 K20/J20 16 J20 J20 K20/J20 17 GND -- -- 18 GND -- -- 19 G20 G20 -- 20 GND -- -- 21 GND -- -- 22 GND -- -- (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 18 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide Table 5.9. J8 Header Pin Connections J8 Pin Number Signal Name ECP5-5G-85 Ball 1 VCCIO3 -- 2 VCCIO3 -- 3 L19 L19 4 M19 M19 5 L20 L20 6 M20 M20 7 L16 L16 8 GND -- Table 5.10. J32 Header Pin Connections J32 Pin Number Signal Name ECP5-5G-85 Ball Differential Pair 1 NC -- -- 2 VCCIO7 -- -- 3 GND -- -- 4 GND -- -- 5 A5 A5 A5/A4 6 A4 A4 A5/A4 7 GND -- -- 8 GND -- -- 9 C5 C5 C5/B5 10 B5 B5 C5/B5 11 GND -- -- 12 GND -- -- 13 B4 B4 B4/C4 14 C4 C4 B4/C4 15 GND -- -- 16 GND -- -- 17 B3 B3 B3/A3 18 A3 A3 B3/A3 19 GND -- -- 20 GND -- -- 21 D5 D5 D5/E4 22 E4 E4 D5/E4 23 GND -- -- 24 GND -- -- 25 D3 D3 D3/C3 26 C3 C3 D3/C3 27 GND -- -- 28 GND -- -- 29 E3 E3 E3/F4 30 F4 F4 E3/F4 (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 19 ECP5TM Evaluation Board User Guide J32 Pin Number Signal Name ECP5-5G-85 Ball Differential Pair 31 GND -- -- 32 GND -- -- 33 F5 F5 F5/E5 34 E5 E5 F5/E5 35 GND -- -- 36 GND -- -- 37 B1 B1 B1/A2 38 A2 A2 B1/A2 39 GND -- -- 40 GND -- -- J33 Pin Number Signal Name ECP5-5G-85 Ball Differential Pair 1 NC -- -- 2 VCCIO7 -- -- 3 GND -- -- 4 GND -- -- 5 C2 C2 C2/B2 6 B2 B2 C2/B2 7 GND -- -- 8 GND -- -- 9 D1 D1 D1/C1 10 C1 C1 D1/C1 11 GND -- -- 12 GND -- -- 13 E1 E1 E1/D2 14 D2 D2 E1/D2 15 GND -- -- 16 GND -- -- 17 G5 G5 G5/H4 18 H4 H4 G5/H4 19 GND -- -- 20 GND -- -- 21 H3 H3 H3/H5 22 H5 H5 H3/H5 23 GND -- -- 24 GND -- -- 25 F3 F3 F3/G3 26 G3 G3 F3/G3 27 GND -- -- 28 GND -- -- 29 E2 E2 E2/F2 Table 5.11. J33 Header Pin Connections (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 20 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide J33 Pin Number Signal Name ECP5-5G-85 Ball Differential Pair 30 F2 F2 E2/F2 31 GND -- -- 32 GND -- -- 5.5. Microphone Expansion Header The J30 header can be used as GPIO, or can mate to the 8:1 Microphone Aggregator Board. It is placed with a nonconnected header in close proximity to allow the physical pairing of the boards. Table 5.12. J30 Header Pin Connections J30 Pin Number Signal Name ECP5-5G-85 Ball 1 VCCIO0 -- 2 I2S_SD_mic1_mic2_card_B6 B6 3 I2S_SCK_mic_D9 D9 4 I2S_SD_mic3_mic4_C9 C9 5 I2S_WS_mic_E9 E9 6 I2S_SD_mic5_mic6_D10 D10 7 GPIO_amp_A6 A6 8 I2S_SD_mic7_E10 E10 9 GND -- 10 GND -- 5.6. PMOD Header The J31 header can be used as GPIO or as a connector to a PMOD interface. Table 5.13. J31 Header Pin Connections J31 Pin Number Signal Name ECP5-5G-85 Ball 1 C6 C6 2 C7 C7 3 E8 E8 4 D8 D8 5 GND -- 6 VCCIO0 -- 7 C8 C8 8 B8 B8 9 A7 A7 10 A8 A8 11 GND -- 12 VCCIO0 -- (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 21 ECP5TM Evaluation Board User Guide 5.7. JTAG Header The J1 header is used to access the JTAG port of the ECP5 or the Raspberry Pi interface. Table 5.14. J1 Header Pin Connections J1 Pin Number Signal Name ECP5-5G-85 Ball 1 VCCIO8 -- 2 TDO V4 3 TDI R5 4 NC -- 5 NC -- 6 TMS U5 7 GND -- 8 TCK T5 5.8. Parallel Configuration Header The J38 header is used to access the SPI port of the ECP5 or the Raspberry Pi interface. Table 5.15. J38 Header Pin Connections J38 Pin Number Signal Name ECP5-5G-85 Ball 1 PROGRAMN W3 2 FLASH_CS R2 (with jumper) 3 WRITEN T3 4 DONE Y3 5 DQ7 R1 6 INITN V3 7 DQ6 T1 8 DQ1_MISO V2 9 DQ5_MISO2 U1 10 DQ0_MOSI W2 11 DQ4_MOSI2 V1 12 CSN T2 13 DQ3 W1 14 CS1N U2 15 DQ2 Y2 16 BUSY_CSSPIN R2 17 CCLK_MCLK_SCK U3 18 DOUT_CSON R3 19 GND -- 20 VCCIO8 -- (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 22 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide 6. Control Buses - I2C, I3C, UART, and SPI This section describes the topology of the various configuration and communication buses. 6.1. I2C and I3C Topology The ECP5 Evaluation Board uses the I2C bus to support ECP5 configuration, and optionally to support Arduino and Raspberry Pi communication. The global I2C bus has the signal names SDA0 and SCL0 and they are routed close to the devices and headers as shown in Figure 3.1 and in more detail in Figure 6.1. To support the Arduino and Raspberry Pi, each header or device is connected to a dedicated ECP5 GPIO bank with a direct local I2C bus. Each local I2C bus can optionally connect to the global I2C bus through resistors. The local I2C connections are summarized in Table 6.1. Table 6.1. I2C Global Bus Connections ECP5 Bank Component (Reference) 2 Arduino header (J6) 3 Raspberry Pi header (JP8) Header Pin ECP5-5G-85 Ball Local Signal Name (Global I2C Signal) Resistor 9 G16 AR_SDA (SDA0) R26 (DNI) 10 F17 AR_SCL (SCL0) R25 (DNI) 27 L18 RASP_ID_SD (SDA0) R33 (DNI) 28 L17 RASP_ID_SC (SCL0) R32 (DNI) The board also has the option to switch to an I3C interface by removing the installed 2.2 k I2C pull-up resistors (R18 and R19) and installing I3C resistors (R52 at 2.2 k, R53 at 100 k, or R54 at 100 k) as shown in Figure 6.1. (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 23 ECP5TM Evaluation Board User Guide BDBUS1/2 SDA0 AR_SCL rst (U1) FTDI 2232H BDBUS0 rst (U3) Bank2 SCL0 AR_SDA Instantiated I 2C Resistors (R18, R19) RASP_ID_SD rst (U3) Bank3 RASP_ID_SC TXD_UART Bank6 rst (U3) RXD_UART SDA0_WPU Bank0 (U3) SDA0_SPU rst SDA0 SCL0_WPU SCL0 Uninstantiated I3C Resistors (R52, R53, R54) Figure 6.1. I2C Architecture, I3C, and UART Options 6.2. UART Topology The board provides support for UART configuration by providing an uninstalled connection between the FTDI and ECP5. Two 0 resistors (R34 and R35) can be installed to connect Port 1 to two general purpose I/Os (PL92A/P2 and PL92C/P3) in Bank 6 as shown in Figure 6.1. 6.3. SPI Topology 6.3.1. SPI Configuration One of the major functions of SPI connections on the board is to support ECP5 configuration from the SPI Flash or the Parallel Configuration Header. The ECP5 Evaluation Board can support both Master SPI (MSPI) and Slave SPI (SSPI) modes for ECP5 configuration. Figure 6.2 from the schematics show the connections between the header, Flash chip, and FPGA. (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 24 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide Table 6.2. ECP5 SPI Connections ECP5-5G-85 Ball Parallel Configuration Header Pin MSPI Mode Direction SSPI Mode Direction CCLK_MCLK_SCK U3 17 Output Input DQ0_MOSI W2 10 Output Input DQ1_MISO V2 8 Input Output BUSY_CSSPIN R2 16 Output Not used DQ2 Y2 15 Input Not used DQ3 W1 13 Input Not used Signal Name 6.3.2. SPI Flash Access Onboard SPI Flash memory can be used to store the ECP5 configuration data in either External or Dual Boot mode. It can also store customer data in certain applications. The ECP5 device includes the JTAG to MSPI pass-through circuit that allows the slave SPI Flash to be erased, programmed, and read with Diamond Programmer. For detailed information on JTAG to MSPI pass-through for slave SPI Flash access, refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039). BUSY_CSSPIN Jumper JP18 ECP5 (U3) FLASH_CS DQ1_MISO DQ2 DQ3 MCLK DQ0_MOSI Quad SPI Flash (U4) Parallel Config Header (J38) CSN CS1N WRITEN DQ7 DQ6 DQ5 DQ4 DOUT_CSON INITN PROGRAMN DONE Note: See schematics for complete INITN, PROGRAMN, and DONE connections. Figure 6.2. SPI Interface (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 25 ECP5TM Evaluation Board User Guide 7. LEDs and Switches This section describes the ECP5 Evaluation Board LEDs and switches that can be used in demo and customer designs. 7.1. DIP Switch Eight ECP5 pins are connected to the SW5 DIP switch to allow for manually actuated inputs to the FPGA. One side of each switch is connected to GPIOs within the VCCIO6 and VCCIO1 bank and pulled up through 4.7 k resistors. The other side is grounded. The designated pins are connected as shown in Table 7.1. Table 7.1. Eight-Position DIP Switch Signals Signal Name ECP5-5G-85 Ball ECP5-5G-85 Bank SW5 DIP Switch Position SWITCH1 J1 6 1 SWITCH2 H1 6 2 SWITCH3 K1 6 3 SWITCH4 E15 1 4 SWITCH5 D16 1 5 SWITCH6 B16 1 6 SWITCH7 C16 1 7 SWITCH8 A16 1 8 7.2. Configuration Mode Switch A DIP switch is provided to allow the selection of the configuration mode between SSPI, MSPI, SCM, and SPCM as specified in ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039). Table 7.2 lists the connectivity of this switch (SW1). Table 7.2. CFGMDN Switch Signals Signal Name Functional Name ECP5-5G-85 Ball ECP5-5G-85 Bank SW1 DIP Switch Position CFG0 CFGMDN0 U4 6 2 CFG1 CFGMDN1 T4 6 3 CFG2 CFGMDN2 R4 6 4 7.3. General Purpose Push Buttons The ECP5 Evaluation Board provides three push button switches - SW2, SW3 and SW4 for demos and user applications. Two of the buttons control pre-defined functional pins, and the third is generic. Pressing these buttons drives a logic level "0" to the corresponding I/O pins. Table 7.3. Push Button Switch Signals Signal Name ECP5-5G-85 Ball Push Button Reference Logic Level at Button Pressed GSRN G2 SW2 0 PROGRAMN W3 SW3 0 BUTTON_1 P4 SW4 0 SW3 is used as a PROGRAMN push button to trigger the configuration process without power cycle. For detailed information on PROGRAMN, refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039). SW2 is intended to be used as a global set/reset pin when active low, but can be substituted for another function if the user desires. SW3 can be used as a generic input. (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 26 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide 7.4. General Purpose LEDs The ECP5 Evaluation Board provides eight red LEDs that are connected to I/Os within Bank 1. The LEDs are lighted when the output is driven LOW. Table 7.4. General Purpose LED Signals Signal Name ECP5-5G-85 Ball ECP5-5G-85 Bank LED0 A13 1 LED1 A12 1 LED2 B19 1 LED3 A18 1 LED4 B18 1 LED5 C17 1 LED6 A17 1 LED7 B17 1 7.5. Indicator LEDs Table 7.5 lists various LEDs and describes their purpose. Table 7.5. Various LED Signals LEDs Signal Name ECP5-5G-85 Ball Color Purpose D1 UART_ACT P3 Green If installed, lights in UART mode D3 INITN V3 Red Lights if configuration error D4 DONE Y3 Green Lights if successful configuration D22 VCCA0 -- Green Lights if voltage present D23 +1.5V -- Green Lights if voltage present D24 +1.2V/VCC_CORE -- Green Lights if voltage present D25 +3.3V -- Green Lights if voltage present D26 +12.0V -- Blue Lights if voltage present (external connection) D31 +2.5V -- Green Lights if voltage present (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 27 ECP5TM Evaluation Board User Guide 8. Software Requirements The following software versions are required to develop designs for the ECP5 Evaluation Board: Diamond 3.10 Diamond Programmer 3.10 LatticeMico System Development Tools 9. Storage and Handling Static electricity can shorten the life span of electronic components. Observe these tips to prevent damage that can occur from electrostatic discharge: Use antistatic precautions such as operating on an antistatic mat and wearing an antistatic wristband. Store the development board in the provided packaging. Touch a metal USB housing to equalize voltage potential between you and the board. 10. Ordering Information Table 10.1. Ordering Information Description Ordering Part Number ECP5 Evaluation Board LFE5UM5G-85F-EVN China RoHS Environment-Friendly Use Period (EFUP) (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 28 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide References Lattice Semiconductor Documents Related documents available from your Lattice Semiconductor sales representative are listed on the table below. Document Title FPGA-UG-02042 FPGA-DS-02012 Programming Cables ECP5 and ECP5-5G Family Data Sheet FPGA-TN-02039 EB103 FPGA-EB-02004 ECP5 and ECP5-5G sysCONFIG Usage Guide ECP5-5G Versa Development Board User Guide MachXO3-9400 Development Board User Guide (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 29 ECP5TM Evaluation Board User Guide Technical Support Assistance Submit a technical support case through www.latticesemi.com/techsupport. (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 30 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide Appendix A. ECP5 Evaluation Board Schematics Figure A. 1. Title Page (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 31 ECP5TM Evaluation Board User Guide 5 4 3 2 1 D D Page 7 Page 9-10 Page 4 C C Page 7 Page 5 B B Page 3 A Page 9 Page 6 A Unless otherwise noted, blocks are on Page7 Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Phone (503) 268-8001 -or- (800) LATTICE Title ALL MEASURMENT UNITS ARE IN MILS Block Diagram Size B Date: 5 4 3 Project Wednesday, May 16, 2018 2 0.1 Schematic Rev ECP5-5G Evaluation Board Sheet 2 Board Rev of 12 B 1 Figure A. 2. Block Diagram (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 32 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide 5 4 3 2 1 +3.3V +3.3V C5 0.1uF 10uF 1 VCCIO8 C7 R1 R2 R3 0.1uF J1 1 FT_VPHY C9 4.7uF 600ohm 500mA C10 VCC1_8FT 1 2 3 4 5 6 7 8 +3.3V 2 2 0.1uF USB_MINI_AB VBUS CASE CASE CASE CASE 0.1uF C142 0.1uF U1 FT2232HL VCC1_8FT 0 4 5 50 6 7 8 9 SHLD C11 0.01uF R10 49 ADBUS0 ADBUS1 ADBUS2 ADBUS3 ADBUS4 ADBUS5 ADBUS6 ADBUS7 VREGIN VREGOUT 100K 7 8 DM DP +3.3V R12 +3.3V FT_RSTb 2.2K 14 C12 R13 R14 10K U2 C14 VCC NU ORG VSS CS CLK DI DO 10K R16 ACBUS0 ACBUS1 ACBUS2 ACBUS3 ACBUS4 ACBUS5 ACBUS6 ACBUS7 FT_REF 6 12K RESET# REF 10K FT_EECS FT_EECLK FT_EEDATA 1 2 3 4 12K 63 62 61 EECS EECLK EEDATA BDBUS0 BDBUS1 BDBUS2 BDBUS3 BDBUS4 BDBUS5 BDBUS6 BDBUS7 R20 2 1 93LC56C-I/SN B DM DP R15 10uF 8 7 6 5 0.1uF JP1 JUMPER 2 3 FT_OSCI 13 OSCI OSCO TEST X1 DP 3 NC2 D+ NC3 D- 5 DM 4 DP FTDI High-Speed USB 4 FT2232H C16 18pF 7M-12.000MAAJ AGND 2 VBUS G1 G2 3 [7] 12MHz ESDR0502N-UDFN6 2 JP2 10 DM GND 6 3 1 PWREN# SUSPEND# C 16 17 18 19 21 22 23 24 ADBUS0 ADBUS1 ADBUS2 ADBUS3 0 0 0 0 R11 R7 R8 R9 TCK [5,9] TDI [5,9] TDO [5,9] TMS [5,9] VCCIO0 26 27 28 29 30 32 33 34 38 39 40 41 43 44 45 46 0 0 DNI R34 DNI R35 D1 TXD_UART [7] RXD_UART [7] VCCIO0 UART_ACT R18 2_2K-0603SMT R19 2_2K-0603SMT 48 52 53 54 55 57 58 59 R21 0R-0603SMT-DNI DNI 1 0 0 0 B TP1 R22 R23 R24 SCL0 [4,5,7] SDA0 [4,5,7] 1 TP2 60 36 GND GND GND GND GND GND GND GND 2 C15 18pF D2 1 FT_OSCO BCBUS0 BCBUS1 BCBUS2 BCBUS3 BCBUS4 BCBUS5 BCBUS6 BCBUS7 R5 2.2K 1 5 11 15 25 35 47 51 1 VBUS_5V 1 Header 1x8 DNI 2_2K-0603SMT NC GND C141 0.1uF 20 31 42 56 DD+ R6 C C13 +3.3V VCCIO VCCIO VCCIO VCCIO 2 3 0 12 37 64 R4 VCORE VCORE VCORE DD+ 1 4 9 VCC VPHY VPLL J2 4.7K 4.7K 4.7K 1 2 3 4 5 6 7 8 G L3 2 1 600ohm 500mA 1 C6 4.7uF 2 +3.3V L2 C4 0.1uF FT_VPLL VBUS_5V 0.1uF C3 0.1uF D L1 2 1 600ohm 500mA C8 C2 0.1uF R17 LED_GREEN_0603 D C1 JUMPER A A Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Phone (503) 268-8001 -or- (800) LATTICE Title USB Interface Size B Date: 5 4 3 Project Wednesday, May 16, 2018 2 0.1 Schematic Rev ECP5-5G Evaluation Board Sheet 3 Board Rev of 12 B 1 Figure A. 3. USB Interface (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 33 ECP5TM Evaluation Board User Guide 5 4 3 VCCIO2 VCCIO2 VCCIO2 VCCIO2 PR11A/URC_GPLL0T_IN PR11B/URC_GPLL0C_IN PR11C PR11D PR14A PR14B PR14C PR14D PR17A PR17B PR17C PR17D PR20A PR20B PR20C PR20D PR29A PR29B PR35A PR35B PR35C/VREF1_2 PR35D PR38A PR38B PR38C PR38D PR41A/GR_PCLK2_1 PR41B PR41C/GR_PCLK2_0 PR41D PR44A/PCLKT2_1 PR44B/PCLKC2_1 PR44C/PCLKT2_0 PR44D/PCLKC2_0 D Bank2 C 1 ARDUINO Connector U3C H14 H15 J15 2 C18 D17 E16 F16 D18 E17 E18 F18 F17 G18 G16 H16 H18 H17 J17 J16 K16 K17 C20 D19 D20 E19 E20 F19 F20 G20 G19 H20 J18 K18 J19 K19 J20 K20 AR_IO14 AR_RESET AR_AD5 AR_AD4 AR_AD3 AR_AD1 AR_AD2 AR_AD0 AR_SCL 0 AR_AREF AR_SDA 0 AR_SCK_IO13 AR_MISO_IO12 AR_SS_IO10 AR_MOSI_IO11 AR_IO9 AR_IO8 AR_IO7 AR_IO6 AR_IO4 AR_IO5 AR_IO3 AR_IO2 AR_IO0 AR_IO1 G20 G19 H20 J18 K18 J19 K19 J20 K20 J3 DNI R25 SCL0 [3,5,7] DNI R26 SDA0 [3,5,7] AR_IO0 AR_IO1 AR_IO2 AR_IO3 AR_IO4 AR_IO5 AR_IO6 AR_IO7 VCCIO2 G19 J18 J19 J20 2 4 6 8 10 12 14 16 18 20 22 1 3 5 7 9 11 13 15 17 19 21 1 3 5 7 9 11 13 15 17 19 21 C83 C84 0.1uF 0.1uF 0.1uF AD5/SCL AD4/SDA AD3 AD2 AD1 AD0 D +12.0V JP3 JUMPER 2 1 H20 J6 AR_IO8 AR_IO9 AR_SS_IO10 AR_MOSI_IO11 AR_MISO_IO12 AR_SCK_IO13 1 2 3 4 5 6 7 AR_AREF 0 DNI R27 8 AR_SDA 9 AR_SCL 10 K18 K19 K20 G20 Header_2x11 DNI IO8 IO9/PWM SS/PWM MOSI/PWM MISO SCK GND AREF AD4/SDA AD5/SCL JP5 JUMPER 2 1 JP4 JUMPER 2 1 AR_RESET AR_IO14 J7 8 7 6 5 4 3 2 1 VIN GND2 GND1 5V0 3V3 RESET IOREF N/A Header 1x8 C Header 1x10 Spacing between J3/J6 column and J4/J7 column: 47.96 mils VCCIO2 C82 6 5 4 3 2 1 Header 1x6 +3.3V_AR VBUS_5V VCCIO2 J5 2 4 6 8 10 12 14 16 18 20 22 Warning Note Needed on Silkscreen: 3V3 ARDUINO ONLY LVDS RX TERMINATION RESISTORS NOTE : PLACE ALL THE TERMINATION RESISTORS ON TOP SIDE AND CLOSE TO THE U3C G19 R28 DNI 100 H20 10uF J4 AR_AD5 AR_AD4 AR_AD3 AR_AD2 AR_AD1 AR_AD0 IO0/RXD IO1/TXD IO2 IO3/PWM IO4 IO5/PWM IO6/PWM IO7 Header 1x8 LFE5G-85F-BG381 C81 1 2 3 4 5 6 7 8 J18 K18 R29 DNI 100 J19 K19 R30 DNI 100 J20 K20 R31 DNI 100 B B Note : 1) Match length within pair as well as other pairs with +/- 5% tolerence 2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals 3)All the power rails should be capable of carrying 1A current Through Hole Prototype Area +2.5V +3.3V A AG1 AF1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AB1 AA1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 A Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Phone (503) 268-8001 -or- (800) LATTICE Title Arduino Interface Size B Date: 5 4 3 Project Wednesday, May 16, 2018 2 0.1 Schematic Rev ECP5-5G Evaluation Board Sheet 4 Board Rev of 12 B 1 Figure A. 4 Arduino Header (BANK2) (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 34 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide 5 4 3 2 VCCIO3 Raspberry PI Connector U3D PR47A/PCLKT3_1 PR47B/PCLKC3_1 PR47C/PCLKT3_0 PR47D/PCLKC3_0 PR50A/GR_PCLK3_0 PR50B PR50C/GR_PCLK3_1 PR50D PR53A PR53B PR53C PR53D PR56A PR56B/VREF1_3 PR56C PR56D PR77A PR83A PR83B PR83C PR83D PR86A PR86B PR86C PR86D PR89A PR89B PR89C PR89D PR92A PR92B PR92C/LRC_GPLL0T_IN PR92D/LRC_GPLL0C_IN D Bank3 C L20 M20 L19 M19 L16 L17 L18 M18 N16 M17 N18 P17 N17 P16 R16 R17 T16 N19 N20 P19 P18 P20 R20 T20 U20 T19 R18 U19 T18 U18 U17 U16 T17 L20 M20 L19 M19 L16 RASP_ID_SC RASP_ID_SD RASP_IO27 RASP_IO26 RASP_IO24 RASP_IO25 RASP_IO23 RASP_IO22 RASP_IO20 RASP_IO21 RASP_IO19 RASP_IO18 RASP_IO17 RASP_IO15 RASP_IO16 RASP_IO14 RASP_IO13 RASP_IO11 RASP_IO12 RASP_IO10 RASP_IO09 RASP_IO07 RASP_IO08 RASP_IO06 RASP_IO05 RASP_IO04 RASP_IO03 RASP_IO02 +3.3V_RASP VBUS_5V 0 0 DNI R32 DNI R33 D 1 VCCIO3 VCCIO3 VCCIO3 SCL0 [3,4,7] SDA0 [3,4,7] JP7 1 2 JP6 JUMPER JUMPER 2 L14 L15 M15 1 C18 C17 0.1uF 0.1uF JP8 R41 DNI R40 DNI R39 DNI 0 0 0 R38 DNI 0 TMS [3,9] TDI [3,9] TDO [3,9] TCK [3,9] 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 RASP_IO02 RASP_IO03 RASP_IO04 RASP_IO17 RASP_IO27 RASP_IO22 RASP_IO10 RASP_IO09 RASP_IO11 RASP_ID_SD RASP_IO05 RASP_IO06 RASP_IO13 RASP_IO19 RASP_IO26 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 LFE5G-85F-BG381 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 RASP_5V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 RASP_IO14 RASP_IO15 RASP_IO18 RASP_IO23 RASP_IO24 RASP_IO25 RASP_IO08 RASP_IO07 RASP_ID_SC C RASP_IO12 RASP_IO16 RASP_IO20 RASP_IO21 Receptacle 20X2 VCCIO3 VCCIO3 J8 C89 C90 C91 C92 10uF 0.1uF 0.1uF 0.1uF L19 L20 L16 1 3 5 7 1 3 5 7 B 2 4 6 8 2 4 6 8 M19 M20 B Header_2x4 DNI A A Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Phone (503) 268-8001 -or- (800) LATTICE Title Raspberry Pi Interface Size B Date: 5 4 3 Project Wednesday, May 16, 2018 2 0.1 Schematic Rev ECP5-5G Evaluation Board Sheet 5 Board Rev of 12 B 1 Figure A. 5. Raspberry Pi Header (BANK3) (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 35 ECP5TM Evaluation Board User Guide 5 4 3 VCCHTX0 VCCHTX1 VCCA_SERDES0 J9 D U3I T7 T8 T10 T9 T11 T12 T14 T13 VCCHTX0_D0CH0 VCCHRX0_D0CH0 VCCHTX1_D0CH1 VCCHRX1_D0CH1 VCCHTX0_D1CH0 VCCHRX0_D1CH0 VCCHTX1_D1CH1 VCCHRX1_D1CH1 HDTXP0_D0CH0 HDTXN0_D0CH0 HDTXP0_D0CH1 HDTXN0_D0CH1 HDRXP0_D0CH0 HDRXN0_D0CH0 HDRXP0_D0CH1 HDRXN0_D0CH1 REFCLKP_D0 REFCLKN_D0 HDTXP0_D1CH0 HDTXN0_D1CH0 HDTXP0_D1CH1 HDTXN0_D1CH1 HDRXP0_D1CH0 HDRXN0_D1CH0 HDRXP0_D1CH1 HDRXN0_D1CH1 REFCLKP_D1 REFCLKN_D1 W4 W5 W8 W9 Y5 Y6 Y7 Y8 Y11 Y12 W13 W14 W17 W18 Y14 Y15 Y16 Y17 Y19 W20 HDTXP_D0C0 HDTXN_D0C0 HDTXP_D0C1 HDTXN_D0C1 HDRXP_D0C0 HDRXN_D0C0 HDRXP_D0C1 HDRXN_D0C1 REFCLKP_D0 REFCLKN_D0 HDTXP_D1C0 HDTXN_D1C0 HDTXP_D1C1 HDTXN_D1C1 HDRXP_D1C0 HDRXN_D1C0 HDRXP_D1C1 HDRXN_D1C1 200MHz 200MHz_N DNI DNI LFE5G-85F-BG381 1UF-10V-0201SMT C28 C29 C30 C145 1UF-16V-0402SMT 100NF-0201SMT 100NF-0201SMT C144 100NF-0201SMT C24 100NF-0402SMT C23 100NF-0201SMT C146 C22 100NF-0402SMT C27 VCCHTX1 1UF-16V-0402SMT 100NF-0402SMT 100NF-0402SMT B C26 100NF-0201SMT VCCA_SERDES1 C25 DNI J16 1HDRXN_D0C1 SMA DNI 1REFCLKN_D0 SMA DNI J20 1HDTXP_D1C0 2 3 4 5 SMA DNI DNI DNI J24 J22 1HDTXP_D1C1 2 3 4 5 SMA 2 3 4 5 SMA DNI J23 J21 1HDRXP_D1C0 J25 C 1HDRXP_D1C1 SMA DNI J26 C143 1UF-16V-0402SMT C21 100NF-0201SMT 100NF-0402SMT 100NF-0402SMT C20 SMA J19 VCCA_SERDES0 D SMA J18 DNI 2 3 4 5 J15 1HDRXP_D0C1 1HDTXN_D0C1 2 3 4 5 SMA 2 3 4 5 DNI 1REFCLKP_D0 2 3 4 5 SMA VCCHTX0 C19 1HDRXN_D0C0 J17 2 3 4 5 DNI J14 1 J12 1HDTXP_D0C1 2 3 4 5 SMA 2 3 4 5 SMA DNI J13 J11 1HDRXP_D0C0 1HDTXN_D0C0 2 3 4 5 SMA 2 3 4 5 SERDES Bank C J10 1HDTXP_D0C0 2 3 4 5 SMA 2 3 4 5 VCCA_SERDES1 2 1HDTXN_D1C0 2 3 4 5 SMA 2 3 4 5 DNI 1HDRXN_D1C0 1HDTXN_D1C1 2 3 4 5 SMA 2 3 4 5 SMA DNI DNI 1HDRXN_D1C1 SMA DNI B +3.3V 2 1 2 JP9 JUMPER 6 DIS# X2 200_00MHz_LVDS 200MHz Q Q_N NC 4 R45 10 5 R46 10 R180 100 200MHz_N GND EPAD C31 100NF-0402SMT C32 VCC R44 10K-0402SMT 3 7 1 1UF-16V-0805SMT L8 2 1 600ohm 500mA A A Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Phone (503) 268-8001 -or- (800) LATTICE Title SERDES SMAs Size B Date: 5 4 3 Project Wednesday, May 16, 2018 2 0.1 Schematic Rev ECP5-5G Evaluation Board Sheet 6 Board Rev of 12 B 1 Figure A. 6. SERDES SMA (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 36 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide 3 TP4 5VIN VCCIO0 GND D EXPCON_2V5 U3A F10 F9 VCCIO0 VCCIO0 PT11A PT11B PT13A PT13B PT15A PT15B PT18A PT18B PT20A PT20B PT4A/ULC_GPLL1T_IN PT4B/ULC_GPLL1C_IN PT54A PT56A PT56B PT58A PT58B PT60A/GR_PCLK0_1 PT60B/GR_PCLK0_0 PT63A/PCLKT0_1 PT63B/PCLKC0_1 PT65A/PCLKT0_0 PT65B/PCLKC0_0 PT6A PT6B PT9A PT9B Bank0 C +3.3V C6 C6 C7 C7 E8 E8 R51 D8 D8 0R-0603SMT C8 C8 B8 B8 A7 A7 A8 A8 I2S_SCK_mic_D9 D9 I2S_WS_mic_E9 E9 GPIO_amp_A6 A6 I2S_SD_mic1_mic2_card_B6 B6 C9 I2S_SD_mic3_mic4_C9 D10 I2S_SD_mic5_mic6_D10 E10 I2S_SD_mic7_E10 SDA0_WPU B9 SDA0_SPU C10 A9 A9 R53 B10 B10 R52 A10 100K-DNI 12MHz [3] A11 A11 2.2K-DNI B11 50MHz_OSC [8] C11 50MHz_OSC_EN [8] E6 SDA0 SCL0_WPU D6 E7 E7 D7 R54 E7 A11 A19 EXPCON_3V3 2 Pin 2 removed for coding of expansion board D15 C15 B20 E11 C12 E12 D13 A14 B10 K5 M5 L3 N2 L2 L1 C14 P1 D14 K4 HDR40 1 J40 K2 A15 H2 J4 J3 L4 M4 N4 N3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Microphone Daughter Board Expansion Connectors (Through Hole) F1 G1 J5 K3 L5 N5 P5 M3 EXPCON_3V3 VCCIO6 M1 N1 Rotate on PCB - Keep a 90 degree orientation difference between J29 / J30 D 2 4 6 8 10 TP3 EXPCON_2V5 B15 B13 D11 B12 D12 C13 E13 A9 R49 0R-0603SMT +2.5V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 J29 2x5 HEADER 61301021121 Wurth DNI 1 3 5 7 9 J39 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 R50 4 0R-0603SMT- DNI 5 E14 CARDSEL# Distance between jumpers should be the same as in the ice40 UltraPlus MDP board HDR40 VERSA Expansion Headers VCCIO0 I2S_SCK_mic_D9 I2S_WS_mic_E9 GPIO_amp_A6 J30 1 3 5 7 9 I2S_SD_mic1_mic2_card_B6 I2S_SD_mic3_mic4_C9 I2S_SD_mic5_mic6_D10 I2S_SD_mic7_E10 2 4 6 8 10 2x5 HEADER 61301021121 Wurth C J31 PMOD Header SDA0 [3,4,5] C6 1 7 C8 C7 2 8 B8 E8 3 9 A7 D8 4 10 A8 5 11 6 12 100K-DNI SCL0 LFE5G-85F-BG381 SCL0 [3,4,5] VCCIO6 VCCIO1 PMOD 2x6 DNI U3E U3B F11 F12 VCCIO1 VCCIO1 B Bank1 A A15 B15 C15 D15 SWITCH4 SWITCH8 SWITCH6 SWITCH7 SWITCH5 LED7 LED5 LED6 LED4 LED3 LED2 A19 B20 D11 E11 B12 C12 D12 E12 LED1 LED0 B13 C13 D13 E13 A14 C14 D14 E14 VCCIO0 C65 C66 C67 10uF 0.1uF 0.1uF LED[0:7] [10] VCCIO1 C73 C74 C75 10uF 0.1uF 0.1uF VCCIO6 C69 C70 C71 C72 10uF 0.1uF 0.1uF 0.1uF [3] TXD_UART [3] RXD_UART [9] BUTTON_1 G2 F1 F1 H2 H2 G1 G1 J4 J4 J5 J5 J3 J3 K3 K3 K2 K2 SWITCH1 J1 SWITCH2 H1 SWITCH3 K1 K4 K4 K5 K5 L4 L4 L5 L5 M5 M5 M4 M4 N5 N5 N4 N4 P5 P5 N3 N3 M3 M3 L3 L3 L2 L2 N2 N2 M1 M1 L1 L1 N1 N1 P1 P1 P2 P3 P4 PL47A/PCLKT6_1 PL47B/PCLKC6_1 PL47C/PCLKT6_0 PL47D/PCLKC6_0 PL50A/GR_PCLK6_0 PL50B PL50C/GR_PCLK6_1 PL50D PL53A PL53B PL53C PL53D PL56A PL56B/VREF1_6 PL56C PL56D PL77A PL83A PL83B PL83C PL83D PL86A PL86B PL86C PL86D PL89A PL89B PL89C PL89D PL92A PL92B PL92C/LLC_GPLL0T_IN PL92D/LLC_GPLL0C_IN VCCIO6 VCCIO6 VCCIO6 0.1uF B SWITCH1 SWITCH2 SWITCH3 SWITCH4 SWITCH5 SWITCH6 SWITCH7 SWITCH8 Bank6 SWITCH[1:8] [10] A Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Phone (503) 268-8001 -or- (800) LATTICE Title IO Breakout Size LFE5G-85F-BG381 LFE5G-85F-BG381 B Date: 5 C33 L6 L7 M6 SWITCH[1..8] PT103A PT105A PT105B PT107A PT107B PT110A PT110B PT112A PT112B PT114A PT114B PT116A PT116B PT119A PT119B PT121A/URC_GPLL1T_IN PT121B/URC_GPLL1C_IN PT69A/PCLKT1_1 PT69B/PCLKC1_1 PT71A/PCLKT1_0 PT71B/PCLKC1_0 PT74A/GR_PCLK1_0 PT74B/GR_PCLK1_1 PT76A PT76B PT78A PT78B PT80A PT80B PT83A PT83B PT85A PT85B A15 B15 C15 D15 E15 A16 B16 C16 D16 B17 C17 A17 B18 A18 B19 A19 B20 D11 E11 B12 C12 D12 E12 A12 A13 B13 C13 D13 E13 A14 C14 D14 E14 [9] GSRN VCCIO0 4 3 Project Wednesday, May 16, 2018 2 0.1 Schematic Rev ECP5-5G Evaluation Board Sheet 7 Board Rev of 12 B 1 Figure A. 7. IO Breakout (BANK0, BANK1, BANK6) (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 37 ECP5TM Evaluation Board User Guide 5 4 3 2 1 D D VCCIO7 VCCIO7 VCCIO7 J32 J33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 A4 B5 C4 A3 E4 C3 F4 C E5 A2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 A5 B2 C5 C1 B4 D2 B3 H4 D5 H5 D3 G3 E3 F2 F5 B1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 U3F 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 A4 A5 B5 C5 C4 B4 A3 B3 E4 D5 C3 D3 F4 E3 E5 F5 A2 B1 B2 C2 C1 D1 D2 E1 H4 G5 H5 H3 G3 F3 F2 E2 C2 D1 E1 G5 H3 F3 E2 Header_2x16 DNI Header2x20 DNI A4 A5 B5 C5 C4 B4 A3 B3 E4 D5 C3 D3 F4 E3 E5 F5 A2 B1 B2 C2 C1 D1 D2 E1 H4 G5 H5 H3 G3 F3 F2 E2 PL11A/ULC_GPLL0T_IN PL11B/ULC_GPLL0C_IN PL11C PL11D PL14A PL14B PL14C PL14D PL17A PL17B PL17C PL17D PL20A PL20B PL20C PL20D PL35A PL35B PL35C/VREF1_7 PL35D PL38A PL38B PL38C PL38D PL41A/GR_PCLK7_1 PL41B PL41C/GR_PCLK7_0 PL41D PL44A/PCLKT7_1 PL44B/PCLKC7_1 PL44C/PCLKT7_0 PL44D/PCLKC7_0 VCCIO7 VCCIO7 VCCIO7 H6 H7 J6 Bank7 C LFE5G-85F-BG381 LVDS RX TERMINATION RESISTORS [7] 50MHz_OSC_EN VCCIO0 NOTE : PLACE ALL THE TERMINATION RESISTORS ON TOP SIDE AND CLOSE TO THE U3F B This is optional R55 to enable or disable the crystal. 0 A4 A5 R56 DNI 100 C1 D1 R57 DNI 100 B5 C5 R58 DNI 100 D2 E1 R59 DNI 100 B X5 1 2 C4 B4 R61 DNI 100 H4 G5 R62 DNI 100 A3 B3 R63 DNI 100 H5 H3 R64 DNI 100 E4 D5 R65 DNI 100 G3 F3 R66 DNI 100 C3 D3 R67 DNI 100 F2 E2 R68 DNI 100 F4 E3 R69 DNI 100 E5 F5 R70 DNI 100 A2 B1 R71 DNI 100 B2 C2 R72 DNI 100 A VCCIO7 EN Vcc C34 C77 C78 C79 C80 0.1uF 10uF 0.1uF 0.1uF 0.1uF 4 3 GND Output LFSPXO01998(3.3V) DNI R60 22 50MHz_OSC [7] 50MHz OSC (3.3 V) Note : 1) Match length within pair as well as other pairs with +/- 5% tolerence 2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals 3)All the power rails should be capable of carrying 1A current A Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Phone (503) 268-8001 -or- (800) LATTICE Title IO Breakout (Diff) Size B Date: 5 4 3 Project Wednesday, May 16, 2018 2 0.1 Schematic Rev ECP5-5G Evaluation Board Sheet 8 Board Rev of 12 B 1 Figure A. 8. IO Breakout (BANK7, Differential Pairs) (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 38 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide 5 4 3 TCK [3,5] TDI [3,5] TDO [3,5] TMS [3,5] R73 LFE5G-85F-BG381 R74 4_7K-0603SMT 4_7K-0603SMT J38 4_7K-0603SMT R75 VCCIO8 1K-0603SMT U3G P10 P9 VCCIO8 VCCIO8 C R79 CCLK/MCLK/SCK CFG_0 CFG_1 CFG_2 DONE INITN PB11A/D1/MISO/IO1 PB11B/D0/MOSI/IO0 PB13A/SN/CSN PB13B/CS1N PB15A/HOLDN/DI/BUSY/CSSPIN/CEN PB15B/DOUT/CSON PB18A/WRITEN PB4A/D7/IO7 PB4B/D6/IO6 PB6A/D5/MISO2/IO5 PB6B/D4/MOSI2/IO4 PB9A/D3/IO3 PB9B/D2/IO2 PROGRAMN U3 U4 T4 R4 Y3 V3 V2 W2 T2 U2 R2 R3 T3 R1 T1 U1 V1 W1 Y2 W3 1K-0603SMT R77 DONE INITN DQ1_MISO DQ0_MOSI CSN CS1N BUSY_CSSPIN DOUT_CSON WRITEN DQ7 DQ6 DQ5_MISO2 DQ4_MOSI2 DQ3 DQ2 PROGRAMN 2 4 6 8 10 12 14 16 18 20 2 4 6 8 10 12 14 16 18 20 FLASH_CS DONE INITN DQ1_MISO DQ0_MOSI CSN CS1N BUSY_CSSPIN DOUT_CSON VCCIO8 D Place as close to Flash as possible R78 TP53 SW1 1K-0603SMT CCLK_MCLK_SCK 50R-0603SMT 1 3 5 7 9 11 13 15 17 19 Header_2x10 DNI TP54 VCCIO8 R76 1 3 5 7 9 11 13 15 17 19 PROGRAMN WRITEN DQ7 DQ6 DQ5_MISO2 DQ4_MOSI2 DQ3 DQ2 CCLK_MCLK_SCK CFG0 CFG1 CFG2 SW DIP-4 VCCIO8 VCCIO8 R80 4_7K-0603SMT RLP-101 VCCIO8 C85 C86 C87 10uF 0.1uF 0.1uF TP5 BUSY_CSSPIN TP6 TP7 DQ1_MISO DQ2 R85 R87 4_7K-0603SMT R82 1K-0603SMT RLP-101 R81 4_7K-0603SMT RLP-101 R83 RLP-101 VCCIO8 1 JP18 2 JUMPER U4 FLASH_CS 0R-0402SMT 0R-0402SMT C37 20pF-0603SMT DNI LFE5G-85F-BG381 128Mb SPI Flash TP11 TP13 TP15 TP18 7 8 9 10 3 4 5 6 CS# VCC SO/SIO1 DNU/SIO3 WP#/SIO2 SCLK GND SI/SIO0 RESET#/NC_3 NC_14 NC_4 NC_13 NC_5 NC_12 NC_6 NC_11 2 1 16 15 14 13 12 11 10NF-0402SMT T5 R5 V4 U5 TCK TDI TDO TMS 1 Parallel Config Header VCCIO8 U3H D 2 C36 100NFX5R-0402SMT C C35 R86 0R-0402SMT R88 0R-0402SMT DQ3 CCLK_MCLK_SCK DQ0_MOSI TP8 TP9 TP10 TP12 TP14 TP16 TP17 MX25L12833FMI-10G VCCIO8 VCCIO6 3 A1 B1 A2 B2 2 C40 GSRN VCCIO8 INITN indicator will light if an error occurs during configuration programming TP19 4 C41 430182043816 SW3 3 A1 B1 A2 B2 2 PROGRAMN 4 TP21 D4 C42 100NF-0402SMT G 1 3 430182043816 Q1 2N2222/SOT23 GP BUTTON A 2 BUTTON_1 [7] R92 10K-0402SMT TP20 LED_RED_0603 INITN DONE PROGRAMN B R93 10K-0402SMT INITN INITN GSRN [7] 100NF-0402SMT R94 D3 2_2K-0603SMT R R95 LED_GREEN_0603 1 C39 C38 20pF-0603SMT 20pF-0603SMT DNI DNI VCCIO8 2_2K-0603SMT SW2 R91 100NF-0402SMT FPGA GSRN R90 10K-0402SMT B 18pF = 12pF + Ground Plane ( 6pF ) 10K-0402SMT R89 10K-0402SMT VCCIO6 DONE indicator will light when configuration is successfully completed R96 1 10K-0603SMTDONE TP22 DONE SW4 1 3 A1 B1 A2 B2 2 4 BUTTON_1 TP23 C43 100NF-0402SMT A Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Phone (503) 268-8001 -or- (800) LATTICE 430182043816 Title CONFIG Status LEDs Configuration Size B Date: 5 4 3 Project Wednesday, May 16, 2018 2 0.1 Schematic Rev ECP5-5G Evaluation Board Sheet 9 Board Rev of 12 B 1 Figure A. 9. Configuration (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 39 ECP5TM Evaluation Board User Guide 4 B19 LED2 D7 LED3 G LED_GREEN_0603 D8 B18 LED4 D9 C17 LED5 D10 LED[0:7] LED3 LED4 D11 B17 LED7 D12 PLL_LK_PU 4 1K 13 EXB-2HV102JV RN1D USR3_PU 5 1K 12 EXB-2HV102JV RN1E D9 G USR2_PU D10 6 1K 11 EXB-2HV102JV RN1F G USR0_PU D11 7 1K 10 EXB-2HV102JV RN1G USR1_PU D12 8 1K 9 EXB-2HV102JV RN1H G LED_GREEN_0603 LED5 LED6 LED_GREEN_0603 LED6 RN1C D8 LED_GREEN_0603 A17 3 1K 14 EXB-2HV102JV D7 G LED_GREEN_0603 A18 POLL_PU G LED7 LED_GREEN_0603 VCCIO6 SWITCH1 SWITCH2 SWITCH3 SWITCH4 SWITCH5 SWITCH6 SWITCH7 SWITCH8 TDA DIP-8 VCC_CORE B14 B7 C19 D4 F13 F14 F7 F8 G10 G11 G12 G13 G14 G15 G17 G4 G6 G7 G8 G9 H19 J10 J11 J12 J14 J2 J7 J9 K10 K11 K12 K14 K15 K6 K7 K9 L10 L11 L12 L9 M10 M11 M12 M14 M16 M2 M7 M9 N14 N15 N6 N7 P11 P12 P13 P14 P7 P8 R19 VCCA0 B C45 1UF-0402SMT 100NF-0402SMT C46 C49 +2.5V C61 C62 C63 C147 RLP-133 1UF-16V-0805SMT C60 100NF-0402SMT VCCAUX 22uF-6.3V-0805SMT C48 1UF-0402SMT VCCA1 C47 100NF-0402SMT VCCA1 100NF-0201SMT U6 T6 U15 T15 P6 P15 F6 F15 V11 V10 V18 V17 W11 W10 100NF-0201SMT VCCA0 VCCA0 VCCA1 VCCA1 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUXA0 VCCAUXA0 VCCAUXA1 VCCAUXA1 RESERVED1 RESERVED2 100NF-0402SMT GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA 100NF-0201SMT C44 U3K U10 U11 U12 U13 U14 U7 U8 U9 V12 V13 V14 V15 V16 V19 V20 V5 V6 V7 V8 V9 W12 W15 W16 W19 W6 W7 J1 SWITCH1 1 16 SWITCH1 1 4_7K EXB2HV472JV RN2A H1 SWITCH2 2 15 SWITCH2 2 4_7K EXB2HV472JV RN2B K1 SWITCH3 3 14 SWITCH3 3 4_7K EXB2HV472JV RN2C E15 SWITCH4 4 13 SWITCH4 4 4_7K EXB2HV472JV RN2D D16 SWITCH5 5 12 SWITCH5 5 4_7K EXB2HV472JV RN2E RN2F D VCCIO1 B16 SWITCH6 6 11 SWITCH6 6 4_7K EXB2HV472JV C16 SWITCH7 7 9 SWITCH7 8 4_7K EXB2HV472JV RN2H A16 SWITCH8 8 10 SWITCH8 7 4_7K EXB2HV472JV RN2G U3J VCCA0 C SWITCH FB2 BLM31KN121SN1L LFE5G-85F-BG381 A GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC H10 H11 H12 H13 H8 H9 J13 J8 K13 K8 L13 L8 M13 M8 N10 N11 N12 N13 N8 N9 C C53 C54 C50 C55 C51 C56 C57 C58 C52 C59 100NF-0201SMT LED2 Signal 100NF-0201SMT D6 SW5 SWITCH[1..8] D LED1 RN1B D6 U1 pin 100NF-0201SMT LED_GREEN_0603 A12 2 1K 15 EXB-2HV102JV L0_PU G LED1 Switch Signal Map DIP SWITCH SWITCH[1:8] [7] 100NF-0201SMT D5 RN1A 100NF-0201SMT LED0 1 1K 16 EXB-2HV102JV D5 100NF-0201SMT LED_GREEN_0603 A13 DL_UP_PU G LED0 1 100NF-0201SMT LEDs LED 100NF-0201SMT Signal 2 LED[0:7] [7] 100NF-0201SMT U1 pin 3 VCCIO1 100NF-0201SMT 5 LEDs Signal Map C68 C76 10uF 10uF B A Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Phone (503) 268-8001 -or- (800) LATTICE Title LFE5G-85F-BG381 Power Decoupling and LEDs Size B Date: 5 4 3 Project Wednesday, May 16, 2018 2 0.1 Schematic Rev ECP5-5G Evaluation Board Sheet Board Rev 10 of 12 B 1 Figure A. 10. Power Decoupling and LEDs (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 40 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide 5 4 3 2 1 TP24 +3.3V VCCIO2 +3.3V VCCIO3 +3.3V VCCIO6 +3.3V VCCIO8 +3.3V VCCIO0 R105 0 R97 0 R98 0 R99 0 R101 0 TP40 D TP25 +2.5V DNI +3.3V_AR +3.3V_RASP +2.5V +2.5V 1 +2.5V 2 4 R100 0 TP27 R102 0 R103 0 R104 TP26 0 1 JP10 HEADER_5PIN +1.5V 0 +2.5V DNI DNI +2.5V TP28 1 DNI TP29 DNI +1.5V 3 Default : Pin 1 & 2 R106 1 R107 0 TP31 R108 1 0 1 +3.3V TP32 1 DNI TP39 DNI This can be configured in a + configuration with VCCIO0 in the middle to reduce space used VCC_CORE TP57 1 TP56 1 TP55 1 TP38 1 TP37 1 TP36 1 TP35 1 TP34 1 1 TP33 C D +2.5V 1 5 1 1 VCC_CORE VCCIO1 1 +3.3V C spread across board, easy access +12.0V +2.5V G 1.5 V VCC_CORE 3 Q4 2N2222/SOT23 G LED_GREEN_0603 D24 R141 1 4.7K-0603SMT 2 +1.5V JP11 HEADER_5PIN 3 B G 4 R139 24K-1206SMT 1.2 V VCC_CORE +12.0V LED_GREEN_0603 D23 +1.5v LED_GREEN_0603 D31 G R137 24K-1206SMT TP30 LED_GREEN_0603 D25 2.5 V 3.3 V R179 470R-0603SMT R135 2_2K-0603SMT 3 5 1 1 Default : Pin 1 & 2 +3.3V VCCIO7 +3.3V 2 +2.5V R138 1 4.7K-0603SMT Q2 2N2222/SOT23 B 2 VCC_CORE +12.0V +12.0V This can be configured in a + configuration with VCCIO0 in the middle to reduce space used R142 R136 24K-1206SMT 1.1 V Analog 1_8K-1206SMT 12VIN GOOD LED_BLUE_0603 Q3 2N2222/SOT23 1 R140 4.7K-0603SMT A Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Phone (503) 268-8001 -or- (800) LATTICE 2 A LED_GREEN_0603 D22 VCCA0 3 B G D26 Title Power Hookup Size B Date: 5 4 3 Project Wednesday, May 16, 2018 2 0.1 Schematic Rev ECP5-5G Evaluation Board Sheet Board Rev 11 of 12 B 1 Figure A. 11.Power Hookup (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 41 ECP5TM Evaluation Board User Guide 5 4 R112 121K-0603SMT C101 FB3 C149 RLP-133 1K FB5 10NFX5R-0402SMT BLM31KN121SN1L VCCHTX current 0.45 v drop at 500 mA max SERDES VCCHTX 1.2 V Power C102 1K 10NFX5R-0402SMT C104 1UF-16V-0805SMT C150 RLP-133 VCCA current FB6 BLM31KN121SN1L C151 RLP-133 SERDES VCCA 1.2 V Power FB7 RLP-133 22uF,6.3V-0805SMT 22 2 PG2 11 1 18 17 4.7uH-SPD62R-472M C1151000pF-0402SMT 19 20 RT/SYNC R123 51K-0402SMT D17 DFLS220L 2 VC2 PG1 12 1 10 9 21 VC1 D15 1N4448W BLM31KN121SN1L 3.3 V Current Freq = 1.0 MHz C100 1UF-16V-0805SMT VCCA1 C106 +1.2 V 500 mA 1UF-16V-0805SMT VCCA_SERDES0 C108 1UF-16V-0805SMT VCCA_SERDES1 C111 1UF-16V-0805SMT C R119 10_7K-0603SMT +3.3V +3.3 V 1.35 A 1.2v/ms 1% R124 3_4K-0603SMT 1% C123 C124 RLP-133 RLP-133 22uF,6.3V-0805SMT Vout = 0.8*(R119/R124+1) = 3.32 V +12.0V B C138 RLP-133 10pF-0402SMT R133 10K-0603SMT 1% 22uF,6.3V-0805SMT 22uF,6.3V-0805SMT VC1 VC2 PG1 PG2 1 19 20 DNI RT/SYNC 4.7uH-SPD62R-472M D21 DFLS220L +1.5 V 1.1 A 1.2v/ms 15K-0603SMT A Vout = 0.8*(R129/R134+1) = 1.51 V Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Phone (503) 268-8001 -or- (800) LATTICE +1.5V C137 10pF-0402SMT R134 16_9K-0603SMT 1% 1% 0.1 1% cr2010_alt1 R1291% R132 20K-0402SMT Freq = 625 KHz Vout = 0.8*(R128/R133+1) = 1.21 V Place current measuring resistor R127 topside TP51 TP52 R127 C1291000pF-0402SMT 17 2 TRACK/SS2 1.5 V 11 18 C133 330pF-0402SMT TRACK/SS1 1.5 V Current C127 220NF-0402SMT 16V L7 C132 10pF-0402SMT FB2 1 VIN2 SW2 FB1 GND1 GND2 GND3 GND4 22 SW1 12 GND6 GND7 GND8 GND9 23 VIN1 2 10 +3.3V D19 1N4448W BOOST2 3 4 5 6 C136 RLP-133 24 DNI R131 63_4K-0402SMT C135 22uF,6.3V-0805SMT RLP-133 C134 C131 10pF-0402SMT VCC_CORE C130 330pF-0402SMT 1.2v/ms R130 30_1K-0402SMT 2 R128 5_11K-0603SMT 1% 1 C1281000pF-0402SMT 2 BOOST1 GND5 1 8 +1.2 V 1.35 A U8 LT3508EUF 13 14 15 16 7 L6 0.1 4.7uH-SPD62R-472M 1% cr2010_alt1 D20 DFLS220L 9 21 SHDN 2 C125 10uF,25V-1206SMT D18 RLP-134 1N4448W 1 Place current measuring resistor R126 topside TP50 TP49 R126 +3.3V C126 220NF-0402SMT 16V B R125 51K-0402SMT 25 Core Power 1.2 V Current C139 C140 RLP-133 RLP-133 22uF,6.3V-0805SMT Title Power Regulators Size 22uF,6.3V-0805SMT B Date: 5 4 D 0.1 1% cr2010_alt1 22uF,6.3V-0805SMT Vout = 0.8*(R118/R120+1) = 2.52 V C153 RLP-133 C113 220NF-0402SMT Place current measuring resistor R117 topside 16V TP47 TP48 L5 R117 C119 330pF-0402SMT R120 1% RLP-133 10K-0603SMT 22uF,6.3V-0805SMT FB2 TRACK/SS2 FB8 +3.3V GND6 GND7 GND8 GND9 C122 23 R122 34K-0402SMT C121 C117 10pF-0402SMT C116 330pF-0402SMT C120 22uF,6.3V-0805SMT RLP-133 FB1 24 R121 51K-0402SMT R118 21_5K-0603SMT 1% +2.5V SW2 2 C114 1000pF-0402SMT TRACK/SS1 2 1.2v/ms BOOST2 SW1 1 0.1 4.7uH-SPD62R-472M 1% cr2010_alt1 D16 DFLS220L +2.5 V 1.1 A BOOST1 8 L4 1 R115 7 GND5 TP46 U7 LT3508EUF 13 14 15 16 TP45 25 2.5 V Current 2 D14 1N4448W 3.3 V VIN2 C112 16V 220NF-0402SMT R116 51K-0402SMT SHDN Place current measuring resistor R115 topside C152 RLP-133 C118 10pF-0402SMT C109 10uF,25V-1206SMT RLP-134 +3.3V VIN1 2.5 V D13 SCHOTTKY/VISHAY-V12P10 POWER INPUT VCCA0 FB4 BLM31KN121SN1L 0.1 1% R113 cr2010_alt1 +12.0V C A R114 121K-0603SMT GND1 GND2 GND3 GND4 1 R110 C98 RLP-133 LT3085 3 4 5 6 +11v to +16v K C97 1UF-16V-0805SMT RLP-133 +1.2 V 500 mA 9 1 2 3 4 BLM31KN121SN1L F1251CT-ND 5A Fast-Blo SMT Socketed Fuse 2 Right angle mount, cable to board edge 1UF-16V-0805SMT VCCHTX1 VCCA Pad IN_8 OUT_1 IN_7 OUT_2 IN_6 OUT_3 VCtrl SET TP44 +12.0V 3 Male Power Jack 2.1mm 8 7 6 5 C94 1% F1 C148 RLP-133 2 J37 PJ-002A 1 U6 +3.3V BLM31KN121SN1L 0.01 1% cr2512_alt1 R111 1 TP43 22uF-6.3V-0805SMT22uF-6.3V-0805SMT 22uF-6.3V-0805SMT22uF-6.3V-0805SMT LT3085 D R109 C96 RLP-133 2 VCCHTX0 1 C95 1UF-16V-0805SMT RLP-133 9 1 2 3 4 3 TP42 10uF-6.3V-0805SMT Pad IN_8 OUT_1 IN_7 OUT_2 IN_6 OUT_3 VCtrl SET 8 7 6 5 10uF-6.3V-0805SMT +3.3V VCCHTX 22uF-6.3V-0805SMT22uF-6.3V-0805SMT TP41 U5 3 Project Wednesday, May 16, 2018 2 0.1 Schematic Rev ECP5-5G Evaluation Board Sheet Board Rev 12 of 12 B 1 Figure A. 12. Power Regulators (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 42 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide Appendix B. ECP5 Evaluation Board Bill of Materials Item Reference Qty Part PCB Footprint Comments Part Number Manufacturer Description 1 AG1,AF1,AE1,AD1,AC1, AB1,AA1,AG2,AF2,AE2, AD2,AC2,AB2,AA2,AG3, AF3,AE3,AD3,AC3,AB3,A A3,AG4,AF4,AE4,AD4,A C4,AB4,AA4,AG5,AF5,A E5,AD5,AC5,AB5,AA5,A G6,AF6,AE6,AD6,AC6,A B6,AA6,AG7,AF7,AE7,A D7,AC7,AB7,AA7,AG8,A F8,AE8,AD8,AC8,AB8,AA 8,AG9,AF9,AE9,AD9,AC 9,AB9,AA9,AG10,AF10, AE10,AD10,AC10,AB10, AA10,AG11,AF11,AE11, AD11,AC11,AB11,AA11 77 T POINT R TP DNL -- -- -- 2 C1,C2,C3,C4,C7,C8,C10, C13,C14,C141,C142 11 0.1uF C0402 -- CL05B104KA5NNNC Samsung CAP CER 0.1UF 25V 10% X7R 0402 3 C5 1 10uF C0402 -- CL05A106MP8NUB8 Samsung CAP CER 10UF 10V X5R 0402 4 C6,C9 2 4.7uF C0603 -- CL10A475KA8NQNC Samsung CAP CER 4.7UF 25V X5R 0603 5 C11 1 0.01uF C0402 -- CL05B103KA5NNNC Samsung CAP CER 10000PF 25V X7R 0402 6 C12 1 10uF C0603 -- CL10A106KO8NNNC Samsung CAP CER 10UF 10V X5R 0603 7 C15,C16 2 18pF C0402 -- CL05C180JA5NNNC Samsung CAP CER 18PF 25V 10% NP0 0402 8 C17,C18 2 0.1uF C0402 -- CL05B104KA5NNNC Samsung CAP CER 0.1UF 25V 10% X7R 0402 9 C19,C20,C25,C26,C28,C 29,C32,C40,C41,C42,C4 3,C46,C48,C60,C62 15 100NF0402SMT RLP-130-A -- CL05B104KA5NNNC Samsung CAP CER 0.1UF 25V 10% X7R 0402 10 C21,C22,C23,C24,C27,C 30,C44,C47,C50,C51,C5 2,C53,C54,C55,C56,C57, C58,C59,C61 19 100NF0201SMT C0201 -- C0603X5R1C104K030 BC TDK CAP CER 0.1UF 16V 10% X5R 0201 11 C31,C63,C94,C95,C97,C 100,C104,C106,C108,C1 11 10 1UF-16V0805SMT RLP-133 -- CL21B105KOFNNNG Samsung CAP CER 1UF 16V X7R 0805 12 C33 1 0.1uF cc0402 -- CL05B104KA5NNNC Samsung CAP CER 0.1UF 25V 10% X7R 0402 13 C34 1 0.1uF cc0402 -- CL05B104KA5NNNC Samsung CAP CER 0.1UF 25V 10% X7R 0402 14 C35 1 10NF-0402SMT RLP-130-A -- CL05B103KA5NNNC Samsung CAP CER 10000PF 25V X7R 0402 15 C36 1 100NFX5R0402SMT RLP-130-A -- CL05A104MP5NNNC Samsung CAP CER 0.1UF 10V X5R 0402 16 C37,C38,C39 3 20pF-0603SMT RLP-132 DNL -- -- -- 17 C45,C49 2 1UF-0402SMT RLP-130-A -- GRM152R60J105ME 15D Murata CAP CER 1UF 6.3V X5R 0402 18 C65,C68,C69,C73,C76,C 77,C81,C85,C89 9 10uF C0603 -- LMK107BJ106MALTD Taiyo Yuden CAP CER 10UF 10V X5R 20% 0603 (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 43 ECP5TM Evaluation Board User Guide Reference Qty Part PCB Footprint Comments Part Number Manufacturer Description 19 C66,C67,C70,C71,C72,C 74,C75,C78,C79,C80,C8 2,C83,C84,C86,C87,C90, C91,C92 18 0.1uF C0201 -- C0603X5R1C104K030 BC TDK CAP CER 0.1UF 16V 10% X5R 0201 20 C96,C98 2 10uF-6.3V0805SMT RLP-133 -- CL21A106KPFNNNE Samsung CAP CER 10UF 10V X5R 0805 21 C101,C102 2 10NFX5R0402SMT RLP-130-A -- GRM155R61C103KA0 1D Murata CAP CER 10000PF 16V X5R 0402 22 C109,C125 2 10uF,25V1206SMT RLP-134 -- TMK316B7106KL-TD Taiyo Yuden CAP CER 10UF 25V X7R 1206 23 C112,C113,C126,C127 4 220NF0402SMT RLP-130-A -- CL05A224KO5NNNC Samsung CAP CER 0.22UF 16V X5R 0402 24 C114,C115,C128,C129 4 1000pF0402SMT RLP-130-A -- CL05B102KB5NFNC Samsung CAP CER 1000PF 50V X7R 0402 25 C116,C119,C130,C133 4 330pF0402SMT RLP-130-A -- CL05B331KB5NNNC Samsung CAP CER 330PF 50V X7R 0402 26 C117,C118,C134,C137 4 10pF-0402SMT RLP-130-A -- CL05C100CB5NNNC Samsung CAP CER 10PF 50V C0G/NP0 0402 27 C120,C121,C122,C123,C 124,C135,C136,C138,C1 39,C140 10 22uF,6.3V0805SMT RLP-133 -- CL21A226MQQNNNE Samsung CAP CER 22UF 6.3V X5R 0805 28 C131,C132 2 10pF-0402SMT RLP-130-A DNL -- -- -- 29 C143,C145,C146 3 1UF-16V0805SMT RLP-130-A -- CL21B105KOFNNNG Samsung CAP CER 1UF 16V X7R 0805 30 C144 1 1UF-10V0201SMT C0201 -- GRM033R61A105ME 15D Murata CAP CER 1UF 10V X5R 0201 31 C147,C148,C149,C150,C 151,C152,C153 7 22uF-6.3V0805SMT RLP-133 -- CL21A226MQQNNNE Samsung CAP CER 22UF 6.3V X5R 0805 32 D1,D4,D5,D6,D7,D8,D9, D10,D11,D12,D22,D23, D24,D25,D31 15 LED_GREEN_0 603 APT1608 -- 150060GS75000 Wurth LED GREEN CLEAR 0603 SMD 33 D2 1 ESDR0502NUDFN6 UDFN6_04 0 -- ESDR0502NMUTBG ON semi TVS DIODE 5.5VWM 6UDFN 34 D3 1 LED_RED_0603 APT1608 -- 150060RS75000 Wurth LED RED CLEAR 0603 SMD 35 D13 1 SCHOTTKY/VIS HAY-V12P10 V12P10 -- V12P10-M3/86A Vishay DIODE SCHOTTKY 100V 12A TO277A 36 D14,D15,D18,D19 4 1N4448W 1N4448W -- 1N4448WS On Semi DIODE GEN PURP 75V 150MA SOD323F 37 D16,D17,D20,D21 4 DFLS220L DFLS220L -- DFLS220L-7 Diodes Incorporated DIODE SCHOTTKY 20V 2A POWERDI123 38 D26 1 LED_BLUE_060 3 APT1608 -- 150060BS75000 Wurth LED BLUE CLEAR 0603 SMD 39 FB2,FB3,FB4,FB5,FB6,FB 7,FB8 7 BLM31KN121S N1L BLM41P -- BLM31KN121SN1L Murata FERRITE BEAD 120 OHM IMPEDANCE Item (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 44 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide Reference Qty Part PCB Footprint Comments Part Number Manufacturer Description 40 F1 1 F1251CT-ND 154010 -- 0154010.DR Littelfuse Inc. FUSE BRD MNT 10A 125VAC/VDC SMD 41 JP1,JP2,JP3,JP4,JP5,JP6,J P7,JP9,JP18 9 JUMPER Header_1x 2 -- 61300211121 Wurth CONN HEADER 2 POS 2.54 42 JP8 1 Receptacle 20X2 HDR2542X20_sock et -- PPTC202LFBN-RC Sullins CONN HEADER FEM 40POS .1" DL TIN 43 JP10,JP11 2 HEADER_5PIN HEADER_5 -- 61300511121 Wurth CONN HEADER 5 POS 2.54 44 J1 1 Header 1x8 hdr_amp_ 87220_8_ 1x8_100 DNL 22284081 Molex CONN HEADER 8POS .100 VERT TIN 45 J2 1 USB_MINI_AB usb2-0rec-2400001-9 -- 651305142821 Wurth CONN RCPT USB MINI AB R/A SMT 46 J3,J7 2 Header 1x8 CONF1X8254P_210 4X240X85 0H_TH -- 61300811121 Wurth CONN HEADER 8 POS 2.54 47 J4 1 Header 1x6 CONF1X6254P_159 6X240X85 0H_TH -- 61300611121 Wurth CONN HEADER 6 POS 2.54 48 J5 1 Header_2x11 Header_2x 11 DNL 61302221121 Wurth CONN HEADER VERT DUAL 22POS 2.54 49 J6 1 Header 1x10 CONF1X10 254P_261 2X240X85 0H_TH -- 61301011121 Wurth CONN HEADER 10POS PIN 2.54MM 50 J8 1 Header_2x4 Header_2x 4 DNL 61300821121 Wurth CONN HEADER VERT DUAL 8POS 2.54 51 J9,J10,J11,J12,J13,J14,J1 5,J16,J17,J18,J19,J20,J2 1,J22,J23,J24,J25,J26 18 SMA 733910060 DNL 73391-0060 Molex CONN SMA RCPT STR 50 OHM PCB 52 J29 1 2x5 HEADER 61301021 121 DNL 61301021121 Wurth CONN HEADER 10POS DL PIN 2.54MM 53 J30 1 2x5 HEADER 61301021 121 -- 61301021121 Wurth CONN HEADER 10POS DL PIN 2.54MM 54 J31 1 PMOD 2x6 skt_sullins _pppc062 _2x6_100 DNL PPPC062LFBN-RC Sullins CONN HEADER FMAL 12PS.1" DL GOLD 55 J32 1 Header2x20 hdr_samte c_mtsw_2 x20_100 DNL 61304021121 Wurth CONN HEADER VERT 40POS 2.54 56 J33 1 Header_2x16 Header_2x 16 DNL 61303221121 Wurth CONN HEADER VERT DUAL 32POS 2.54 57 J37 1 PJ-002A pj_002a_3 p -- 694106301002 Wurth CONN PWR JACK 2X5.5MM SOLDER 58 J38 1 Header_2x10 Header_2x 10 DNL 61302021121 Wurth CONN HEADER VERT DUAL 20POS 2.54 59 J39,J40 2 HDR40 HDR-20x2 -- 61304021121 Wurth CONN HEADER VERT 40POS 2.54 Item (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 45 ECP5TM Evaluation Board User Guide PCB Footprint Comments Part Number Manufacturer Description 600ohm 500mA fb0603 -- BLM18AG601SN1D Murata FERRITE CHIP 600 OHM 500MA 0603 4 4.7uH-SPD62R472M SPD62R -- SPD62R-472M API Delevan Inc. FIXED IND 4.7UH 2A 150 MOHM SMD Q1,Q2,Q3,Q4 4 2N2222/SOT23 MMBT222 2ALT-1 -- MMBT2222ALT1G ON Semiconductor TRANS NPN 40V 0.6A SOT23 63 RN1 1 EXB-2HV102JV EXB-2HV -- EXB-2HV102JV Panasonic RES ARRAY 8 RES 1K OHM 1506 64 RN2 1 EXB2HV472JV EXB-2HV -- EXB2HV472JV Panasonic RES ARRAY 8 RES 4.7K OHM 1506 65 R1,R2,R3 3 4.7K R0603 -- RC0603FR-074K7L yageo RES 4.70K OHM 1/10W 1% 0603 SMD 66 R4,R6 2 0 R0402 -- RC0402FR-070RL yageo RES SMD 0 OHM JUMPER 1/16W 0402 67 R5,R12 2 2.2K R0603 -- RC0603FR-072K2L yageo RES SMD 2.2K OHM 1% 1/10W 0603 68 R7,R8,R9,R11,R22,R23,R 24 7 0 R0603 -- RC0603FR-070RL yageo RES SMD 0 OHM JUMPER 1/10W 0603 69 R10 1 100K R0603 -- RC0603FR-07100KL yageo RES SMD 100K OHM 1% 1/10W 0603 70 R13,R14,R15 3 10K R0603 -- RC0603FR-0710KL Yageo RES SMD 10K OHM 1% 1/10W 0603 71 R16,R20 2 12K R0603 -- RC0603FR-0712KL yageo RES SMD 12K OHM 1/10W 1% 0603 72 R17,R18,R19,R94,R95,R 135 6 2_2K-0603SMT RLP-101 -- RC0603FR-072K2L yageo RES SMD 2.2K OHM 1% 1/10W 0603 73 R21 1 0R-0603SMTDNI RLP-101 DNL -- -- -- 74 R25,R26,R27,R34,R35 5 0 R0603 DNL RC0603FR-070RL yageo RES SMD 0 OHM JUMPER 1/10W 0603 75 R28,R29,R30,R31,R56,R 57,R58,R59,R61,R62,R6 3,R64,R65,R66,R67,R68, R69,R70,R71,R72 20 100 cr0201 DNL RC0201JR-07100RL Yageo RES SMD 100 OHM 5% 1/20W 0201 76 R32,R33,R38,R39,R40,R 41 6 0 R0603 DNL RC0603JR-070RL Yageo RES 0.0 OHM 1/10W JUMP 0603 SMD 77 R44,R89,R90,R91,R92,R 93 6 10K-0402SMT RLP-100 -- RC0402FR-0710KL Yageo RES SMD 10K OHM 1% 1/16W 0402 78 R45,R46 2 10 R0603 -- RC0603FR-0710RL yageo RES SMD 10 OHM 1% 1/10W 0603 79 R60 1 22 R0603 -- RC0603FR-0722RL yageo RES SMD 22 OHM 1% 1/10W 0603 80 R49,R51 2 0R-0603SMT RLP-101 -- RC0603FR-070RL yageo RES SMD 0 OHM JUMPER 1/10W 0603 81 R50 1 0R-0603SMTDNI RLP-101 DNL -- -- -- 82 R52 1 2.2K-DNI R0603 DNL RC0603FR-072K2L yageo RES SMD 2.2K OHM 1% 1/10W 0603 83 R53,R54 2 100K-DNI R0603 DNL RC0603FR-07100KL yageo RES SMD 100K OHM 1% 1/10W 0603 84 R55 1 0 cr0603 -- RC0603FR-070RL yageo RES SMD 0 OHM JUMPER 1/10W 0603 85 R73,R74,R75,R80,R81,R 83 6 4_7K-0603SMT RLP-101 -- RC0603FR-074K7L yageo RES 4.70K OHM 1/10W 1% 0603 SMD Item Reference Qty Part 60 L1,L2,L3,L8 4 61 L4,L5,L6,L7 62 (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 46 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide Reference Qty Part PCB Footprint Comments Part Number Manufacturer Description 86 R76,R77,R78,R82 4 1K-0603SMT RLP-101 -- RC0603FR-071KL yageo RES SMD 1K OHM 1/10W 1% 0603 87 R79 1 50R-0603SMT RLP-101 -- RC0603FR-0749R9L yageo RES SMD 49.9 OHM 1% 1/10W 0603 88 R85,R86,R87,R88 4 0R-0402SMT RLP-100 -- RC0402FR-070RL yageo RES SMD 0 OHM JUMPER 1/16W 0402 89 R94 1 2_2K-0603SMT RLP-101 -- RC0603FR-072K2L yageo RES SMD 2.2K OHM 1% 1/10W 0603 90 R95,R135 2 2_2K-0603SMT RLP-101 -- RC0603FR-072K2L yageo RES SMD 2.2K OHM 1% 1/10W 0603 91 R96,R120,R133 3 10K-0603SMT RLP-101 -- RC0603FR-0710KL Yageo RES SMD 10K OHM 1% 1/10W 0603 92 R97,R98,R99,R100,R101 5 0 R0603 -- RC0603JR-070RL Yageo RES SMD 0 OHM JUMPER 1/10W 0603 93 R102,R103,R104,R105,R 106,R107,R108 7 0 R0603 DNL RC0603JR-070RL Yageo RES SMD 0 OHM JUMPER 1/10W 0603 94 R109 1 0.01 cr2512_alt 1 -- PE2512FKE7W0R01L Yageo RES 0.01 OHM 1% 2W 2512 95 R110,R115,R117,R126,R 127 5 0.1 cr2010_alt 1 -- WSL2010R1000FEA Vishay Dale RES 0.1 OHM 1% 1/2W 2010 96 R111,R113 2 1K R0603 -- RC0603FR-071KL yageo RES SMD 1K OHM 1/10W 1% 0603 97 R112,R114 2 121K-0603SMT RLP-101 -- RC0603FR-07121KL yageo RES SMD 121K OHM 1% 1/10W 0603 98 R116,R121,R123,R125 4 51K-0402SMT RLP-100 -- RC0402FR-0751KL yageo RES SMD 51K OHM 1% 1/16W 0402 99 R118 1 21_5K0603SMT RLP-101 -- RC0603FR-0721K5L yageo RES SMD 21.5K OHM 1% 1/10W 0603 100 R119 1 10_7K0603SMT RLP-101 -- RC0603FR-0710K7L yageo RES SMD 10.7K OHM 1% 1/10W 0603 101 R122 1 34K-0402SMT RLP-100 -- RC0402FR-0734KL yageo RES SMD 34K OHM 1% 1/16W 0402 102 R124 1 3_4K-0603SMT RLP-101 -- RC0603FR-073K4L yageo RES SMD 3.4K OHM 1% 1/10W 0603 103 R128 1 5_11K0603SMT RLP-101 -- RC0603FR-075K11L yageo RES SMD 5.11K OHM 1% 1/10W 0603 104 R129 1 15K-0603SMT RLP-101 -- RC0603FR-0715KL yageo RES SMD 15K OHM 1% 1/10W 0603 105 R130 1 30_1K0402SMT RLP-100 -- ERJ-2RKF3012X Panasonic RES SMD 30.1K OHM 1% 1/10W 0402 106 R131 1 63_4K0402SMT RLP-100 -- ERJ-2RKF6342X Panasonic RES SMD 63.4K OHM 1% 1/10W 0402 107 R132 1 20K-0402SMT RLP-100 -- ERJ-2RKF2002X Panasonic RES SMD 20K OHM 1% 1/10W 0402 108 R134 1 16_9K0603SMT RLP-101 -- RC0603FR-0716K9L yageo RES SMD 16.9K OHM 1% 1/10W 0603 109 R136,R137,R139 3 24K-1206SMT RLP-103 - RC1206JR-0724KL Panasonic RES SMD 24K OHM 5% 1/4W 1206 110 R138,R140,R141 3 4.7K-0603SMT RLP-101 -- RC0603FR-074K7L yageo RES SMD 4.7K OHM 1% 1/10W 0603 111 R142 1 1_8K-1206SMT RLP-103 - RC1206JR-071K8L Yageo RES SMD 1.8K OHM 5% 1/4W 1206 112 R179 1 470R-0603SMT RLP-101 - RC0603FR-07470RL yageo RES SMD 470 OHM 1% 1/10W 0603 113 R180 1 100 R0402 -- ERJ-2RKF1000X Panasonic RES SMD 100 OHM 1% 1/10W 0402 114 SW1 1 SW DIP-4 41812127 0804 -- 418121270804 Wurth SWITCH SLIDE DIP SPST 25MA 24V Item (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 47 ECP5TM Evaluation Board User Guide Item Reference Qty Part 115 SW2,SW3,SW4 3 430182043816 116 SW5 1 117 TP1,TP2,TP24,TP25,TP2 6,TP27,TP28,TP29,TP30, TP31,TP32,TP33,TP34,T P35,TP36,TP37,TP38,TP 39,TP40,TP55,TP56,TP5 7 118 PCB Footprint Comments Part Number Manufacturer Description sw_sp_st_ ck_pts645 _sm -- 430182043816 Wurth SWITCH TACTILE SPST-NO 0.05A 12V TDA DIP-8 TDA08H0S B1 -- 416131160808 Wurth SWITCH SLIDE DIP SPST 25MA 24V 22 TP_S_40_63 TP DNL -- -- Square test point, 40mil inner diameter, 63mil outer diameter TP3,TP4,TP5,TP6,TP7,TP 8,TP9,TP10,TP11,TP12,T P13,TP14,TP15,TP16,TP 17,TP18,TP19,TP20,TP2 1,TP22,TP23,TP41,TP42, TP43,TP44,TP45,TP46,T P47,TP48,TP49,TP50,TP 51,TP52,TP53,TP54 35 TestPoint TP50 DNL -- -- -- 119 U1 1 FT2232HL tqfp64_0p 5_12p2x1 2p2_h1p6 -- FT2232HL-REEL FTDI IC USB HS DUAL UART/FIFO 64-LQFP 120 U2 1 93LC56C-I/SN so8_50_24 4 -- 93LC56C-I/SN Microchip Technology IC EEPROM 2KBIT 3MHZ 8SOIC 121 U3 1 LFE5G-85FBG381 LFE5G85F-BG381 -- LFE5UM5G-85F8BG381 Lattice 83.6K LUTS, 205 /O, 1.1V, -8 SPE 122 U4 1 MX25L12833F MI-10G SO16W -- MX25L12833FMI10G Macronix International IC FLASH 128MBIT 133MHZ 16SOIC 123 U5,U6 2 LT3085 msop8_26 _198_ep -- LT3085IMS8E#PBF Linear Technology/An alog Devices IC REG LIN POS ADJ 500MA 8MSOP 124 U7,U8 2 LT3508EUF LT3508EU F -- LT3508EUF#PBF Linear Technology/An alog Devices IC REG BUCK ADJ 1.4A DL 24QFN 125 X1 1 7M12.000MAAJ xtal_4p_7 m -- 7M-12.000MAAJ-T TXC CRYSTAL 12MHZ 18PF SMD 126 X2 1 200_00MHz_L VDS DSC1123A E2 -- DSC1123AE2200.0000 Microchip Technology OSC MEMS 200.000MHZ LVDS SMD 127 X5 1 LFSPXO01998 osc_4p_cb 3lv DNL LFSPXO019987Reel IQD OSC XO 50.000MHZ HCMOS TTL SMD 128 Shorting-Jumper 4 ShortingJumper -- -- 929957-08 3M SHORTING JUMPERS GOLD PLATED GRY 129 ECP5 EVALUATION BOARD REV A PCB 1 -- -- -- 305-PD-18-0078 PACTRON -- (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 48 FPGA-EB-02017-1.0 ECP5TM Evaluation Board User Guide Revision History Revision 1.0, July 2018 Initial release. (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02017-1.0 49 7th Floor, 111 SW 5th Avenue Portland, OR 97204, USA T 503.268.8000 www.latticesemi.com