SC1402 Multi-Output, Low-Noise Power Supply Controller for Notebook Computers POWER MANAGEMENT Description The SC1402 is pin compatible with the MAX1632 with improved load regulation performance. The SC1402 is a multiple-output power supply controller designed to power logic supply components in battery operated systems. The SC1402 utilizes synchronous rectified buck topologies to generate two voltages, (3.3V and 5V fixed or adjustable) with up to 95% efficiency. It also provides two linear regulators for system housekeeping functions. The 12V linear regulator output is generated from a coupled inductor of the 5V switching regulator. Control functions include: power up sequencing, soft start, power-good signaling, automatic bootstrapping for high side MOSFETs, and frequency synchronization. An internal precision 2.5V reference ensures 2% output voltage. The internal oscillator can be adjusted to 200kHz, 300kHz or synchronized to an external clock. The MOSFET drivers provide 1A peak drive current for fast MOSFET switching. Features ! 6V to 30V Input range ! 3.3V and 5V dual synchronous rectified outputs ! Fixed frequency or PSAVE mode for maximum ! ! ! ! ! ! ! ! ! ! efficiency over wide load current range 5V/50mA linear regulator 12V/120mA linear regulator Precision 2.5V reference output Programmable power-up sequence Power-good output (RESET) Output over-current protection Output over-voltage protection Output under-voltage shutdown 4A typical shutdown current 7mW typical quiescent power Applications ! Notebook and subnotebook computers ! PDAs and Mobile communications ! Desktop DC-DC converters The SC1402 includes a PSAVE enable input to select a pulse skipping mode for high efficiency or a fixed frequency mode for low noise operation. Typical Application Circuit Revision 3, February 2001 1 www.semtech.com SC1402 POWER MANAGEMENT Absolute Maximum Ratings Parameters Maximum Units V+, BST3, BST5 to GND -0.3 to +36 V 0.3 V PHASE3 to BST3, and PHASE5 to BST5 -6 to +0.3 V VL to GND -0.3 to 6 V REF, SYNC, SEQ, PSAVE, TIME_ON5, RESET to GND -0.3 to (VL + 0.3V) V RUN/ON3, SHDN to GND -0.3 to (V+ + 0.3V) V -0.3 to +30V V -0.3 to (VDD + 0.3V) V VL, REF Short to GND Continuous se c. 12 Out Short to GND Continuous se c. REF Current +5 mA VL Current +50 mA 12 Out Current +200 mA VDD Shunt Current +15 mA -65 to +150 C +300, 10 seconds C PGND to GND VDD to GND 12 Out to GND TS Storage Temperature TL Lead soldering temperature Electrical Characteristics (Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = VL, VL load = 0mA, REF load = 0mA, PSAVE = 0V, TA =-40 to +85C. Typical values are at TA = +25C). Parameters Conditions MIN TYP MAX Units 30.0 V MAIN SMPS CONTROLLERS Input Voltage Range 3V Output Voltage in Adjustable Mode 3V Output Voltage in Fixed Mode 5V Output Voltage in Adjustable Mode 5V Output Voltage in Fixed Mode Output Voltage Adjust Range Adjustable-Mode Threshold Voltage 2001 Semtech Corp. 6.0 V+ = 6V to 30V, CSH3-CSL3 = 0V, CSL3 tied to FB3 2.45 2.5 2.55 V V+ = 6V to 30V. 0mV < CSH3-CSL3 < 80mV, FB3 = 0V 3.17 3.3 3.43 V V+ = 6V to 30V, CSL5 tied to FB5 2.45 2.5 2.55 V V+ = 6V to 30V, 0mV < CSH5-CSL5 < 80mV, FB5 = 0V 4.82 5.0 5.18 V Either SMPS REF 5.5 V Dual Mode comparator 0.5 1.3 V 2 www.semtech.com SC1402 POWER MANAGEMENT Electrical Characteristics (Cont.) (Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = VL, VL load = 0mA, REF load = 0mA, PSAVE = 0V, TA =-40 to +85C. Typical values are at TA = +25C). Parameters Conditions MIN TYP MAX Units MAIN SMPS CONTROLLERS (Cont.) Load Regulation Either SMPS, 0V < CSL-CSL < 80mV -0.8 % Line Regulation Either SMPS, 6V < V+ < 30V 0.03 %/V Current-Limit Threshold CSH3-CSL3 or CSH5-CSL5 PSAVE = VL or V12OUT < 11.9V 80 -50 100 -100 120 -150 mV PSAVE Mode Threshold PSAVE = 0V, not tested 10 25 40 mV Soft-Start Ramp Time From enable to 95% full current limit with respect to fOSC (2) 512 Oscillator Frequency SYNC = VL SYNC = 0V 270 170 300 200 Maximum Duty Factor SYNC = VL, 300kHz SYNC = 0V, 200kHz 90 92 94 96 SYNC Input High Pulse Width kHz % 300 ns 200 (2) SYNC Input Frequency Range Current-Sense Input Leakage Current 330 235 300 (2) SYNC Input Low Pulse Width (2) SYNC Tise/Fall Time clks 240 V+ = VL = 0V, CSL3 = CSH3 = CSL5 = CSH5 = 5.5V 0.01 350 kHz 10 A 20 V 30 mA 30 A 12.50 V FLYBACK CONTROLLER VDD Shunt Threshold VDD Shunt Sink Current VDD Leakage Current Rising edge, hysteresis = 1% 18 V D D = 20V 5 10 VDD = 5V, Standby mode 12V LINEAR REGULATION 12OUT Output Voltage 12OUT Current Limit 0mA < Load < 120mA 12.1 12OUT forced to 11V, VDD = 13V 150 mA Falling edge 11.9 V VDD = 18V, run mode, no 12OUT load 50 12OUT Regulation Threshold Quiescent VDD Current 11.55 100 A 5.2 V 4.0 V INTERNAL REGULATOR AND REFERENCE VL Output Voltage Undervoltage Fault Lockout Threshold 2001 Semtech Corp. SHDN = V+, 6V < V+ < 30V, 0mA < ILOAD < 50mA, RUN/ON3 = TIME/ON = 0V 4.6 Falling edge, hysteresis = 0.9V 3.5 3 3.7 www.semtech.com SC1402 POWER MANAGEMENT Electrical Characteristics (Cont.) (Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = VL, VL load = 0mA, REF load = 0mA, PSAVE = 0V, TA =-40 to +85C. Typical values are at TA = +25C). Parameters C onditions MIN TYP MAX U nits IN TER N AL R EGU LATOR AN D R EFER EN C E (C ont.) Swi tchover Threshold REF Output Voltage REF Load Regulati on Swi tch over at startup No external load, Standby mode 4.5 2.45 2.55 V 0A < LOAD < 50A 12.5 mV 0mA < LOAD < 5mA 50 REF Si nk C urrent REF Fault Lockout Voltage V+ Operati ng Supply C urrent V+ Standby Supply C urrent V+ Shutdown Supply C urrent Qui escent Power C onsumpti on 2.5 V 10 Falli ng edge 1.8 A 2.2 VL Swi tched over to C SL5, 5V SMPS on 10 V+ = 6V to 30V, SMPS off, i ncludes current i nto SHD N 180 V+ = 6V to 30V, SHD N = 0V 4 SMPS enabled, FB3 = FB5 = 0V, C SL3 = C SH3 = 3.5V, C SL5 = C SH5 = 5.5V 7.5 V 50 A 20 mW FAU LT D ETEC TION Overvoltage Tri p Threshold Overvoltage-Fault Propagati on D elay Output Undervoltage Threshold Output Undervoltage Lockout Ti me Thermal Shutdown Threshold Wi th respect to unloaded output voltage 3.5 C SL dri ven 2% above overvoltage tri p threshold 7 10 1.5 % s Wi th respect to unloaded output voltage 60 70 80 % From each SMPS enabled, wi th respect to fOSC 5000 6144 7000 clks Typi cal hysteresi s = +10C 150 C R ESET RESET Tri p Threshold RESET Propagati on D elay RESET D elay Ti me Wi th respect to unloaded output voltage, falli ng edge; typi cal hysteresi s = 1% -10 -7 -4 % Falli ng edge, C SL dri ven 2% below RESET tri p threshold 1.5 s Wi gh respect to fosc 27.000 32,000 37,000 clks IN PU TS AN D OU TPU TS Logi c Input Low Voltage RUN/ON3, PSAVE, TIME/ON5 (SEQ = REF), SHD N, SYNC Logi c Input Hi gh Voltage RUN/ON3, PSAVE, TIME/ON5 (SEQ = REF), SHD N, SYNC Input Leakage C urrent 2001 Semtech Corp. RUN/ON3, PSAVE, TIME/ON5 (SEQ = REF), SHD N, SYNC , SEQ = 0V or 3.3V 4 0.6 2.4 V V 1 A www.semtech.com SC1402 POWER MANAGEMENT Electrical Characteristics (Cont.) (Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = VL, VL load = 0mA, REF load = 0mA, PSAVE = 0V, TA =-40 to +85C. Typical values are at TA = +25C). Parameters C onditions MIN TYP MAX U nits 0.4 V IN PU TS AN D OU TPU TS (C ont.) Logi c Output Low Voltage RESET, ISINK = 4mA Logi c Output Hi gh C urrent RESET = 3.5V 1 TIME/ON5 Input Tri p Level S E Q = 0 or V L 2.4 TIME/ON5 Source C urrent TIME/ON5 = 0V, SEQ = 0V or VL 2 TIME/ON5 On-Resi stance TIME/ON5, RUN/ON3 = 0V, S E Q = 0V or V L 100 ohm D L3, D H3, D L5, D H5, forced to 2V 1 A Hi gh or low 1.5 Gate D ri ver Si nk/Source C urrent Gate D ri ver On-Resi stance mA 3 2.6 V 4 A 7 ohm Notes: 1. This device is ESD sensitive. Use of standard ESD handling precautions is required. 2. Guaranteed by design. 2001 Semtech Corp. 5 www.semtech.com SC1402 POWER MANAGEMENT Pin Configuration Ordering Information Top View DEVICE PACKAGE TEMP. (TA) SC1402ISS SSOP-28 -40 - +85C Notes: 1. Only available in tape and reel packaging. A reel contains 1000 devices. SSOP-28 Pin Descriptions Pin# Pin Name 1 CSH3 Current Sense Input for the 3.3V SMPS. Current limit level is 100mV referred to C S L3. 2 C S L3 Current Sense Input for 3.3V SMPS. 3 FB 3 Feedback Input for the 3.3V SMPS; Connect FB3 to a resistor divider for adjustable output mode and FB3 is regulated to REF (approx. 2.5V). FB3 selects the 3.3V fixed output voltage setting when tied to GND. 4 12OUT 12V, 120mA Linear Regulator Output. Input supply comes from VDD. Bypass 12 OUT to GND with 1F minimum capacitor. 5 VD D Supply Voltage Input for the 12 OUT Linear Regulator. Also connects to a 18V overvoltage shunt regulator clamp. 6 SYNC Oscillator Synchronization and Frequency Select. Tie to VL for 300kHz operation; tie to GND for 200kHz. Driven externally to SYNC between 240kHz and 350kHz. 7 TIME/ON5 8 GND 2001 Semtech Corp. Pin Function Dual Purpose Timing Capacitor Pin and 5V SMPS ON/OFF Control Input. Input resistor of 1K is required when using ON/OFF control input. Low noise Analog Ground and feedback reference point. 6 www.semtech.com SC1402 POWER MANAGEMENT Pin Descriptions (Cont.) Pin# Pin Name Pin Function 9 REF 10 PSAVE Logic control input that disables PSAVE mode when high. Connect to GND for power save mode. 11 RESET Active low timed output. RESET swings from GND to VL. Goes high after 32,000 clock cycle delay following power up as a power good signal. 12 FB 5 13 C S L5 Current sense input for 5V SMPS. 14 CSH5 Current sense input for 5V SMPS. 15 SEQ Inputs that selects SMPS power up sequence. 16 DH5 Gate drive output for the 5V, high side N-Channel MOSFET. 17 PHASE5 18 BST5 19 D L5 20 PGND 21 VL 5V, Internal linear regulator output. 22 V+ Battery voltage input. 23 SHDN 24 D L3 25 BST3 26 PHASE3 27 DH3 28 RUN/ON3 2.5V Reference voltage output. Bypass to GND with 1F minimum capacitor. Feedback input for 5V SMPS. Connect FB5 to a resistor divider for adjustable output mode and FB5 regulates to REF (approx. 2.5V). FB5 selects the 5V fixed output voltage setting when tied to GND. Switching node inductor connection. Boost capacitor connection for 5V, SMPS high-side gate drive. Connect a 0.1F capacitor. Gate drive output for the 5V, SMPS low-side N-Channel MOSFET. Power ground. Shutdown control input, active low. Gate drive output for the 3.3V, SMPS low-side N-Channel MOSFET. Boost capacitor connection for high side gate drive. Connect a 0.1F capacitor. Switching node inductor connection. Gate drive output for the 3.3V, high-side N-Channel MOSFET. ON/OFF control input of 3.3V SMPS. Note: 1. All logic level inputs and outputs are open collector TTL compatible. 2001 Semtech Corp. 7 www.semtech.com SC1402 POWER MANAGEMENT Block Diagram VL 2001 Semtech Corp. 8 www.semtech.com SC1402 POWER MANAGEMENT Functional Block Diagram PIN Descriptions PWM Controller Diagram (Fig. 1) 2001 Semtech Corp. 9 www.semtech.com SC1402 POWER MANAGEMENT Detailed Description The SC1402 is a multiple-output, high efficiency, versatile power supply controller designed to power battery operated systems. Four high current gate drive outputs are supplied to control all MOSFETs in two synchronous rectified buck converters. These buck converters can be programmed to operate at either fixed or adjustable output voltages. The power save feature of the SC1402 achieves high efficiency over a wide range of load current. The control and fault monitoring circuitry associated with each PWM controller includes digital softstart, turn-on sequencing, voltage error amplifier with slope compensation, pulse width modulator, power save, over-current and over-voltage and under voltage fault protection. Two linear regulators and a precision reference voltage are also provided by the SC1402. PWM Control Block The two PWM control blocks for the 3V and 5V power supply outputs are identical. The SC1402 employs peak current mode control with slope compensation to provide fast output response to load and line transients. The PWM control block consists of an analog PWM modulator followed by PWM logic control. The analog modulator combines the output current, slope compensation signal and error voltage to generate a PWM pulse train. The PWM logic uses the pulse train from the modulator and other control signals to generate the output states for the high and low side gate driver outputs. A block diagram of the PWM control block is shown on page 8. An error amplifier generates the difference signal between the reference voltage and the feedback voltage to generate the error voltage for the peak current mode comparator. A nominal gain of 8 is used in the error amplifier to increase the system loop gain and to reduce the load regulation error typically seen in low loop-gain, current-mode controllers. The increased gain in the voltage loop is compensated by pole-zero-pole response of the voltage error amplifier. The current feedback signal is summed with the slope compensation signal and compared to the error voltage at the PWM comparator. When the power supply is operating in continuous conduction mode, the high-side MOSFET is turned on at the beginning of each switching cycle. The high-side MOSFET is turned off when the desired duty cycle is reached. Active shoot-thruough protection delays the turn-on of the low-side MOSFET until the phase node drops below 2.5V. The low-side MOSFET remains on until the beginning of the next switching cycle. Again, active shoot-through protection ensures that the gate to the lowside MOSFET has dropped low before the high side MOSFET is turned on. When PSAVE is enabled (low) and the output current drops below 25% of its peak level, the PWM logic will automatically enter PSAVE mode to improve efficiency. When the controller enters power save, it increases the regulation point by 0.8%, 2001 Semtech Corp. typically issuing one more high side pulse as the converter enters PSAVE. The PWM control then disables switching cycles until the FB falls below the reference. At light loads the effective switching frequency will drop dramatically and efficiency will increase because of the reduced gate charge current required to switch the power stage. Boosting the regulation point when entering PSAVE gives the output improved dynamic regulation because the output voltage is not allowed to droop below the nominal regulation point. Load current steps, that cause the converter to come out of PSAVE, will not cause as large a negative dip in the output voltage. Gate Drive/Control The gate driver on the SC1402 are designed to switch large MOSFETs up to 350kHz. The high side gate driver is required to drive the gates of the high side MOSFET above the V+ input. The supply for the gate driver is generated by charging a bootstrap capacitor from the VL supply when the low-side driver is on. Monitoring circuit ensures that the bootstrap capacitor is charged when coming out of shutdown or fault conditions where the bootstrap capacitor may be depleted. In continuous conduction mode, the low-side driver output that controls the synchronous rectifier in the power stage is on when the high-side driver is off. Under light load conditions the inductor ripple current will approach the point where it reverses polarity. This is detected by the low side driver control and the synchronous rectifier is turned off before the current reverses, preventing energy drain from the output. The low-side driver operation is also affected by various fault conditions as described in the Fault Protection section. Internal Bias Supply The VL linear regulator provides a 5V output that is used to power the gate drivers, 2.5V reference, and internal control sections of the SC1402. The regulator is capable of supplying up to 50mA (including MOSFET gate charge current). The VL pin should be bypassed to GND with 4.7uF to supply the peak current requirements of the gate driver outputs. This regulator receives its input power from the V+ battery input. Efficiency is improved by providing a boot-strapping mode for the VL bias. When the 5V SMPS output voltage reaches 5V, internal circuitry detects this condition and turns on a PMOS pass device between CSL5 and VL. The internal VL regulator is then disabled and the VL bias is provided by the high efficiency switch mode power supply. The REF output is accurate to +/- 2% over temperature. It is capable of delivering 5mA max and should be bypassed with 1uF minimum capacitor. Loading the REF output will reduce the REF voltage slightly. 10 www.semtech.com SC1402 POWER MANAGEMENT Current Sense (CSH,CSL) The output current of the power supply is sensed as the voltage drop across an external resistor between the CSH and CSL pins. Over-current is detected when the current sense voltage exceeds +/-100mV. The negative current limit (i.e. 100mV) is required for operation with PSAVE mode disabled, and also to limit the output current when charging the bulk supply capacitor of the 12V regulator. A positive over-current will turn off the high-side driver, a negative over-current will turn off the low-side driver, each on a cycle by cycle basis. The current sense is also used for peak current feed back in the main PWM loop and for determining the current level for entering power save mode and the turn off time for the synchronous rectifier. Oscillator The SC1402 oscillator frequency is trimmed to +/- 10%. When the SYNC pin is set high the oscillator runs at 300kHz; when SYNC is set low the frequency is 200kHz. The oscillator can also be synchronized to the falling edge of a clock on the SYNC pin with a frequency between 240kHz and 350kHz. In general, 200kHz operation is used for highest efficiency, and the 300kHz for minimum output ripple and/or smaller inductor and output capacitor sizes. Fault Protection In addition to cycle-by-cycle current limit, the SC1402 monitors over-temperature, and output over-voltage and under-voltage conditions. The over-temperature detect will shut the part down if the die temperature exceeds 150C with 10C of hysteresis. SHD N RUN/ ON3 TIME/ ON5 MOD E D ESC RIPTION Low X X Shutdown Mi ni mum bi as current Hi gh Low Low Standby VREF and VL regulator enable Hi gh Hi gh Hi gh Run Mode Both SMPS Runni ng Output Voltage Selection If FB is connected to ground, internal resistors setup 3.3V and 5V output voltages. If external resistors are used, the internal feedback is disabled and the output is regulated based on 2.5V at the FB pin. 12OUT Supply The 12OUT linear regulator is capable of supplying 120mA. The input voltage to the 12OUT regulator is generated by a secondary winding on the 5V SMPS inductor. A heavy load on the 12OUT regulator when the 5V SMPS is in PSAVE will cause the VDD input to drop, browning out the regulator. If the output drops 0.8% from its nominal value, the 5V SMPS is forced out of PSAVE mode and into continuous conduction mode for 8 cycles. This recharges the bulk input capacitor on VDD. The 12OUT linear regulator has a current limit to prevent damage under short circuit conditions. If either SMPS output is greater than 7% above its nominal value, both SMPS are latched off and synchronous rectifiers are latched on. To prevent the output from ringing below, ground a 1A Schottky diode should be placed across each output, anode at GND. Over-voltage protection is provided on the VDD input. If the VDD input is above 19V, an over-voltage is detected and a 10mA current shunt load is applied to VDD. The over-voltage threshold has 0.5V of hysteresis. Two different levels of undervoltage are detected. If the output falls 5% below its nominal output, the RESET output is pulled low. If the output falls 30% below its nominal output following a start-up delay, both SMPS are latched off. The user has control of the SC1402 startup sequence by setting the SEQ, RUN/ON3 and TIME/ON5 pins as described in the following table. Power up Controls and Soft Start Shutdown and Operating Modes Each SMPS contains its own counter and DAC to gradually increase the current limit at startup to prevent input surge currents. The current limit is increased from 0, 20%, 40%, 60%, 80%, to 100% linearly over the course of 512 switching cycles. Holding the SHDN pin low disables the SC1402, reducing the V+ input current to <10uA. When SHDN goes high, the part enters a standby mode where the VL regulator and VREF are enabled. Turning on either SMPS will put the SC1402 in run mode. A RESET output is also generated at startup. The RESET pin is held low for 32K switching cycles. Another timer is used to enable the undervoltage protection. The undervoltage protection circuitry is enabled after 6144 switching cycles at which time the SMPS should be in regulation. Both of the latched fault modes will remain in effect until SHDN or RUN/ON3 is toggled or the V+ input is brought below 1V. When SEQ is set to REF, the RESET only monitors the 3.3V SMPS in regulation. The 5V SMPS is ignored. 2001 Semtech Corp. 11 www.semtech.com SC1402 POWER MANAGEMENT SC1402 Startup Sequence Chart SEQ RUN/ON3 TIME/ON5 RESET DESCRIPTION REF LOW LOW Follows 3.3V SMPS. Independant start control mode. Both SMPSs off. REF LOW HIGH Low. 5V SMPS ON, 3.3V SMPS OFF. REF HIGH LOW Follows 3.3V SMPS. 3.3V SMPS ON, 5V SMPS OFF. REF HIGH HIGH Follows 3.3V SMPS. Both SMPSs on. GND LOW TIMING CAP Low. Both SMPSs off. GND HIGH TIMING CAP High after both outputs are in regulation. 5V starts on rising edge of RUN/ON3, 3V starts when TIME/ON5 > REF. VL LOW TIMING CAP Low. Both SMPSs off. VL HIGH TIMING CAP High after both outputs are in regulation. 3.3V starts on rising edge of RUN/ON3, 5V starts when TIME/ON5 > REF. Application Information Introduction The SC1402 is a versatile dual switching regulator adjustable from 2.5V to 5.5V with fixed 5V and 3.3V modes. In addition, there are two on-chip 12V & 5V linear regulators capable of supplying 120mA & 50mA of output current, respectively. The SC1402 is designed for notebook applications but has applications anywhere high efficiency, small size and low cost are required. The Semtech SC1402 EVAL board consists of a 3.3V, 3A switcher, a 5.0V, 3A switcher, an onboard 12V linear regulator. A 15V flyback supply developed off the 5V SMPS inductor delivers the input voltage to the onboard 12V linear regulator. Design Guidelines The schematic for the EVAL board is shown on page 18. The EVAL board is configured as follows: Switching Regulator 1 Switching Regulator 2 Linear Regulator 1 Vout1 = 3.3V, 3A Vout2 = 5.0V, 3A Vout3 = 12V, 120mA Linear Regulator 2 Vout4 = 5V, 50mA So once the ripple voltage specification is selected, the capacitor ESR is chosen usually based on capacitor cost and size constraints. This then sets the maximum output ripple current through the capacitor and inductor. For the EVAL board 3.3V switcher, we selected a maximum ripple voltage of 50mV. Choosing two 330uF, 6.3V tantalum capacitors C21 & C22, each having an ESR of 100mW, their combined ESR equaling 50mW, sets the maximum ripple current as follows: 0.05 VO IO = = 1Amp 0.05 ESR Be sure that the two output capacitors can handle this ripple current. Ripple current specifications are found in the capacitor data sheet for high quality capacitors intended for use in switching power supplies. IO = The inductance can now be found: L1 = (VINMAX - VO ) * D * t IO These inductance and duty cycle equations exclude any resistive drops due to winding resistance and MOSFET on resistance. Designing the Output Filter Where: Before calculating the output filter inductance and output capacitor, an acceptable amount of output ripple current is to be determined. The ESR of the output capacitor multiplied by the ripple current sets the maximum allowable ripple voltage. For f = 300KHz, t = 1/f 2001 Semtech Corp. V D = O ; L1 = VIN 12 (28 - 3.3) * 3.3 * 3.33 * 10 - 6 28 1 www.semtech.com SC1402 POWER MANAGEMENT Application Information (Cont.) From this calculation we choose L1 to be 10uH. For a 200kHz operating frequency, L1 calculates to be 14.5uH. Choosing Inductor & FET Current Rating The current carrying capability of the inductor and MOSFETs should be sized to handle the maximum current of the supply set by the current sense resistor, Rsense = R9. Here we use the minimum current threshold value: R9 = 80mV IPEAK Vinmin = 6V Where Fs is the switching frequency. Vout is the output voltage. Vinmin is the minimum input voltage. Vref is the SC1402 reference voltage. Rs is the sense resistor, (R9 on the EVAL board). Fc = IO 2 Ipeak = 3.5 Amps 0.080 R9 = = 0.023 3.5 Here we chose a sense resistor of 20m. Now we can determine FET and inductor current carrying capability by using the maximum current limit threshold: IPEAK = System Paramaters: Fs = 300000Hz Vout = 3.3V Vref = 2.5V Rs = 0.020 Step 1: Determine the Crossover Frequency Where Ipeak equals: IPEAK = IOUT + the output capacitor and ESR ensuring a stable control loop is shown below for the 3.3V supply. The same procedure should also be implemented for the 5V supply. 0.120 0.120 = = 6 Amps R9 0.020 From this value choose an inductor with Isat > 6 Amps, and for the FET choose a continuous conduction current rating greater than 6 Amps. Fs Vout 3 1 + Vinmin Fc = 64.516KHz Step 2: Determine the Maximum & Minimum ESR Capacitance ESRmax = Vout Vref Rs ESRmax= 0.026 ESRmin= ESRmax (1.2)2 ESRm in= 0.018 Step 3: Determine the Minimum Output Capacitance The same calculation process can be made for the 5V supply for its Inductor L2 and Rsense resistor, R8. The results are: L2 = 13.4 uH at 300KHz, 20uH at 200KHz, For our EVAL board we choose the transformer with a 11uH primary at the expense of slightly higher ripple current. R8 = 0.02 Co = C18 = 330uF/10V Calculating Output Capacitance and ESR for Stability. Comin = Vref 2 Fc Vout Rs tan 30 ( ) Comin = 162uF Step 4: Determine the Actual Output Capacitance Co = ESRm ax ESRm in Comin Co = 233uF Step 5: Determine the Actual ESR Value Now that the basic output filter has been designed, it is time to check if the output filter will allow stable operation. Since the control loop is internal to the SC1402, the output filter capacitor and its associated equivilant series resistance (ESR), will effect stability. It is important to choose a capacitor with its ESR for stable SMPS operation. A seven step procedure for choosing 2001 Semtech Corp. ESR = ESRm ax+ ESRm in 2 ESR = 0.022 13 www.semtech.com SC1402 POWER MANAGEMENT Application Information (Cont.) Step 6: From Above Calculations Choose: Co 233uF The RMS ripple current is under a worse-case condition at full load, 3A each when both SMPSs are on. ESR= 0.022 Step 7: Check the Ripple Current If Co can handle the ripple current you're done. Otherwise increase the output capacitance to handle the ripple current at maximum Vin and recheck the ESR using the equation for determining the actual output capacitance. If you are using tantalum or electrolytic capacitors you should increase the capacitance to the level of approaching the calculated ESR. If you are using poly capacitors a small resistor in series with the capacitor to bring the ESR to the desired level may be necessary for stability due to their low ESR values. If your ESR value varies significantly from the calculated value and you don't want to add more capacitance or add a series resistor in the capacitor path as described above. We recommend that you bench test the supply over temperature to verify transient response and operation of the SMPS. Input Capacitor Selection Input capacitor is selected based upon the input ripple current demand of the converter. First determine the input ripple current expected and then choose a capacitor to meet that demand. The input RMS ripple current can be calculated as follows: IRMS = VOUT * (VIN - VOUT ) * IOUT VIN The worse case input RMS ripple current occurs at 50% duty cycle (D = 0.5 or Vin = 2 Vout) and therefore under this condition the IRMS ripple current can be approximated by: IRMS = ILOAD 2 Therefore, for a maximum load current of 3.0A , the input capacitors should be able to safely handle 1.5A of ripple current. For the EVAL board there are two such regulators that operate simultaneously. Each capable of 1.5A of ripple current, although it is impossible for both regulators to be at 50% duty cycle at the same time since they have different output voltages. For the EVAL board, we chose four 10uF, 30V OS-CON capacitors, two for each supply. Each capacitor has a ripple current capability of 1.38A at 100KHz, 45C. Following the capacitor 2001 Semtech Corp. derating chart for temperature and frequency operation at 300KHz, two of these capacitors in parallel will suffice, as calculated below: When the 5V output is at maximum ripple of 1.5A (D = 50%), the 3.3V output adds 1.41A of ripple current. The maximum ripple current is then calculated by: IRMS(MAX) = 1.5 2 + 1.412 = 2.06A Conversely: When the 3V output is at maximum ripple 1.5A (D = 50%), the 5V output adds 1.29A of ripple current. The worse case ripple current is then calculated by: IRMS(MAX) = 1.5 2 + 1.29 2 = 1.98A Clearly, the combined input capacitor bank must be chosen to handle 2A of ripple current under worse-case conditions. MOSFET Switches After selecting the voltage and current requirements of each MOSFET device for the upper and lower switches, the next step is to determine their power handling capability. For the EVAL board the IRF7413 met the voltage and current requirements. These are 30V, 9A FET's. Based on 85C ambient temperature, 150C junction temperature and thermal resistance, their power handling is calculated as follows: Power Limit for Upper & Lower FET: TJ = 150C; TA = 85C; ja = 50C/W PT = TJ - TA 150 - 85 = = 1.3W JA 50 Each FET must not exceed 1.3W of power dissipation. The conduction losses for the upper & lower FET can be determined. For the calculations below, a nominal input voltage of 12V, for Vout = 3.3V, Iout = 3A and f = 300KHz. The Rdson value for the upper & lower FET is 11m. We will calculate the conduction losses and switching losses for each FET. From the calculations below we are well within the 1.3W dissipation limit as calculated above. 14 www.semtech.com SC1402 POWER MANAGEMENT Application Information (Cont.) Note that as Vin increases the power dissipation from switching losses will also increase. This is especially important if the input to the supply is from an AC adapter. Therefore, it is necessary to check the calculations with your maximum input voltage specification. In addition, the distribution of power in the upper and lower FET will change as input voltage increases. Conduction Losses Upper FET: PCU = R DS D I2 3.3 12 PCU = 0.011 3 2 = 0.027W Other losses to consider are gate charge losses, inductor switching and copper losses, and losses in the input and output capacitors. All these items will decrease efficiency and need to be carefully analyzed to obtain the highest efficiency possible, especially if running off battery power. Conduction Losses Lower FET: PCL = R DS (1 - D) PCL = 0.011 I2 3.3 2 1 - 3 = 0.072W 12 Basic Application Circuit Switching Losses Upper FET: PSU = C RSS * VIN2 * F * IOUT IG The basic dual-output 3.3V / 5V synchronous buck converter 240 * 10 -12 * 122 * 300000 * 3 is shown on page 16. This circuit shows the minimum = = 0.031W requirements for successful operation. For varying current 1 Note: switching losses exist on the upper FET only because the clamp diode across the lower FET will turn on prior to the lower FET turning on. Where Ig is the gate driver current. This is equal to 1A for the SC1402. levels, Table 3 provides a useful selection of components for varying supply requirements and is based on the calculations described previously. Input voltage ranges for all designs in the table are 6.5V to 28V. Frequency used in calculations is 300KHz. Crss is the reverse transfer capacitance of the FET; in this case it equals 240pF for the IRF7413. So the total FET losses equate to: PFETS = 0.027+0.072+0.031 = 0.130W 2A 3A 4A High & Low Side FETs IR IRF7901D1 Siliconix Si4412 IR IRF7413 Siliconix Si4412 IR IRF7805 Siliconix Si4410 Input Capacitor 10F, 30V Sanyo OS-CON 2 X 10F, 30V Sanyo OS-CON 3 X 10F, 30V Sanyo OS-CON Output Capacitor 330F, 6.3V/10V* AVX TPS 2 X 330F, 6.3V/10V* AVX TPS 4 X 330F, 6.3V/10V* AVX TPS Resistor 0.033 ohm, Dale WSL2010-R033-F 0.02 ohm, Dale WSL2010-R020-F 0.12 ohm, Dale WSL2512-R012-F Inductor 15F, Coilcraft DO-3316P-153 10F, Coilcraft DO3316P-103 4.7F, Coilcraft DO3316P-472 *10V for 5V SMPS. 6.3V for 3V SMPS Table 3 2001 Semtech Corp. 15 www.semtech.com SC1402 POWER MANAGEMENT PCB Layout As with any high frequency switching regulator it is advisable to practice a careful layout strategy. This includes keeping loop area as small as possible. Properly decoupling lines that pull large amounts of current in short periods of time. To keep loop area small always use a ground plane and if possible split the plane in two areas, signal GND and power GND then tie the two together at one point. Be sure that high current paths have low inductance by making track widths wide where possible. Evaluation Board Schematic VIN VIN 1 GND C1 C2 + 1 GND 10U,30V C7 C8 0.22 C5 C6 4.7U,6.3V 0.1 A D3 C10 C11 0.1 0.01 22 25 OPEN Q1 27 IR7413 VL CMPD2838 C D5 Q3 140T3 24 VDD DH3 BST5 IR7413 A R20 +3.3V 301K 1 C26 R9 LX5 DL5 2 3 R11 3.32K C21 OPEN C22 C23 10 330U,10V 330U,10V 23 A 7 1 JU9 28 C27 100pF R17 2M SHDN R16 2M R15 2M R14 2M CSH5 CSL3 CSL5 Q2 0.1 16 FB5 9 10 T2/L2 7 SEQ REF TIME/ON5 RUN/ON3 RESET 1 D4 C14 C31 2.2U,25V 0.1uF 17 Q4 19 20 C D6 C28 140T3 21 453 TTI5870 0.1uF R23 R8 .02 301K 14 +5V +5V 13 C 12 C18 15 C19 330U,10V PSAVE SHDN 1 RAW15V MBRS1100 C IR7413 FB3 C24 0.01 A C17 18 A CSH3 SYNC R13 5 IR7413 1 10.7K 4 DL3 .02 0.1uF 1 GND DH5 1 +12V JU2 12OUT PGND 2 GND VL LX3 VL 0.01 21 BST3 SC1402ISS 26 C U1 V+ 0.1 10uH 140T3 0.1 VL C13 4.7U,16V C16 L1 3 D8 1 1 C12 C9 C15 +5V1 VDD VDD GND OPEN D9 + 10U,30V 10U,30V 10U,30V 4.7U,35V C C4 + CMPSH-3A 1 VDD C3 D1 R1 10 + 9 R10 10.7K C20 OPEN 140T3 OPEN 1 GND A REF 1 1 D7 1 1 6 JP5 JP3 11 2 C30 GND 0.1uF 8 C25 4.7U,16V 2 JP4 2 VL C29 100pF JU7 R12 10.7K REF REF 1 R18 100K 1 SYNC ON5 1 R19 JP6 1 1k 2 1 GND 1 ON3 RESET 1 1 PSAVE 4 3 2 1 1 S1 SW DIP-4 Title SC1402 Eval Board VIN 2001 Semtech Corp. 5 6 7 8 Size B VL Date: 16 Document Number Rev RTP00005 Thursday, April 13, 2000 E Sheet 1 of 1 www.semtech.com SC1402 POWER MANAGEMENT Typical Characteristics 5V LINE REGULATION 4.96 3.28 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 4.95 4.94 4.93 3.27 3.26 4.92 4.91 3.3V LINE REGULATION 3.29 3.25 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 3.24 30 5 7.5 10 12.5 15 17.5 20 Vini INPUT VOLTAGE (V) Vini INPUT VOLTAGE (V) ILOAD = 0.5A ILOAD = 1A ILOAD = 3A 5V LOAD REGULATION 3.284 4.948 3.278 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 4.954 4.941 4.935 4.929 j 3.265 3.259 3.253 4.916 3.246 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.24 3 0 0.3 0.6 0.9 VIN = 15V VIN = 6V 1.5 1.8 2.1 2.4 2.7 3 VIN= 15V VIN = 6V EFFICIENCY vs. 5V LOAD CURRENT EFFICIENCY vs. 3.3V LOAD CURRENT 100 95 95 90 90 85 85 80 80 75 75 EFFICIENCY (%) EFFICIENCY (%) 1.2 Iouti , Ioutj LOAD CURRENT (A) Iouti ,Iout2 j LOAD CURRENT (A) 100 30 3.271 4.923 0.3 27.5 3.3V LOAD REGULATION 3.29 0 25 ILOAD = 0.5A ILOAD = 1A ILOAD = 3A 4.96 4.91 22.5 70 65 60 70 65 60 55 55 50 50 45 45 40 40 35 35 30 30 0 .1 1 30 10 0 .1 Iou ti , Iou t2j 5 V LOAD CURRENT (A) VIN = 15V VIN = 6V 2001 Semtech Corp. 1 10 Iou ti , Iou t2j 3 V LOAD CURRENT (A) VIN = 15V VIN = 6V 17 www.semtech.com SC1402 POWER MANAGEMENT Outline Drawing - SSOP-28 Land Pattern Contact Information Semtech Corporation Power Management Products Division 652 Mitchell Rd., Newbury Park, CA 91320 Phone: (805)498-2111 FAX (805)498-3804 2001 Semtech Corp. 18 www.semtech.com