July 2011 Doc ID 12585 Rev 5 1/34
34
RHF1201
Rad-hard 12-bit 50 Msps A/D converter
Features
■Qml-V qualified, smd 5962-05217
■Rad hard: 300 kRad(Si) TID
■Failure immune (SEFI) and latchup immune
(SEL) up to 120 MeV-cm2/mg at 2.7 V and
125° C
■Hermetic package
■Wide sampling range
■Tested at 50 Msps
■OptimwattTM adaptive power:
44 mW at 0.5 Msps, 100 mW at 50 Msps
■Optimized for 2 Vpp differential input
■SFDR up to 75 dB at FS= 50 Msps,
Fin =15MHz
■2.5 V/3.3 V compatible digital I/O
■Built-in reference voltage with external bias
capability
Applications
■Digital communication satellites
■Space data acquisition systems
■Aerospace instrumentation
■Nuclear and high-energy physics
Description
The RHF1201 is a 12-bit 50 Msps sampling
frequency analog-to-digital converter that uses
pure (ELDRS-free) CMOS 0.25 µm technology
combining high performance, radiation
robustness and very low power consumption. The
device is based on a pipeline structure and digital
error correction to provide excellent static
linearity. Specifically designed to optimize the
speed power consumption ratio, the RHF1201
integrates a proprietary track-and-hold structure
making it ideal for IF-sampling applications up to
150 MHz. A voltage reference network is
integrated in the circuit to simplify the design and
minimize external components. A tri-state
capability is available on the outputs to allow
common bus sharing. Output data can be coded
in two different formats. A Data Ready signal,
raised when the data is valid on the output, can be
used for synchronization purposes.
Ceramic SO-48 package
The upper metallic lid is not electrically connected to any
pins, nor to the IC die inside the package.
Table 1. Device summary
Order code (1)
1. Contact your ST sales office for information about the specific conditions for products in die form and for information about
SMD packages.
SMD pin Quality
level Package Lead
finish Packing Marking EPPL
RHF1201KSO1 - Engineering
model SO-48 Gold Strip
pack RHF1201KSO1 -
RHF1201KSO-01V 5962F0521701VXC QMLV-Flight SO-48 Gold Strip
pack 5962F0521701VXC -
www.st.com
Contents RHF1201
2/34 Doc ID 12585 Rev 5
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 9
7 Electrical characteristics (unchanged after 300 kRad) . . . . . . . . . . . . 10
7.1 RHF1201 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1.1 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1.2 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2 Driving the analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.3 Reference connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3.1 Internal reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3.2 External reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5 Power consumption optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.6 Layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8 Definitions of specified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1 Static parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2 Dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
RHF1201 Block diagram
Doc ID 12585 Rev 5 3/34
1 Block diagram
Figure 1. Block diagram
AM04529
VIN
INCM
VINB
CLK
GND
OR
D11
D0
DR
OEB
SRC
DFSB
VREFM
IPOL
GNDA
+2.5 V +2.5 V/3.3 V VREFP
stage
1
stage
1
stage
2
stage
2
stage
n
stage
n
Digital data correction
Buffers
Reference
circuit
Sequencer-phase shifting
Timing
VCCBI VCCBE
Pin connections RHF1201
4/34 Doc ID 12585 Rev 5
2 Pin connections
Figure 2. Pin connections (top view)
GNDBI
GNDBE
VCCBE
NC
NC
OR
(MSB)D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
(LSB)D0
DR
NC
NC
VCCBE
GNDBE
VCCBI
DGND
DGND
CLK
DGND
DVCC
DVCC
AVCC
AVCC
AGND
INCM
AGND
VINB
AGND
VIN
AGND
VREFM
VREFP
IPOL
AGND
AVCC
AVCC
DFSB
OEB
SRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GNDBI
GNDBE
VCCBE
NC
NC
OR
(MSB)D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
(LSB)D0
DR
NC
NC
VCCBE
GNDBE
VCCBI
DGND
DGND
CLK
DGND
DVCC
DVCC
AVCC
AVCC
AGND
INCM
AGND
VINB
AGND
VIN
AGND
VREFM
VREFP
IPOL
AGND
AVCC
AVCC
DFSB
OEB
SRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GNDBI
GNDBE
VCCBE
NC
NC
OR
(MSB)D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
(LSB)D0
DR
NC
NC
VCCBE
GNDBE
VCCBI
DGND
DGND
CLK
DGND
DVCC
DVCC
AVCC
AVCC
AGND
INCM
AGND
VINB
AGND
VIN
AGND
VREFM
VREFP
IPOL
AGND
AVCC
AVCC
DFSB
OEB
SRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
RHF1201 Pin descriptions
Doc ID 12585 Rev 5 5/34
3 Pin descriptions
Table 2. Pin descriptions
Pin Name Description Note Pin Name Description Note
1 GNDBI Digital buffer ground 0 V 25 SRC Slew rate control input 2.5 V/3.3 V CMOS
input
2 GNDBE Digital buffer ground 0 V 26 OEB Output Enable input 2.5 V/3.3 V CMOS
input
3 VCCBE Digital buffer power
supply 2.5 V/3.3 V 27 DFSB Data Format Select input 2.5 V/3.3 V CMOS
input
4NC Not connected to the
dice 28 AVCC Analog power supply 2.5 V
5NC Not connected to the
dice 29 AVCC Analog power supply 2.5 V
6 OR Out-of-range output CMOS output
(2.5 V/3.3 V) 30 AGND Analog ground 0 V
7 D11(MSB) Most significant bit
output
CMOS output
(2.5 V/3.3 V) 31 IPOL Analog bias current input
8 D10 Digital output CMOS output
(2.5 V/3.3 V) 32 VREFP Top voltage reference Can be internal or
external
9 D9 Digital output CMOS output
(2.5 V/3.3 V) 33 VREFM Bottom voltage
reference External
10 D8 Digital output CMOS output
(2.5 V/3.3 V) 34 AGND Analog ground 0 V
11 D7 Digital output CMOS output
(2.5 V/3.3 V) 35 VIN Analog input Optimized for 1Vpp
12 D6 Digital output CMOS output
(2.5 V/3.3 V) 36 AGND Analog ground 0 V
13 D5 Digital output CMOS output
(2.5 V/3.3 V) 37 VINB Inverted analog input Optimized for 1Vpp
14 D4 Digital output CMOS output
(2.5 V/3.3 V) 38 AGND Analog ground 0 V
15 D3 Digital output CMOS output
(2.5 V/3.3 V) 39 INCM Input common mode Can be internal or
external
16 D2 Digital output CMOS output
(2.5 V/3.3 V) 40 AGND Analog ground 0 V
17 D1 Digital output CMOS output
(2.5 V/3.3 V) 41 AVCC Analog power supply 2.5 V
18 D0(LSB) Least significant bit
output
CMOS output
(2.5 V/3.3 V) 42 AVCC Analog power supply 2.5 V
19 DR Data ready output CMOS output
(2.5 V/3.3 V) 43 DVCC Digital power supply 2.5 V
20 NC Not connected to the
dice 44 DVCC Digital power supply 2.5 V
21 NC Not connected to the
dice 45 DGND Digital ground 0 V
22 VCCBE Digital buffer power
supply 2.5 V/3.3 V 46 CLK Clock input 2.5 V compatible
CMOS input
23 GNDBE Digital buffer ground 0 V 47 DGND Digital ground 0 V
24 VCCBI Digital buffer power
supply 2.5 V 48 DGND Digital ground 0 V
Equivalent circuits RHF1201
6/34 Doc ID 12585 Rev 5
4 Equivalent circuits
Figure 3. Analog inputs Figure 4. Output buffers
AM04530
VIN or VINB
(pad)
AVCC
AGND
7 pF
AM04531
D0 …D13
7 pF
(pad)
VCCBE
GNDBE
AGND
OEB
Data
AVCC
Figure 5. Clock input Figure 6. Data format input
AM04532
CLK
7 pF
(pad)
DVCC
DGND
AM04533
DFSB
7 pF
(pad)
VCCBE
GNDBE
Figure 7. Slew rate control input Figure 8. Output enable input
AM04534
SRC
7 pF
(pad)
VCCBE
GNDBE
AM04535
OEB
7 pF
(pad)
VCCBE
GNDBE
RHF1201 Equivalent circuits
Doc ID 12585 Rev 5 7/34
Figure 9. VREFP and INCM input
Figure 10. VREFM input
AM04536
VREFP
Input impedance = 39Ω
7 pF
(pad)
AVCC
AGND
INCM
= 50 Ω
7 pF
(pad)
AVCC
AGND
Input impedance
AM04537
VREFM
AVCC
AGND
7 pF
(pad)
High input impedance
Timing characteristics RHF1201
8/34 Doc ID 12585 Rev 5
5 Timing characteristics
Figure 11. Timing diagram
The input signal is sampled on the rising edge of the clock while the digital outputs are
synchronized on the falling edge of the clock. The duty cycles on DR and CLK are the same.
Table 3. Timing table
Symbol Parameter Test conditions Min Typ Max Unit
DC Clock duty cycle(1)
1. See Figure 34.
FS = 45 Msps 45 50 65 %
Tod
Data output delay (2)
(fall of clock to data valid)
2. Guaranteed by design.
10 pF load 4 5 6 ns
Tpd Data pipeline delay (2) 5.5 5.5 5.5 cycles
Tdr
Data ready rising edge delay
after data change (3)
3. Tdr is linked to the duty cycle, conditioned by the duration of the low level of DR signal.
Duty cycle = 50% 0.5 cycles
Ton
Falling edge of OEB to
digital output valid data 13ns
Toff
Rising edge of OEB to digital
output tri-state 13ns
TrD Data rising time(4)
4. See Figure 35 and Figure 36.
5pF load, SRC=0 2.8 ns
5pF load, SRC=1 5.7 ns
TfD Data falling time(4) 5pF load, SRC=0 2 ns
5pF load, SRC=1 4.3 ns
CLK
OEB
DR
Tdr
AM06133
N - 3
N - 2 N - 1
N+4
N + 5
N
N+ 3
N+1
N+2
N + 6
Tof f
Tpd + Tod
HZ state
N-8N-7 N-6 N
N-5 N-4
N-9 N-3N-1
Data
output
Ton
Tod
RHF1201 Absolute maximum ratings and operating conditions
Doc ID 12585 Rev 5 9/34
6 Absolute maximum ratings and operating conditions
Table 4. Absolute maximum ratings
Symbol Parameter Values Unit
AVCC Analog supply voltage 3.3 V
DVCC Digital supply voltage 3.3 V
VCCBI Digital buffer supply voltage 3.3 V
VCCBE Digital buffer supply voltage 3.6 V
VIN
VINB
Analog inputs: bottom limit −> top limit -0.6 V −> AVCC+0.6 V V
VREFP
VINCM
External references: bottom limit −> top limit -0.6 V −> AVCC+0.6 V V
IDout Digital output current -100 to 100 mA
Tstg Storage temperature -65 to +150 °C
Rthjc Thermal resistance junction to case 22 °C/W
Rthja Thermal resistance junction to ambient 125 °C/W
ESD HBM (human body model)(1)
1. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a
1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations
while the other pins are floating.
2kV
Table 5. Operating conditions
Symbol Parameter Min Typ Max Unit
AVCC Analog supply voltage 2.3 2.5 2.7 V
DVCC Digital supply voltage 2.3 2.5 2.7 V
VCCBI Digital internal buffer supply 2.3 2.5 2.7 V
VCCBE Digital output buffer supply 2.3 2.5 3.4 V
VREFP Top external reference voltage 0.5 1.4 V
VREFM Bottom external reference voltage 0 0.5 V
VINCM Forced common mode voltage 0.2 1.1 V
VIN
VIN maximum voltage versus GND 1.6 V
VIN minimum voltage versus GND -0.2 V
VINB
VINB maximum voltage versus GND 1.6 V
VINB minimum voltage versus GND -0.2 V
DFSB
Digital inputs(1)
1. See Table 9 for thresholds.
GND VCCBE VSRC
OEB
Electrical characteristics (unchanged after 300 kRad) RHF1201
10/34 Doc ID 12585 Rev 5
7 Electrical characteristics (unchanged after 300 kRad)
Unless otherwise specified, the test conditions in the following tables are:
AVCC =DV
CC =V
CCBI =V
CCBE = 2.5 V, FS= 50 Msps, differential input configuration,
Fin =15MHz, V
REFP = internal, VREFM =0V, T
amb = 25° C.
Table 6. Analog inputs
Symbol Parameter Test conditions Min Typ Max Unit
VIN-VINB
Full-scale input differential voltage(1)
(FS)(2) 2V
p-p
Cin Input capacitance 7.0 pF
Rin Input resistance 5 kΩ
ERB Effective resolution bandwidth(1) 95 MHz
1. See Chapter 8: Definitions of specified parameters on page 29 for more information.
2. Optimized differential input: 2 Vp-p. The optimized single-ended input is below 1.5 Vp-p.
Table 7. Internal reference voltage
Symbol Parameter Test conditions Min Typ Max Unit
VREFP Top internal reference voltage(1) AVCC =2.5 V 0.79 0.95 1.16 V
VINCM Input common mode voltage(1) AVCC =2.5 V 0.40 0.52 0.67 V
Te m p C o Temperature coefficient of VREFP(1) Tmin <T
amb <T
max 0.12 mV/°C
Temperature coefficient of INCM(1) Tmin <T
amb <T
max 0.12 mV/°C
1. Not fully tested over the temperature range. Guaranteed by sampling.
Table 8. Accuracy at Fs = 50 Msps
Symbol Parameter Test conditions Min Typ Max Unit
OE Offset error Fin = 2 MHz,
VIN = 1Vp-p +/-0.3 LSB
DNL Differential non-linearity(1) Fin = 2 MHz,
VIN = 1Vp-p +/-0.5 LSB
INL Integral non-linearity(1) Fin = 2 MHz,
VIN = 1Vp-p +/-1.7 LSB
- Monotonicity and no missing codes Guaranteed
1. See Chapter 8 for more information.
RHF1201 Electrical characteristics (unchanged after 300 kRad)
Doc ID 12585 Rev 5 11/34
Table 9. Digital inputs and outputs
Symbol Parameter Test conditions Min Typ Max Unit
Clock input
CT Clock threshold DVCC = 2.5 V 1.25 V
CA Clock amplitude
(DC component = 1.25 V)
Square clock
DVCC = 2.5 V 0.8 2.5 Vp-p
Digital inputs
VIL Logic "0" voltage 0 0.25 x
VCCBE
V
VIH Logic "1" voltage 0.75 x
VCCBE
VCCBE V
Digital outputs
VOL Logic "0" voltage IOL =-1mA 0 0.2 V
VOH Logic "1" voltage IOH =1mA VCCBE
- 0.2 V V
IOZ High impedance leakage current OEB set to VIH -15 15 µA
Table 10. Dynamic characteristics
Symbol Parameter Test conditions Min Typ Max Unit
SFDR Spurious free dynamic range
Fin =15MHz -75 -63 dBc
Fin =95MHz -70
Fin = 145 MHz -57 dBc
SNR Signal to noise ratio
Fin = 15 MHz 59 63 dB
Fin = 95 MHz 60 dB
Fin = 145 MHz 59
THD Total harmonics distortion
Fin =15MHz -76 -64 dB
Fin =95MHz -72 dB
Fin = 145 MHz -58
SINAD Signal to noise and distortion ratio
Fin = 15 MHz 58 63 dB
Fin =95MHz 60
Fin = 145 MHz 56.5 dB
ENOB Effective number of bits
Fin = 15 MHz 9.7 10.3 bits
Fin = 95 MHz 9.5 bits
Fin = 145 MHz 9.1
PSRR Power supply rejection ratio
F = 260 kHz
Fs = 2 MHz
Rpol =200kΩ
each power supply
at 2.5 V decoupled
by 10 µF//470 nF
93 dB
Electrical characteristics (unchanged after 300 kRad) RHF1201
12/34 Doc ID 12585 Rev 5
Figure 12. Differential input configuration
AM04539
Differential
input signal
VIN
VINB
INCM
REFM
REFP
Ground
External or internal
External or
internal
2.5 V
VCCBE
VCCBI
AVCC
DVCC
Figure 13. ENOB vs. diff. input, square clock Figure 14. SINAD vs. diff. input, square clock
1k 10k 100k 1M 10M 100M 1G
6
7
8
9
10
11
Ω
Ω
ΩΩ
ENOB (#bit)
Input Frequency (Hz)
1k 10k 100k 1M 10M 100M 1G
40
50
60
70
Ω
Ω
Ω
Ω
SINAD (dB)
Input Frequency (Hz)
Figure 15. THD vs. diff. input, square clock Figure 16. SNR vs. diff. input, square clock
1k 10k 100k 1M 10M 100M 1G
-90
-80
-70
-60
-50
-40
-30
Ω
Ω
Ω
Ω
THD (dB)
Input Frequency (Hz)
1k 10k 100k 1M 10M 100M 1G
40
50
60
70
Ω
Ω
Ω
Ω
SNR (dB)
Input Frequency (Hz)
RHF1201 Electrical characteristics (unchanged after 300 kRad)
Doc ID 12585 Rev 5 13/34
Figure 17. SFDR vs. diff. input, square clock Figure 18. ENOB vs diff. input, sine clock
1k 10k 100k 1M 10M 100M 1G
-90
-80
-70
-60
-50
-40
-30
Ω
Ω
Ω
Ω
SFDR (dB)
Input Frequency (Hz)
1k 10k 100k 1M 10M 100M 1G
6
7
8
9
10
11
Ω
Ω
ΩΩ
ENOB (#bit)
Input Frequency (Hz)
Figure 19. SINAD vs. diff. input, sine clock Figure 20. THD vs. diff. input, sine clock
1k 10k 100k 1M 10M 100M 1G
35
40
45
50
55
60
65
70
Ω
Ω
Ω
Ω
SINAD (dB)
Input Frequency (Hz)
1k 10k 100k 1M 10M 100M 1G
35
40
45
50
55
60
65
70
75
80
85
Ω
Ω
Ω
Ω
THD (dB)
Input Frequency (Hz)
Figure 21. SNR vs. diff. input, sine clock Figure 22. SFDR vs. diff. input, sine clock
1k 10k 100k 1M 10M 100M 1G
40
45
50
55
60
65
70
75
Ω
Ω
Ω
Ω
SNR (dB)
Input Frequency (Hz)
1k 10k 100k 1M 10M 100M 1G
40
45
50
55
60
65
70
75
80
85
Ω
Ω
Ω
Ω
SNR (dB)
Input Frequency (Hz)
Electrical characteristics (unchanged after 300 kRad) RHF1201
14/34 Doc ID 12585 Rev 5
Figure 23. ENOB vs. square clock, diff. input Figure 24. SINAD vs. square clock, diff. input
1 10 100
6
7
8
9
10
11
ENOB (#bit)
Clock Frequency (Msps)
1 10 100
40
45
50
55
60
65
70
SINAD (dB)
Clock Frequency (Msps)
Figure 25. THD vs. square clock, diff. input Figure 26. SNR vs. square clock, diff. input
1 10 100
50
55
60
65
70
75
80
85
THD (dB)
Clock Frequency (Msps)
1 10 100
40
45
50
55
60
65
70
SNR (dB)
Clock Frequency (Msps)
Figure 27. SFDR vs. square clock, diff. input Figure 28. ENOB vs. sine clock, diff. input
1 10 100
40
45
50
55
60
65
70
SNR (dB)
Clock Frequency (Msps)
1 10 100
6
7
8
9
10
11
ENOB (#bit)
Clock Frequency (Msps)
RHF1201 Electrical characteristics (unchanged after 300 kRad)
Doc ID 12585 Rev 5 15/34
Figure 29. SINAD vs. sine clock, diff. input Figure 30. THD vs. sine clock, diff. input
1 10 100
40
45
50
55
60
65
70
SINAD (dB)
Clock Frequency (Msps)
1 10 100
40
45
50
55
60
65
70
75
80
THD (dB)
Clock Frequency (Msps)
Figure 31. SNR vs. sine clock, diff. input Figure 32. SFDR vs. sine clock, diff. input
1 10 100
40
45
50
55
60
65
70
SNR (dB)
Clock Frequency (Msps)
1 10 100
40
45
50
55
60
65
70
75
80
SFDR (dB)
Clock Frequency (Msps)
Figure 33. Clock threshold vs. temperature Figure 34. ENOB vs. clock duty cycle
-60 -40 -20 0 20 40 60 80 100 120 140
1.22
1.23
1.24
1.25
1.26
1.27
1.28
Clock threshold (V)
Temperature (°C)
0 102030405060708090100
6
7
8
9
10
11 Ω
Ω
ENOB (#bit)
Clock duty cycle (%)
Electrical characteristics (unchanged after 300 kRad) RHF1201
16/34 Doc ID 12585 Rev 5
Figure 35. Output buffer fall time Figure 36. Output buffer rise time
0 5 10 15 20 25 30 35 40 45 50
0
5
10
15
20
25
30
fall time (ns)
capa-load (pF)
0 5 10 15 20 25 30 35 40 45 50
0
5
10
15
20
25
30
rise time (ns)
capa-load (pF)
RHF1201 Electrical characteristics (unchanged after 300 kRad)
Doc ID 12585 Rev 5 17/34
Figure 37. Single-ended input configuration
AM04540
Single-ended
input signal
Ground
External or internal
External or
internal
2.5 V
VIN
VINB
INCM
REFM
REFP
VCCBE
VCCBI
AVCC
DVCC
SRC
Figure 38. ENOB vs. Fin, single-ended Figure 39. SINAD vs. Fin, single-ended
1k 10k 100k 1M 10M 100M 1G
6
7
8
9
10
11
Ω
Ω
Ω
ENOB (#bit)
Input Frequency (Hz)
1k 10k 100k 1M 10M 100M 1G
35
40
45
50
55
60
65
70
Ω
ΩΩ
SINAD (dB)
Input Frequency (Hz)
Figure 40. THD vs. Fin, single-ended Figure 41. SNR vs. Fin, single-ended
1k 10k 100k 1M 10M 100M 1G
35
40
45
50
55
60
65
70
75
80
Ω
Ω
Ω
THD (dB)
Input Frequency (Hz)
1k 10k 100k 1M 10M 100M 1G
30
35
40
45
50
55
60
65
70
Ω
Ω
Ω
SNR (dBc)
Input Frequency (Hz)
Electrical characteristics (unchanged after 300 kRad) RHF1201
18/34 Doc ID 12585 Rev 5
Figure 42. SFDR vs. Fin, single-ended Figure 43. ENOB vs. Vin, single-ended
1k 10k 100k 1M 10M 100M 1G
45
50
55
60
65
70
75
80
85
Ω
Ω
Ω
SFDR (dB)
Input Frequency (Hz)
0.2 0.4 0.6 0.8 1.0 1.2 1.4
6
7
8
9
10
11
ENOB (#bit)
Vin peak-peak (V)
Figure 44. ENOB vs. INCM, single-ended Figure 45. ENOB vs. Vin min, single-ended
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
5
6
7
8
9
10
11
ENOB (#bit)
INCM (V)
-0.2 -0.1 0.0 0.1 0.2
3
4
5
6
7
8
9
10
11
ENOB (#bit)
Vin min (V)
RHF1201 Electrical characteristics (unchanged after 300 kRad)
Doc ID 12585 Rev 5 19/34
7.1 RHF1201 operating modes
Extra functionalities are provided to simplify the application board as much as possible. The
operating modes offered by the RHF1201 are described in Ta bl e 1 1 .
7.1.1 Inputs
Data format select (DFSB): when set to low level (VIL), the digital input DFSB provides a
two’s complement digital output MSB. This can be of interest when performing some further
signal processing. When set to high level (VIH), DFSB provides a standard binary output
coding.
Output enable (OEB): when set to low level (VIL), all digital outputs remain active. When
set to high level (VIH), all digital output buffers are in high impedance state while the
converter goes on sampling. When OEB is set to a low level again, the data arrives on the
output with a very short Ton delay. This feature enables the chip select of the device.
Figure 11 on page 8 summarizes this functionality.
Slew rate control (SRC): when set to high level (VIH), all digital output currents are limited
to a clamp value so that any digital noise power is reduced to the minimum. When set to low
level (VIL), the output edges are twice as fast.
Table 11. RHF1201 operating modes
Inputs Outputs
Analog input
differential amplitude DFSB OEB SRC OR DR Most significant bit
(MSB)
(VIN-VINB) above
maximum range
HLXH CLK D11
L L X H CLK D11 complemented
(VIN-VINB) below
minimum range
HLXH CLK D11
L L X H CLK D11 complemented
(VIN-VINB) within range HLXL CLK D11
L L X L CLK D11 complemented
X X H X High Impedance
XXLHX
CLK
low slew rate Low slew rate
XXLLX
CLK
high slew rate High slew rate
Electrical characteristics (unchanged after 300 kRad) RHF1201
20/34 Doc ID 12585 Rev 5
7.1.2 Outputs
Out-of-range (OR): this function is implemented at the output stage to automatically detect
any digital data that is over the full-scale range. For data within the range, OR remains in a
low-level state (VOL), but switches to a high-level state (VOH) as soon as out-of-range data is
detected.
Data ready (DR): the data ready output is an image of the clock being synchronized on the
output data (D0 to D11). This is a very helpful signal that simplifies the synchronization of
the measurement equipment or of the controlling DSP.
As all other digital outputs, DR and OR go into a high impedance state when OEB is set to
high level, as shown in Figure 11 on page 8.
RHF1201 Electrical characteristics (unchanged after 300 kRad)
Doc ID 12585 Rev 5 21/34
7.2 Driving the analog input
Figure 46. Equivalent VIN - VINB (differential input)
Figure 47. Maximum input swing on each VIN or VINB input
Figure 48. Optimized single-ended configuration at VREFP = 1 V (DC coupling)
AM04541
INCM (level 0, code 2047)
(level - FS, code 0)
(level +FS, code 4095)
FS (full-scale)
= 2(VREFP - VREFM)
VIN
VINB
VIN -VINB
AM04542
+1.6 V (high input max)
0 V (ground)
- 0.2 V (low input min)
AM04543
VIN
VINB
External
VIN
INCM
Ground
INCM
VIN -VINB
REFM
+1.6 V (high input max)
INCM
0 V (ground)
- 0.2 V (low input min)
Vp -p
REFP
External
Electrical characteristics (unchanged after 300 kRad) RHF1201
22/34 Doc ID 12585 Rev 5
The RHF1201 is designed for use in a differential input configuration. Nevertheless, it can
achieve good performance in a single-ended input configuration. In single-ended, a good-
quality conversion can be achieved by using an input amplitude up to 1.4 Vp-p with external
references INCM and VREFP (see Figure 38 on page 17).
Figure 49. 2 Vp-p differential input
The RHF1201 is designed to obtain optimum performance when driven on differential inputs
with a differential amplitude of 2 V peak-to-peak (2 Vp-p). This is the result of 1 Vp-p on the
VIN and VINB inputs in phase opposition.
The RHF1201 is specifically designed to meet sampling requirements for IF, intermediate
frequency input signals. In particular, the track-and-hold in the first stage of the pipeline is
designed to minimize the linearity limitations as the analog frequency increases. This is
achieved by making the input impedance independent of the input frequency.
Figure 50 on page 23 shows a differential input solution. The input signal is fed to the
transformer’s primary, while the secondary drives both ADC inputs. The transformer must be
50 Ω matched (for proper matching with a 50 Ω generator), and it must be loaded with 50 Ω
on the secondary, as close as the ADC. Tracks between the secondary and VIN and VINB
pins must be as short as possible.
The common mode voltage of the ADC (INCM) is connected to the center tap of the
transformer’s secondary in order to bias the input signal around this common voltage,
internally set to 0.52 V (see Table 7 on page 10).The INCM is decoupled to maintain a low
noise level on this node. Ceramic technology for decoupling provides good capacitor
stability across a wide bandwidth.
AM04544
VIN
VINB
1 Vp -p
INCM
(Internal
or external)
1 Vp -p
Ground
REFP
REFM
INCM
VIN -VINB (2 Vp-p)
1 V
RHF1201 Electrical characteristics (unchanged after 300 kRad)
Doc ID 12585 Rev 5 23/34
Figure 50. Differential implementation using a balun
Figure 51. Single-to-differential implementation with op-amps
With (Vout-diff) = (2R2/R1) x (Vin-single) and the following conditions on resistors:
R1/(R1+R2) = R3/(R3+R4) and R4/(R6+R4) = (R5+R2)/R1 (refer to the RHF310-330-350
datasheet for the choice of R2).
Some applications may require a single-ended input, which can easily be achieved with the
configuration shown in Figure 52. However, with this type of configuration a degradation in
the rated performance of the RHF1201 may occur, compared to a differential configuration.
To avoid this, a sufficiently decoupled DC reference should be used to bias the RHF1201
inputs. One may also use an AC-coupled analog input and set the DC analog level with a
high value resistor R (10 kΩ to 100 kΩ) connected to a proper DC source.
AM04545
100 nF* ceramic
(as close as
possible to
INCM pin)
50 Ω
100 pF
ADT1 -1
1:1
Analog input signal
50 Ω track Short track
470 nF* ceramic
(as close as possible
to the transformer)
External
INCM
(optional)
*the use of a ceramic technology is
preferable for a large bandwidth
stability of the capacitor
VIN
VINB
INCM
RHF1201
REFM
REFP
Ground
(50 Ω output)
AM06134
External INCM
(optional)
VIN
VINB
INCM
RHF1201
REFM
REFP
Ground
RHF310
RHF330
RHF350
R4
R2
R5
+
Vin - single
GND
R3
R1
R6
R2
R4
INCM
-Vinpp x R2/R1
GND
Riso
Riso
0 V
INCM
_
RHF310
RHF330
RHF350
+
_
Vinpp
+Vinpp
x R2/R1
1 V
2 Vpp
Electrical characteristics (unchanged after 300 kRad) RHF1201
24/34 Doc ID 12585 Rev 5
Cin and R behave like a high-pass filter and are calculated to set the lowest possible cut-off
frequency. An example of VINB decoupling to reduce noise is shown in Figure 52.
Figure 52. AC-coupling single-ended input configuration
Figure 53. AC-coupling single-ended input configuration for low frequencies
The C capacitor (in the range of 33 pF for example) is dedicated to a low input frequency
range. This capacitor is efficient in reducing noise at higher frequencies. When coupled with
the resistors, R and C together behave like a high-pass filter. For example, if R = 10 k and
C = 33 pF, the cut-off frequency of this filter equals 482 kHz.
AM04546
100 nF ceramic*
(as close as possible
to INCM pin)
R
Cin
Short track
50 Ω
External INCM
(optional)
R
VIN
VINB
INCM RHF1201
Short track
470 pF
ceramic*
100 nF
ceramic*
*the use of a ceramic technology is
preferable for a large bandwidth
stability of the capacitor
Analog input signal
(50 Ω output)
50 Ω track
AM04547
100 nF ceramic*
(as close as possible
to INCM pin)
R
Short track
50 Ω
External INCM
(optional)
*ceramic technology for a large
bandwidth stability of the capacitor
R
VIN
VINB
INCM RHF1201
Short track
C
Analog input signal
(50 Ω output)
50 Ω track
RHF1201 Electrical characteristics (unchanged after 300 kRad)
Doc ID 12585 Rev 5 25/34
7.3 Reference connection
7.3.1 Internal reference
In the standard configuration, the ADC is biased with the internal reference voltage. The
VREFM pin is connected to analog ground while VREFP is internally set to a voltage close to
1.0 V. VREFP should be decoupled so as to minimize low and high frequency noise.
Figure 54 shows the schematics.
Figure 54. Internal reference setting
7.3.2 External reference
An external reference voltage can be used for specific applications requiring even better
linearity or enhanced temperature behavior. In such cases, the amplitude of the external
voltage must be at least equal to the internal reference (see Table 7: Internal reference
voltage on page 10). An external voltage reference with the configuration shown in
Figure 55 and Figure 56 can be used to obtain optimum performance. Decoupling is
achieved by using ceramic capacitors, which provide optimum linearity versus frequency.
Note: * The use of ceramic technology is preferable for large bandwidth stability of the capacitor.
AM04548
470 nF*
100 nF*
VIN
VINB
VREFM
VREFP
RHF1201
As close as possible
the ADC pins
*the use of a ceramic technology is
preferable for a large bandwidth
stability of the capacitor.
Figure 55. External reference setting Figure 56. Example with a zener
AM04549
470 nF*
100 nF*
VIN
VINB
VREFM
VCCA VREFP
As close as possible
the ADC pins
DC
source
AM04550
470 nF*
100 nF*
VIN
VINB
VREFM
VCCA VREFP
R
As close as possible
the ADC pins
Electrical characteristics (unchanged after 300 kRad) RHF1201
26/34 Doc ID 12585 Rev 5
7.4 Clock input
The quality of the converter very much depends on the accuracy of the clock input in terms
of jitter. The use of a low jitter, crystal-controlled oscillator is recommended.
The following points should also be considered.
●At 45 Msps, the duty cycle must be between 45% and 65%.
●The clock power supplies must be independent of the ADC output supplies to avoid
digital noise modulation on the output.
●When powered-on, the circuit needs several clock periods to reach its normal operating
conditions.
●The clock input is a MOS input. To bias this input stage properly, a bias current of 10 nA
is sufficient.
Figure 57. Clock input schematic
The signal applied to the CLK pin is critical to obtain full performance from the RHF1201.
We recommend using a 0 to 2.5 V square signal with fast transition times, and to place
proper termination resistors as close as possible to the device.
The sampling instant is determined by the rising edge of the clock signal. The jitter
associated with this instant must be as low as possible to avoid SNR degradation on
fast-moving input signals. To ensure that LSB errors stay below 0.5, the total jitter Tj must
satisfy the following condition for a full-scale input signal.
n being the number of bits.
In most cases, the clock signal jitter is the major contributor of total noise. Therefore,
particular attention should be given to the clock signal when acquiring fast signals with a
low-frequency clock.
AM04551
50 Ω
CLK
DVcc/2
DVcc/2
Square clock
Sine clock Short track
CLK
Short track
50 Ω
50 Ω clock generator
Tj
1
πFin 2n1+
⋅⋅
---------------------------------
<
RHF1201 Electrical characteristics (unchanged after 300 kRad)
Doc ID 12585 Rev 5 27/34
7.5 Power consumption optimization
The internal architecture of the RHF1201 makes it possible to optimize the power
consumption according to the sampling frequency of the application. For this purpose, an
external Rpol resistor is placed between the IPOL pin and the analog ground. Therefore, the
total dissipation can be adjusted across the entire sampling range from 0.5 Msps to
50 Msps to fulfill the requirements of applications where power saving is critical.
For low sampling frequencies, the resistor value may be adjusted to decrease the analog
current without any deterioration of the dynamic performance.
The current consumption Icca, depending on the value of Rpol, is as shown in Figure 58.
Figure 58. Rpol versus Fs
0 102030405060708090
10
100
Rpol (k ) - Icca (mA)
Sampling Frequency, Fs (MHz)
Electrical characteristics (unchanged after 300 kRad) RHF1201
28/34 Doc ID 12585 Rev 5
7.6 Layout precautions
●Use of dedicated analog and digital ground planes on the PCB is recommended for
high-speed circuit applications to provide low parasitic inductance and resistance.
Ground planes under the digital pins and layers should be avoided to minimize parasitic
capacitances.
●The separation of the analog signal from the digital output is mandatory to prevent
noise from coupling onto the input signal.
●Power supply bypass capacitors must be placed as close as possible to the IC pins to
improve high-frequency bypassing and reduce harmonic distortion.
●All leads must be as short as possible, especially for the analog input, so as to
decrease parasitic capacitance and inductance.
●To minimize the transition current when the output changes, the capacitive load at the
digital outputs must be reduced as much as possible by using the shortest-possible
routing tracks.
●Choose the smallest-possible component sizes (SMD).
RHF1201 Definitions of specified parameters
Doc ID 12585 Rev 5 29/34
8 Definitions of specified parameters
8.1 Static parameters
Differential non-linearity (DNL)
The average deviation of any output code width from the ideal code width of 1 LSB.
Integral non-linearity (INL)
An ideal converter exhibits a transfer function which is a straight line from the starting code
to the ending code. The INL is the deviation from this ideal line for each transition.
8.2 Dynamic parameters
Spurious free dynamic range (SFDR)
The ratio between the power of the worst spurious signal (not always a harmonic) and the
amplitude of the fundamental tone (signal power) over the full Nyquist band. Expressed in
dBc.
Total harmonic distortion (THD)
The ratio of the rms sum of the first five harmonic distortion components to the rms value of
the fundamental line. Expressed in dB.
Signal to noise ratio (SNR)
The ratio of the rms value of the fundamental component to the rms sum of all other spectral
components in the Nyquist band (fs/2) excluding DC, fundamental and the first five
harmonics. SNR is reported in dB.
Signal to noise and distortion ratio (SINAD)
Similar ratio as for SNR but including the harmonic distortion components in the noise figure
(not DC signal). Expressed in dB.
The effective number of bits (ENOB) is easily deduced from the SINAD, using the formula:
SINAD = 6.02 × ENOB + 1.76 dB
When the applied signal is not full-scale (FS) but has an amplitude A0, the SINAD
expression becomes:
SINAD = 6.02 × ENOB + 1.76 dB + 20 log (A0/FS)
ENOB is expressed in bits.
Effective resolution bandwidth
For a given sampling rate and clock jitter, this is the analog input frequency at which the
SINAD is reduced by 3 dB, and the ENOB is reduced by 0.5 bits.
Definitions of specified parameters RHF1201
30/34 Doc ID 12585 Rev 5
Pipeline delay
Delay between the initial sample of the analog input and the availability of the corresponding
digital data output on the output bus. Also called data latency, it is expressed as a number of
clock cycles.
When powering off to on, there is a delay of several clock cycles before the ADC can
achieve a reliable and stable signal conversion. During this delay, some conversion artefacts
may appear.
RHF1201 Package information
Doc ID 12585 Rev 5 31/34
9 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 59. Ceramic SO-48 package mechanical drawing
Note: The upper metallic lid is not electrically connected to any pins, nor to the IC die inside the
package. Connecting unused pins or metal lid to ground or to the power supply will not affect
the electrical characteristics.
Package information RHF1201
32/34 Doc ID 12585 Rev 5
Table 12. Ceramic SO-48 package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 2.18 2.47 2.72 0.086 0.097 0.107
b 0.20 0.254 0.30 0.008 0.010 0.012
c 0.12 0.15 0.18 0.005 0.006 0.007
D 15.57 15.75 15.92 0.613 0.620 0.627
E 9.52 9.65 9.78 0.375 0.380 0.385
E1 10.90 0.429
E2 6.22 6.35 6.48 0.245 0.250 0.255
E3 1.52 1.65 1.78 0.060 0.065 0.070
e 0.635 0.025
f 0.20 0.008
L 12.28 12.58 12.88 0.483 0.495 0.507
P 1.30 1.45 1.60 0.051 0.057 0.063
Q 0.66 0.79 0.92 0.026 0.031 0.036
S1 0.25 0.43 0.61 0.010 0.017 0.024
RHF1201 Revision history
Doc ID 12585 Rev 5 33/34
10 Revision history
Table 13. Document revision history
Date Revision Changes
01-Sep-2006 1 Initial release in new format.
29-Jun-2007 2
Updated failure immune and latchup immune value to 120 MeV-
cm2/mg.
Updated package mechanical data.
Removed reference to non rad-hard components from Section 7.3.2:
External reference on page 25.
10-Oct-2008 3
Changed cover page graphic.
Changed Figure 2.
Added Chapter 4: Equivalent circuits.
Added Note 1 under Tabl e 4 .
Expanded Ta b l e 5 with additional parameters.
Modified "Test conditions" and Vrefp/Vincm in Ta b l e 7 .
Improved readability in Ta bl e 1 1 .
Added Figure 46 to Figure 49.
Modified Figure 50 and Figure 52.
Added Figure 53.
Removed IF sampling section.
Modified Figure 54 and Figure 16. Added Figure 58.
Added ECOPACK information and updated presentation in
Chapter 9.
09-Apr-2010 4
Modified description on cover page.
Added Table 1: Device summary on page 1.
Removed RHF1201KSO2 order code from Ta b l e 1 .
Removed Fs and Tck values from Ta b l e 3 .
Added Figure 7 and Figure 8.
Added DFS, OEB and SRC values in Ta bl e 5 .
Changed VINCM values in Ta bl e 5 .
Removed Fin values from Ta ble 5 .
Removed output capacitive load values from Table 9.
Changed clock threshold values in Ta b l e 9 .
Added PSRR values in Ta bl e 1 0 .
Added Figure 13 on page 12 to Figure 45.
Modified Figure 46, Figure 48 and Figure 49.
29-Jul-2011 5 Added Note: on page 31 and in the "Pin connections" diagram on the
coverpage.
RHF1201
34/34 Doc ID 12585 Rev 5
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2011 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
