RHF1201 Rad-hard 12-bit 50 Msps A/D converter Features Ceramic SO-48 package Qml-V qualified, smd 5962-05217 Rad hard: 300 kRad(Si) TID Failure immune (SEFI) and latchup immune (SEL) up to 120 MeV-cm2/mg at 2.7 V and 125 C Hermetic package Wide sampling range Tested at 50 Msps OptimwattTM adaptive power: 44 mW at 0.5 Msps, 100 mW at 50 Msps Optimized for 2 Vpp differential input SFDR up to 75 dB at FS = 50 Msps, Fin = 15 MHz 2.5 V/3.3 V compatible digital I/O Built-in reference voltage with external bias capability Applications Digital communication satellites Space data acquisition systems Aerospace instrumentation Nuclear and high-energy physics Table 1. The upper metallic lid is not electrically connected to any pins, nor to the IC die inside the package. Description The RHF1201 is a 12-bit 50 Msps sampling frequency analog-to-digital converter that uses pure (ELDRS-free) CMOS 0.25 m technology combining high performance, radiation robustness and very low power consumption. The device is based on a pipeline structure and digital error correction to provide excellent static linearity. Specifically designed to optimize the speed power consumption ratio, the RHF1201 integrates a proprietary track-and-hold structure making it ideal for IF-sampling applications up to 150 MHz. A voltage reference network is integrated in the circuit to simplify the design and minimize external components. A tri-state capability is available on the outputs to allow common bus sharing. Output data can be coded in two different formats. A Data Ready signal, raised when the data is valid on the output, can be used for synchronization purposes. Device summary SMD pin Quality level Package - Engineering model SO-48 Gold RHF1201KSO-01V 5962F0521701VXC QMLV-Flight SO-48 Gold Order code (1) RHF1201KSO1 Lead Packing finish Marking EPPL Strip pack RHF1201KSO1 - Strip pack 5962F0521701VXC - 1. Contact your ST sales office for information about the specific conditions for products in die form and for information about SMD packages. July 2011 Doc ID 12585 Rev 5 1/34 www.st.com 34 Contents RHF1201 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 9 7 Electrical characteristics (unchanged after 300 kRad) . . . . . . . . . . . . 10 7.1 8 RHF1201 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1.1 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1.2 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.2 Driving the analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.3 Reference connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.3.1 Internal reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.3.2 External reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.5 Power consumption optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.6 Layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Definitions of specified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1 Static parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2 Dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2/34 Doc ID 12585 Rev 5 RHF1201 1 Block diagram Block diagram Figure 1. Block diagram +2.5 V +2.5 V/3.3 V VREFP GNDA VIN INCM stage 1 stage 2 stage n Reference circuit IPOL VINB VREFM DFSB SRC Sequencer-phase shifting CLK OEB Timing DR Digital data correction D0 Buffers D11 OR GND VCCBI VCCBE AM04529 Doc ID 12585 Rev 5 3/34 Pin connections 2 RHF1201 Pin connections Figure 2. Pin connections (top view) GNDBI GNDBE VCCBE NC NC OR (MSB)D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 (LSB)D0 DR NC NC VCCBE GNDBE VCCBI 4/34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Doc ID 12585 Rev 5 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 DGND DGND CLK DGND DVCC DVCC AVCC AVCC AGND INCM AGND VINB AGND VIN AGND VREFM VREFP IPOL AGND AVCC AVCC DFSB OEB SRC RHF1201 Pin descriptions 3 Pin descriptions Table 2. Pin descriptions Pin Name Description 1 GNDBI Digital buffer ground 2 GNDBE 3 VCCBE Note Pin Name Description Note 0V 25 SRC Slew rate control input 2.5 V/3.3 V CMOS input Digital buffer ground 0V 26 OEB Output Enable input 2.5 V/3.3 V CMOS input Digital buffer power supply 2.5 V/3.3 V 27 DFSB Data Format Select input 2.5 V/3.3 V CMOS input 4 NC Not connected to the dice 28 AVCC Analog power supply 2.5 V 5 NC Not connected to the dice 29 AVCC Analog power supply 2.5 V 0V 6 OR Out-of-range output CMOS output (2.5 V/3.3 V) 30 AGND Analog ground 7 D11(MSB) Most significant bit output CMOS output (2.5 V/3.3 V) 31 IPOL Analog bias current input 8 D10 Digital output CMOS output (2.5 V/3.3 V) 32 VREFP Top voltage reference Can be internal or external 9 D9 Digital output CMOS output (2.5 V/3.3 V) 33 VREFM Bottom voltage reference External 10 D8 Digital output CMOS output (2.5 V/3.3 V) 34 AGND Analog ground 0V 11 D7 Digital output CMOS output (2.5 V/3.3 V) 35 VIN Analog input Optimized for 1Vpp 12 D6 Digital output CMOS output (2.5 V/3.3 V) 36 AGND Analog ground 0V 13 D5 Digital output CMOS output (2.5 V/3.3 V) 37 VINB Inverted analog input Optimized for 1Vpp 14 D4 Digital output CMOS output (2.5 V/3.3 V) 38 AGND Analog ground 0V 15 D3 Digital output CMOS output (2.5 V/3.3 V) 39 INCM Input common mode Can be internal or external 16 D2 Digital output CMOS output (2.5 V/3.3 V) 40 AGND Analog ground 0V 17 D1 Digital output CMOS output (2.5 V/3.3 V) 41 AVCC Analog power supply 2.5 V 18 D0(LSB) Least significant bit output CMOS output (2.5 V/3.3 V) 42 AVCC Analog power supply 2.5 V 19 DR Data ready output CMOS output (2.5 V/3.3 V) 43 DVCC Digital power supply 2.5 V 20 NC Not connected to the dice 44 DVCC Digital power supply 2.5 V 21 NC Not connected to the dice 45 DGND Digital ground 0V Clock input 2.5 V compatible CMOS input 22 VCCBE Digital buffer power supply 2.5 V/3.3 V 46 CLK 23 GNDBE Digital buffer ground 0V 47 DGND Digital ground 0V 24 VCCBI Digital buffer power supply 2.5 V 48 DGND Digital ground 0V Doc ID 12585 Rev 5 5/34 Equivalent circuits RHF1201 4 Equivalent circuits Figure 3. Analog inputs Figure 4. Output buffers VCCBE AVCC OEB VIN or VINB AGND D0 ...D13 Data 7 pF (pad) AVCC 7 pF (pad) AGND AM04530 GNDBE AM04531 Figure 5. Clock input Figure 6. Data format input VCCBE DVCC DFSB CLK 7 pF (pad) 7 pF (pad) GNDBE DGND AM04532 Figure 7. AM04533 Slew rate control input Figure 8. Output enable input VCCBE VCCBE SRC OEB 7 pF (pad) 7 pF (pad) GNDBE GNDBE AM04534 6/34 Doc ID 12585 Rev 5 AM04535 RHF1201 Equivalent circuits Figure 9. VREFP and INCM input AVCC AVCC INCM Input impedance = 50 VREFP Input impedance = 39 7 pF (pad) 7 pF (pad) AGND AGND AM04536 Figure 10. VREFM input AVCC VREFM High input impedance 7 pF (pad) AGND AM04537 Doc ID 12585 Rev 5 7/34 Timing characteristics 5 RHF1201 Timing characteristics Table 3. Timing table Symbol DC Parameter Test conditions Clock duty cycle(1) Min Typ Max Unit FS = 45 Msps 45 50 65 % 10 pF load 4 5 6 ns 5.5 5.5 5.5 cycles (2) Tod Data output delay (fall of clock to data valid) Tpd Data pipeline delay (2) Tdr Data ready rising edge delay Duty cycle = 50% after data change (3) Ton Falling edge of OEB to digital output valid data 1 3 ns Toff Rising edge of OEB to digital output tri-state 1 3 ns TrD Data rising time(4) TfD Data falling time(4) 0.5 cycles 5 pF load, SRC = 0 2.8 ns 5 pF load, SRC = 1 5.7 ns 5 pF load, SRC = 0 2 ns 5 pF load, SRC = 1 4.3 ns 1. See Figure 34. 2. Guaranteed by design. 3. Tdr is linked to the duty cycle, conditioned by the duration of the low level of DR signal. 4. See Figure 35 and Figure 36. Figure 11. Timing diagram N+2 N+ 3 N+4 N+1 N +5 N N -3 N -1 N -2 N +6 CLK Tdr Tpd + Tod OEB Tod Data output Tof f N-9 N -8 N -7 N -6 N -5 N -4 Ton N -1 N -3 N DR HZ state AM06133 The input signal is sampled on the rising edge of the clock while the digital outputs are synchronized on the falling edge of the clock. The duty cycles on DR and CLK are the same. 8/34 Doc ID 12585 Rev 5 RHF1201 6 Absolute maximum ratings and operating conditions Absolute maximum ratings and operating conditions Table 4. Absolute maximum ratings Symbol Parameter Values Unit AVCC Analog supply voltage 3.3 V DVCC Digital supply voltage 3.3 V VCCBI Digital buffer supply voltage 3.3 V VCCBE Digital buffer supply voltage 3.6 V Analog inputs: bottom limit -> top limit -0.6 V -> AVCC+0.6 V V External references: bottom limit -> top limit -0.6 V -> AVCC+0.6 V V VIN VINB VREFP VINCM IDout Digital output current -100 to 100 mA Tstg Storage temperature -65 to +150 C Rthjc Thermal resistance junction to case 22 C/W Rthja Thermal resistance junction to ambient 125 C/W 2 kV ESD HBM (human body model)(1) 1. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5 k resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating. Table 5. Operating conditions Symbol Parameter Min Typ Max Unit AVCC Analog supply voltage 2.3 2.5 2.7 V DVCC Digital supply voltage 2.3 2.5 2.7 V VCCBI Digital internal buffer supply 2.3 2.5 2.7 V VCCBE Digital output buffer supply 2.3 2.5 3.4 V VREFP Top external reference voltage 0.5 1.4 V VREFM Bottom external reference voltage 0 0.5 V VINCM Forced common mode voltage 0.2 1.1 V VIN VINB VIN maximum voltage versus GND 1.6 V VIN minimum voltage versus GND -0.2 V VINB maximum voltage versus GND 1.6 V VINB minimum voltage versus GND -0.2 V DFSB SRC Digital inputs(1) GND VCCBE V OEB 1. See Table 9 for thresholds. Doc ID 12585 Rev 5 9/34 Electrical characteristics (unchanged after 300 kRad) 7 RHF1201 Electrical characteristics (unchanged after 300 kRad) Unless otherwise specified, the test conditions in the following tables are: AVCC = DVCC = VCCBI = VCCBE = 2.5 V, FS = 50 Msps, differential input configuration, Fin = 15 MHz, VREFP = internal, VREFM = 0 V, Tamb = 25 C. Table 6. Analog inputs Symbol VIN-VINB Parameter Full-scale input differential voltage (FS)(2) Cin Input capacitance Rin Input resistance ERB Test conditions Effective resolution bandwidth Min Typ Max Unit (1) (1) 2 Vp-p 7.0 pF 5 k 95 MHz 1. See Chapter 8: Definitions of specified parameters on page 29 for more information. 2. Optimized differential input: 2 Vp-p. The optimized single-ended input is below 1.5 Vp-p. Table 7. Internal reference voltage Symbol Parameter Test conditions VREFP Top internal reference voltage(1) VINCM Input common mode voltage(1) TempCo Temperature coefficient of VREFP Temperature coefficient of (1) INCM(1) Min Typ Max Unit AVCC =2.5 V 0.79 0.95 1.16 V AVCC =2.5 V 0.40 0.52 0.67 V Tmin < Tamb < Tmax 0.12 mV/C Tmin < Tamb < Tmax 0.12 mV/C 1. Not fully tested over the temperature range. Guaranteed by sampling. Table 8. Accuracy at Fs = 50 Msps Symbol Parameter Test conditions Min Typ Max Unit OE Offset error Fin = 2 MHz, VIN = 1Vp-p +/-0.3 LSB DNL Differential non-linearity(1) Fin = 2 MHz, VIN = 1Vp-p +/-0.5 LSB INL Integral non-linearity(1) Fin = 2 MHz, VIN = 1Vp-p +/-1.7 LSB - Monotonicity and no missing codes 1. See Chapter 8 for more information. 10/34 Doc ID 12585 Rev 5 Guaranteed RHF1201 Table 9. Electrical characteristics (unchanged after 300 kRad) Digital inputs and outputs Symbol Parameter Test conditions Min Typ Max Unit Clock input CT Clock threshold DVCC = 2.5 V CA Clock amplitude (DC component = 1.25 V) Square clock DVCC = 2.5 V 1.25 0.8 V 2.5 Vp-p 0.25 x VCCBE V Digital inputs VIL Logic "0" voltage VIH Logic "1" voltage 0 0.75 x VCCBE VCCBE V Digital outputs VOL Logic "0" voltage IOL = -1 mA VOH Logic "1" voltage IOH = 1 mA IOZ High impedance leakage current OEB set to VIH Table 10. Symbol SFDR THD PSRR V -15 Typ Max Unit Fin = 15 MHz -75 -63 dBc Fin = 95 MHz -70 Fin = 145 MHz -57 dBc 63 dB Fin = 95 MHz 60 dB Fin = 145 MHz 59 Fin = 15 MHz -76 Fin = 95 MHz -72 Fin = 145 MHz -58 Dynamic characteristics Parameter Test conditions Spurious free dynamic range Signal to noise ratio Total harmonics distortion Signal to noise and distortion ratio Effective number of bits Power supply rejection ratio Min 59 58 63 -64 dB dB dB Fin = 95 MHz 60 Fin = 145 MHz 56.5 dB 10.3 bits Fin = 95 MHz 9.5 bits Fin = 145 MHz 9.1 F = 260 kHz Fs = 2 MHz Rpol = 200 k each power supply at 2.5 V decoupled by 10 F//470 nF 93 Fin = 15 MHz ENOB VCCBE - 0.2 V V A Fin = 15 MHz SINAD 0.2 15 Fin = 15 MHz SNR 0 Doc ID 12585 Rev 5 9.7 dB 11/34 Electrical characteristics (unchanged after 300 kRad) RHF1201 Figure 12. Differential input configuration 2.5 V VIN Differential input signal VCCBE VCCBI AVCC DVCC External or internal REFP INCM VINB REFM External or internal Ground AM04539 Figure 13. ENOB vs. diff. input, square clock Figure 14. SINAD vs. diff. input, square clock 70 11 60 SINAD (dB) ENOB (#bit) 10 9 8 50 7 6 1k 10k 100k 1M 10M 100M 40 1k 1G 10k Input Frequency (Hz) 100k 1M 10M 100M 1G Input Frequency (Hz) Figure 15. THD vs. diff. input, square clock Figure 16. SNR vs. diff. input, square clock 70 -30 -40 60 SNR (dB) THD (dB) -50 -60 50 -70 -80 -90 1k 10k 100k 1M 10M 100M 1G 40 1k Input Frequency (Hz) 12/34 10k 100k 1M 10M Input Frequency (Hz) Doc ID 12585 Rev 5 100M 1G RHF1201 Electrical characteristics (unchanged after 300 kRad) Figure 17. SFDR vs. diff. input, square clock Figure 18. ENOB vs diff. input, sine clock -30 11 -40 10 ENOB (#bit) SFDR (dB) -50 -60 -70 8 7 -80 -90 1k 9 10k 100k 1M 10M 100M 6 1k 1G 10k 100k 1M 10M 100M 1G Input Frequency (Hz) Input Frequency (Hz) Figure 19. SINAD vs. diff. input, sine clock Figure 20. THD vs. diff. input, sine clock 85 70 80 65 75 55 70 THD (dB) SINAD (dB) 60 50 65 60 55 50 45 45 40 40 35 1k 10k 100k 1M 10M 100M 35 1k 1G 10k 100k Input Frequency (Hz) 1M 10M 100M 1G Input Frequency (Hz) Figure 21. SNR vs. diff. input, sine clock Figure 22. SFDR vs. diff. input, sine clock 75 85 70 80 75 65 SNR (dB) SNR (dB) 70 60 55 65 60 55 50 40 1k 50 45 45 10k 100k 1M 10M 100M 1G 40 1k Input Frequency (Hz) 10k 100k 1M 10M 100M 1G Input Frequency (Hz) Doc ID 12585 Rev 5 13/34 Electrical characteristics (unchanged after 300 kRad) Figure 23. ENOB vs. square clock, diff. input RHF1201 Figure 24. SINAD vs. square clock, diff. input 70 11 65 60 SINAD (dB) ENOB (#bit) 10 9 8 7 55 50 45 6 40 1 10 100 1 Clock Frequency (Msps) 10 100 Clock Frequency (Msps) Figure 25. THD vs. square clock, diff. input Figure 26. SNR vs. square clock, diff. input 85 70 80 65 75 SNR (dB) THD (dB) 60 70 65 55 50 60 45 55 50 40 1 10 100 1 Clock Frequency (Msps) 10 100 Clock Frequency (Msps) Figure 27. SFDR vs. square clock, diff. input Figure 28. ENOB vs. sine clock, diff. input 70 11 65 10 ENOB (#bit) SNR (dB) 60 55 50 9 8 7 45 6 40 1 10 100 1 14/34 10 Clock Frequency (Msps) Clock Frequency (Msps) Doc ID 12585 Rev 5 100 RHF1201 Electrical characteristics (unchanged after 300 kRad) Figure 29. SINAD vs. sine clock, diff. input Figure 30. THD vs. sine clock, diff. input 80 70 75 65 70 THD (dB) SINAD (dB) 60 55 65 60 55 50 50 45 45 40 40 1 10 1 100 10 Clock Frequency (Msps) 100 Clock Frequency (Msps) Figure 31. SNR vs. sine clock, diff. input Figure 32. SFDR vs. sine clock, diff. input 80 70 75 65 70 SFDR (dB) SNR (dB) 60 55 65 60 55 50 50 45 45 40 40 1 10 100 1 10 Clock Frequency (Msps) 100 Clock Frequency (Msps) Figure 33. Clock threshold vs. temperature Figure 34. ENOB vs. clock duty cycle 1.28 11 10 1.26 ENOB (#bit) Clock threshold (V) 1.27 1.25 1.24 9 8 7 1.23 1.22 -60 6 -40 -20 0 20 40 60 80 100 120 140 0 10 20 30 40 50 60 70 80 90 100 Clock duty cycle (%) Temperature (C) Doc ID 12585 Rev 5 15/34 Electrical characteristics (unchanged after 300 kRad) Figure 36. Output buffer rise time 30 30 25 25 20 20 rise time (ns) fall time (ns) Figure 35. Output buffer fall time RHF1201 15 10 5 15 10 5 0 0 0 5 10 15 20 25 30 35 40 45 50 0 capa-load (pF) 16/34 5 10 15 20 25 30 capa-load (pF) Doc ID 12585 Rev 5 35 40 45 50 RHF1201 Electrical characteristics (unchanged after 300 kRad) Figure 37. Single-ended input configuration External or internal 2.5 V Single-ended input signal VCCBE VCCBI AVCC DVCC VIN REFP INCM VINB SRC REFM External or internal Ground AM04540 Figure 38. ENOB vs. Fin, single-ended Figure 39. SINAD vs. Fin, single-ended 70 11 65 60 SINAD (dB) ENOB (#bit) 10 9 8 55 50 45 7 40 6 1k 10k 100k 1M 10M 100M 35 1k 1G 10k Input Frequency (Hz) 100k 1M 10M 100M 1G Input Frequency (Hz) Figure 40. THD vs. Fin, single-ended Figure 41. SNR vs. Fin, single-ended 70 80 75 65 70 60 SNR (dBc) THD (dB) 65 60 55 55 50 45 50 40 45 35 40 35 1k 10k 100k 1M 10M 100M 1G 30 1k Input Frequency (Hz) 10k 100k 1M 10M 100M 1G Input Frequency (Hz) Doc ID 12585 Rev 5 17/34 Electrical characteristics (unchanged after 300 kRad) Figure 42. SFDR vs. Fin, single-ended RHF1201 Figure 43. ENOB vs. Vin, single-ended 85 11 80 10 70 ENOB (#bit) SFDR (dB) 75 65 60 9 8 55 7 50 45 1k 10k 100k 1M 10M 100M 6 0.2 1G 0.4 0.6 0.8 1.0 1.2 1.4 Vin peak-peak (V) Input Frequency (Hz) Figure 44. ENOB vs. INCM, single-ended Figure 45. ENOB vs. Vin min, single-ended 11 11 10 9 ENOB (#bit) ENOB (#bit) 10 9 8 8 7 6 7 5 6 5 0.3 4 0.4 0.5 0.6 0.7 0.8 0.9 1.0 3 -0.2 INCM (V) 18/34 -0.1 0.0 Vin min (V) Doc ID 12585 Rev 5 0.1 0.2 RHF1201 7.1 Electrical characteristics (unchanged after 300 kRad) RHF1201 operating modes Extra functionalities are provided to simplify the application board as much as possible. The operating modes offered by the RHF1201 are described in Table 11. Table 11. RHF1201 operating modes Inputs Analog input differential amplitude DFSB OEB SRC OR DR Most significant bit (MSB) (VIN-VINB) above maximum range H L X H CLK D11 L L X H CLK D11 complemented (VIN-VINB) below minimum range H L X H CLK D11 L L X H CLK D11 complemented H L X L CLK D11 L L X L CLK D11 complemented X X H X X X L H X CLK low slew rate Low slew rate X X L L X CLK high slew rate High slew rate (VIN-VINB) within range 7.1.1 Outputs High Impedance Inputs Data format select (DFSB): when set to low level (VIL), the digital input DFSB provides a two's complement digital output MSB. This can be of interest when performing some further signal processing. When set to high level (VIH), DFSB provides a standard binary output coding. Output enable (OEB): when set to low level (VIL), all digital outputs remain active. When set to high level (VIH), all digital output buffers are in high impedance state while the converter goes on sampling. When OEB is set to a low level again, the data arrives on the output with a very short Ton delay. This feature enables the chip select of the device. Figure 11 on page 8 summarizes this functionality. Slew rate control (SRC): when set to high level (VIH), all digital output currents are limited to a clamp value so that any digital noise power is reduced to the minimum. When set to low level (VIL), the output edges are twice as fast. Doc ID 12585 Rev 5 19/34 Electrical characteristics (unchanged after 300 kRad) 7.1.2 RHF1201 Outputs Out-of-range (OR): this function is implemented at the output stage to automatically detect any digital data that is over the full-scale range. For data within the range, OR remains in a low-level state (VOL), but switches to a high-level state (VOH) as soon as out-of-range data is detected. Data ready (DR): the data ready output is an image of the clock being synchronized on the output data (D0 to D11). This is a very helpful signal that simplifies the synchronization of the measurement equipment or of the controlling DSP. As all other digital outputs, DR and OR go into a high impedance state when OEB is set to high level, as shown in Figure 11 on page 8. 20/34 Doc ID 12585 Rev 5 RHF1201 7.2 Electrical characteristics (unchanged after 300 kRad) Driving the analog input Figure 46. Equivalent VIN - VINB (differential input) VIN -VINB (level +FS, code 4095) VIN FS (full-scale) = 2(VREFP - VREFM) INCM (level 0, code 2047) VINB (level - FS, code 0) AM04541 Figure 47. Maximum input swing on each VIN or VINB input +1.6 V (high input max) 0 V (ground) - 0.2 V (low input min) AM04542 Figure 48. Optimized single-ended configuration at VREFP = 1 V (DC coupling) VIN External +1.6 V (high input max) REFP VIN INCM Vp -p 0 V (ground) VINB - 0.2 V (low input min) INCM REFM Ground VIN -VINB External INCM AM04543 Doc ID 12585 Rev 5 21/34 Electrical characteristics (unchanged after 300 kRad) RHF1201 The RHF1201 is designed for use in a differential input configuration. Nevertheless, it can achieve good performance in a single-ended input configuration. In single-ended, a goodquality conversion can be achieved by using an input amplitude up to 1.4 Vp-p with external references INCM and VREFP (see Figure 38 on page 17). Figure 49. 2 Vp-p differential input 1V 1 Vp -p 1 Vp -p REFP VIN VINB INCM (Internal or external) REFM Ground VIN -VINB (2 Vp-p) INCM AM04544 The RHF1201 is designed to obtain optimum performance when driven on differential inputs with a differential amplitude of 2 V peak-to-peak (2 Vp-p). This is the result of 1 Vp-p on the VIN and VINB inputs in phase opposition. The RHF1201 is specifically designed to meet sampling requirements for IF, intermediate frequency input signals. In particular, the track-and-hold in the first stage of the pipeline is designed to minimize the linearity limitations as the analog frequency increases. This is achieved by making the input impedance independent of the input frequency. Figure 50 on page 23 shows a differential input solution. The input signal is fed to the transformer's primary, while the secondary drives both ADC inputs. The transformer must be 50 matched (for proper matching with a 50 generator), and it must be loaded with 50 on the secondary, as close as the ADC. Tracks between the secondary and VIN and VINB pins must be as short as possible. The common mode voltage of the ADC (INCM) is connected to the center tap of the transformer's secondary in order to bias the input signal around this common voltage, internally set to 0.52 V (see Table 7 on page 10).The INCM is decoupled to maintain a low noise level on this node. Ceramic technology for decoupling provides good capacitor stability across a wide bandwidth. 22/34 Doc ID 12585 Rev 5 RHF1201 Electrical characteristics (unchanged after 300 kRad) Figure 50. Differential implementation using a balun 50 track ADT1 -1 1:1 Short track Analog input signal (50 output) 100 pF REFP VIN 50 RHF1201 VINB REFM Ground INCM 470 nF* ceramic (as close as possible to the transformer) 100 nF* ceramic (as close as possible to INCM pin) External INCM (optional) *the use of a ceramic technology is preferable for a large bandwidth stability of the capacitor AM04545 Figure 51. Single-to-differential implementation with op-amps R2 R1 Vin - single Vinpp _ 0V RHF310 RHF330 RHF350 + GND Riso 1V -Vinpp x R2/R1 R3 REFP INCM VIN R4 2 Vpp R6 +Vinpp x R2/R1 + R5 RHF1201 R4 INCM RHF310 RHF330 RHF350 _ GND R2 VINB REFM INCM Ground Riso External INCM (optional) AM06134 With (Vout-diff) = (2R2/R1) x (Vin-single) and the following conditions on resistors: R1/(R1+R2) = R3/(R3+R4) and R4/(R6+R4) = (R5+R2)/R1 (refer to the RHF310-330-350 datasheet for the choice of R2). Some applications may require a single-ended input, which can easily be achieved with the configuration shown in Figure 52. However, with this type of configuration a degradation in the rated performance of the RHF1201 may occur, compared to a differential configuration. To avoid this, a sufficiently decoupled DC reference should be used to bias the RHF1201 inputs. One may also use an AC-coupled analog input and set the DC analog level with a high value resistor R (10 k to 100 k) connected to a proper DC source. Doc ID 12585 Rev 5 23/34 Electrical characteristics (unchanged after 300 kRad) RHF1201 Cin and R behave like a high-pass filter and are calculated to set the lowest possible cut-off frequency. An example of VINB decoupling to reduce noise is shown in Figure 52. Figure 52. AC-coupling single-ended input configuration Cin Short track 50 track Analog input signal (50 output) VIN 50 R INCM RHF1201 R VINB Short track 470 pF ceramic* 100 nF ceramic* External INCM (optional) 100 nF ceramic* (as close as possible to INCM pin) *the use of a ceramic technology is preferable for a large bandwidth stability of the capacitor AM04546 Figure 53. AC-coupling single-ended input configuration for low frequencies 50 track Analog input signal (50 output) Short track 50 VIN R C INCM RHF1201 R VINB Short track *ceramic technology for a large bandwidth stability of the capacitor External INCM (optional) 100 nF ceramic* (as close as possible to INCM pin) AM04547 The C capacitor (in the range of 33 pF for example) is dedicated to a low input frequency range. This capacitor is efficient in reducing noise at higher frequencies. When coupled with the resistors, R and C together behave like a high-pass filter. For example, if R = 10 k and C = 33 pF, the cut-off frequency of this filter equals 482 kHz. 24/34 Doc ID 12585 Rev 5 RHF1201 Electrical characteristics (unchanged after 300 kRad) 7.3 Reference connection 7.3.1 Internal reference In the standard configuration, the ADC is biased with the internal reference voltage. The VREFM pin is connected to analog ground while VREFP is internally set to a voltage close to 1.0 V. VREFP should be decoupled so as to minimize low and high frequency noise. Figure 54 shows the schematics. Figure 54. Internal reference setting As close as possible the ADC pins 100 nF* 470 nF* VREFP VIN RHF1201 VINB VREFM *the use of a ceramic technology is preferable for a large bandwidth stability of the capacitor. AM04548 7.3.2 External reference An external reference voltage can be used for specific applications requiring even better linearity or enhanced temperature behavior. In such cases, the amplitude of the external voltage must be at least equal to the internal reference (see Table 7: Internal reference voltage on page 10). An external voltage reference with the configuration shown in Figure 55 and Figure 56 can be used to obtain optimum performance. Decoupling is achieved by using ceramic capacitors, which provide optimum linearity versus frequency. Figure 55. External reference setting Figure 56. Example with a zener As close as possible the ADC pins 100 nF* VCCA 470 nF* As close as possible the ADC pins R DC source 100 nF* VREFP VCCA VIN 470 nF* VREFP VIN VINB VINB VREFM VREFM AM04549 AM04550 Note: * The use of ceramic technology is preferable for large bandwidth stability of the capacitor. Doc ID 12585 Rev 5 25/34 Electrical characteristics (unchanged after 300 kRad) 7.4 RHF1201 Clock input The quality of the converter very much depends on the accuracy of the clock input in terms of jitter. The use of a low jitter, crystal-controlled oscillator is recommended. The following points should also be considered. At 45 Msps, the duty cycle must be between 45% and 65%. The clock power supplies must be independent of the ADC output supplies to avoid digital noise modulation on the output. When powered-on, the circuit needs several clock periods to reach its normal operating conditions. The clock input is a MOS input. To bias this input stage properly, a bias current of 10 nA is sufficient. Figure 57. Clock input schematic Square clock 50 clock generator CLK DVcc/2 CLK 50 Sine clock Short track Short track 50 DVcc/2 AM04551 The signal applied to the CLK pin is critical to obtain full performance from the RHF1201. We recommend using a 0 to 2.5 V square signal with fast transition times, and to place proper termination resistors as close as possible to the device. The sampling instant is determined by the rising edge of the clock signal. The jitter associated with this instant must be as low as possible to avoid SNR degradation on fast-moving input signals. To ensure that LSB errors stay below 0.5, the total jitter Tj must satisfy the following condition for a full-scale input signal. 1 T j < --------------------------------n+1 F in 2 n being the number of bits. In most cases, the clock signal jitter is the major contributor of total noise. Therefore, particular attention should be given to the clock signal when acquiring fast signals with a low-frequency clock. 26/34 Doc ID 12585 Rev 5 RHF1201 Power consumption optimization The internal architecture of the RHF1201 makes it possible to optimize the power consumption according to the sampling frequency of the application. For this purpose, an external Rpol resistor is placed between the IPOL pin and the analog ground. Therefore, the total dissipation can be adjusted across the entire sampling range from 0.5 Msps to 50 Msps to fulfill the requirements of applications where power saving is critical. For low sampling frequencies, the resistor value may be adjusted to decrease the analog current without any deterioration of the dynamic performance. The current consumption Icca, depending on the value of Rpol, is as shown in Figure 58. Figure 58. Rpol versus Fs Rpol (k ) - Icca (mA) 7.5 Electrical characteristics (unchanged after 300 kRad) 100 10 0 10 20 30 40 50 60 70 80 90 Sampling Frequency, Fs (MHz) Doc ID 12585 Rev 5 27/34 Electrical characteristics (unchanged after 300 kRad) 7.6 28/34 RHF1201 Layout precautions Use of dedicated analog and digital ground planes on the PCB is recommended for high-speed circuit applications to provide low parasitic inductance and resistance. Ground planes under the digital pins and layers should be avoided to minimize parasitic capacitances. The separation of the analog signal from the digital output is mandatory to prevent noise from coupling onto the input signal. Power supply bypass capacitors must be placed as close as possible to the IC pins to improve high-frequency bypassing and reduce harmonic distortion. All leads must be as short as possible, especially for the analog input, so as to decrease parasitic capacitance and inductance. To minimize the transition current when the output changes, the capacitive load at the digital outputs must be reduced as much as possible by using the shortest-possible routing tracks. Choose the smallest-possible component sizes (SMD). Doc ID 12585 Rev 5 RHF1201 Definitions of specified parameters 8 Definitions of specified parameters 8.1 Static parameters Differential non-linearity (DNL) The average deviation of any output code width from the ideal code width of 1 LSB. Integral non-linearity (INL) An ideal converter exhibits a transfer function which is a straight line from the starting code to the ending code. The INL is the deviation from this ideal line for each transition. 8.2 Dynamic parameters Spurious free dynamic range (SFDR) The ratio between the power of the worst spurious signal (not always a harmonic) and the amplitude of the fundamental tone (signal power) over the full Nyquist band. Expressed in dBc. Total harmonic distortion (THD) The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. Expressed in dB. Signal to noise ratio (SNR) The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (fs/2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB. Signal to noise and distortion ratio (SINAD) Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). Expressed in dB. The effective number of bits (ENOB) is easily deduced from the SINAD, using the formula: SINAD = 6.02 x ENOB + 1.76 dB When the applied signal is not full-scale (FS) but has an amplitude A0, the SINAD expression becomes: SINAD = 6.02 x ENOB + 1.76 dB + 20 log (A0/FS) ENOB is expressed in bits. Effective resolution bandwidth For a given sampling rate and clock jitter, this is the analog input frequency at which the SINAD is reduced by 3 dB, and the ENOB is reduced by 0.5 bits. Doc ID 12585 Rev 5 29/34 Definitions of specified parameters RHF1201 Pipeline delay Delay between the initial sample of the analog input and the availability of the corresponding digital data output on the output bus. Also called data latency, it is expressed as a number of clock cycles. When powering off to on, there is a delay of several clock cycles before the ADC can achieve a reliable and stable signal conversion. During this delay, some conversion artefacts may appear. 30/34 Doc ID 12585 Rev 5 RHF1201 9 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 59. Ceramic SO-48 package mechanical drawing Note: The upper metallic lid is not electrically connected to any pins, nor to the IC die inside the package. Connecting unused pins or metal lid to ground or to the power supply will not affect the electrical characteristics. Doc ID 12585 Rev 5 31/34 Package information Table 12. RHF1201 Ceramic SO-48 package mechanical data Dimensions Ref. Millimeters Min. Typ. Max. Min. Typ. Max. A 2.18 2.47 2.72 0.086 0.097 0.107 b 0.20 0.254 0.30 0.008 0.010 0.012 c 0.12 0.15 0.18 0.005 0.006 0.007 D 15.57 15.75 15.92 0.613 0.620 0.627 E 9.52 9.65 9.78 0.375 0.380 0.385 E1 32/34 Inches 10.90 0.429 E2 6.22 6.35 6.48 0.245 0.250 0.255 E3 1.52 1.65 1.78 0.060 0.065 0.070 e 0.635 0.025 f 0.20 0.008 L 12.28 12.58 12.88 0.483 0.495 0.507 P 1.30 1.45 1.60 0.051 0.057 0.063 Q 0.66 0.79 0.92 0.026 0.031 0.036 S1 0.25 0.43 0.61 0.010 0.017 0.024 Doc ID 12585 Rev 5 RHF1201 10 Revision history Revision history Table 13. Document revision history Date Revision 01-Sep-2006 1 Changes Initial release in new format. Updated failure immune and latchup immune value to 120 MeV- cm2/mg. 29-Jun-2007 2 Updated package mechanical data. Removed reference to non rad-hard components from Section 7.3.2: External reference on page 25. 3 Changed cover page graphic. Changed Figure 2. Added Chapter 4: Equivalent circuits. Added Note 1 under Table 4. Expanded Table 5 with additional parameters. Modified "Test conditions" and Vrefp/Vincm in Table 7. Improved readability in Table 11. Added Figure 46 to Figure 49. Modified Figure 50 and Figure 52. Added Figure 53. Removed IF sampling section. Modified Figure 54 and Figure 16. Added Figure 58. Added ECOPACK information and updated presentation in Chapter 9. 09-Apr-2010 4 Modified description on cover page. Added Table 1: Device summary on page 1. Removed RHF1201KSO2 order code from Table 1. Removed Fs and Tck values from Table 3. Added Figure 7 and Figure 8. Added DFS, OEB and SRC values in Table 5. Changed VINCM values in Table 5. Removed Fin values from Table 5. Removed output capacitive load values from Table 9. Changed clock threshold values in Table 9. Added PSRR values in Table 10. Added Figure 13 on page 12 to Figure 45. Modified Figure 46, Figure 48 and Figure 49. 29-Jul-2011 5 Added Note: on page 31 and in the "Pin connections" diagram on the coverpage. 10-Oct-2008 Doc ID 12585 Rev 5 33/34 RHF1201 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 34/34 Doc ID 12585 Rev 5