THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
10-Bit Resolution 30 MSPS
Analog-to-Digital Converter:
D
Configurable Input: Single-Ended or
Differential
D
Differential Nonlinearity: ±0.3 LSB
D
Signal-to-Noise: 57 dB
D
Spurious Free Dynamic Range: 60 dB
D
Adjustable Internal Voltage Reference
D
Out-of-Range Indicator
D
Power-Down Mode
D
Pin Compatible with TLC876
description
The THS1030 is a CMOS, low power, 10-bit, 30
MSPS analog-to-digital converter (ADC) that can
operate with a supply range from 2.7 V to 3.3 V.
The THS1030 has been designed to give circuit
developers more flexibility. The analog input to the
THS1030 can be either single-ended or differential. The THS1030 provides a wide selection of voltage
references to match the user’s design requirements. For more design flexibility, the internal reference can be
bypassed to use an external reference to suit the dc accuracy and temperature drift requirements of the
application. The out-of-range output is used to monitor any out-of-range condition in THS1030s input range.
The speed, resolution, and single-supply operation of the THS1030 are suited for applications in STB, video,
multimedia, imaging, high-speed acquisition, and communications. The speed and resolution ideally suit
charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and
camcorders. A wide input voltage range between REFBS and REFTS allows the THS1030 to be applied in both
imaging and communications systems.
The THS1030I is characterized for operation from –40°C to 85°C
AVAILABLE OPTIONS
TA
PACKAGED DEVICES
T
A28-TSSOP (PW) 28-SOIC (DW)
0°C to 70°C THS1030CPW THS1030CDW
–40°C to 85°C THS1030IPW THS1030IDW
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
DVDD
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
OVR
DGND
AVDD
AIN
VREF
REFBS
REFBF
MODE
REFTF
REFTS
876M
AGND
REFSENSE
STBY
OE
CLK
28-PIN TSSOP/SOIC PACKAGE
(TOP VIEW)
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
SHA Output
Buffers
Timing
Circuit
A/D
SW3
DC
REF
VBG
REFSENSE VREF CLK
REFBF
REFTF
MODE
REFBS
REFTS
AIN I/O0 –
I/O9
OVR
OE
SW4
STBY
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AGND 1, 19 IAnalog ground
AIN 27 IAnalog input
AVDD 28 IAnalog supply
CLK 15 IClock input
DGND 14 IDigital ground
DVDD 2 I Digital driver supply
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
3
4
5
6
7
8
9
10
11
12
I/O
Digital I/O bit 0 (LSB)
Digital I/O bit 1
Digital I/O bit 2
Digital I/O bit 3
Digital I/O bit 4
Digital I/O bit 5
Digital I/O bit 6
Digital I/O bit 7
Digital I/O bit 8
Digital I/O bit 9 (MSB)
MODE 23 IMode input
OE 16 IHI to the 3-state data bus, LO to enable the data bus
OVR 13 OOut-of-range indicator
REFBS 25 IReference bottom sense
REFBF 24 IReference bottom decoupling
REFSENSE 18 IReference sense
REFTF 22 IReference top decoupling
REFTS 21 IReference top sense
STBY 17 IHI = power down mode, LO = normal operation mode
VREF 26 I/O Internal and external reference for ADC
876M 20 IHI = THS1030 mode, LO = TLC876 mode (see section 4 for TLC876 mode)
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage: AVDD to AGND, DVDD to DGND –0.3 to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AGND to DGND –0.3 to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AVDD to DVDD –6.5 to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode input MODE to AGND –0.3 to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference voltage input range REFTF, REFTB, REFTS, REFBS to AGND –0.3 to AVDD + 0.3 V. . . . . . . . .
Analog input voltage range AIN to AGND –0.3 to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input VREF to AGND –0.3 to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference output VREF to AGND –0.3 to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock input CLK to AGND –0.3 to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input to DGND –0.3 to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital output to DGND –0.3 to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating junction temperature range, TJ 0°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, TSTG –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
recommended operating conditions
digital inputs
MIN NOM MAX UNIT
High-level input voltage, VIH 2.4 V
Low-level input voltage, VIL 0.2 x DVDD V
analog inputs
MIN NOM MAX UNIT
Analog input voltage, VI(AIN) REFBS REFTS V
Reference input voltage, VI(VREF) 1 2 V
Reference input voltage, VI(REFTS) 1AVDD V
Reference input voltage, VI(REFBS) 0AVDD–1 V
power supply
MIN NOM MAX UNIT
Su
pp
ly voltage
Maximum sam
p
ling rate = 30 MSPS
AVDD 2.7 3 5.5
V
S
u
ppl
y v
oltage
Ma
x
im
u
m
sampling
rate
=
30
MSPS
DVDD 2.7 3 5.5
V
REFTS, REFBS reference voltages (MODE = AVDD)
PARAMETER MIN NOM MAX UNIT
REFTS Reference input voltage (top) 1AVDD V
REFBS Reference input voltage (bottom) 0AVDD–1 V
Differential input (REFTS – REFBS) 1 2 V
Switched input capacitance on REFTS 0.5 pF
sampling rate and resolution
PARAMETER MIN NOM MAX UNIT
Fs 5 30 MSPS
Resolution 10 Bits
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions, A VDD = 3 V , DVDD = 3 V, Fs = 30
MSPS/50% duty cycle, MODE = AVDD, 2 V input span from 0.5 V to 2.5 V, external reference, TA =
–40°C to 85°C (unless otherwise noted)
analog inputs
PARAMETER MIN TYP MAX UNIT
VI(AIN) Analog input voltage REFBS REFTS V
CISwitched input capacitance 1.2 pF
FPBW Full power BW (–3 dB) 150 MHz
DC leakage current (input = ±FS) 60 µA
VREF reference voltages
PARAMETER MIN TYP MAX UNIT
Internal 1 V reference (REFSENSE = VREF) 0.95 1 1.05 V
Internal 2 V reference (REFSENSE = AVSS) 1.90 2 2.10 V
External reference (REFSENSE = AVDD) 1 2 V
Reference input resistance 18 kΩ
REFTF, REFBF reference voltages
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Differential input (REFTF – REFBF) 1 2 V
In
p
ut common mode (REFTF + REFBF)/2
AVDD = 3 V 1.3 1.5 1.7
V
Inp
u
t
common
mode
(REFTF
+
REFBF)/2
AVDD = 5 V 2 2.5 3
V
VREF =1V
AVDD = 3 V 2
V
REFTF (MODE = AVDD)
V
REF =
1
V
AVDD = 5 V 3
V
REFTF
(MODE
=
AV
DD
)
VREF =2V
AVDD = 3 V 2.5
V
V
REF =
2
V
AVDD = 5 V 3.5
V
VREF =1V
AVDD = 3 V 1
V
REFBF (MODE = AVDD)
V
REF =
1
V
AVDD = 5 V 0.5
V
REFBF
(MODE
=
AV
DD
)
VREF =2V
AVDD = 3 V 2
V
V
REF =
2
V
AVDD = 5 V 1.5
V
Input resistance between REFTF and REFBF 600 Ω
dc accuracy
PARAMETER MIN TYP MAX UNIT
INL Integral nonlinearity ±1±2 LSB
DNL Differential nonlinearity ±0.3 ±1 LSB
Offset error 0.4 1.4 %FSR
Gain error 1.4 3.5 %FSR
Missing code No missing code assured
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions, A VDD = 3 V , DVDD = 3 V, Fs = 30
MSPS/50% duty cycle, MODE = AVDD, 2 V input span from 0.5 V to 2.5 V, external reference, TA =
–40°C to 85°C (unless otherwise noted) (continued)
dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f = 3.5 MHz 8.4 9
ENOB
Effective number of bits
f = 3.5 MHz, AVDD = 5 V 9
Bits
ENOB
Effecti
v
e
n
u
mber
of
bits
f = 15 MHz, 3 V 7.8
Bits
f = 15 MHz, AVDD = 5 V 7.7
f = 3.5 MHz 56 60.6
SFDR
S
p
urious free dynamic range
f = 3.5 MHz, AVDD = 5 V 64.6 dB
SFDR
Sp
u
rio
u
s
free
d
y
namic
range
f = 15 MHz 48.5
f = 15 MHz, AVDD = 5 V 53
f = 3.5 MHz –60 –56
THD
Total harmonic distortion
f = 3.5 MHz, AVDD = 5 V –66.9 dB
THD
Total
harmonic
distortion
f = 15 MHz –47.5
f = 15 MHz, AVDD = 5 V –53.1
f = 3.5 MHz 53 57
dB
SNR
Signal to noise
f = 3.5 MHz, AVDD = 5 V 56
dB
SNR
Signal
-
to
-
noise
f = 15 MHz 53.1
f = 15 MHz, AVDD = 5 V 49.4
f = 3.5 MHz 52.5 56
SINAD
Signal to noise and distortion
f = 3.5 MHz, AVDD = 5 V 56
dB
SINAD
Signal
-
to
-
noise
and
distortion
f = 15 MHz 48.6
dB
f = 15 MHz, AVDD = 5 V 48.1
clock
PARAMETER MIN TYP MAX UNIT
t(CK) Clock period 33 ns
t(CKH) Pulse duration, clock high 15 16.5 ns
t(CKL) Pulse duration, clock low 15 16.5 ns
tdClock to data valid 20 ns
Pipeline latency 3 Cycles
t(ap) Aperture delay 4 ns
Aperture uncertainty (jitter) 2 ps
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC Operating supply current AVDD =DVDD = 3 V, MODE = AGND 29 40 mA
Power dissi
p
ation
AVDD = DVDD = 3 V 87 120
mW
D
Po
w
er
dissipation
AVDD = DVDD = 5 V 150
mW
PD(STBY) Standby power AVDD =DVDD = 3 V, MODE = AGND 3 5 mW
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
(See
Note A)
NOTE A: All timing measurements are based on 50% of edge transition.
Analog Input
Input Clock
Digital Output
Sample 1
Sample 2 Sample 3
Sample 4 Sample 5
t(CK)
t(CKH) t(CKL)
td
Pipeline Latency
Sample 1 Sample 2
Figure 1. Digital Output Timing Diagram
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
76
78
80
82
84
86
88
90
5 1015202530
POWER
vs
SAMPLING FREQUENCY
fs – Sampling Frequency – MHz
AVDD = DVDD = 3 V
Fin = 3.5 MHz
TA = 25°C
Figure 2
Power – mW
7
7.5
8.0
8.5
9.0
9.5
10.0
–40 –15 10 35 60 85
EFFECTIVE NUMBER OF BITS
vs
TEMPERATURE
Temperature – °C
AVDD = DVDD = 3 V
Fin = 3.5 MHz
Fs = 30 MSPS
Figure 3
Effective Number of Bits
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
7
7.5
8.0
8.5
9.0
9.5
10.0
5 1015202530
EFFECTIVE NUMBER OF BITS
vs
FREQUENCY
fs – Sampling Clock – MSPS
AVDD = DVDD = 3 V
Fin = 3.5 MHz
TA = 25°C
Figure 4
Effective Number of Bits
7
7.5
8.0
8.5
9.0
9.5
10.0
5 1015202530
EFFECTIVE NUMBER OF BITS
vs
FREQUENCY
fs – Sampling Clock – MSPS
AVDD = 5 V
DVDD = 3 V
Fin = 3.5 MHz
TA = 25°C
Figure 5
Effective Number of Bits
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
7
7.5
8.0
8.5
9.0
9.5
10.0
5 1015202530
EFFECTIVE NUMBER OF BITS
vs
FREQUENCY
Figure 6
Effective Number of Bits
fs – Sampling Clock – MSPS
AVDD = DVDD = 5 V
Fin = 3.5 MHz
TA = 25°C
–1.00
–0.80
–0.60
–0.40
–0.20
–0.00
0.20
0.40
0.60
0.80
1.00
0 128 256 384 512 640 768 896 1024
DIFFERENTIAL NONLINEARITY
vs
INPUT CODE
Input Code
Figure 7
DNL – Differential Nonlinearity – LSB
AVDD = 3 V
DVDD = 3 V
Fs = 30 MSPS
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
–2
–1.5
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
0 128 256 384 512 640 768 896 1024
INTEGRAL NONLINEARITY
vs
INPUT CODE
Input Code
Figure 8
INL – Integral Nonlinearity – LSB
AVDD = 3 V
DVDD = 3 V
Fs = 30 MSPS
–140
–120
–100
–80
–60
–40
–20
0
02468101214
FFT
vs
FREQUENCY
Figure 9
f – Frequency – MHz
dB
AVDD = 3 V
DVDD = 3 V
Fin = 3.5 MHz
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Table 1. Mode Selection
MODES ANALOG
INPUT INPUT
SPAN MODE
PIN REFSENSE
PIN VREF
PIN REFTS
PIN REFBS
PIN FIGURE
AIN 1 V AVDD Short together AGND 7, 14
AIN 2 V AVDD AGND Short together AGND 8, 15
Top/bottom AIN 1+Ra/RbAVDD Mid Ra & RbShort together to RaAGND 9, 14, 15
AIN External
VREF AVDD AVDD NC NC AGND 10, 14, 15
AIN 1 V AVDD/2 Short together 7, 13
Center s
p
an
AIN 2 V AVDD/2 AGND NC Short together to the common 8, 13
Center
span
AIN 1+Ra/RbAVDD/2 Mid Ra & RbRa
g
mode voltage 9, 13
AIN VREF AVDD/2 AVDD External 10, 13
External
reference AIN 2 V max AGND See Note 1 See Note 1 Voltage within supply
(REFTS–REBS) = 2 V max 11, 12
AIN is input 1
REFTS & 1 V AVDD Short together
Differential
input REFBS are
shorted 2 V AVDD AGND NC Short together AVDD/2 16
together for
input 2 VREF AVDD AVDD External
NOTE 1: In external reference mode, VREF can be available for external use with CENTER SPAN set-up.
reference operations
VREF-pin reference
The voltage reference sources on the VREF pin are controlled by the REFSENSE pin as shown in Table 2.
Table 2. VREF Reference Selection
REFSENSE VREF
AGND 2 V
AVDD The internal reference is disabled and an external reference should be connected to VREF pin.
Short to VREF 1 V
Connect to Ra/Rb1+Ra/Rb
D
1-V reference: The internal reference may be set to 1 V by connecting REFSENSE to VREF.
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
VREF-pin reference (continued)
VBG
VREF = 1 V
_
+
ADC/DAC
REF
REFSENSE
AGND
+
–
THS1030
Figure 10. VREF 1-V Reference Mode
D
2-V reference: The internal reference may be set to 2 V by connecting REFSENSE to AGND.
VBG
VREF = 2 V
_
+
ADC/DAC
REF
REFSENSE
AGND
+
–
THS1030
Figure 11. VREF 2-V Reference Mode
D
External divider: The internal reference can be set to a voltage between 1 V and 2 V by adding external
resistors.
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
VREF-pin reference (continued)
VBG
VREF = 1 + (Ra/Rb)
_
+
ADC/DAC
REF
REFSENSE
AGND
+
–
THS1030
Ra
Rb
Figure 12. VREF External-Divider Reference Mode
D
External reference: The internal reference may be overridden by using an external reference. This
condition is met by connecting REFSENSE to AVDD and an external reference circuit to the VREF pin.
VBG
VREF = External
_
+
ADC/DAC
REF
REFSENSE
AGND
+
–
THS1030
AGND
AVDD
Figure 13. VREF External Reference Mode
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
ADC reference
The MODE pin is used to select the reference source for the ADC.
D
Internal ADC Reference: Connect the MODE pin to A VDD to use the reference source for ADC generated
on the VREF pin. (See VREF REFERENCE described in Table 2) such that (REFTF–REFBF) = VREF and
(REFTF+REFBF)/2 is set to a voltage for optimum operation of the ADC (near AVDD/2).
D
External ADC Reference: To supply an external reference source to the ADC, connect the MODE pin to
AGND. An external reference source should be connected to REFTF/REFTS and REFBF/REFBS.
MODE = AGND closes internal switches to allow a Kelvin connection through REFTS/REFBS, and disables
the on-chip amplifiers which drive on to the ADC references. Differential input is not supported
analog input mode
single-ended input
The single-ended input can be configured to work with either an external ADC reference or internal ADC
reference.
D
External ADC Reference Mode: A single-ended analog input is accepted at the AIN pin where the input
signal is bounded by the voltages on the REFTS and REFBS pins. Figure 14 shows an example of applying
external reference to REFTS and REFBS pins in which REFTS is connected to the low-impedance 2-V
source and REFBS is connected to the low-impedance 2-V source. REFTS and REFBS may be driven to
any voltage within the supply as long as the difference (REFTS – REFBS) is between 1 V and 2 V as
specified in Table 2. Figure 15 shows an example of an external reference using a Kelvin connection to
eliminate line voltage drop errors.
SHA A/D
SW3
REFBF
REFTF
MODE
REFBS
REFTS
10 µF0.1 µF
0.1 µF
0.1 µF
2 V
1 V
AIN
2 V
1 V
THS1030
Figure 14. External ADC Reference Mode
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
single-ended input (continued)
SHA A/D
SW3
REFBF
REFTF
MODE
REFBS
REFTS
10 µF0.1 µF
0.1 µF
0.1 µF
AIN
REFTF
REFBF
REFT
0.1 µF
REFB
0.1 µF
THS1030
Figure 15. Kelvin Connection With External ADC Reference Mode
D
Internal ADC Reference Mode With External Input Common Mode: The input common mode is supplied
to pins REFTS and REFBS while connected together. The input signal should be centered around this
common mode with peak-to-peak input equal to the voltage on the VREF pin. Input can be either dc-coupled
or ac-coupled to the same common mode voltage (see Figure 16) or any other voltage within the input
voltage range.
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
single-ended input (continued)
SHA A/D
REFBF
REFTF
MODE
REFBS
REFTS
10 µF
0.1 µF
1.5 V
AIN
2 V
1 V
THS1030
AVDD
0.1 µF
ADC
REF
_
++–
1 V
REFSENSE
VREF
0.1 µF
Figure 16. External Input Common Mode
D
Internal ADC Reference Mode With Common Mode Input VREF/2: The input common mode is set to
VREF/2 by connecting REFTS to VREF and REFBS to AVSS. The input signal at AIN will swing between VREF
and AVSS.
SHA A/D
REFBF
REFTF
MODE
REFBS
REFTS
10 µF
0.1 µF
1.5 V
AIN
2 V
1 V
THS1030
AVDD
0.1 µF
ADC
REF
_
++–
1 V
REFSENSE
VREF
0.1 µF
Figure 17. Common Mode Input VREF/2 With 1-V Internal Reference
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
single-ended input (continued)
SHA A/D
REFBF
REFTF
MODE
REFBS
REFTS
10 µF
0.1 µF
1.5 V
AIN
2 V
1 V
THS1030
AVDD
0.1 µF
ADC
REF
_
++–
1 V
REFSENSE
VREF
0.1 µF
Figure 18. Common Mode Input VREF/2 With 2-V Internal Reference
differential input
In this mode, the first differential input is applied to the AIN pin and the second differential input is applied to the
common point where REFTS and REFBS are tied together. The common mode of the input should be set to
AVDD/2 as shown in
Figure 19
.
The maximum magnitude of the differential input signal should be equal to VREF.
SHA A/D
REFBF
REFTF
MODE
REFBS
REFTS
10 µF
0.1 µF
AIN
VREF
THS1030
AVDD/2
0.1 µF
ADC
REF
VREF
0.1 µF
AVDD
VREF is either internal or external
Figure 19. Differential Input
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
digital input mode
D
3-State Output: The digital outputs can be set to high-impedance state by applying a LO logic to the OE
pin.
D
Power Down: The whole device will power down by applying a HI logic to the STBY pin. The ADC will wake
up in 400 ns after the pin STBY is reset.
TLC876 mode
The THS1030 is pin compatible with the TI TLC876 and thus enables users of TLC876 to upgrade to higher
speed by dropping the THS1030 into their sockets. Floating the MODE pin effectively puts the THS1030 into
876 mode using the external ADC reference. The REFSENSE pin will be connected to DVDD by the TLC876
socket. In the TLC876/AD876 mode, the pipeline latency will be switched to 3.5 cycles to match TLC876/AD876
specifications.
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
THS1030
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243A – NOVEMBER 1999 – REVISED JANUAR Y 2000
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE
16 PINS SHOWN
4040000/C 07/96
Seating Plane
0.400 (10,15)
0.419 (10,65)
0.104 (2,65) MAX
1
0.012 (0,30)
0.004 (0,10)
A
8
16
0.020 (0,51)
0.014 (0,35)
0.293 (7,45)
0.299 (7,59)
9
0.010 (0,25)
0.050 (1,27)
0.016 (0,40)
(15,24)
(15,49)
PINS **
0.010 (0,25) NOM
A MAX
DIM
A MIN
Gage Plane
20
0.500
(12,70)
(12,95)
0.510
(10,16)
(10,41)
0.400
0.410
16
0.600
24
0.610
(17,78)
28
0.700
(18,03)
0.710
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
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