THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 D D D D D D D D D 28-PIN TSSOP/SOIC PACKAGE (TOP VIEW) 10-Bit Resolution 30 MSPS Analog-to-Digital Converter: Configurable Input: Single-Ended or Differential Differential Nonlinearity: 0.3 LSB Signal-to-Noise: 57 dB Spurious Free Dynamic Range: 60 dB Adjustable Internal Voltage Reference Out-of-Range Indicator Power-Down Mode Pin Compatible with TLC876 AGND DVDD I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 OVR DGND description 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 AVDD AIN VREF REFBS REFBF MODE REFTF REFTS 876M AGND REFSENSE STBY OE CLK The THS1030 is a CMOS, low power, 10-bit, 30 14 15 MSPS analog-to-digital converter (ADC) that can operate with a supply range from 2.7 V to 3.3 V. The THS1030 has been designed to give circuit developers more flexibility. The analog input to the THS1030 can be either single-ended or differential. The THS1030 provides a wide selection of voltage references to match the user's design requirements. For more design flexibility, the internal reference can be bypassed to use an external reference to suit the dc accuracy and temperature drift requirements of the application. The out-of-range output is used to monitor any out-of-range condition in THS1030s input range. The speed, resolution, and single-supply operation of the THS1030 are suited for applications in STB, video, multimedia, imaging, high-speed acquisition, and communications. The speed and resolution ideally suit charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and camcorders. A wide input voltage range between REFBS and REFTS allows the THS1030 to be applied in both imaging and communications systems. The THS1030I is characterized for operation from - 40C to 85C AVAILABLE OPTIONS PACKAGED DEVICES TA 28-TSSOP (PW) 28-SOIC (DW) 0C to 70C THS1030CPW THS1030CDW - 40C to 85C THS1030IPW THS1030IDW Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI is a trademark of Texas Instruments Incorporated. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 functional block diagram AIN A/D SHA REFTS Output Buffers I/O0 - I/O9 REFBS MODE OVR DC REF OE SW3 Timing Circuit REFTF REFBF VBG SW4 REFSENSE 2 VREF POST OFFICE BOX 655303 STBY * DALLAS, TEXAS 75265 CLK THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 Terminal Functions TERMINAL NAME AGND NO. I/O DESCRIPTION 1, 19 I Analog ground AIN 27 I Analog input AVDD CLK 28 I Analog supply 15 I Clock input DGND 14 I Digital ground DVDD 2 I Digital driver supply I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 3 4 5 6 7 8 9 10 11 12 I/O MODE 23 I Mode input OE 16 I HI to the 3-state data bus, LO to enable the data bus OVR 13 O Out-of-range indicator REFBS 25 I Reference bottom sense REFBF 24 I Reference bottom decoupling REFSENSE 18 I Reference sense REFTF 22 I Reference top decoupling REFTS 21 I Reference top sense STBY 17 I HI = power down mode, LO = normal operation mode VREF 876M 26 I/O 20 I Digital I/O bit 0 (LSB) Digital I/O bit 1 Digital I/O bit 2 Digital I/O bit 3 Digital I/O bit 4 Digital I/O bit 5 Digital I/O bit 6 Digital I/O bit 7 Digital I/O bit 8 Digital I/O bit 9 (MSB) Internal and external reference for ADC HI = THS1030 mode, LO = TLC876 mode (see section 4 for TLC876 mode) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage: AVDD to AGND, DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to 6.5 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to 0.3 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 6.5 to 6.5 V Mode input MODE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to AVDD + 0.3 V Reference voltage input range REFTF, REFTB, REFTS, REFBS to AGND . . . . . . . . . - 0.3 to AVDD + 0.3 V Analog input voltage range AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to AVDD + 0.3 V Reference input VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to AVDD + 0.3 V Reference output VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to AVDD + 0.3 V Clock input CLK to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to AVDD + 0.3 V Digital input to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to DVDD + 0.3 V Digital output to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to DVDD + 0.3 V Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 150C Storage temperature range, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions digital inputs MIN High-level input voltage, VIH NOM MAX 2.4 UNIT V Low-level input voltage, VIL 0.2 x DVDD V analog inputs MIN Analog input voltage, VI(AIN) NOM MAX UNIT REFBS REFTS V Reference input voltage, VI(VREF) 1 2 V Reference input voltage, VI(REFTS) 1 0 AVDD AVDD-1 V Reference input voltage, VI(REFBS) V power supply Supply voltage Maximum sampling rate = 30 MSPS AVDD DVDD MIN NOM MAX 2.7 3 5.5 2.7 3 5.5 UNIT V REFTS, REFBS reference voltages (MODE = AVDD) PARAMETER MIN REFTS Reference input voltage (top) 1 REFBS Reference input voltage (bottom) 0 Differential input (REFTS - REFBS) 1 NOM MAX UNIT AVDD AVDD-1 V 2 Switched input capacitance on REFTS V V 0.5 pF sampling rate and resolution PARAMETER MIN Fs Resolution 4 NOM 5 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MAX UNIT 30 MSPS Bits THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AVDD, 2 V input span from 0.5 V to 2.5 V, external reference, TA = -40C to 85C (unless otherwise noted) analog inputs PARAMETER MIN TYP MAX REFBS REFTS UNIT VI(AIN) CI Analog input voltage Switched input capacitance 1.2 pF FPBW Full power BW (-3 dB) 150 MHz 60 A DC leakage current (input = FS) V VREF reference voltages PARAMETER MIN TYP MAX UNIT Internal 1 V reference (REFSENSE = VREF) 0.95 1 1.05 V Internal 2 V reference (REFSENSE = AVSS) 1.90 2 2.10 V 2 V External reference (REFSENSE = AVDD) 1 Reference input resistance 18 k REFTF, REFBF reference voltages PARAMETER TEST CONDITIONS Differential input (REFTF - REFBF) MIN TYP 1 AVDD = 3 V AVDD = 5 V Input common mode (REFTF + REFBF)/2 2 1.3 1.5 1.7 2 2.5 3 VREF = 1 V AVDD = 3 V AVDD = 5 V 2 VREF = 2 V AVDD = 3 V AVDD = 5 V 2.5 VREF = 1 V AVDD = 3 V AVDD = 5 V VREF = 2 V AVDD = 3 V AVDD = 5 V REFTF (MODE = AVDD) REFBF (MODE = AVDD) MAX V V V 3 V 3.5 1 V 0.5 2 V 1.5 Input resistance between REFTF and REFBF UNIT 600 dc accuracy PARAMETER INL Integral nonlinearity DNL Differential nonlinearity MIN TYP MAX UNIT 1 2 LSB 0.3 1 LSB Offset error 0.4 1.4 %FSR Gain error 1.4 3.5 %FSR Missing code No missing code assured POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AVDD, 2 V input span from 0.5 V to 2.5 V, external reference, TA = -40C to 85C (unless otherwise noted) (continued) dynamic performance PARAMETER TEST CONDITIONS f = 3.5 MHz ENOB TYP 8.4 9 f = 3.5 MHz, AVDD = 5 V Effective number of bits Spurious free dynamic range 7.8 f = 15 MHz, AVDD = 5 V 7.7 56 64.6 f = 15 MHz 48.5 - 60 f = 3.5 MHz, AVDD = 5 V - 66.9 f = 15 MHz - 47.5 f = 15 MHz, AVDD = 5 V f = 3.5 MHz SNR 57 dB 49.4 52.5 f = 3.5 MHz, AVDD = 5 V Signal to noise and distortion Signal-to-noise dB 53.1 f = 15 MHz, AVDD = 5 V SINAD - 56 56 f = 15 MHz f = 3.5 MHz dB - 53.1 53 f = 3.5 MHz, AVDD = 5 V Signal to noise Signal-to-noise Bits 53 f = 3.5 MHz Total harmonic distortion UNIT 60.6 f = 3.5 MHz, AVDD = 5 V f = 15 MHz, AVDD = 5 V THD MAX 9 f = 15 MHz, 3 V f = 3.5 MHz SFDR MIN 56 56 f = 15 MHz 48.6 f = 15 MHz, AVDD = 5 V 48.1 dB clock PARAMETER MIN TYP t(CK) t(CKH) Clock period 33 Pulse duration, clock high 15 16.5 t(CKL) td Pulse duration, clock low 15 16.5 t(ap) MAX UNIT ns Clock to data valid ns ns 20 ns Pipeline latency 3 Cycles Aperture delay 4 ns Aperture uncertainty (jitter) 2 ps power supply PARAMETER ICC Operating supply current PD Power dissipation PD(STBY) Standby power 6 TYP MAX AVDD =DVDD = 3 V, MODE = AGND AVDD = DVDD = 3 V TEST CONDITIONS 29 40 87 120 AVDD = DVDD = 5 V AVDD =DVDD = 3 V, MODE = AGND 150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MIN 3 5 UNIT mA mW mW THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION Sample 2 Sample 3 Sample 1 Sample 5 Sample 4 Analog Input t(CK) t(CKL) t(CKH) Input Clock (See Note A) td Pipeline Latency Digital Output Sample 1 Sample 2 NOTE A: All timing measurements are based on 50% of edge transition. Figure 1. Digital Output Timing Diagram POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 TYPICAL CHARACTERISTICS POWER vs SAMPLING FREQUENCY 90 AVDD = DVDD = 3 V Fin = 3.5 MHz TA = 25C 88 Power - mW 86 84 82 80 78 76 5 10 15 20 25 30 60 85 fs - Sampling Frequency - MHz Figure 2 EFFECTIVE NUMBER OF BITS vs TEMPERATURE Effective Number of Bits 10.0 9.5 9.0 AVDD = DVDD = 3 V Fin = 3.5 MHz Fs = 30 MSPS 8.5 8.0 7.5 7 -40 -15 10 35 Temperature - C Figure 3 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS vs FREQUENCY Effective Number of Bits 10.0 9.5 9.0 8.5 8.0 AVDD = DVDD = 3 V Fin = 3.5 MHz TA = 25C 7.5 7 5 10 15 20 25 30 25 30 fs - Sampling Clock - MSPS Figure 4 EFFECTIVE NUMBER OF BITS vs FREQUENCY Effective Number of Bits 10.0 9.5 9.0 8.5 8.0 AVDD = 5 V DVDD = 3 V Fin = 3.5 MHz TA = 25C 7.5 7 5 10 15 20 fs - Sampling Clock - MSPS Figure 5 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS vs FREQUENCY Effective Number of Bits 10.0 AVDD = DVDD = 5 V Fin = 3.5 MHz TA = 25C 9.5 9.0 8.5 8.0 7.5 7 5 10 15 20 25 30 fs - Sampling Clock - MSPS Figure 6 DNL - Differential Nonlinearity - LSB DIFFERENTIAL NONLINEARITY vs INPUT CODE 1.00 0.80 0.60 0.40 0.20 -0.00 -0.20 -0.40 -0.60 -0.80 -1.00 AVDD = 3 V DVDD = 3 V Fs = 30 MSPS 0 128 256 384 512 640 Input Code Figure 7 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 768 896 1024 THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 TYPICAL CHARACTERISTICS INL - Integral Nonlinearity - LSB INTEGRAL NONLINEARITY vs INPUT CODE 2.0 AVDD = 3 V DVDD = 3 V Fs = 30 MSPS 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2 0 128 256 384 512 640 768 896 1024 Input Code Figure 8 FFT vs FREQUENCY 0 AVDD = 3 V DVDD = 3 V Fin = 3.5 MHz -20 dB -40 -60 -80 -100 -120 -140 0 2 4 6 8 10 12 14 f - Frequency - MHz Figure 9 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 PRINCIPLES OF OPERATION Table 1. Mode Selection MODES ANALOG INPUT INPUT SPAN MODE PIN REFSENSE PIN AIN 1V AIN 2V AVDD AVDD AGND Short together AGND 8, 15 AIN 1+Ra/Rb External VREF AVDD Mid Ra & Rb Short together to Ra AGND 9, 14, 15 AVDD AVDD NC AGND 10, 14, 15 AIN 1V AIN 2V AVDD/2 AVDD/2 AGND NC AIN 1+Ra/Rb VREF AVDD/2 AVDD/2 Mid Ra & Rb Ra AVDD External Top/bottom AIN Center span AIN VREF PIN REFTS PIN Short together NC REFBS PIN FIGURE AGND 7, 14 Short together 7, 13 Short together g to the common mode voltage External reference AIN 2 V max AGND 1V AVDD Differential input AIN is input 1 REFTS & REFBS are shorted together for input 2 2V AVDD AGND NC VREF AVDD AVDD External See Note 1 See Note 1 8, 13 9, 13 10, 13 Voltage within supply (REFTS-REBS) = 2 V max 11, 12 Short together AVDD/2 16 Short together NOTE 1: In external reference mode, VREF can be available for external use with CENTER SPAN set-up. reference operations VREF-pin reference The voltage reference sources on the VREF pin are controlled by the REFSENSE pin as shown in Table 2. Table 2. VREF Reference Selection REFSENSE VREF AGND 2V AVDD Short to VREF The internal reference is disabled and an external reference should be connected to VREF pin. Connect to Ra/Rb 1+Ra/Rb D 12 1V 1-V reference: The internal reference may be set to 1 V by connecting REFSENSE to VREF . POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 PRINCIPLES OF OPERATION VREF-pin reference (continued) THS1030 ADC/DAC REF + _ VBG VREF = 1 V + - REFSENSE AGND Figure 10. VREF 1-V Reference Mode D 2-V reference: The internal reference may be set to 2 V by connecting REFSENSE to AGND. THS1030 ADC/DAC REF + _ VBG VREF = 2 V + - REFSENSE AGND Figure 11. VREF 2-V Reference Mode D External divider: The internal reference can be set to a voltage between 1 V and 2 V by adding external resistors. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 PRINCIPLES OF OPERATION VREF-pin reference (continued) THS1030 ADC/DAC REF + _ VREF = 1 + (Ra/Rb) + - VBG Ra REFSENSE Rb AGND Figure 12. VREF External-Divider Reference Mode D External reference: The internal reference may be overridden by using an external reference. This condition is met by connecting REFSENSE to AVDD and an external reference circuit to the VREF pin. THS1030 ADC/DAC REF + _ VBG VREF = External + - REFSENSE AVDD AGND Figure 13. VREF External Reference Mode 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 PRINCIPLES OF OPERATION ADC reference The MODE pin is used to select the reference source for the ADC. D D Internal ADC Reference: Connect the MODE pin to AVDD to use the reference source for ADC generated on the VREF pin. (See VREF REFERENCE described in Table 2) such that (REFTF-REFBF) = VREF and (REFTF+REFBF)/2 is set to a voltage for optimum operation of the ADC (near AVDD/2). External ADC Reference: To supply an external reference source to the ADC, connect the MODE pin to AGND. An external reference source should be connected to REFTF/REFTS and REFBF/REFBS. MODE = AGND closes internal switches to allow a Kelvin connection through REFTS/REFBS, and disables the on-chip amplifiers which drive on to the ADC references. Differential input is not supported analog input mode single-ended input The single-ended input can be configured to work with either an external ADC reference or internal ADC reference. D External ADC Reference Mode: A single-ended analog input is accepted at the AIN pin where the input signal is bounded by the voltages on the REFTS and REFBS pins. Figure 14 shows an example of applying external reference to REFTS and REFBS pins in which REFTS is connected to the low-impedance 2-V source and REFBS is connected to the low-impedance 2-V source. REFTS and REFBS may be driven to any voltage within the supply as long as the difference (REFTS - REFBS) is between 1 V and 2 V as specified in Table 2. Figure 15 shows an example of an external reference using a Kelvin connection to eliminate line voltage drop errors. 2V THS1030 AIN 1V 2V 1V SHA REFTS A/D REFBS MODE SW3 REFTF 0.1 F 0.1 F 10 F REFBF 0.1 F Figure 14. External ADC Reference Mode POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 PRINCIPLES OF OPERATION single-ended input (continued) REFTF THS1030 AIN REFBF SHA REFTS A/D REFBS MODE 0.1 F SW3 REFTF REFT 0.1 F 0.1 F 0.1 F REFB 10 F REFBF 0.1 F Figure 15. Kelvin Connection With External ADC Reference Mode D 16 Internal ADC Reference Mode With External Input Common Mode: The input common mode is supplied to pins REFTS and REFBS while connected together. The input signal should be centered around this common mode with peak-to-peak input equal to the voltage on the VREF pin. Input can be either dc-coupled or ac-coupled to the same common mode voltage (see Figure 16) or any other voltage within the input voltage range. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 PRINCIPLES OF OPERATION single-ended input (continued) 2V THS1030 AIN 1V A/D SHA REFTS 1.5 V REFBS AVDD MODE REFTF ADC REF VREF + _ 0.1 F 0.1 F - + 10 F REFBF 1V 0.1 F REFSENSE Figure 16. External Input Common Mode D Internal ADC Reference Mode With Common Mode Input VREF/2: The input common mode is set to VREF/2 by connecting REFTS to VREF and REFBS to AVSS. The input signal at AIN will swing between VREF and AVSS. 2V THS1030 AIN 1V A/D SHA REFTS 1.5 V REFBS AVDD MODE REFTF ADC REF VREF + _ - + 1V 0.1 F 0.1 F 10 F REFBF 0.1 F REFSENSE Figure 17. Common Mode Input VREF/2 With 1-V Internal Reference POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 PRINCIPLES OF OPERATION single-ended input (continued) 2V THS1030 AIN 1V A/D SHA REFTS 1.5 V REFBS MODE AVDD REFTF ADC REF VREF + _ 0.1 F 0.1 F - + 10 F REFBF 1V 0.1 F REFSENSE Figure 18. Common Mode Input VREF/2 With 2-V Internal Reference differential input In this mode, the first differential input is applied to the AIN pin and the second differential input is applied to the common point where REFTS and REFBS are tied together. The common mode of the input should be set to AVDD/2 as shown in Figure 19. The maximum magnitude of the differential input signal should be equal to VREF. VREF THS1030 AIN AVDD/2 REFTS A/D SHA REFBS AVDD MODE REFTF VREF VREF is either internal or external ADC REF 0.1 F 0.1 F 10 F REFBF 0.1 F Figure 19. Differential Input 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 PRINCIPLES OF OPERATION digital input mode D D 3-State Output: The digital outputs can be set to high-impedance state by applying a LO logic to the OE pin. Power Down: The whole device will power down by applying a HI logic to the STBY pin. The ADC will wake up in 400 ns after the pin STBY is reset. TLC876 mode The THS1030 is pin compatible with the TI TLC876 and thus enables users of TLC876 to upgrade to higher speed by dropping the THS1030 into their sockets. Floating the MODE pin effectively puts the THS1030 into 876 mode using the external ADC reference. The REFSENSE pin will be connected to DVDD by the TLC876 socket. In the TLC876/AD876 mode, the pipeline latency will be switched to 3.5 cycles to match TLC876/AD876 specifications. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. 20 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1030 2.7 V - 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER SLAS243A - NOVEMBER 1999 - REVISED JANUARY 2000 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE 16 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.293 (7,45) Gage Plane 0.010 (0,25) 1 8 0- 8 A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** 0.004 (0,10) 16 20 24 28 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 4040000 / C 07/96 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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