i CMOS STATIC RAM IDT6116SA eg at 16K (2K x 8 BIT) IDT6116LA Integrated Device Technology, Inc. FEATURES: DESCRIPTION: * High-speed access and chip select times Military: 20/25/35/45/55/70/90/1 20/150ns (max.) Commercial: 15/20/25/35/45ns (max.) Low-power consumption Battery backup operation 2V data retention voltage (LA version only) Produced with advanced CMOS high-performance technology CMOS process virtually eliminates alpha particle soft-error rates Input and output directly TTL-compatible Static operation: no clocks or refresh required Available in ceramic and plastic 24-pin DIP, 24-pin Thin Dip and 24-pin SOIC and 24-pin SOJ Military product compliant to MIL-STD-833, Class B The IDT6116SA/LA is a 16,384-bit high-speed static RAM organized as 2K x 8. It is fabricated using IDT's high-perfor- mance, high-reliability CMOS technology. Access times as fast as 15ns are available. The circuit also offers a reduced power standby mode. When CS goes HIGH, the circuit will automatically go to, and remain in, a standby power mode, as long as CS remains HIGH. This capability provides significant system level power and cooling savings. The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1pW to 4uW operating off a 2V battery. All inputs and outputs of the IDT6116SA/LA are TTL- compatible. Fully static asynchronous circuitry is used, requir- ing no clocks or refreshing for operation. The IDT6116SA/LA is packaged in 24-pin 600 and 300 mil plastic or ceramic DIP and a 24-lead guil-wing SOIC, anda 24 -lead J-bend SOJ providing high board-level packing densi- ties. Military grade product is manufactured in compliance to the latest version of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. FUNCTIONAL BLOCK DIAGRAM ADDRESS DECODER VOo INPUT DATA CIRCUIT Vec 128 X 128 MEMORY ARRAY GND VO CONTROL VvO?7 cs OE CONTROL WE CIRCUIT 3089 drw 01 The IDT logo is aregistered trademark of Integrated Device Technology, tnc. MILITARY AND COMMERCIAL TEMPERATURE RANGES MARCH 1996 308m/1 1996 integrated Device Technology, Inc. 1IDT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS ari 24 Bvec Ae G2 23 2 ps As({3 = page 622 FE Ag As 4 P24-1 21 EWE A3 5 D24-2 20 [J OF az C6 D24-1 19 Flat aiQ]7 so24-2 i18fI Cs Ao s & 17 ) Vor voo G9 $024-4 16 [9 I/O6 vo1 G10 15 2 Os vo2 11 14 Os GND E412 13 [ vos DIP/SOIC/SOU TOP VIEW PIN DESCRIPTIONS Ao-A13 VOo-/07 TRUTH TABLE") Mode Read Read Address Data Select Write Enable Enable Power 4. H=Vin, L = VIL, X = Don't Care. 3089 drw 02 3089 tol 01 High-Z DATAIN 3089 tbl 02 CAPACITANCE (Ta = +25C, F = 1.0 MHz) Symbol Parameter) Conditions | Max. | Unit CIN Input Capacitance VIN = OV 8 pF Cvo VO Capacitance VouT = 0V 8 pF NOTE: 3089 tbi 03 1. This parameter is determined by device characterization, but is not production tested. ABSOLUTE MAXIMUM RATINGS Symbol Rating Commercial] Military | Unit Terminal Voltage Vterm)| with Respect to GND|-0.5 to + 7.0|-0.5 to +7.0] V Operating Ta Temperature Oto+70 |-55to +125} C Temperature TBIAS Under Bias -55 to + 125 |-65 to +135] C Storage TsTG Temperature ~-55 to + 125/-65 to +150] C Power PT Dissipation 1.0 1.0 Ww lout DC Output Current 50 50 mA NOTES: 3089 tbl 04 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc +0.5V.(OT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES RECOMMENDED OPERATING RECOMMENDED DC TEMPERATURE AND SUPPLY VOLTAGE OPERATING CONDITIONS Ambient Symbol Parameter Min. | Typ. Max. [Unit Grade Temperature GND vcc Voc Supply Voltage 45 5.0 552) Vv Military ~55C to +125C ov 5.0V + 10% GND Supply Ground 0 0 0 Vv Commercial |_0C to +70C ov 5.0V = 10% | ViH Input High Voltage | 22 | 3.5 | Vcc +05] V VIL input Low Voltage | -0.5) | 0.8 Vv NOTES: 3089 tbl 06 1. Vit (min.) = -3.0V for pulse width less than 20ns, once per cycle. 2. VIN must not exceed Vcc +0.5V, DC ELECTRICAL CHARACTERISTICS Voc =5.0V + 10% IDT6116SA IDT6116LA Symbol Parameter Test Conditions Min. Max. | Min. Max. Unit MIL. _ 10 _ 5 Heel Input Leakage Current Vcc = Max., VIN = GND to Vcc COM'L. 5 _ 2 pA Vec = Max. MIL. _ 10 _ 5 ilLol. | Output Leakage Current CS = Vin, VouT = GND to Voc COM'L. _ 5 _ 2 HA VoL Output Low Voltage loL_ = 8mA, Vcc = Min. _- 0.4 _ 0.4 v VOH Output High Voltage (oH =-4mA, Vcc = Min. 2.4 2.4 Vv 3089 tht 07 DC ELECTRICAL CHARACTERISTICS ") Vcc =5.0V + 10%, VLC = 0.2V, VHC = Vcc - 0.2V 6116SA15?) 6116SA20 6116SA25 6116SA35 6116LA15@) 6116LA20 6116LA25 6116LA35 Symbol! Parameter Power | Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Unit Icct | Operating Power Supply SA 105 _ 105 130 80 90 80 90 mA Current, GS < ViL, Outputs Open, LA 95 _ 95 120 75 85 75 85 Vcc =Max.,f=0 Icc2 Dynamic Operating SA 150 _ 130 150 120 135 100 115 mA Current, CS < Vit, Vcc = Max., LA 140 _ 120 140 110 125 95 105 Outputs Open, f = fmax IsB Standby Power Supply SA 40 _ 40 50 40 45 25 35 mA Current (TTL Level) CS 2 Vin, Voc = Max., LA 35 _ 35 45 35 40 25 30 Outputs Open, f = fmMax') \sp+ | Full Standby Power SA 2 _ 2 10 2 10 2 10 mA Supply Current (CMOS Level), CS2 Vue, LA 0.1 _ 0.1 0.9 0.1 0.9 0.1 0.9 Veco =Max., Vin > VHC or Vin s Vic, f=0 NOTES: 3089 tbl 08 1. All values are maximum guaranteed values. 2. 0C to + 70C temperature range only. 3. ~S5C to + 125C temperature range only. 4. fmMax = 1/tRc, only address inputs are cycling at fmax, f = 0 means address inputs are not changing. 5.1 3IDT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS ) (Continued) Vcc =5.0V + 10%, Vic = 0.2V, VHC = Voc - 0.2V 8116SA45 6116SA55 6116SA70@ | 6116SA90 | 6116S5A120 | 6116SA150 6116LA45 6116LA55@ 6116LA70 | 6116LA90 | 6116LA120 | 6116LA150 Symbol Parameter Power|Com't| Mil. | Com'l.| Mil. | Com't.| Mil. |Com'l| Mil. | Com'L| Mil. | Com't. | Mil. | Unit (cc1 Operating Power Supply SA | 80 90 _ 90 _ 90 _ 90 _ 90 90 | mA Current, CS < VIL, Outputs Open, LA | 75 | 85 | 8 _ 85 85 _ 85 _ 85 Vcc = Max.,f=0 lece2 Dynamic Operating SA | 100 | 100 | 100 1 100 _ 100 _ 100 ~ g0 | mA Current, CS < VIL, Vcc = Max., LA | 90 | 95 | 90 _ 90 _ 85 _ 85 _ 85 Outputs Open, f = fmax' IsB Standby Power Supply SA | 25 25 _ 25 _ 25 _ 25 _ 25 _ 25 | mA Current (TTL Level) CS 2 Vin, Voc = Max., LA 20 20 _ 20 _ 20 _ 25 _ 15 _ 15 Outputs Open, f = fuax IsB1 Full Standby Power SA 2 10 | 10 _ 10 _ 10 _ 10 10 | mA Supply Current (CMOS Level), CS 2 Vuc,| LA | 0.1 | 09 | 09 | 09 _ 0.9 _ 0.9 _ 0.9 Vcc = Max., VIN > VHC or VIN Ss Vic, f= 0 NOTES: 3089 tb! 09 1. All values are maximum guaranteed values. 2. OC to + 70C temperature range only. 3. 55C to + 125C temperature range only. 4. fmax = 1/tRc, only address inouts are toggling at fMax, f = 0 means address inputs are not changing. DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (LA Version Only) Vic = 0.2V, VHC = Vcc 0.2V Typ. Max. Vec Veco Symbol Parameter Test Conditions Min. 2.0V 3.0V 2.0V 3.0V Unit Vor Vcc for Data Retention _ 2.0 _ _ _- Vv !ecDA Data Retention Current MIL. = 0.5 1.5 200 300 pA CS = Vic COMLL, 0.5 1.5 20 30 tcpr) Data Deselect to Data Vin > VHC or < VLC _ 0 = _ ns Retention Time tr Operation Recovery Time trc) _ ns tut Input Leakage Current _ _ 2 2 pA NOTES: 3089 tht 10 1. Ta=4 25C 2. tac = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but is not production tested. 5.1 4IDT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) LOW Vcc DATA RETENTION WAVEFORM DATA RETENTION MODE MILITARY AND COMMERCIAL TEMPERATURE RANGES vee asv TS __Vorzav a sy tcoR a te i as ~ VR a SY VIH ViH 3089 drw 03 AC TEST CONDITIONS Input Puise Leveis GND to 3.0V Input Rise/Fali Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 3089 tbl 11 5V 5V 4800 48002 DATA ouT DATAouT 2550 30pF* 2550 SpF* 3089 drw 04 3089 drw 05 Figure 1. AC Test Load Figure 2. AC Test Load {for to1z, tc.z, tonz, twuz, tcnz & tow} including scope and jig. 5 5.1IDT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Vcc = 5V + 10%, All Temperature Ranges) 6116SA15") 6116SA20 6116SA25 6116SA35 6116LA15() 6116LA20 6116LA25 6116LA35 Symbol| Parameter Min. | Max. Min. | Max. Min. | Max. Min. | Max. | Unit READ CYCLE {Rc Read Cycle Time 15 = 20 _ 25 _ 35 ns taa Address Access Time _ 15 = 19 =- 25 _ 35 ns tacs Chip Select Access Time _ 15 _ 20 _ 25 35 ns tc.z) | Chip Select to Output in 5 _ 5 ~ 5 _ 5 _ ns Low-Z toe Output Enable to Output _ 10 _ 10 _ 13 _ 20 ns Valid to.z) } Output Enable to Output 0 ~ 0 _ 5 = 5 _ ns in Low-Z tcHz) | Chip Deselect to Output _ 10 _ cB] _ 12 ~ 15 ns in High-Z toxz) | Output Disable to Output 8 _ 8 - 10 _ 13 ns in High-Z toH Output Hold from 5 _ 5 _ 5 _ 5 ns Address Change tpy) Chip Select to Power-Up 0 _ 0 0 _ 0 _ ns Time tpp) Chip Deselect to Power- 15 = 20 _ 25 35 ns Down Time 3089 tbl 12 AC ELECTRICAL CHARACTERISTICS (Vcc = 5V + 10%, All Temperature Ranges) (Continued) 6116SA45 | 6116SA557 | 6116SA70| 6116SA90" | 6116SA120)| 6116SA150%) 6116LA45 | 6116LA557) | 6116LA70")| 6116LA907 | 6116LA1207)| 6116LA150) Symbol Parameter Min. I Max. Min. | Max. Min. | Max. Min. | Max. | Min. | Max. Min. | Max. | Unit READ CYCLE tRC Read Cycle Time 45 _ 55 _ 70 _ 90 _ 120 _ 150 _ ns taa Address Access Time _ 45 _ 55 70 _ 90 _ 120 _ 150 | ns {acs Chip Select Access Time] 45 _ 50 _ 65 _ 90 _ 120 _ 150 | ns tciz) | Chip Select to Output in | 5 ~ 5 5 - 5 | 5 _ 5 | ns Low-Z 10E Output Enable to Output | 25 _ 40 _ 50 60 _ 80 _ 100 | ns Valid to.z") | Output Enable to Output | 5 5 _ 5 _ 5 | 5 5 | ns in Low-Z tcuz | Chip Deselect to Output | | 20 | 30 | ~ | 3 | 40 | 40 | ~ 40 | ns in High-Z tonz) | Qutput Disable to Output} | 15 {30 | ~ | 35 | 40 | 4o | 40 | ns in High-Z ton Output Hold from 5 _ 5 _ 5 _ 5 _ 5 _ 5 _ ns Address Change NOTES: 3089 tbl 13 1. OC to + 70C temperature range only. 2. -55C to + 125C temperature range only. 3. This parameter guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. 5.1IDT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ CYCLE No. 1: 3) tRc gl ADDRESS *K x DATA out lec Voc te ernrrene nen Supply Currents {sa 3089 drw 06 TIMING WAVEFORM OF READ CYCLE NO. 2 12:4) at tac ADDRESS a >*K P+ ton tH DATA ouT PREVIOUS DATA VALID DATA VALID 3089 drw 07 TIMING WAVEFORM OF READ CYCLE NO. 3 3: 4) SN AEA tacs | (6) < taz) ~ tcHz DATA ouT DATA VALID NOTES: 1. WE is HIGH for Read cycle. 2. Device is continously selected, CS is LOW. 3. Address valid prior to or coincident with CS transition LOW. 4. OE is Low. 5. Transition is measured +500mvV from steady state. 3089 drw 08 5.1 7IDT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Vcc = 5V + 10%, All Temperature Ranges) 6116SA15 6116SA20 6116SA25 6116SA35 6116LA15) 6116LA20 6116LA25 6116LA35 Symbol Parameter Min. | Max. Min. | Max. Min. | Max. Min. | Max. | Unit WRITE CYCLE two Write Cycle Time 15 _ 20 25 _ 35 _ ns tcw Chip Select to End-of- 13 _ 15 _ 17 _ 25 _ ns Write taw Address Valid to End- 14 16 17 _ 25 _ ns of-Write tAS Address Set-up Time 0 0 _ 0 0 ns twe Write Pulse Width 12 _ 12 _ 16 _ 20 _ ns {wR Write Recovery Time 0 _ 0 _ 0 _ 0 _ ns twuz) | Write to Output 7 _ 8 _ 16 20 ns in High-Z tow Data to Write Time 12 12 _ 13 _ 15 ns Overlap toH) | Data Hold from Write 0 _ 0 0 0 _ ns Time tow?)! Output Active from 0 _ 0 _ 0 _ 0 _ ns End-ol-Write 3089 th! 14 AC ELECTRICAL CHARACTERISTICS (Vcc = 5V + 10%, All Temperature Ranges) 6116SA45 | 6116SA55) | 6116SA702) | 6116SA90) | 6116SA120) | 6116SA1502) 6116LA45 | 6116LA55@ | 6116LA70 | 6116LA90% | 6116LA120@ | 6116LA150@ Symbol Parameter Min. | Max.} Min. | Max. Min. | Max. | Min. } Max.| Min. | Max. | Min. | Max. | Unit WRITE CYCLE two Write Cycle Time 45 _ 55 _ 70 _ 90 _ 120 _ 150 _ ns tcw Chip Select to End of 30 40 _- 40 _- 55 70 _ 90 _ ns Write tAw Address Valid to End 36 _ 45 _ 65 80 _ 105 _ 126 _ ns of Write . tAs Address Set-up Time 0 _ 5 _ 15 15 20 _ 20 _ ns twe Write Pulse Width 25 _ 40 _ 40 55 _ 70 _ 90 _ ns twR Write Recovery Time 0 _ 5 _ 5 _ 5 _ 5 10 _ ns twHz) | Write to Output _ 25 - 30 | 35 40 _ 40 _ 40 | ns in High-Z tbw Data to Write Time 20 25 _ 30 30 35 40 _ ns Overlap toH =| Data Hold from Write 0 _ 5 _ 5 _ 5 _ 5 10 _ ns Time tow4)) Output Active from 0 0 _ 0 _ 0 _ 0 _ 0 |ns End of Write NOTES: 3089 thi 15 1. 0C to +70C temperature range only. 2, ~55C to +125C temperature range only. 3. This parameter guaranteed with AC Load (Figure 2) by device characterization, but is not production tested. 4. The specification for toy must be met by the device supplying write data to the RAM under all operation conditions. Although tov and tow values will vary over voltage and temperature, the actual ton will always be smaller than the actual tow. 5.1 8IDT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1, (WE CONTROLLED TIMING) "1:2: 5: 7) neat at tw ADDRESS > < t AW cs N, KLE | ee pttwr tcxz ) va tow) oma VALID PREVIOUS DATA VALID } a tow Orion DATA IN DATA VALID 3089 drw 09 TIMING WAVEFORM OF WRITE CYCLE NO. 2, (CS CONTROLLED TIMING) 1:2 3:57) twc ADDRESS al DATA In DATA VALID 3089 drw 10 NOTES: . WE or CS must be HIGH during all address transitions. . Awrite occurs during the overlap of a LOW CS and a LOW WE. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. . During this period, the I/O pins are in the output state and the input signals must not be applied. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. . Transition is measured +500mV from steady state. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of twr or (twHz + tow) to allow the VO drivers to turn off and data to be placed on the bus for the required tow. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse is the specified twe. For a CS controlled write cycle, OE may be LOW with no degradation to tcw. NOORWH 5.1 9IDT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) ORDERING INFORMATION IDT 6116 XX XXX X X Device Type Power Speed Package Process/ Temperature Range Blank B MILITARY AND COMMERCIAL TEMPERATURE RANGES Commercial (0C to +70C) Military (-55C to + 125C) Compliant to MIL-STD-883, Class B 300 mil Plastic DIP (P24-1) 600 mil Plastic DIP (P24-2) 300 mil CERDIP (D24-1) 600 mil CERDIP (024-2) 300 mil Small Outline IC, Gull-Wing Bend (SO24-2) 300 mil SOU, J-Bend (SO24-4) Commercial Only Military Only Speed in nanoseconds Military Only Military Only Military Only Military Only Standard Power Low Power 3089 dew 11 5.1