ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY BURST CellularRAMTM MT45W2MW16BAFB Features Figure 1: Ball Assignment 54-Ball FBGA * * * * * * * * Single device supports asynchronous, page, and burst operations VCC, VCCQ Voltages 1.70V-1.95V VCC 1.70V-2.25V VCCQ (Option W) 2.30V-2.70V VCCQ (Option V--contact factory) 2.70V-3.30V VCCQ (Option L--contact factory) Random Access Time: 70ns Burst Mode Write Access Continuous burst Burst Mode Read Access 4, 8, or 16 words, or continuous burst 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CRE B DQ8 UB# A3 A4 CE# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 MAX clock rate: 104 MHz (tCLK = 9.62ns) Burst initial latency: 39ns (4 clocks) @ 104 MHz D VSSQ DQ11 A17 A7 DQ3 VCC tACLK: 6.5ns @ 104 MHz E VCCQ DQ12 NC A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 A20 J WAIT CLK ADV# NC NC NC Page Mode Read Access Sixteen-word page size Interpage read access: 70ns Intrapage read access: 20ns Low Power Consumption Asynchronous READ < 25mA Intrapage READ < 15mA Initial access, burst READ: (39ns [4 clocks] @ 104 MHz) < 35mA Continuous burst READ < 15mA Standby: 90A Low-power; 110A Standard Deep power-down < 10A Low-Power Features Temperature Compensated Refresh (TCR) On-Chip Sensor Control Partial Array Refresh (PAR) Deep Power-Down (DPD) Mode Top View (Ball Down) See Table 1 on page 6 for ball descriptions, and Figure 44 on page 52 for 54-ball mechanical drawing. Options (continued) Options * * * Configuration: 2 Meg x 16 VCC Core Voltage Supply: 1.80V - MT45WxMx16BA VCCQ I/O Voltage 3.0V - MT45WxML16BA 2.5V - MT45WxMV16BA * * 1.8V - MT45WxMW16BA Package 54-ball FBGA 54-ball FBGA--Lead-free Timing 60ns access 70ns access 85ns access 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN * Designator MT45W2Mx16BA * W L1 * V1 W Designator Frequency 66 MHz 104 MHz 6 11 Standby Power Standard Low-power None L Operating Temperature Range Wireless (-25C to +85C) Industrial (-40C to +85C) WT IT1 NOTE: FB 1. Contact factory. BB1 -601 -70 -85 Part Number Example: MT45W2MW16BAFB-706LWT 1 (c)2004 Micron Technology, Inc. All Rights Reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Burst Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Wait Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Temperature Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Partial Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Deep Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Access Using CRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Software Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Burst Length (BCR[2:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Burst Wrap (BCR[3]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output Impedance (BCR[5]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 WAIT Configuration (BCR[8]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 WAIT Polarity (BCR[10]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Latency Counter (BCR[13:11]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Operating Mode (BCR[15]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Partial Array Refresh (RCR[2:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Deep Power-Down (RCR[4]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Temperature Compensated Refresh (RCR[6:5]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Page Mode Operation (RCR[7]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Data Sheet Designation: PRELIMINARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 How Extended Timings Impact CellularRAM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Asynchronous WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Extended WRITE Timing--Asynchronous WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Burst-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Table 34: Table 35: Table 36: Table 37: Table 38: Table 39: Table 40: Table 41: Table 42: Table 43: Table 44: Table 45: Table 46: Table 47: Table 48: Table 49: FBGA Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bus Operations - Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus Operations - Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviated Component Marks - CellularRAM FBGA-Packaged Components . . . . . . . . . . . . . . . . . . . . . 8 Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Latency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 32Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Temperature Compensated Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Partial Array Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Asynchronous WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Burst WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Asynchronous READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Asynchronous READ Timing Parameters Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Asynchronous READ Timing Parameters--Page Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Burst READ Timing Parameters--Single Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Burst READ Timing Parameters--4-Word Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Burst READ Timing Parameters--4-Word Burst with LB#/UB#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Burst READ Timing Parameters--Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Burst READ Timing Parameters--BCR[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Asynchronous WRITE Timing Parameters--CE#-Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Asynchronous WRITE Timing Parameters--LB#/UB#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Asynchronous WRITE Timing Parameters--WE#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Asynchronous WRITE Timing Parameters Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Burst WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Burst WRITE Timing Parameters--BCR[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 WRITE Timing Parameters--Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 READ Timing Parameters--Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 WRITE Timing Parameters--Async WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 READ Timing Parameters--Async WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 WRITE Timing Parameters--Async WRITE Followed by Burst READ--ADV# LOW . . . . . . . . . . . . . . . . 47 READ Timing Parameters--Async WRITE Followed by Burst READ--ADV# LOW . . . . . . . . . . . . . . . . . 47 Burst READ Timing Parameters--Burst READ Followed by Async WRITE (WE#-Control) . . . . . . . . . . 48 Asynchronous WRITE Timing Parameters--Burst READ Followed by Async WRITE (WE#-Control) . 48 Burst READ Timing Parameters--Burst READ Followed by Async WRITE Using ADV# . . . . . . . . . . . . 49 Asynchronous WRITE Timing Parameters--Burst READ Followed by Async WRITE Using ADV# . . . 49 WRITE Timing Parameters--Async WRITE Followed by Async READ--ADV# LOW . . . . . . . . . . . . . . . 50 READ Timing Parameters--Async WRITE Followed by Async READ--ADV# LOW . . . . . . . . . . . . . . . . 50 WRITE Timing Parameters--Async WRITE Followed by Async READ . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 READ Timing Parameters--Async WRITE Followed by Async READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Extended Cycle Impact on READ and WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Ball Assignment 54-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional Block Diagram - 4 Meg x 16 and 2 Meg x 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Power-Up Initialization Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Page Mode READ Operation (ADV = LOW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Burst Mode READ (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Burst Mode WRITE (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Wired or WAIT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Refresh Collision During READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Refresh Collision During WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Configuration Register WRITE in Asynchronous Mode Followed by READ . . . . . . . . . . . . . . . . . . . . . . . 15 Configuration Register WRITE in Synchronous Mode Followed by READ . . . . . . . . . . . . . . . . . . . . . . . . 15 Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 WAIT Configuration (BCR[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 WAIT Configuration (BCR[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 WAIT Configuration During Burst Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Latency Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Asynchronous READ Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Page Mode READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Single-Access Burst READ Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4-Word Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4-Word Burst READ Operation (with LB#/UB#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 READ Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Continuous Burst READ with Output Delay, BCR[8] = 0(1) for End-of-Row Condition . . . . . . . . . . . . . 38 CE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 LB#/UB#-Controlled Asynchronous WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 WE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Asynchronous WRITE Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Burst WRITE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Continuous Burst WRITE with Output Delay, BCR[8] = 0(1) for End-of-Row Condition . . . . . . . . . . . . 44 Burst WRITE Followed by Burst READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Asynchronous WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Asynchronous WRITE Followed By Burst READ--ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Burst READ Followed by Asynchronous WRITE (WE#-Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Burst READ Followed by Asynchronous WRITE Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Asynchronous WRITE Followed by Asynchronous READ--ADV# LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 54-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Extended Timing for tCEM, Page Mode Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Extended Timing for tTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Extended WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY General Description Micron CellularRAMTM products are high-speed, CMOS dynamic random access memories developed for low-power, portable applications. The MT45W2MW16BA is a 32Mb device organized as 2 Meg x 16 bits. These devices include an industrystandard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-power SRAM or Pseudo SRAM offerings. To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. CellularRAM products include three system-accessible mechanisms to minimize standby current. Partial array refresh (PAR) limits refresh to only that part of the DRAM array that contains essential data. Temperature compensated refresh (TCR) uses an on-chip sensor to adjust the refresh rate to match the device temperature. The refresh rate decreases at lower temperatures to minimize current consumption during standby. TCR can also be set by the system for maximum device temperatures of +85C, +45C, and +15C. Deep power-down (DPD) halts the refresh operation altogether and is used when no vital information is stored in the device. These three refresh mechanisms are accessed through the RCR. Figure 2: Functional Block Diagram--2 Meg x 16 A[20:0] Address Decode Logic 2,048K x 16 DRAM MEMORY ARRAY Input/ Output MUX and Buffers DQ[7:0] DQ[15:8] Refresh Configuration Register (RCR) Bus Configuration Register (BCR) CE# WE# OE# CLK ADV# CRE WAIT LB# UB# Control Logic NOTE: Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing diagrams for detailed information. 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY l 1: Table FBGA Ball Descriptions FBGA ASSIGNMENT SYMBOL TYPE DESCRIPTION A3, A4, A5, B3, B4, C3, C4, D4, H2, H3, H4, H5, G3, G4, F3, F4, E4, D3, H1, G2, H6 J2 A[20:0] Input Address Inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the bus configuration register or the refresh configuration register. CLK Input J3 ADV# Input A6 CRE Input B5 CE# Input A2 OE# Input G5 WE# Input A1 B2 B6, C5, C6, D5, E5, F5, F6, G6, B1, C1, C2, D2, E2, F2, F1, G1 J1 LB# UB# DQ[15:0] Input Input Input/ Output Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is active. CLK is static (HIGH or LOW) during asynchronous access READ and WRITE operations and during PAGE READ ACCESS operations. Address Valid: Indicates that a valid address is present on the address inputs. Addresses can be latched on the rising edge of ADV# during asynchronous READ and WRITE operations. ADV# can be held LOW during asynchronous READ and WRITE operations. Configuration Register Enable: When CRE is HIGH, WRITE operations load the refresh configuration register or bus configuration register. Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby or deep power-down mode. Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a configuration register or to the memory array. Lower Byte Enable. DQ[7:0] Upper Byte Enable. DQ[15:8] Data Inputs/Outputs. WAIT Output E3, J4, J5, J6 D6 E1 E6 D1 NC VCC VCCQ VSS VSSQ - Supply Supply Supply Supply Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is gated by CE#. WAIT is used to arbitrate collisions between refresh and READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary. WAIT is also used to mask the delay associated with opening a new internal page. WAIT is asserted and should be ignored during asynchronous and page mode operations. WAIT is High-Z when CE# is HIGH. Not internally connected. Device Power Supply: (1.70V-1.95V) Power supply for device core operation. I/O Power Supply: (1.70V-1.95V) Power supply for input/output buffers. VSS must be connected to ground. VSSQ must be connected to ground. NOTE: The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. WAIT will be asserted but should be ignored during asynchronous and page mode operations. 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 2: Bus Operations--Asynchronous Mode MODE POWER CLK1 ADV# CE# OE# WE# CRE LB#/ UB# WAIT2 DQ[15:0]3 NOTES Read Write Standby No Operation Configuration Register DPD Active Active Standby Idle Active X X X X X L L X X L L L H L L L X X X H H L X X L L L L L H L L X X X Low-Z Low-Z High-Z Low-Z Low-Z Data-Out Data-In High-Z X High-Z 4 4 5, 6 4, 6 Deep Power-Down X X H X X X X High-Z High-Z 7 Table 3: Bus Operations--Burst Mode MODE POWER CLK1 ADV# CE# OE# WE# CRE LB#/ UB# WAIT2 DQ[15:0]3 NOTES Async Read Async Write Standby No Operation Initial Burst Read Active Active Standby Idle Active X X X X L L X X L L L H L L L X X X X H L X X H L L L L L L L X X L Low-Z Low-Z High-Z Low-Z Low-Z Data-Out Data-In High-Z X Data-Out 4 4 5, 6 4, 6 4, 8 Initial Burst Write Active L L H L L X Low-Z Data-In 4, 8 Burst Continue Active H L X X L X Low-Z Data-In or Data-Out 4, 8 Burst Suspend Configuration Register Active Active X X L L L H H X L L H X X Low-Z Low-Z High-Z High-Z 4, 8 8 Deep Power-Down X X H X X X X High-Z High-Z 7 DPD NOTE: 1. CLK may be HIGH or LOW, but must be static during async read, async write, burst suspend, and DPD modes; and to achieve standby power during standby and active modes. 2. The WAIT polarity is configured through the bus configuration register (BCR[10]). 3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are affected. 4. The device will consume active power in this mode whenever addresses are changed. 5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 6. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve standby current. 7. DPD is maintained until RCR is reconfigured. 8. Burst mode operation is initialized through the bus configuration register (BCR[15]). 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 4: Abbreviated Component Marks-- CellularRAM FBGA-Packaged Components PART NUMBER MT45W2MW16BAFB-701 WT MT45W2MW16BAFB-706 WT MT45W2MW16BAFB-856 WT ENGINEERING SAMPLE QUALIFIED SAMPLE PX4081 PX406 PX409 PW4081 PW406 PW409 NOTE: 1. Contact factory for availability. 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Functional Description In general, the MT45W2MW16BA device is a highdensity alternative to SRAM and Pseudo SRAM products, popular in low-power, portable applications. The MT45W2MW16BA contains 33,554,432 bits organized as 2,097,152 addresses by 16 bits. The device implements the same high-speed bus interface found on burst mode Flash products. The CellularRAM bus interface supports both asynchronous and burst mode transfers. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. UB# are driven LOW. During asynchronous WRITE operations, the OE# level is a "Don't Care," and WE# will override OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page mode disabled) can either use the ADV input to latch the address, or ADV can be driven LOW during the entire READ/WRITE operation. During asynchronous operation, the CLK input must be static (HIGH or LOW--no transition). WAIT will be driven while the device is enabled and its state should be ignored. Power-Up Initialization Figure 4: READ Operation (ADV = LOW) CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization process. Initialization will configure the BCR and the RCR with their default settings (see Table 5 on page 17 and Table 8 on page 21). VCC and VCCQ must be applied simultaneously. When they reach a stable level at or above 1.70V, the device will require 150s to complete its self-initialization process. During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation. CE# OE# WE# ADDRESS DATA Figure 3: Power-Up Initialization Timing Vcc = 1.70V Vcc VccQ ADDRESS VALID DATA VALID LB#/UB# tRC = READ Cycle Time tPU > 150s Device ready for Device Initialization normal operation DON'T CARE NOTE: ADV must remain LOW for page mode operation. Bus Operating Modes The MT45W2MW16BA CellularRAM product incorporates a burst mode interface found on Flash products targeting low-power, wireless applications. This bus interface supports asynchronous, page mode, and burst mode read and write transfers. The specific interface supported is defined by the value loaded into the bus configuration register. Page mode is controlled by the refresh configuration register (RCR[7]). Figure 5: WRITE Operation (ADV = LOW) CE# OE# WE# ADDRESS Asynchronous Mode CellularRAM products power up in the asynchronous operating mode. This mode uses the industrystandard SRAM control bus (CE#, OE#, WE#, LB#/ UB#). READ operations (Figure 4) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations (Figure 5) occur when CE#, WE#, and LB#/ 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN DATA ADDRESS VALID DATA VALID LB#/UB# tWC = WRITE Cycle Time DON'T CARE 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Page Mode READ Operation Burst Mode Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In pagemode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the low-order address. Addresses A[3:0] are used to determine the members of the 16-address CellularRAM page. Addresses A[4] and higher must remain fixed during the entire page mode access. Figure 6 shows the timing for a page mode access. Page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. WRITE operations do not include comparable page mode functionality. During asynchronous page mode operation, the CLK input must be held LOW. CE# must be driven HIGH upon completion of a page mode access. WAIT will be driven while the device is enabled and its state should be ignored. Page mode is enabled by setting RCR[7] to HIGH. WRITE operations do not include comparable page mode functionality. ADV must be driven LOW during all page mode read accesses. Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a multi-clock sequence that must be performed in an ordered fashion. After CE# goes LOW, the address to access is latched on the next rising edge of CLK that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation is going to be a READ (WE# = HIGH, Figure 7 on page 11) or WRITE (WE# = LOW, Figure 8 on page 11). The size of a burst can be specified in the BCR as either a fixed length or continuous. Fixed-length bursts consist of four, eight, or sixteen words. Continuous bursts have the ability to start at a specified address and burst through the entire memory. The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between the processor and CellularRAM device. The WAIT output will be asserted as soon as a burst is initiated, and will be de-asserted to indicate when data is to be transferred into (or out of ) the memory. WAIT will again be asserted if the burst crosses a row boundary. Once the CellularRAM device has restored the previous row's data and accessed the next row, WAIT will be de-asserted and the burst can continue (see Figure 30 on page 38). The processor can access other devices without incurring the timing penalty of the initial latency for a new burst by suspending burst mode. Bursts are suspended by stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus while the burst is suspended, OE# should be taken HIGH to disable the CellularRAM outputs; otherwise, OE# can remain LOW. Note that the WAIT output will continue to be active, and as a result no other devices should directly share the WAIT connection to the controller. To continue the burst sequence, OE# is taken LOW, then CLK is restarted after valid data is available on the bus. See the APPENDIX A on page 53 for restrictions on the maximum CE# LOW time during burst operations. If a burst suspension will cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and the burst restarted with a new CE# LOW/ADV# LOW cycle. Figure 6: Page Mode READ Operation (ADV = LOW) CE# OE# WE# ADDRESS Add[0] Add[1] tAA tAPA DATA D[0] Add[2] tAPA D[1] Add[3] tAPA D[2] D[3] LB#/UB# DON'T CARE 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 7: Burst Mode READ (4-word burst)1 CLK A[20:0] ADDRESS VALID ADV# Latency Code 2 (3 clocks) CE# OE# WE# WAIT DQ[15:0] D[0] D[1] D[2] D[3] LB#/UB# DON'T CARE READ Burst Identified (WE# = HIGH) UNDEFINED NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. Figure 8: Burst Mode WRITE (4-word burst)1 CLK A[20:0] ADDRESS VALID ADV# CE# Latency Code 2 (3 clocks) OE# WE# WAIT DQ[15:0] D[0] D[1] D[2] D[3] LB#/UB# DON'T CARE WRITE Burst Identified (WE# = LOW) NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Mixed-Mode Operation WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When WAIT transitions to an inactive state, the data burst will progress on successive clock edges. CE# must remain asserted during WAIT cycles (WAIT asserted and WAIT configuration BCR[8] = 1). Bringing CE# HIGH during WAIT cycles may cause data corruption. (Note that for BCR[8] = 0, the actual WAIT cycles end one cycle after WAIT deasserts, and for row boundary crossings, start one cycle after the WAIT signal asserts.) The WAIT output also performs an arbitration role when a READ or WRITE operation is launched while an on-chip refresh is in progress. If a collision occurs, the WAIT pin is asserted for additional clock cycles until the refresh has completed (see Figures 10 and 11 on page 13). When the refresh operation has completed, the READ or WRITE operation will continue normally. WAIT is also asserted when a continuous READ or WRITE burst crosses a row boundary. The WAIT assertion allows time for the new row to be accessed, and permits any pending refresh operations to be performed. The device can support a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for synchronous operation. The asynchronous WRITE operation requires that the clock (CLK) remain static (HIGH or LOW) during the entire sequence. The ADV# signal can be used to latch the target address, or it can remain LOW during the entire WRITE operation. CE# must return HIGH when transitioning between mixed-mode operations. Note that the tCKA period is the same as a READ or WRITE cycle. This time is required to ensure adequate refresh. Mixed-mode operation facilitates a seamless interface to legacy burst mode Flash memory controllers. See Figure 38 on page 46 for the "Asynchronous WRITE Followed by Burst READ" timing diagram. WAIT Operation The WAIT output on a CellularRAM device is typically connected to a shared, system-level WAIT signal (see Figure 9 below). The shared WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus. Figure 9: Wired or WAIT Configuration LB#/UB# Operation CellularRAM WAIT External Pull-Up/ Pull-Down Resistor The LB# enable and UB# enable signals support byte-wide data transfers. During READ operations, the enabled byte(s) are driven onto the DQs. The DQs associated with a disabled byte are put into a High-Z state during a READ operation. During WRITE operations, any disabled bytes will not be transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. When both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW. READY Processor WAIT WAIT Other Device Other Device Once a READ or WRITE operation has been initiated, WAIT goes active to indicate that the CellularRAM device requires additional time before data can be transferred. For READ operations, WAIT will remain active until valid data is output from the device. For 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 10: Refresh Collision During READ Operation1 CLK A[20:0] ADV# CE# OE# WE# LB#/UB# WAIT DQ[15:0] VIH VIL VIH VALID ADDRESS VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High-Z VOH D[0] VOL D[1] Additional WAIT states inserted to allow refresh completion. D[2] D[3] UNDEFINED DON'T CARE NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. Figure 11: Refresh Collision During WRITE Operation1 CLK A[20:0] ADV# CE# OE# WE# LB#/UB# WAIT DQ[15:0] VIH VIL VIH VIL VALID ADDRESS VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High-Z VOH D[0] VOL D[1] D[2] Additional WAIT states inserted to allow refresh completion. D[3] DON'T CARE NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Low-Power Operation Standby Mode Operation Deep Power-Down Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion of a READ or WRITE operation, or when the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the address or control inputs. Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled by rewriting the RCR, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. During this 150s period, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. DPD cannot be enabled or disabled by writing to the RCR using the software access sequence; the RCR should be accessed using CRE instead. Temperature Compensated Refresh Temperature compensated refresh (TCR) allows for adequate refresh at different temperatures. This CellularRAM device includes an on-chip temperature sensor. When the sensor is enabled, it continually adjusts the refresh rate according to the operating temperature. The on-chip sensor is enabled by default. Three fixed refresh rates are also available, corresponding to temperature thresholds of +15C, +45C, and +85C. The setting selected must be for a temperature higher than the case temperature of the CellularRAM device. If the case temperature is +35C, the system can minimize self-refresh current consumption by selecting the +45C setting. The +15C setting would result in inadequate refreshing and cause data corruption. Configuration Registers Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up, and can be updated any time the devices are operating in a standby state. Access Using CRE Partial Array Refresh The configuration registers are loaded using either a synchronous or an asynchronous WRITE operation when the configuration register enable (CRE) input is HIGH (see Figures 12 and 13 on page 15). When CRE is LOW, a READ or WRITE operation will access the memory array. The register values are placed on address pins A[20:0]. In an asynchronous WRITE, the values are are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are "Don't Care." Access using CRE is WRITE only. The BCR is accessed when A[19] is HIGH; the RCR is accessed when A[19] is LOW. Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, three-quarters array, one-half array, one-quarter array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Table 9 on page 22). READ and WRITE operations to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become corrupted. When reenabling additional portions of the array, the new portions are available immediately upon writing to the RCR. 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 12: Configuration Register WRITE in Asynchronous Mode Followed by READ ARRAY Operation CLK A[20:0] (except A19) OPCODE ADDRESS tAVH tAVS Select Control Register A191 ADDRESS tAVS CRE tAVH tVPH ADV# tVP tCBPH Initiate Control Register Access CE# tCW OE# tWP Write Address Bus Value to Control Register WE# LB#/UB# DQ[15:0] DATA VALID DON'T CARE NOTE: 1. A[19] = LOW to load RCR; A[19] = HIGH to load BCR. Figure 13: Configuration Register WRITE in Synchronous Mode Followed by READ ARRAY Operation1 CLK Latch Control Register Value A[20:0] (except A19) ADDRESS OPCODE tSP tHD Latch Control Register Address A192 ADDRESS tSP CRE tSP ADV# tHD tHD tCBPH3 tCSP CE# OE# tSP WE# tHD LB#/UB# WAIT tCW High-Z High-Z DATA VALID DQ[15:0] DON'T CARE NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR. 3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored--additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Software Access Figure 14: Load Configuration Register Software access of the configuration registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the configuration registers can be read or modified using the software sequence. The configuration registers are loaded using a fourstep sequence consisting of two asynchronous READ operations followed by two asynchronous WRITE operations (see Figure 14). The read sequence is virtually identical except that an asynchronous READ is performed during the fourth operation (see Figure 15). The address used during all READ and WRITE operations is the highest address of the CellularRAM device being accessed (1FFFFFh for 32Mb); the contents of this address are not changed by using this sequence. The data value presented during the third operation (WRITE) in the sequence defines whether the BCR or the RCR is to be accessed. If the data is 0000h, the sequence will access the RCR; if the data is 0001h, the sequence will access the BCR. During the fourth operation, the data bus is used to transfer data in to or out of the configuration registers. The use of the software sequence does not affect the ability to perform the standard (CRE-controlled) method of loading the configuration registers. However, the software nature of this access mechanism eliminates the need for the control register enable (CRE) pin. If the software mechanism is used, the CRE pin can simply be tied to VSS. The port line often used for CRE control purposes is no longer required. Software access of the RCR should not be used to enter or exit DPD. ADDRESS READ READ WRITE WRITE ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) XXXXh XXXXh CE# OE# WE# LB#/UB# DATA CR VALUE IN RCR: 0000h BCR: 0001h DON'T CARE Figure 15: Read Configuration Register ADDRESS READ READ WRITE READ ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) CE# NOTE OE# WE# LB#/UB# DATA XXXXh CR VALUE OUT XXXXh RCR: 0000h BCR: 0001h DON'T CARE NOTE: CE# must be HIGH for 150ns before performing the cycle that reads a configuration register. 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Bus Configuration Register The BCR is accessed using CRE and A[19] HIGH, or through the configuration register software sequence with DQ = 0001h on the third cycle. The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Table 5 on page 17 describes the control bits in the BCR. At power-up, the BCR is set to 9D4Fh. Table 5: Bus Configuration Register Definition A[20] 20 Reserved A15 A19 A[18:16] 18-16 19 Register Select Reserved 15 14 Operating Mode Must be set to "0" All must be set to "0" A14 A13 A12A11 A10 Reserved 13 12 11 Latency Counter Must be set to "0" BCR[13] BCR[12] BCR[11] 9 WAIT Polarity A7 Reserved A5 A6 7 8 WAIT Configuration (WC) Reserved Must be set to "0" A4 4 5 6 Clock Configuration (CC) Output Impedance Must be set to "0" Reserved A3 A2 A1 A0 3 2 1 0 Burst Burst Wrap (BW)* Length (BL)* Must be set to "0" Latency Counter 0 0 0 Code 0-Reserved 0 0 1 Code 1-Reserved 0 1 0 Code 2 0 1 1 Code 3 (Default) 1 0 0 Code 4-Reserved 1 0 1 Code 5-Reserved 1 1 0 Code 6-Reserved 1 1 1 Code 7-Reserved BCR[10] Burst Wrap (Note 1) BCR[3] 0 Burst wraps within the burst length 1 Burst no wrap (default) WAIT Polarity 0 Active LOW 1 Active HIGH (default) BCR[8] BCR[15] 10 A8 A9 Output Impedance BCR[5] 0 Full Drive (default) 1 1/4 Drive WAIT Configuration BCR[6] 0 Asserted during delay 1 Asserted one data cycle before delay (default) Clock Configuration 0 Not supported 1 Rising edge (default) Operation Mode 0 Synchronous burst access mode 1 Asynchronous access mode (default) BCR[2] Register Select BCR[19] 0 Select RCR 1 Select BCR BCR[1] BCR[0] Burst Length (Note 1) 0 0 1 4 words 0 1 0 8 words 0 1 1 16 words 1 1 1 Continuous burst (default) NOTE: 1. All burst WRITEs are continuous. 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 6: Sequence and Burst Length BURST WRAP STARTING ADDRESS 4-WORD BURST LENGTH BCR[3] WRAP (DECIMAL) LINEAR LINEAR LINEAR LINEAR 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-... 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3-4-5-6-7-... 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4-5-6-7-8-... 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5-6-7-8-9-... 4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-7-8-9-10-... 5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-6-7-8-9-10-11-... 6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-8-9-10-11-12- 7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-8-9-10-11-12-13-... 0 Yes 8-WORD BURST LENGTH ... ... ... 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-17-18-19-20-.. 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-18-19-20-21.. 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-... 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-4-5-6-7-... 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 2-3-4-5-6-7-8-... 3 3-4-5-6 4 No CONTINUOUS BURST 14 15 1 16-WORD BURST LENGTH 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 4-5-6-7-8-9-10-... 5 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-...-15-16-17-18-19-20 5-6-7-8-9-10-11... 6 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-...-16-17-18-19-20-21 6-7-8-9-10-11-12... 7 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13-14-...-17-18-19-20-21-22 7-8-9-10-11-12-13... ... ... ... 14 14-15-16-17-18-19-...-23-24-25-26-27-28-29 14-15-16-17-18-19-20-... 15 15-16-17-18-19-20-...-24-25-26-27-28-29-30 15-16-17-18-19-20-21-... Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength The output driver strength can be altered to adjust for different data bus loading scenarios. The reducedstrength option should be more than adequate in stacked chip (Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced-drivestrength option is included to minimize noise generated on the data bus during READ operations. Normal output impedance should be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment. Partial drive is approximately one-quarter full drive strength. Outputs are configured at full drive strength during testing. Burst Length (BCR[2:0]) Default = Continuous Burst Burst lengths define the number of words the device outputs during a burst READ operation. The device supports a burst length of 4, 8, or 16 words. The device can also be set in continuous burst mode where data is output sequentially without regard to address boundaries. WRITE bursts are always performed using continuous burst mode. Burst Wrap (BCR[3]) Default = Burst No Wrap The burst wrap option determines if a 4-, 8-, or 16word burst READ wraps within the burst length or steps through sequential addresses. If the wrap option is not enabled, the device outputs data from sequential addresses without regard to burst boundaries. When continuous burst operation is selected, the internal address wraps to 000000h if the device is read past the last address. 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after WAIT transitions to the de-asserted or asserted state, respectively (Figures 16 and 18). When A8 = 1, the WAIT signal transitions one clock period prior to the data bus going valid or invalid (Figures 17 and 16). Figure 16: WAIT Configuration (BCR[8] = 0) WAIT Polarity (BCR[10]) Default = WAIT Active HIGH The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down resistor to maintain the de-asserted state. Figure 17: WAIT Configuration (BCR[8] = 1) CLK WAIT DQ[15:0] High-Z Data[0] Data[1] Data immediately valid (or invalid) NOTE: 1. Note: Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 18. CLK WAIT D[15:0] High-Z Data[0] Data valid (or invalid) after one clock delay NOTE: 1. Note: Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 18. Figure 18: WAIT Configuration During Burst Operation1 CLK BCR[8] = 0 DATA VALID IN CURRENT CYCLE WAIT BCR[8] = 1 DATA VALID IN NEXT CYCLE WAIT DQ[15:0] D[0] D[1] D[2] D[3] D[4] DON'T CARE NOTE: 1. Non-default BCR setting: WAIT active LOW. 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Operating Mode (BCR[15]) Default = Asynchronous Operation The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation. Latency Counter (BCR[13:11]) Default = Three-Clock Latency The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data value transferred. Only latency code two (three clocks) or latency code three (four clocks) is allowed (see Table 7 and Figure 19 below). Table 7: Latency Configuration MAX INPUT CLK FREQUENCY (MHz) LATENCY CONFIGURATION CODE -701 -706 2 (3 clocks) 66 (15.2ns) 3 (4 clocks) - default 104 (9.62ns) -856 1 (22.7ns) 441 (22.7ns) 44 66 (15.2ns) 66 (15.2ns) NOTE: 1. Clock rates below 50 MHz are allowed as long as tCSP specifications are met. Figure 19: Latency Counter CLK A[20:0] ADV# VIH VIL VIH VIL VALID ADDRESS VIH VIL Code 2 DQ[15:0] VOH VALID OUTPUT VOL Code 3 DQ[15:0] VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT (Default) VOH VOL DON'T CARE 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 20 UNDEFINED Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Refresh Configuration Register Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, three-quarters array, one-half array, one-quarter array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Table 9 on page 22. The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Table 8 below describes the control bits used in the RCR. At power-up, the RCR is set to 0010h. The RCR is accessed using CRE and A[19] LOW; or through the configuration register software access sequence with DQ = 0000h on the third cycle (see Configuration Registers on page 14.) Table 8: Refresh Configuration Register Mapping A20 20 RESERVED A19 19 Register Select A[18:8] 18-8 RESERVED A6 A7 7 PAGE 6 A5 A4 5 TCR 4 Select RCR 1 Select BCR RCR[7] A0 0 1 2 RESERVED Address Bus Read Configuration Register PAR Must be set to "0" Refresh Coverage RCR[2] RCR[1] RCR[0] 0 0 0 Full array (default) 0 0 1 Bottom 3/4 array 0 1 0 Bottom 1/2 array 0 1 1 Bottom 1/4 array Register Select 0 A1 A2 3 DPD All must be set to "0" All must be set to "0" RCR[19] A3 Page Mode Enable/Disable 1 0 0 None of array 1 0 1 Top 3/4 array 0 Page Mode Disabled (default) 1 1 0 Top 1/2 array 1 Page Mode Enable 1 1 1 Top 1/4 array RCR[6] RCR[5] Maximum Case Temp. RCR[4] Deep Power-Down 1 1 +85C 0 DPD Enable 0 0 Internal sensor (default) 1 DPD Disable (default) 0 1 +45C 1 0 +15C 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 9: 32Mb Address Patterns for PAR (RCR[4] = 1) RCR[2] RCR[1] RCR[0] ACTIVE SECTION ADDRESS SPACE SIZE DENSITY 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Full die Three-quarters of die One-half of die One-quarter of die None of die Three-quarters of die One-half of die One-quarter of die 000000h-1FFFFFh 000000h-17FFFFh 000000h-0FFFFFh 000000h-07FFFFh 0 080000h-1FFFFFh 100000h-1FFFFFh 180000h-1FFFFFh 2 Meg x 16 1.5 Meg x 16 1 Meg x 16 512K x 16 0 Meg x 16 1.5 Meg x 16 1 Meg x 16 512K x 16 32Mb 24Mb 16Mb 8Mb 0Mb 24Mb 16Mb 8Mb Deep Power-Down (RCR[4]) Default = DPD Disabled The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. Deep power-down is enabled when RCR[4] = 0, and remains enabled until RCR[4] is set to "1." DPD should not be enabled or disabled with the software access sequence; instead, use CRE to access the RCR. other TCR setting enables a fixed refresh rate. When the on-chip temperature sensor is enabled, the device continually adjusts the refresh rate according to the operating temperature. The TCR bits also allow for adequate fixed-rate refresh at three different temperature thresholds (+15C, +45C, and +85C). The setting selected must be for a temperature higher than the case temperature of the CellularRAM device. If the case temperature is +35C, the system can minimize self refresh current consumption by selecting the +45C setting. The +15C setting would result in inadequate refreshing and cause data corruption. Temperature Compensated Refresh (RCR[6:5]) Default = On-Chip Temperature Sensor This CellularRAM device includes an on-chip temperature sensor that automatically adjusts the refresh rate according to the operating temperature. The onchip TCR is enabled by clearing both of the TCR bits in the refresh configuration register (RCR[6:5] = 00b). Any 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN Page Mode Operation (RCR[7]) Default = Disabled The page mode operation bit determines whether page mode is enabled for asynchronous READ operations. In the power-up default state, page mode is disabled. 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Absolute Maximum Ratings* *Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage to Any Ball Except VCC, VCCQ Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50V to (4.0V or VCCQ + 0.3V, whichever is less) Voltage on VCC Supply Relative to VSS . . -0.2V to +2.45V Voltage on VCCQ Supply Relative to VSS . -0.2V to +4.0V Storage Temperature (plastic). . . . . . . . -55C to +150C Operating Temperature (case) Wireless. . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C Industrial . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Soldering Temperature and Time 10s (lead only) . . . . . . . . . . . . . . . . . . . . . . . . . . . +260C Table 10: Electrical Characteristics and Operating Conditions Wireless Temperature (-25C < TC < +85C); Industrial Temperature (-40C < TC < +85C) DESCRIPTION CONDITIONS VCC VCCQ Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Operating Current Asynchronous Random READ SYMBOL IOH = -0.2mA IOL = +0.2mA VIN = 0 to VCCQ OE# = VIH or Chip Disabled VIH VIL VOH VOL ILI ILO VIN = VCCQ or 0V Chip Enabled, IOUT = 0 ICC1 VIN = VCCQ or 0V Chip Enabled, IOUT = 0 ICC1 WRITE Operating Current VIN = VCCQ or 0V Chip Enabled ICC2 Standby Current VIN = VCCQ or 0V CE# = VCCQ ISB Asynchronous Page READ Initial Access, Burst READ Continuous Burst READ W: 1.8V V: 2.5V L: 3.0V MIN MAX UNITS 1.70 1.70 2.30 2.70 1.40 -0.20 0.80 VCCQ 1.95 2.25 2.70 3.30 VCCQ + 0.2 0.4 V V V V V V V V A A 0.20 VCCQ 1 1 -70 -85 -70 -85 104 MHz 66 MHz 104 MHz 66 MHz -70 -85 Standard Low-Power (L) 25 20 15 12 35 30 11 11 25 20 110 90 NOTES 1 2 3 3 mA 4 mA 4 mA A 5 NOTE: 1. 2. 3. 4. Input signals may overshoot to VccQ + 1.0V for periods less than 2ns during transitions. Input signals may undershoot to Vss - 1.0V for periods less than 2ns during transitions. BCR[5:4] = 00b. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected in the actual system. 5. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85C. In order to achieve low standby current, all inputs must be driven to either VCCQ or VSS. 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 11: Temperature Compensated Refresh Specifications and Conditions DESCRIPTION Temperature Compensated Refresh Standby Current CONDITIONS SYMBOL POWER VIN = VCCQ or 0V CE# = VCCQ ITCR Standard Power (no desig.) MAX CASE TEMPERATURE SETTING (RCR[6:5]) MAX UNITS +85C +45C +15C +85C +45C +15C 110 TBD TBD 90 TBD TBD A Low-Power Option (L) A NOTE: ITCR (MAX) values measured with PAR set to FULL ARRAY. Table 12: Partial Array Refresh Specifications and Conditions DESCRIPTION Partial Array Refresh Standby Current CONDITIONS SYMBOL VIN = VCCQ or 0V, CE# = VCCQ IPAR POWER ARRAY PARTITION MAX UNITS Standard Power (no desig.) Full 3/4 1/2 1/4 0 Full 3/4 1/2 1/4 0 110 TBD TBD TBD TBD 90 TBD TBD TBD TBD A Low-Power Option (L) A NOTE: IPAR (MAX) values measured with TCR set to 85C. Table 13: Deep Power-Down Specifications DESCRIPTION Deep Power-Down 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN CONDITIONS SYMBOL TYP UNITS VIN = VCCQ or 0V; +25C IZZ 10 A 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 14: Capacitance DESCRIPTION Input Capacitance Input/Output Capacitance (DQ) CONDITIONS SYMBOL MIN MAX UNITS NOTES TC = +25C; f = 1 MHz; VIN = 0V CIN CIO - - 6 6 pF pF 1 1 NOTE: 1. These parameters are verified in device characterization and are not 100% tested. Figure 20: AC Input/Output Reference Waveform VCCQ Input 1 VCC/2 2 VCCQ/2 Test Points 3 Output VSS NOTE: 1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. 2. Input timing begins at VCC/2. Due to the possibility of a difference between VCC and VCCQ, the input test point may not be shown to scale. 3. Output timing ends at VCCQ/2. Figure 21: Output Load Circuit Table 15: Output Load Circuit VccQ R1 Test Point DUT 30pF R2 VCCQ R1/R2 1.8V 2.5V 3.0V 2.7K 3.7K 4.5K NOTE: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0). 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 16: Asynchronous READ Cycle Timing Requirements1 -701, -706 PARAMETER SYMBOL Address Access Time tAA 70 85 ns ADV# Access Time t AADV 70 85 ns Page Access Time t APA 20 25 ns Address Hold from ADV# HIGH t AVH 5 5 ns Address Setup to ADV# HIGH t AVS 10 10 ns LB#/UB# Access Time tBA LB#/UB# Disable to DQ High-Z Output tBHZ LB#/UB# Enable to Low-Z Output t CE# HIGH between Subsequent Mixed-Mode Operations tCBPH Maximum CE# Pulse Width tCEM BLZ MIN MAX -856 MIN MAX UNITS NOTES 70 85 ns 8 8 ns 4 3 10 10 ns 5 5 ns 10 1 CE# LOW to WAIT Valid tCEW Chip Select Access Time tCO CE# LOW to ADV# HIGH tCVS Chip Disable to DQ and WAIT High-Z Output tHZ Chip Enable to Low-Z Output tLZ Output Enable to Valid Output tOE Output Hold from Address Change tOH Output Disable to DQ High-Z Output tOHZ Output Enable to Low-Z Output tOLZ 5 Page Cycle Time tPC READ Cycle Time tRC ADV# Pulse Width LOW tVP ADV# Pulse Width HIGH tVPH 7.5 1 70 10 10 s 7.5 ns 85 ns 10 8 10 ns 8 10 20 5 20 5 8 2 ns 4 ns 3 ns ns 8 ns 4 5 ns 3 20 25 ns 70 85 ns 10 10 ns 10 10 ns NOTE: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0). 2. See the Appendix at the end of this data sheet. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 21 on page 25. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 4. Low-Z to High-Z timings are tested with the circuit shown in Figure 21 on page 25. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 17: Burst READ Cycle Timing Requirements1 -701 PARAMETER SYMBOL Burst to READ Access Time tABA CLK to Output Delay t Burst OE# LOW to Output Delay t MAX UNITS 35 55 ns ACLK 6.5 10 ns BOE 20 20 ns CE# HIGH between Subsequent Mixed-Mode Operations tCBPH t CE# LOW to WAIT Valid CEW MIN -706, -856 MAX 5 MIN 5 ns 1 7.5 1 7.5 ns CLK Period tCLK 9.62 20 15 20 ns CE# Setup Time to Active CLK Edge tCSP 4 20 5 20 ns Hold Time from Active CLK Edge t 2 Chip Disable to DQ and WAIT High-Z Output tHZ CLK Rise or Fall Time tKHKL CLK to WAIT Valid tKHTL CLK to DQ High-Z Output tKHZ 3 8 3 CLK to Low-Z Output tKLZ 2 5 2 Output HOLD from CLK tKOH 2 2 ns CLK HIGH or LOW Time tKP 3 3 ns Output Disable to DQ High-Z Output tOHZ Output Enable to Low-Z Output tOLZ 5 Setup Time to Active CLK Edge tSP 3 HD 2 8 ns 1.6 1.6 ns 10 ns 8 ns 5 ns 8 4 ns 8 6.5 NOTES 8 2 ns 2 5 ns 3 3 ns NOTE: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0). 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 21 on page 25. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 21 on page 25. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 4. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 18: Asynchronous WRITE Cycle Timing Requirements -701, -706 PARAMETER SYMBOL Address and ADV# LOW Setup Time t 0 0 ns Address Hold from ADV# Going HIGH t 5 5 ns Address Setup to ADV# Going HIGH tAVS 10 10 ns Address Valid to End of Write t 70 85 ns LB#/UB# Select to End of Write t 70 85 ns Maximum CE# Pulse Width t CE# LOW to WAIT Valid t CEW 1 Async Address-to-Burst Transition Time tCKA 70 85 ns CE# Low to ADV# HIGH tCVS 10 10 ns Chip Enable to End of Write tCW 70 85 ns Data Hold from Write Time tDH 0 0 ns Data WRITE Setup Time tDW 23 23 ns Chip Disable to WAIT High-Z Output tHZ Chip Enable to Low-Z Output tLZ End WRITE to Low-Z Output tOW ADV# Pulse Width AS AVH AW BW MIN MAX -856 MIN 10 CEM 7.5 1 8 MAX UNITS 10 s 7.5 ns 8 NOTES 1 1 ns 10 10 ns 3 5 5 ns 3 tVP 10 10 ns ADV# Pulse Width HIGH tVPH 10 10 ns ADV# Setup to End of WRITE tVS 70 85 ns WRITE Cycle Time tWC 70 85 ns WRITE to DQ High-Z Output tWHZ WRITE Pulse Width tWP 46 WRITE Pulse Width HIGH tWPH WRITE Recovery Time tWR 8 8 ns 2 55 ns 1 10 10 ns 0 0 ns NOTE: 1. See the Appendix at the end of this data sheet. 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 21 on page 25. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 21 on page 25. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 19: Burst WRITE Cycle Timing Requirements -701 PARAMETER SYMBOL MIN -706, -856 MAX MIN MAX CE# HIGH between Subsequent Mixed-Mode Operations tCBPH 5 CE# LOW to WAIT Valid t 1 7.5 1 7.5 ns Clock Period tCLK 9.62 20 15 20 ns CE# Setup to CLK Active Edge t CSP 4 20 5 20 ns Hold Time from Active CLK Edge t HD 2 Chip Disable to WAIT High-Z Output t HZ CLK Rise or Fall Time t CEW 5 UNITS NOTES ns 2 1 ns 8 8 ns KHKL 1.6 1.6 ns Clock to WAIT Valid tKHTL 6.5 10 ns CLK HIGH or LOW Time tKP 3 3 ns Setup Time to Activate CLK Edge tSP 3 3 ns NOTE: 1. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY TIMING DIAGRAMS Figure 22: Initialization Period Vcc (MIN) Vcc, VccQ = 1.70V tPU Device ready for normal operation Table 20: Initialization Timing Parameters -701, -706 PARAMETER SYMBOL Initialization Period (required before normal operations) tPU 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 30 MIN MAX 150 -856 MIN MAX UNITS 150 s NOTE Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 23: Asynchronous READ tRC VIH A[20:0] VALID ADDRESS VIL tAA ADV# VIH VIL tCBPH CE# tHZ VIH VIL LB#/UB# tCO tBA VIH tBHZ VIL tOE OE# WE# tOHZ VIH VIL VIH VIL tBLZ tOLZ tLZ VOH DQ[15:0] High-Z VOL VALID OUTPUT tCEW tHZ VIH WAIT High-Z VIL High-Z DON'T CARE UNDEFINED Table 21: Asynchronous READ Timing Parameters -701, -706 SYMBOL MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL MIN MAX -856 MIN AA 70 85 ns 70 85 ns tLZ 8 8 ns t OE 20 20 ns 8 8 ns BHZ HZ 10 10 ns tOHZ tCBPH 5 5 ns tOLZ t 1 7.5 ns t 85 ns tBLZ CEW tCO 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 7.5 70 1 31 RC 10 8 UNITS tBA t 8 MAX t t 10 ns ns 5 5 ns 70 85 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 24: Asynchronous READ Using ADV# VIH A[20:0] VALID ADDRESS VIL tAA tAVS tVPH tAVH VIH ADV# VIL tAADV tVP tCBPH tCVS tHZ VIH CE# VIL tCO tBA tBHZ VIH LB#/UB# VIL tOE tOHZ VIH OE# VIL VIH WE# tOLZ tBLZ VIL tLZ VOH DQ[15:0] High-Z VALID OUTPUT VOL tCEW tHZ VIH WAIT High-Z VIL High-Z DON'T CARE UNDEFINED Table 22: Asynchronous READ Timing Parameters Using ADV# -701, -706 SYMBOL tAA tAADV t AVH tAVS MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL 70 85 ns tCO 70 85 ns tCVS 5 5 ns t 10 10 ns tLZ MIN MAX -856 MIN 70 10 UNITS 85 ns 10 8 HZ MAX 10 ns 8 10 ns ns BA 70 85 ns t OE 20 20 ns tBHZ 8 8 ns tOHZ 8 8 ns t tBLZ t CBPH tCEW 10 10 ns tOLZ 5 5 ns t ns 1 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 7.5 1 7.5 32 5 5 ns VP 10 10 ns tVPH 10 10 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 25: Page Mode READ tRC A[20:4] VIH VALID ADDRESS VIL VIH A[3:0] ADV# VALID ADDRESS VIL VALID ADDRESS VALID ADDRESS tPC tAA VIH VALID ADDRESS VIL tCEM VIH tCBPH tHZ tCO tCBPH CE# VIL LB#/UB# tBA VIH tBHZ VIL tOHZ tOE VIH OE# VIL VIH WE# tOLZ tBLZ VIL VOH DQ[15:0] tAPA tOH tLZ VALID OUTPUT High-Z VOL VALID OUTPUT tCEW VALID OUTPUT tHZ VIH WAIT VALID OUTPUT High-Z VIL High-Z DON'T CARE UNDEFINED Table 23: Asynchronous READ Timing Parameters--Page Mode Operation -701, -706 SYMBOL MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL tAA 70 85 ns tHZ t 20 25 ns t 70 85 ns tOE 8 8 ns t APA tBA t BHZ tBLZ tCBPH t OH 10 10 ns tOHZ 5 5 ns tOLZ 10 CEM tCEW LZ 1 tCO 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 7.5 70 1 MIN MAX -856 MIN 8 10 UNITS 8 ns 10 20 5 ns 20 5 8 5 MAX ns ns 8 ns 5 ns 10 s t PC 20 25 ns 7.5 ns tRC 70 85 ns 85 ns 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 26: Single-Access Burst READ Operation1 tCLK tKP tKP tKHKL VIH CLK A[20:0] VIL tSP VIH tHD VALID ADDRESS VIL tSP tHD VIH ADV# VIL tHD CE# tCSP VIH tHZ tABA VIL tBOE tOHZ VIH OE# VIL tSP WE# tOLZ tHD VIH VIL tHD tSP VIH LB#/UB# VIL tCEW VOH WAIT tKHTL High-Z High-Z VOL DQ[15:0] tKOH tACLK VOH VALID OUTPUT High-Z VOL READ Burst Identified (WE# = HIGH) DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 24: Burst READ Timing Parameters--Single Access -706, -856 -701 SYMBOL MIN MAX MIN -706, -856 -701 MAX UNITS MAX UNITS tABA 35 55 ns SYMBOL tKHKL 1.6 1.6 ns tACLK 6.5 10 ns tKHTL 6.5 10 ns tBOE 20 20 ns tKOH 2 2 ns 3 3 ns t 1 7.5 1 7.5 ns t t CEW KP MIN MAX MIN CLK 9.62 20 15 20 ns t tCSP 4 20 5 20 ns tOLZ 5 5 ns tHD 2 ns tSP 3 3 ns t HZ 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 2 8 8 8 OHZ 8 ns ns 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 27: 4-Word Burst READ Operation1 tKHKL CLK A[20:0] CE# tKP VIL tHD tSP VIH VALID ADDRESS VIL tSP ADV# tKP tCLK VIH tHD VIH VIL tHD tABA tCSP VIH VIL tCBPH tHZ tBOE OE# WE# LB#/UB# VIH VIL tOHZ tSP tHD tSP tHD tOLZ VIH VIL VIH VIL tKHTL tCEW WAIT VOH High-Z VOL High-Z tACLK DQ[15:0] VOH VALID OUTPUT High-Z VOL tKOH VALID OUTPUT VALID OUTPUT VALID OUTPUT READ Burst Identified (WE# = HIGH) UNDEFINED DON'T CARE NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 25: Burst READ Timing Parameters--4-Word Burst -701 SYMBOL MIN -706, -856 MAX UNITS 35 55 ns t 8 8 ns 6.5 10 ns tKHKL 1.6 1.6 ns 20 ns tKHTL 6.5 10 ns ns t 2 2 ns 3 3 ns ABA tACLK tBOE 20 5 t 1 7.5 1 7.5 ns t CEW MIN HZ t CBPH 5 SYMBOL -706, -856 MAX t MIN -701 KOH KP MAX MIN 9.62 20 15 20 ns t CSP 4 20 5 20 ns t 5 5 ns tHD 2 ns tSP 3 3 ns 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 2 OLZ 35 8 UNITS tOHZ tCLK 8 MAX ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 28: 4-Word Burst READ Operation (with LB#/UB#)1 tCLK CLK A[20:0] VIH VIL tHD tSP VIH VALID ADDRESS VIL tSP ADV# CE# tHD VIH VIL tHD tABA tCSP VIH tCBPH VIL tHZ tBOE OE# WE# LB#/UB# VIH VIL tOHZ tSP tHD tSP tHD tOLZ VIH VIL VIH VIL tCEW WAIT tKHTL VOH High-Z VOL High-Z tKOH tACLK DQ[15:0] VOH VALID OUTPUT High-Z VOL tKHZ tKHZ tKLZ VALID OUTPUT VALID OUTPUT High-Z READ Burst Identified (WE# = HIGH) DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. BCR configured with a burst length of four. Table 26: Burst READ Timing Parameters--4-Word Burst with LB#/UB# -706, -856 -701 SYMBOL MIN MAX UNITS tABA 35 55 ns tHZ t 6.5 10 ns t 20 20 ns tKHZ 3 8 ns t KLZ 2 5 2 ACLK tBOE MAX MIN -706, -856 -701 CBPH 5 t CEW 1 7.5 1 7.5 ns t KOH t CLK 9.62 20 15 20 ns t OHZ CSP 4 20 5 20 ns t OLZ tHD 2 ns tSP 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 2 36 MIN KHTL t t 5 SYMBOL MAX MAX UNITS 8 MIN 8 ns 6.5 10 ns 3 8 ns 2 5 ns 2 8 ns 8 ns 5 5 ns 3 3 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 29: READ Burst Suspend1 tCLK VIH CLK VIL tSP VIH A[20:0] VIL tHD VALID ADDRESS VALID ADDRESS tSP tHD VIH ADV# VIL tCBPH VIH tHZ tCSP CE# VIL tOHZ OE# tOHZ VIH VIL VIH WE# VIL VIH LB#/UB# VIL tSP tHD tSP tHD tBOE VOH tOLZ WAIT VOL High-Z tKOH VALID OUTPUT High-Z VALID OUTPUT VALID OUTPUT High-Z tBOE tOLZ VOH DQ[15:0] VOL VALID OUTPUT VALID OUTPUT VALID OUTPUT tACLK DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 27: Burst READ Timing Parameters--Burst Suspend -701 SYMBOL t MIN ACLK tBOE tCBPH -706, -856 MAX MAX UNITS 6.5 10 ns t 20 20 ns tKOH ns tOHZ 5 MIN -701 5 SYMBOL CLK 9.62 20 15 20 ns tCSP 4 20 5 20 ns tSP tHD 2 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 2 OLZ MAX MIN 8 HZ t t MIN -706, -856 2 MAX UNITS 8 ns 2 8 ns 8 ns 5 5 ns 3 3 ns ns 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 30: Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition1 CLK VIH VIL tCLK A[20:0] VIH VIL ADV# VIH VIL LB#/UB# VIH VIL CE# VIH VIL OE# VIH VIL WE# VIH VIL tKHTL tKHTL WAIT VOH VOL DQ[15:0] VOH VALID OUTPUT VALID OUTPUT VOL VALID OUTPUT VALID OUTPUT tKOH tACLK DON'T CARE NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 28: Burst READ Timing Parameters--BCR[8] = 0 -701 SYMBOL t MIN MAX MIN 6.5 ACLK tCLK -706, -856 9.62 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 20 15 -701 MAX UNITS SYMBOL 10 ns t 20 ns tKOH 38 MIN -706, -856 MAX MIN 6.5 KHTL 2 2 MAX UNITS 10 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 31: CE#-Controlled Asynchronous WRITE tWC A[20:0] VIH VALID ADDRESS VIL tAW tWR tAS VIH ADV# VIL tCEM CE# tCW VIH VIL tBW VIH LB#/UB# OE# VIL VIH VIL tWPH tWP VIH WE# VIL tDH tDW DQ[15:0] IN VIH DQ[15:0] OUT VOH High-Z VIL tWHZ tLZ WAIT VALID INPUT VOL tCEW VIH tHZ High-Z VIL High-Z DON'T CARE Table 29: Asynchronous WRITE Timing Parameters--CE#-Controlled -701, -706 SYMBOL MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL MIN MAX -856 MIN UNITS 8 ns AS 0 0 ns t tAW 70 85 ns tLZ 10 10 ns t 70 85 ns t 70 85 ns 10 s tWHZ 7.5 ns tWP 46 55 10 10 ns 0 0 ns t BW 10 tCEM tCEW 1 7.5 1 HZ WC CW 70 85 ns t tDH 0 0 ns tWR tDW 23 23 ns t 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 8 MAX WPH 39 8 8 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 32: LB#/UB#-Controlled Asynchronous WRITE tWC A[20:0] VIH VALID ADDRESS VIL tAW tAS ADV# CE# LB#/UB# OE# tWR VIH VIL tCEM tCW VIH VIL tBW VIH VIL VIH VIL tWP tWPH VIH WE# VIL tDW DQ[15:0] IN VIH DQ[15:0] OUT VOH High-Z VIL tDH VALID INPUT tWHZ tLZ VOL tCEW tHZ VIH WAIT High-Z High-Z VIL DON'T CARE Table 30: Asynchronous WRITE Timing Parameters--LB#/UB#-Controlled -701, -706 SYMBOL MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL MIN AS 0 0 ns t tAW 70 85 ns tLZ 10 t 70 85 70 t t BW 10 CEM tCEW 1 7.5 1 UNITS 8 ns 10 ns ns 10 s t 7.5 ns tWP 46 55 ns 10 10 ns 0 0 ns WC t tDH 0 0 ns tWR tDW 23 23 ns 40 WPH 85 8 WHZ ns 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN MAX t 85 CW MIN 8 HZ 70 t MAX -856 ns 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 33: WE#-Controlled Asynchronous WRITE tWC VIH A[20:0] VALID ADDRESS VIL tAW tWR VIH ADV# VIL tCEM tCW VIH CE# VIL tBW VIH LB#/UB# VIL VIH OE# VIL tAS tWP tWPH VIH WE# VIL tDH tDW DQ[15:0] IN VIH High-Z VIL tOW tWHZ tLZ DQ[15:0] OUT VALID INPUT VOH VOL tCEW tHZ VIH WAIT High-Z VIL High-Z DON'T CARE Table 31: Asynchronous WRITE Timing Parameters--WE#-Controlled -701, -706 SYMBOL MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL MIN MAX -856 MIN UNITS 8 ns 0 0 ns AW 70 85 ns t LZ 10 10 ns tBW 70 85 ns tOW 5 5 ns 10 s tWC 70 85 ns 7.5 ns t t 10 tCEM t CEW 1 7.5 1 8 MAX tHZ tAS 8 WHZ 8 ns tCW 70 85 ns tWP 46 55 ns tDH 0 0 ns tWPH 10 10 ns tDW 23 23 ns tWR 0 0 ns 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 34: Asynchronous WRITE Using ADV# A[20:0] VIH VALID ADDRESS VIL tAVH tAVS tVS tVPH ADV# tVP tAS VIH VIL tAS tAW tCEM tCW VIH CE# VIL tBW VIH LB#/UB# OE# VIL VIH VIL tWPH tWP WE# VIH VIL tDW DQ[15:0] VIH IN VIL DQ[15:0] VOH OUT VOL High-Z VALID INPUT tWHZ tLZ tOW tCEW WAIT tDH tHZ VIH High-Z VIL High-Z DON'T CARE Table 32: Asynchronous WRITE Timing Parameters Using ADV# -701, -706 SYMBOL MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL 0 0 ns t 5 5 ns tLZ AVS 10 10 ns t tAW 70 85 ns tBW 70 85 t AS tAVH t t 10 CEM tCEW 1 7.5 1 MAX MIN 8 HZ MAX UNITS 8 ns 10 10 ns 5 5 ns tVP 10 10 ns ns tVPH 10 10 ns 10 s t 70 85 ns 7.5 ns tWHZ 46 55 ns 10 10 ns OW VS tCW 70 85 ns tWP tDH 0 0 ns tWPH tDW 23 23 ns 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN MIN -856 42 8 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 35: Burst WRITE Operation1 tCLK CLK tKP tKP tKHKL VIH VIL tSP A[20:0] VALID ADDRESS VIL tSP ADV# tHD VIH tHD VIH VIL tSP tHD LB#/UB# VIH VIL CE# tHD tCSP VIH tCBPH VIL OE# VIH VIL tSP WE# tHD VIH VIL tCEW VOH WAIT tKHTL tHZ High-Z VOL High-Z tSP tHD VIH DQ[15:0] D[0] VIL D[1] D[2] D[3] WRITE Burst Identified (WE# = LOW) DON'T CARE NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 33: Burst WRITE Timing Parameters -701 SYMBOL MIN -706, -856 MAX MIN tCBPH 5 tCEW 1 7.5 1 CLK 9.62 20 tCSP 4 20 tHD 2 t 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN MAX 5 -701 UNITS SYMBOL MAX UNITS 8 8 ns tKHKL 1.6 1.6 ns ns t 6.5 10 ns ns tKP 3 3 ns ns tSP 3 3 ns ns tHZ 7.5 ns 15 20 5 20 2 MIN -706, -856 KHTL 43 MAX MIN Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 36: Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition1 CLK VIH VIL tCLK A[20:0] VIH VIL ADV# VIH VIL LB#/UB# VIH VIL CE# VIH VIL VIH WE# VIL VIH OE# VIL tKHTL tKHTL WAIT VOH VOL tSP VIH DQ[15:0] tHD VALID INPUT D[n] VIL VALID INPUT D[n+1] VALID INPUT D[n+2] VALID INPUT D[n+3] END OF ROW DON'T CARE NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 34: Burst WRITE Timing Parameters--BCR[8] = 0 -701 -706, -856 -701 SYMBOL MIN MAX MIN MAX UNITS t 9.62 20 15 20 ns t ns tSP CLK tHD 2 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 2 SYMBOL 44 MIN -706, -856 MAX MIN 6.5 KHTL 3 3 MAX UNITS 10 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 37: Burst WRITE Followed by Burst READ1 tCLK CLK VIH VIL A[20:0] VIH VIL ADV# VIH VIL tSP tHD LB#/UB# tSP VALID ADDRESS tSP tHD tSP tHD tSP tHD VIH VIL tCSP CE# OE# tHD VIH VIL tCBPH2 tABA tCSP VIH VIL tOHZ tSP tHD VIH WE# VIL WAIT tHD VALID ADDRESS tSP tHD VOH VOL tBOE High-Z tSP tHD DQ[15:0] VIH IN/OUT VIL High-Z D[0] D[1] D[2] D[3] VOL High-Z tKOH tACLK VOH VALID OUTPUT High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. To allow self-refresh operations to occur between transactions, CE# must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. 3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 35: WRITE Timing Parameters--Burst WRITE Followed by Burst READ -701 SYMBOL t CBPH tCLK t CSP MIN -706, -856 MAX 5 MIN MAX 5 -701 UNITS SYMBOL ns t tSP 9.62 20 15 20 ns 4 20 5 20 ns HD MIN -706, -856 MAX MIN MAX UNITS 2 2 ns 3 3 ns Table 36: READ Timing Parameters--Burst WRITE Followed by Burst READ -701 SYMBOL MIN -706, -856 MAX MIN -701 MAX UNITS SYMBOL MIN -706, -856 MAX MIN MAX UNITS ABA 35 55 ns t HD 2 2 ns tACLK 6.5 10 ns tKOH 2 2 ns tBOE 20 20 ns tOHZ tSP t tCLK 9.62 20 15 20 ns tCSP 4 20 5 20 ns 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 45 8 3 8 3 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 38: Asynchronous WRITE Followed by Burst READ1 tCLK VIH CLK VIL ADV# VIH VIL VALID ADDRESS tAVS tAW tSP tWR tSP tVP tCVS tVS tBW tHD tSP tHD tCBPH2 tCW VIH VIL tHD VALID ADDRESS VALID ADDRESS tAVH tVPH VIH LB#/UB# VIL CE# tCKA tWC tWC VIH A[20:0] VIL tABA tCSP tAS tOHZ VIH OE# VIL VIH WE# VIL WAIT tWC tAS tWP tSP tHD tWPH tCEW VOH VOL DQ[15:0] VIH IN/OUT VIL tBOE tWHZ High-Z DATA tDH VOH DATA VOL tDW High-Z tKOH tACLK VALID OUTPUT High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and burst operations, CE# must go HIGH. CE# must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. 3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 37: WRITE Timing Parameters--Async WRITE Followed by Burst READ -701, -706 SYMBOL MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL MIN MAX -856 MIN MAX UNITS tAS 0 0 ns tDW 20 23 ns tAVH 5 5 ns tVP 10 10 ns tAVS 10 10 ns tVPH 10 10 ns tAW 70 85 ns tVS 70 85 ns tBW 70 85 ns tWC 70 85 tCKA 70 85 ns tWHZ tCVS 10 10 ns tWP 46 55 ns tCW 70 85 ns tWPH 10 10 ns tDH 0 0 ns tWR 0 0 ns 8 ns 8 ns Table 38: READ Timing Parameters--Async WRITE Followed by Burst READ -701 SYMBOL MIN -706, -856 MAX MIN -701 MAX UNITS MIN MAX MIN MAX UNITS tABA 35 55 ns tCSP 4 20 5 20 ns tACLK 6.5 10 ns tHD 2 2 ns tBOE 20 20 ns tKOH 2 2 ns tCBPH 5 ns tOHZ tCEW 1 7.5 1 7.5 ns tSP tCLK 9.62 20 15 20 ns 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 5 SYMBOL -706, -856 46 8 3 8 3 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 39: Asynchronous WRITE Followed By Burst READ--ADV# LOW1 CLK VIH VIL A[20:0] VIH VIL ADV# LB#/UB# CE# tCLK tWC tWC VALID ADDRESS VALID ADDRESS tWR tAW tCKA tSP tHD VALID ADDRESS tSP tHD VIH VIL tBW VIH tSP tHD VIL tCBPH2 tCW VIH tCSP tABA VIL tOHZ OE# WE# WAIT VIH tWP VIH tSP tHD tWPH VIL VOH tCEW tBOE VOL VIH DQ[15:0] IN/OUT tWC VIL VIL tWHZ High-Z DATA tDH VOH DATA VOL tDW High-Z tKOH tACLK VALID OUTPUT High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT UNDEFINED DON'T CARE NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and burst operations, CE# must go HIGH. CE# must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. 3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 39: Asynchronous WRITE Timing Parameters--ADV# LOW -701, -706 SYMBOL MIN MAX -856 MIN -701, -706 MAX UNITS SYMBOL MIN MAX 70 -856 MIN MAX 85 UNITS tAW 70 85 ns tWC tBW 70 85 ns tWHZ t CKA 70 85 ns t WP 46 55 ns t CW 70 85 ns t WPH 10 10 ns tDH 0 0 ns tWR 0 0 ns tDW 23 23 ns 8 ns 8 ns Table 40: Burst READ Timing Parameters -701 SYMBOL t t MIN -706, -856 MAX UNITS ABA 35 55 ns t ACLK 6.5 10 ns t 20 20 ns ns tOHZ t tBOE MAX MIN -701 tCBPH 5 t CEW 1 7.5 1 7.5 ns t CLK 9.62 20 15 20 ns 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 5 SYMBOL 47 -706, -856 MIN MAX MIN MAX CSP 4 20 5 20 HD 2 tKOH 2 SP 2 3 ns 8 3 ns ns 2 8 UNITS ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 40: Burst READ Followed by Asynchronous WRITE (WE#-Controlled) tCLK VIH CLK A[20:0] VIL tSP VIH tWC tHD VALID ADDRESS VALID ADDRESS VIL tSP tAW tHD tWR VIH ADV# VIL tHD CE# tCSP VIH tCEM tHZ tABA tCW tCBPH VIL tBOE tOHZ VIH OE# VIL tAS tSP WE# tHD tOLZ tWP tWPH VIH VIL tHD tSP tBW VIH LB#/UB# VIL tCEW tKHTL tCEW tHZ VOH WAIT High-Z High-Z VOL DQ[15:0] tKOH tACLK VOH VALID INPUT VALID OUTPUT High-Z VOL tDH tDW READ Burst Identified (WE# = HIGH) DON'T CARE UNDEFINED Table 41: Burst READ Timing Parameters -701 SYMBOL t t MIN -706, -856 MAX UNITS ABA 35 55 ns t HD ACLK 6.5 10 ns t HZ 20 20 ns tKHTL ns tKOH tBOE tCBPH MAX 5 MIN -701 5 SYMBOL 1 7.5 1 7.5 ns t tCLK 9.62 20 15 20 ns tSP tCSP 4 20 5 20 ns t CEW MIN -706, -856 MAX 2 MIN MAX 2 ns 8 8 ns 6.5 10 ns 2 2 ns 8 OHZ UNITS 3 8 3 ns ns Table 42: Asynchronous WRITE Timing Parameters--WE# Controlled -701, -706 SYMBOL MIN MAX -856 MIN -701, -706 MAX UNITS 0 SYMBOL MIN AS 0 ns t tAW 70 85 ns tHZ tBW 70 85 ns tWC 70 t 10 t MAX UNITS 8 ns 23 8 ns 85 ns ns s 46 55 CW 70 85 ns t 10 10 ns DH 0 0 ns t 0 0 ns 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 10 23 MIN tWP tCEM t DW MAX -856 WPH WR 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 41: Burst READ Followed by Asynchronous WRITE Using ADV# CLK A[20:0] tCLK VIH VIL VIH tSP VIL tSP VIH ADV# tHD VALID ADDRESS VALID ADDRESS tAVS tVPH tHD VIL tCSP VIH tAW WE# tAS tHZ tABA tCEM tCW tCBPH VIL tOHZ tBOE VIH OE# tVS tVP tHD CE# tAVH VIL tSP VIH tHD tAS tOLZ tWP tWPH VIL tHD tSP VIH tBW LB#/UB# VIL tCEW tKHTL tCEW tHZ VOH WAIT High-Z VOL High-Z tACLK DQ[15:0] VOH tDH tDW VALID INPUT VALID OUTPUT High-Z VOL tKOH READ Burst Identified (WE# = HIGH) DON'T CARE UNDEFINED Table 43: Burst READ Timing Parameters -701 SYMBOL MIN -706, -856 MAX MAX UNITS 35 55 ns t 6.5 10 ns tHZ 20 ns tKHTL ns tKOH 7.5 ns tOHZ tSP tABA tACLK tBOE 20 tCBPH 5 tCEW 1 tCLK tCSP MIN -701 5 7.5 1 9.62 20 15 20 ns 4 20 5 20 ns SYMBOL MIN -706, -856 MAX MAX UNITS 8 8 ns 6.5 10 ns 2 HD MIN 2 2 ns 2 ns 8 3 8 3 ns ns Table 44: Asynchronous WRITE Timing Parameters Using ADV# -701, -706 SYMBOL tAS MIN MAX 0 -856 MIN -701, -706 MAX UNITS SYMBOL MIN 0 ns tDH 0 23 MAX -856 MIN MAX 0 UNITS ns tAVH 5 5 ns tDW tAVS 10 10 ns tHZ tAW 70 85 ns tVP 10 10 tBW 70 85 ns tVPH 10 10 ns s tVS 70 85 ns ns tWP 46 55 ns ns tWPH 10 10 ns 10 tCEM tCEW tCW 1 70 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 7.5 10 1 85 7.5 49 23 8 ns 8 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 42: Asynchronous WRITE Followed by Asynchronous READ--ADV# LOW A[20:0] VIH VALID ADDRESS VIL VALID ADDRESS VALID ADDRESS tAA tWR tAW VIH ADV# LB#/UB# CE# VIL tBHZ tBLZ tBW VIH VIL tHZ tCEM tCBPH1 tCW VIH VIL tLZ OE# VIH VIL tWC tWPH tWP WE# WAIT tOHZ tOE VIH VIL tHZ tHZ VOH VOL DQ[15:0] VIH IN/OUT VIL tOLZ tWHZ High-Z DATA VOH High-Z DATA VALID OUTPUT VOL tDW tDH UNDEFINED DON'T CARE NOTE: 1. CE# must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. Table 45: WRITE Timing Parameters--ADV# LOW -856 -701, -706 SYMBOL MIN MAX MIN -856 -701, -706 MAX UNITS SYMBOL MIN MAX MAX AW 70 85 ns t 70 85 ns tWHZ t 70 85 ns t WP 46 55 ns 0 0 ns tWPH 10 10 ns 23 23 ns t 0 0 ns CW tDH t t DW 8 HZ 8 WC WR 85 UNITS tBW t 70 MIN ns 8 8 ns ns Table 46: READ Timing Parameters--ADV# LOW -856 -701, -706 SYMBOL t t t t MIN MAX MIN MAX UNITS SYMBOL AA 70 85 ns t HZ BHZ 8 8 LZ MIN MAX ns BLZ 10 10 ns t OE 20 CBPH 5 5 ns t OHZ 8 s tOLZ 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 10 10 50 MIN 8 t tCEM -856 -701, -706 10 5 MAX UNITS 8 ns 20 ns 8 ns 10 5 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 43: Asynchronous WRITE Followed by Asynchronous READ A[20:0] VIH VIL VALID ADDRESS tAVS ADV# LB#/UB# CE# VIH tVPH VALID ADDRESS tAVH VALID ADDRESS tAA tWR tAW tVS tVP VIL tBW tCVS VIH VIL tCW VIH tCEM tCBPH1 WE# WAIT tHZ VIL tLZ tAS OE# tBHZ tBLZ tOHZ VIH VIL tWC tAS VIH tWP tOLZ tWPH VIL VOH VOL DQ[15:0] VIH IN/OUT VIL tOE tWHZ High-Z DATA VOH DATA VALID OUTPUT High-Z VOL tDW tDH DON'T CARE UNDEFINED NOTE: 1. CE# must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. Table 47: WRITE Timing Parameters--Async WRITE Followed by Async READ -701, -706 SYMBOL MIN 0 MAX UNITS ns SYMBOL VP 5 5 ns tVPH 10 10 ns tAVS 10 10 ns tVS 70 85 ns tAW 70 85 ns tWC 70 t 85 ns t t BW 70 t CVS 10 10 ns t t CW 70 85 ns t DH 0 0 ns t DW 23 23 ns t t MAX -856 tAVH AS MAX -701, -706 MIN 10 t MIN 0 -856 MIN 10 MAX 85 ns 8 WHZ UNITS ns 8 ns WP 46 55 ns WPH 10 10 ns WR 0 0 ns Table 48: READ Timing Parameters--Async WRITE Followed by Async READ -701, -706 SYMBOL t AA MAX 70 t BHZ 8 t t t MIN -856 MIN -701, -706 MAX 85 UNITS ns 8 SYMBOL t HZ ns t LZ BLZ 10 10 ns t OE CBPH 5 5 ns t OHZ s t CEM 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 10 10 51 OLZ MIN MAX 8 10 -856 MIN UNITS ns 20 ns 8 ns 10 20 8 5 MAX 8 5 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 44: 54-Ball FBGA 0.70 0.05 SEATING PLANE C SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag or 96.5% Sn, 3% Ag, 0.5% Cu SOLDER BALL PAD: O0.30 SOLDER MASK DEFINED SUBSTRATE: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC 0.10 C 54X O0.35 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS O0.35. 3.75 0.75 TYP BALL A1 ID BALL A1 ID 4.00 0.05 BALL A6 BALL A1 8.00 0.10 6.00 3.05 0.05 0.75 TYP C 1.875 0.050 3.00 0.05 1.00 MAX 6.00 0.10 NOTE: 1. All dimensions in millimeters; MAX/MIN, or typical, as noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. Data Sheet Designation: ADVANCE This data sheet contains initial descriptions of products still in development. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, and the Micron and M Logos are trademarks and/or service marks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc., inside the U.S. and a trademark of Infineon Technologies outside the U.S. All other trademarks are the property of their respective owners. 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY APPENDIX A How Extended Timings Impact CellularRAMTM Operation Introduction Figure 45: Extended Timing for tCEM This note describes CellularRAM timing requirements in systems that perform extended operations. CellularRAM products use a DRAM technology that periodically requires refresh to ensure against data corruption. CellularRAM devices include on-chip circuitry that performs the required refresh in a manner that is completely transparent in systems with normal bus timings. The refresh circuitry imposes constraints on timings in systems that take longer than 10s to complete an operation. WRITE operations are affected if the device is configured for asynchronous operation. Both READ and WRITE operations are affected if the device is configured for page or burst-mode operation. tCEM < 10s CE# ADDRESS Figure 46: Extended Timing for tTM Asynchronous WRITE Operation The timing parameters provided in Table 18 on page 28 require that all WRITE operations must be completed within 10s. After completing a WRITE operation, the device must either enter standby (by transitioning CE# HIGH), or else perform a second operation (READ or WRITE) using a new address. Figures 45 and 46 demonstrate these constraints as they apply during an asynchronous (page-mode-disabled) operation. Either the CE# active period (tCEM in Figure 45) or the address valid period (tTM in Figure 46) must be less than 10s during any WRITE operation, otherwise, the extended WRITE timings must be used. CE# tTM < 10s ADDRESS Table 49: Extended Cycle Impact on READ and WRITE Cycles PAGE MODE Asynchronous Page Mode Disabled Asynchronous Page Mode Enabled Burst 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN TIMING CONSTRAINT READ CYCLE WRITE CYCLE tCEM and tTM > 10s (See Figures 45 and 46 above.) No impact. Must use extended WRITE timing. (See Figure 47 on page 54.) Not allowed. t CEM > 10s (See Figure 45 above.) Burst must cross a row boundary within 10s. tCEM > 10s (See Figure 45 above.) 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Page Mode READ Operation Extended WRITE Timing-- Asynchronous WRITE Operation Modified timings are required during extended WRITE operations (see Figure 47 below). An extended WRITE operation requires that both the write pulse width (tWP) and the data valid period (tDW) be lengthened to at least the minimum WRITE cycle time (tWC [MIN]). These increased timings ensure that time is available for both a refresh operation and a successful completion of the WRITE operation. When a CellularRAM device is configured for page mode operation, the address inputs are used to accelerate read accesses and cannot be used by the on-chip circuitry to schedule refresh. If CE# is LOW longer than the tCEM maximum time of 10s, no refresh will occur and data may be lost. Page mode should only be used in systems that can limit CE#-LOW times to less than 10s. Burst-Mode Operation When configured for burst-mode operation, it is necessary to allow the device to perform a refresh within any 10s window. One of two conditions will enable the device to schedule a refresh within 10s. The first condition is when all burst operations complete within 10s. A burst completes when the CE# signal is registered HIGH on a rising clock edge. The second condition that allows a refresh is when a burst access crosses a row boundary. The row-boundary crossing causes WAIT to be asserted while the next row is accessed and enables the scheduling of refresh. Figure 47: Extended WRITE Operation tCEM or tTM > 10s ADDRESS CE# LB#/UB# WE# tWP > tWC (MIN) Summary CellularRAM products are designed to ensure that any possible asynchronous timings do not cause data corruption due to lack of refresh. Slow bus timings on asynchronous WRITE operations require that tWP and t DW be lengthened. Asynchronous page bus timings must limit CE# LOW to less than 10s. Burst mode timings must allow the device to perform a refresh within any 10s period. A burst operation must either complete (CE# registered HIGH) or cross a row boundary within 10s to ensure successful refresh scheduling. These timing requirements are likely to have little or no impact when interfacing a CellularRAM device with a low-speed memory bus. tDW > tWC (MIN) DATA-IN 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN Data Valid 54 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. ADVANCE 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Revision History Rev. A, Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/04 * CR WRITE diagram titles updated to reflect WRITEs followed by READ ARRAY operation. Rev. A, Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/04 * Last address not changed by software access * Added on-chip sensor to TCR. sequence. Rev. A, Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/04 * Clarified software access. Rev. A, Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/03 * Initial Release 09005aef80ec6f63 Burst CellularRAM_32.fm - Rev. A 2/18/04 EN 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved.