853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
1
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS853111-02 is a low skew, high per-
formance 1-to-10 Differential-to-2.5V/3.3V
LVPECL/ECL Fanout Buffer and a member
of the HiPerClockS™ f amily of High Perfor-
mance Clock Solutions from ICS. The
ICS853111-02 is characterized to operate from either
a 2.5V or a 3.3V power supply. Guaranteed output and
part-to-part skew characteristics make the ICS853111-
02 ideal for those clock distribution applications de-
manding well defined performance and repeatability.
FEATURES
•Ten differential 2.5V/3.3V LVPECL / ECL outputs
•Two selectable differential input pairs
•PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
•Maximum output frequency: 3.2GHz
•Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
•Output skew: 25ps (typical)
•Part-to-part skew: 85ps (typical)
•Propagation delay: 680ps (typical)
•Jitter, RMS: < 0.03ps (typical)
•LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
•ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
•-40°C to 85°C ambient operating temperature
•Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM PIN ASSIGNMENT
HiPerClockS™
ICS
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
PCLK0
nPCLK0 0
1
PCLK1
nPCLK1
CLK_SEL
VBB
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
32-Lead TQFP
7mm x 7mm x 1.0mm package body
Y Package
Top View
24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
VCCO
Q7
nQ7
Q8
nQ8
Q9
nQ9
VCCO
VCCO
nQ2
Q2
nQ1
Q1
nQ0
Q0
VCCO
ICS853111-02
VCC
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VEE
853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
2
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
TABLE 3B. CONTROL INPUT
FUNCTION TABLE
TABLE 3A. CLOCK INPUT FUNCTION TABLE
rebmuNemaNepyTnoitpircseD
1V
CC
rewoP.nipylppuseroC
2LES_KLCtupnInwodlluP
.stupni1KLCPn,1KLCPstceles,HGIHnehW.tupnitceleskcolC
.stupni0KLCPn
,0KLCPstceles,WOLnehW
.slevelecafretniLTTVL/SOMCVL
30KLCPtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
40
KLCPntupnInwodlluP/pulluP .tupnikcolcLCEPVLlaitnereffidgnitrevnI
V
CC
.gnitaolftfelnehwtluafed2/
5V
BB
tuptuO.egatlovsaiB
61KLCPtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
71KLCPntupnInwodlluP/pulluP .tupnikco
lcLCEPVLlaitnereffidgnitrevnI
V
CC
.gnitaolftfelnehwtluafed2/
8V
EE
rewoP.nipylppusevitageN
23,52,61,9V
OCC
rewoP.snipylppustuptuO
11,019Q,9QntuptuO .slevelecafretniLCEPVL.riaptuptuolaitnereffiD
31,218Q,8QntuptuO .slev
elecafretniLCEPVL.riaptuptuolaitnereffiD
51,417Q,7QntuptuO .slevelecafretniLCEPVL.riaptuptuolaitnereffiD
8
1,716Q,6QntuptuO .slevelecafretniLCEPVL.riaptuptuolaitnereffiD
02,915Q,5QntuptuO .slevelecafretniLCEPVL.riap
tuptuolaitnereffiD
22,124Q,4QntuptuO .slevelecafretniLCEPVL.riaptuptuolaitnereffiD
42,323Q,3QntuptuO .slevele
cafretniLCEPVL.riaptuptuolaitnereffiD
72,622Q,2QntuptuO .slevelecafretniLCEPVL.riaptuptuolaitnereffiD
92,8
21Q,1QntuptuO .slevelecafretniLCEPVL.riaptuptuolaitnereffiD
13,030Q,0QntuptuO .slevelecafretniLCEPVL.riaptup
tuolaitnereffiD
:ETON nwodlluPdnapulluP .seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilan
retniotrefer
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
R
NWODLLUP
rotsiseRnwodlluPtupnI 57kΩ
R
/CCV
2
srotsiseRnwodlluP/pulluP 05kΩ
stupnIstuptuO edoMtuptuOottupnIytiraloP
xKLCPxKLCPn9Q:0Q9Q:0Qn
01WOLHGIHlaitnereffiDotlaitnereffiDgnitrevnInoN
10 HGIHW
OLlaitnereffiDotlaitnereffiDgnitrevnInoN
0;desaiB
1ETON WOLHGIHlaitnereffiDotdednEelgniSgnitrevnInoN
1;desaiB
1
ETON HGIHWOLlaitnereffiDotdednEelgniSgnitrevnInoN
;desaiB
1ETON 0HGIHWOLlaitnereffiDotdednEelgniSgnitrevnI
;desai
B
1ETON 1WOLHGIHlaitnereffiDotdednEelgniSgnitrevnI
ottupnIlaitnereffiDehtgniriW",noitamrofnInoitacilppAehtot
referesaelP:1ETON
."sleveLdednEelgniStpeccA
stupnI
LES_KLCecruoSdetceleS
00KLCPn,0KLCP
11KLCPn,1KLCP
853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
3
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 3.8V; VEE = 0V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSevitisoP 573.23.38.3V
I
EE
tnerruCylppuSrewoP 58Am
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
lobmySretemaraP C°04-C°52C°58 stinU
niMpyTxaMniMpyTxaMniMpyTxaM
V
HO
1ETON;egatloVhgiHtuptuO
571.2572.283.2522.2592.273.2592.233.2563.2V
V
LO
1ETON;egatloVwoLtuptuO
504.1545.186.1524.125.1516.144.1535.136.1V
V
HI
egatloVhgiHtupnI
)dednE-elgniS(
570.263.2570.263.2570.263.2V
V
LI
egatloVwoLtupnI
)dednE-elgniS(
34.1567.134.1567.134.1567.1V
V
BB
2ETON;ecnerefeRegatloVtuptuO
68.189.168.189.168.189.1V
V
PP
egatloVtupnIkaeP-ot-kaeP
051008002105100800210510080021V
V
RMC
egatloVhgiHtupnI
4,3ETON;egnaRedoMnommoC
2.13.32.13.32.13.3V
I
HI
tnerruChgiHtupnI 1KLCP,0KLCP
1KLCPn,0KLCPn
051051051Aµ
I
LI
tnerruCwoLtupnI 1KLCP,0KLCP
1KLCPn,0KLCPn
051-051-051-Aµ
Vhtiw1:1yravsretemaraptuptuodnatupnI
CC
V.
EE
.V5.0-otV529.0+yravnac
05htiwdetanimretstuptuO:1ETON ΩVot
OCC
.V2-
Vdetimilsinoitarepotupnidedne-elgniS:2ETON
CC
≥.edomLCEPVLniV3
VsadenifedsiegatlovedomnommoC:3ETON
HI
.
1KLCPn,1KLCPdna0KLCPn,0KLCProfegatlovtupnimumixameht,snoitacilppadedne-elgnisroF:4ETON
Vsi
CC
.V3.0+
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC 4.6V (LVPECL mode, VEE = 0)
Negative Supply Voltage, VEE -4.6V (ECL mode, VCC = 0)
Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5 V
Inputs, VI (ECL mode) 0.5V to VEE - 0.5V
Outputs, IO
Continuous Current 50mA
Surge Current 100mA
VBB Sink/Source, IBB ± 0.5mA
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG -65°C to 150°C
Package Thermal Impedance, θJA 49.5°C/W (0 lfpm)
(Junction-to-Ambient)
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
4
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
lobmySretemaraP C°04-C°52C°58 stinU
niMpyTxaMniMpyTxaMniMpyTxaM
V
HO
1ETON;egatloVhgiHtuptuO
573.1574.185.1524.1594.175.1594.135.1565.1V
V
LO
1ETON;egatloVwoLtuptuO
506.0547.088.0526.027.0518.046.0537.038.0V
V
HI
egatloVhgiHtupnI
)dednE-elgniS(
572.165.1572.165.1572.18.0-V
V
LI
egatloVwoLtupnI
)dednE-elgniS(
36.0569.036.0569.036.0569.0V
V
PP
egatloVtupnIkaeP-ot-kaeP
051008002105100800210510080021V
V
RMC
egatloVhgiHtupnI
3,2ETON;egnaRedoMnommoC
2.15.22.15.22.15.2V
I
HI
tnerruChgiHtupnI 1KLCP,0KLCP
1KLCPn,0KLCPn
051051051Aµ
I
LI
tnerruCwoLtupnI 1KLCP,0KLCP
1KLCPn,0KLCPn
051-051-051-Aµ
Vhtiw1:1yravsretemaraptuptuodnatupnI
CC
V.
EE
.V3.1-otV521.0+yravnac
05htiwdetanimretstuptuO:1ETON ΩVot
OCC
.V2-
VsadenifedsiegatlovedomnommoC:2ETON
HI
.
1KLCPn,1KLCPdna0KLCPn,0KLCProfegatlovtupnimumixameht,snoitacilppadedne-elgnisroF:3ETON
Vsi
CC
.V3.0+
lobmySretemaraP C°04-C°52C°58 stinU
niMpyTxaMniMpyTxaMniMpyTxaM
V
HO
1ETON;egatloVhgiHtuptuO
521.1-520.1-29.0-570.1-500.1-39.0-500.1-79.0-539.0-V
V
LO
1ETON;egatloVwoLtuptuO
598.1-557.1-26.1-578.1-87.1-586.1-68.1-567.1-76.1-V
V
HI
egatloVhgiHtupnI
)dednE-elgniS(
522.1-49.0-522.1-49.0-522.1-49.0-V
V
LI
egatloVwoLtupnI
)dednE-elgniS(
78.1-535.1-78.1-535.1-78.1-535.1-V
V
BB
;ecnerefeRegatloVtuptuO
2ETON
684.1-683.1-684.1-683.1-684.1-683.1-V
V
PP
egatloVtupnIkaeP-ot-kaeP
051008002105100800210510080021V
V
RMC
egatloVhgiHtupnI
;egnaRedoMnommoC
4,3ETON
V
EE
V2.1+0V
EE
V2.1+0V
EE
V2.1+0V
I
HI
tupnI
tnerruChgiH
1KLCP,0KLCP
1KLCPn,0KLCPn
051051051Aµ
I
LI
tupnI
tnerruCwoL
1KLCP,0KLCP
1KLCPn,0KLCPn
051-051-051-Aµ
Vhtiw1:1yravsretemaraptuptuodnatupnI
CC
V.
EE
.V5.0-otV529.0+yravnac
05htiwdetanimretstuptuO:1ETON ΩVot
OCC
.V2-
Vdetimilsinoitarepotupnidedne-elgniS:2ETON
CC
≥.edomLCEPVLniV3
VsadenifedsiegatlovedomnommoC:3ETON
HI
.
1KLCPn,1KLCPdna0KLCPn,0KLCProfegatlovtupnimumixameht,snoitacilppadedne-elgnisroF:4ETON
Vsi
CC
.V3.0+
853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
5
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V OR VCC = 2.375 TO 3.8V; VEE = 0V
lobmySretemaraP C°04-C°52C°58 stinU
niMpyTxaMniMpyTxaMniMpyTxaM
f
XAM
ycneuqerFtuptuO2.32.32.3zHG
t
DP
1ETON;yaleDnoitagaporP006086057056527097096097098sp
t)o(ks4,2ETON;wekStuptuO527352735273sp
t)pp(ks4,3ETON;wekStraP-ot-traP5
85225852258522sp
ttij ;SMR,rettiJesahPevitiddAreffuB
noitcesrettiJesahPevitiddAotrefer 30.030.030.0sp
t
R
/t
F
emiTllaF/esiRtuptuO%08ot%0206002523001002082031002072sp
derusaemerasretemarapllA ≤.detonesiwrehtosselnuzHG1
.tniopg
nissorctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON
.snoitidnocdaollauqe
htiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
.stniopssorclaitnereffidtuptuoehttaderu
saeM
segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
derusaemerastu
ptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna
.stniopssorclaitnereffidehtta
.
56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
6
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise . This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
Additive Phase Jitter at
155.52MHz = 0.03ps (typical)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
7
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
PART-TO-PART SKEW
OUTPUT RISE/FALL TIME PROPAGATION DELAY
V
CMR
Cross Points
V
PP
VEE
nCLK0, nCLK1
VCC
CLK0, CLK1
SCOPE
Qx
nQx
LVPECL
VCC,
VCCO
-0.375V to -1.8V
tsk(pp)
t
sk(o)
nQx
Qx
nQy
Qy
PART 1
PART 2
nQx
Qx
nQy
Qy
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWING
t
PD
nCLK0,
nCLK1
Q0:Q9
nQ0:nQ9
CLK0,
CLK1
2V
VEE
853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
8
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
FIGURE 2A. SINGLE ENDED LVCMOS SIGNAL DRIVING DIFFERENTIAL INPUT
Figure 2A shows an example of the differential input that
can be wired to accept single ended LVCMOS levels. The
reference voltage level VBB generated from the device is
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS
connected to the negative input. The C1 capacitor should
be located as close as possible to the input pin.
FIGURE 2B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
Figure 2B shows an example of the differential input that
can be wired to accept single ended LVPECL levels. The
reference voltage level VBB generated from the device is
connected to the negative input. The C1 capacitor should
be located as close as possible to the input pin.
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
CLK_IN
C1
0.1uF
VDD(or VCC)
+
-
VBB
VCC
R2
1K
V_REF
C1
0.1u
R1
1K
Single Ended Clock Input
PCLK
nPCLK
853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
9
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 3A to 3E show inter-
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
FIGURE 3A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 3B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 3C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
FIGURE 3E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
R5
100 - 200
3.3V
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
C2
R2
1K
R5
100
Zo = 50 Ohm
3.3V
3.3V
C1
R3
1K
LVDS
R4
1K
HiPerClockS
PCLK
nPCLK
R1
1K
Zo = 50 Ohm
3.3V
PCLK/nPCLK
853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
10
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
V
CC
- 2V
50Ω50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125Ω125Ω
84Ω84Ω
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 4A and
4B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and
clock component process variations.
FIGURE 4B. LVPECL OUTPUT T ERMINATIONFIGURE 4A. LVPECL OUTPUT T ERMINATION
TERMINATION FOR 3.3V LVPECL OUTPUTS
INPUTS:
PCLK/nPCLK INPUT:
For applications not requiring the use of a differential input,
both the PCLK and nPCLK pins can be left floating. Though
not required, but for additional protection, a 1kΩ resistor can
be tied from PCLK to ground.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
11
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to ter-
minating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
close to ground level. The R3 in Figure 5B can be eliminated
and the termination is shown in Figure 5C.
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driver
FIGURE 5B. 2.5V LVPECL DRIVER T ERMINATION EXAMPLE
VCCO=2.5V
R1
50
R2
50
Zo = 50 Ohm
R3
18
2,5V LVPECL
Driver
Zo = 50 Ohm
+
-
2.5V
FIGURE 5A. 2.5V LVPECL DRIVER T ERMINATION EXAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driv er
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
12
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
SCHEMATIC EXAMPLE
This application note provides general design guide using
ICS853111-02 LVPECL buffer. Figure 6 shows a schematic ex-
ample of the ICS853111-02 LVPECL clock buffer. In this ex-
FIGURE 6. EXAMPLE ICS853111-02 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC
ample, the input is driven by an LVPECL driver. CLK_SEL is set
at logic high to select PCLK0/nPCLK0 input.
C4
0.1uF
C6 (Option)
0.1u
Zo = 50
R7
50
Zo = 50
R2
50
VCC
R1
50
VCC
VCC=3.3V
C7 (Option)
0.1u
R3
50
(U1-16)
U1
ICS853111
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
VCC
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VEE
VCCO
nQ9
Q9
nQ8
Q8
nQ7
Q7
VCCO
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
VCCO
Q0
nQ0
Q1
nQ1
Q2
nQ2
VCCO
R4
1K
Zo = 50
C2
0.1uF
(U1-9)
R8
50
Zo = 50 Ohm
C8 (Option)
0.1u
+
-
C5
0.1uF
R10
50
R11
50
3.3V LVPECL
+
-
VCC
(U1-32)
R13
50
C1
0.1uF
Zo = 50 Ohm
R9
50
C3
0.1uF
(U1-25)
VCC
Zo = 50
(U1-1)
EXPOSED PAD
Expose Metal Pad
(GROUND PAD)
GROUND PLANE
SOLDER
SIGNAL
TRACE
SIGNAL
TRACE
THERM AL VIA
SOLDER M ASK
FIGURE 7. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
THERMAL RELEASE PATH
The expose metal pad provides heat transfer from the device to
the P.C. board. The expose metal pad is ground pad connected
to ground plane through thermal via. The exposed pad on the
device to the exposed metal pad on the PCB is contacted through
solder as shown in Figure 7. For further information, please re-
fer to the Application Note on Surface Mount Assembly of
Amkor’s Thermally /Electrically Enhance Leadframe Base Pack-
age, Amkor Technology.
853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
13
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853111-02.
Equations and example calculations are also provided.
1. P ower Dissipation.
The total power dissipation for the ICS853111-02 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 85mA = 323mW
•Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 30.94mW = 309.4mW
Total Power_MAX (3.8V, with all outputs switching) = 323mW + 309.4mW = 632.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43.8°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.632W * 43.8°C/W = 112.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 69.3°C/W 57.8°C/W 52.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 49.5°C/W 43.8°C/W 41.3°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6. THERMAL RESISTANCE θθ
θθ
θJA FOR 32-PIN TQFP, E-PAD, FORCED CONVECTION
853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
14
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 8.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CCO
- 2V.
• For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.935V
(VCC_MAX - VOH_MAX
) = 0.935V
• For logic low, VOUT = VOL_MAX = VCCO_MAX
– 1.67V
(VCCO_MAX - VOL_MAX
) = 1.67V
Pd_H = [(VOH_MAX
– (VCCO_MAX
- 2V))/R
L
] * (VCCO_MAX
- VOH_MAX) = [(2V - (V
CCO_MAX - VOH_MAX
))/R
L
] * (VCCO _MAX- VOH_MAX) =
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
Pd_L = [(VOL_MAX
– (VCCO_MAX
- 2V))/R
L
] * (VCCO_MAX
- VOL_MAX) = [(2V - (V
CCO_MAX - VOL_MAX
))/R
L
] * (VCCO_MAX
- VOL_MAX) =
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
Figure 8. LVPECL Driver Circuit and Termination
VCCO - 2V
Q1
VOUT
RL
50
VCCO
853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
15
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS853111-02 is: 1340
Pin compatible with MC100EP111 and MC100LVEP111
TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD TQFP, E-PAD
θθ
θθ
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 69.3°C/W 57.8°C/W 52.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 49.5°C/W 43.8°C/W 41.3°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
16
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Reference Document: JEDEC Publication 95, MS-026
TQFP PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD TQFP, E-PAD
TABLE 8. PACKAGE DIMENSIONS
-HD VERSION
HEAT SLUG DOWN
NOITAIRAVCEDEJ
SRETEMILLIMNISNOISNEMIDLLA
LOBMYS
DH-ABA
MUMINIMLANIMONMUMIXAM
N23
A----02.1
1A 50.001.051.0
2A 59.00.15
0.1
b03.053.004.0
c90.0--02.0
DCISAB00.9
1D CISAB00.7
2D .feR06.5
3D CISAB00.4
ECISAB00.9
1E CISAB00.7
2E .feR06.5
3E CIS
AB00.4
eCISAB08.0
L54.006.057.0
θθ
θ
θθ 0
°
-- 7
°
ccc ----01.0
853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
17
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT
20-YA111358SCI20A111358SCIPFQTdaP-E,dael23yartC°58o
tC°04-
T20-YA111358SCI20A111358SCIPFQTdaP-E,dael23leer&epat0001C°58otC°04-
FL20-YA111358SCIL20A111358SCIPFQTd
aP-E",eerF-daeL"dael23yartC°58otC°04-
TFL20-YA111358SCIL20A111358SCIPFQTdaP-E",eerF-daeL"dael23leer&epat000
1C°58otC°04-
.tnailpmocSHoReradnanoitarugifnoceerF-bPehterarebmuntrapehtotxiffus"FL"nahtiwderedroeratah
tstraP:ETON
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
853111AY-02 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
18
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TEEHSYROTSIHNOISIVER
veRelbaTegaPegnahCfonoitpircseDetaD
A9T
01
71
deddA .sniPtuptuOdnatupnIdesunUrofsnoitadnem
moceR
.gnikrameerF-daeLdedda-elbaTnoitamrofnIgniredrO 60/01/1
