Philips Semiconductors Product specification
SA630Single pole double throw (SPDT) switch
1997 Nov 07 4
AC ELECTRICAL CHARACTERISTICS1 - D PACKAGE
VDD = +5V, TA = 25°C; unless otherwise stated. LIMITS
SYMBOL PARAMETER TEST CONDITIONS SA630 UNITS
MIN TYP MAX
S21, S12 Insertion loss (ON channel) DC - 100MHz
500MHz
900MHz
1
1.4
22.8 dB
S21, S12 Isolation (OFF channel)210MHz
100MHz
500MHz
900MHz
70
24
80
60
50
30 dB
S11, S22 Return loss (ON channel) DC - 400MHz
900MHz 20
12 dB
S11, S22 Return loss (OFF channel) DC - 400MHz
900MHz 17
13 dB
tDSwitching speed (on-off delay) 50% TTL to 90/10% RF 20 ns
tr, tfSwitching speeds (on-off rise/fall time) 90%/10% to 10%/90% RF 5 ns
Switching transients 165 mVP-P
P-1dB 1dB gain compression DC - 1GHz +18 dBm
IP3Third-order intermodulation intercept 100MHz +33 dBm
IP2Second-order intermodulation intercept 100MHz +52 dBm
NF Noise figure (ZO = 50Ω ) 100MHz
900MHz 1.0
2.0 dB
NOTE:
1. All measurements include the effects of the D package SA630 Evaluation Board (see Figure 4B). Measurement system impedance is 50Ω.
2. The placement of the AC bypass capacitor is critical to achieve these specifications. See the applications section for more details.
AC ELECTRICAL CHARACTERISTICS1 - N PACKAGE
VDD = +5V, TA = 25°C; all other characteristics similar to the D-Package, unless otherwise stated. LIMITS
SYMBOL PARAMETER TEST CONDITIONS SA630 UNITS
MIN TYP MAX
S21, S12 Insertion loss (ON channel) DC - 100MHz
500MHz
900MHz
1
1.4
2.5 dB
S21, S12 Isolation (OFF channel) 10MHz
100MHz
500MHz
900MHz 58 68
50
37
15 dB
NF Noise figure (ZO = 50Ω ) 100MHz
900MHz 1.0
2.5 dB
NOTE:
1. All measurements include the effects of the N package SA630 Evaluation Board (see Figure 4C). Measurement system impedance is 50Ω.
APPLICATIONS
The typical applications schematic and printed circuit board layout of
the SA630 evaluation board is shown in Figure 4. The layout of the
board is simple, but a few cautions need to be observed. The input
and output traces should be 50Ω. The placement of the AC bypass
capacitor is
extremely critical
if a symmetric isolation between the
two channels is desired. The trace from Pin 7 should be drawn back
towards the package and then be routed downwards. The capacitor
should be placed straight down as close to the device as practical.
For better isolation between the two channels at higher frequencies,
it is also advisable to run the two output/input traces at an angle.
This also minimizes any inductive coupling between the two traces.
The power supply bypass capacitor should be placed close to the
device. Figure 10 shows the frequency response of the SA630.
The loss matching between the two channels is excellent to 1.2GHz
as shown in Figure 13.