CY7C1009B-35VC - Cypress Semiconductor Corp.

128K x 8 Static RAM

CY7C109B

CY7C1009B

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05038 Rev. *B Revised October 11, 2005

Features

•High speed

—t

AA = 12 ns

• Low active power

— 495 mW (max. 12 ns)

• Low CMOS standby power

— 55 mW (max .) 4 m W

• 2.0V Data Retention

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE1, CE2, and OE options

Functional Description[1]

The CY7C109B/CY7C1009B is a high-performance CMOS

static RAM organized as 131,072 words by 8 bits. Easy

memory expansion is provided by an active LOW Chip Enable

(CE1), an active HIGH Chip Enable (CE2), an active LOW

Output Enable (OE), and three-state drivers. Writing to the

device is accomplished by taking Chip Enable One (CE1) and

Write Enable (WE) inputs LOW and Chip Enable Two (CE2)

input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is

then written into the location specified on the address pins (A0

through A16).

Reading from the device is accomplished by taking Chip

Enable One (CE1) and Output Enable (OE) LOW while forcing

Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under

these conditions, the contents of the memory location

specified by the address pins will appear on the I/O pins.

The eight input/output pins (I/O0 through I/O7) are placed in a

high-impedance state when the device is deselected (CE1

HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or

during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).

The CY7C109B is available in standard 400-mil-wide SOJ and

32-pin TSOP type I packages. The CY7C1009B is available in

a 300-mil-wide SOJ package. The CY7C1009B and

CY7C109B are functionally equivalent in all other respects.

Note:

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

Logic Block Diagram Pin Configurations

COLUMN

DECODER

ROW DECO D ER

SENSE AMPS

INPUT BUFFER

POWER

DOWN

I/O0

CE2

I/O1

I/O2

I/O3

512x256x8

ARRAY

I/O7

I/O6

I/O5

I/O4

A11

A13

A12

A10

CE1

A16

14 19

Top View

SOJ

15 17

GND

A16

A14

A12

VCC

A15

A13

I/O7

I/O6

I/O5

I/O4

I/O0

I/O1

I/O2

CE1

A10

I/O3

A11

CE2

A16

A14

A12

VCC

A13

A9OE

TSOP I

Top View

(not to scale)

I/O2

I/O1

GND

I/O7

I/O4

I/O5

I/O6

I/O0

A11

A517

CE2

A15

A10

I/O3

Selection Guide 7C109B-12

7C1009B-12 7C109B-15

7C1009B-15 7C109B-20

7C1009B-20 7C109B-25

7C1009B-25 7C109B-35

7C1009B-35 Unit

Maximum Access Time 12 15 20 25 35 ns

Maximum Operating Current 90 80 75 70 60 mA

Maximum CMOS Standby Current 10 10 10 10 10 mA

Maximum CMOS Standby Current

Low Power Version 2 2 2 - - mA

CY7C109B

CY7C1009B

Document #: 38-05038 Rev. *B Page 2 of 11

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .. ... ... ................. ........–65°C to +150°C

Ambient Temperature with

Power Applied...... .. ............... .. ... .............. ...–55°C to +125°C

Supply Voltage on VCC to Relative GND[2] ....–0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State[2] ....................................–0.5V to VCC + 0.5V

DC Input V oltage[2].................................–0.5V to VCC + 0.5V

Current into Outputs (LO W).........................................20 mA

St atic Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.....................................................>200 mA

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +70°C 5V ± 10%

Industrial −40°C to +85°C5V ± 10%

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

7C109B-12

7C1009B-12 7C109B-15

7C1009B-15

UnitMin. Max. Min. Max.

VOH Output HIGH Voltage VCC = Min.,

IOH = –4.0 mA 2.4 2.4 V

VOL Output LOW Voltage VCC = Min.,

IOL = 8.0 mA 0.4 0.4 V

VIH Input HIGH Voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V

VIL Input LOW Voltage[2] –0.3 0.8 –0.3 0.8 V

IIX Input Load Current GND < VI < VCC –1 +1 –1 +1 μA

IOZ Output Leakage

Current GND < VI < VCC,

Output Disabled –5 +5 –5 +5 μA

IOS Output Short

Circuit Current[3] VCC = Max.,

VOUT = GND –300 –300 mA

ICC VCC Operating

Supply Current VCC = Max.,

IOUT = 0 mA,

f = fMAX = 1/tRC

90 80 mA

ISB1 Automatic CE

Power-Down Current

—TTL Inputs

Max. VCC, CE1 > VIH

or CE2 < VIL,

VIN > VIH or

VIN < VIL, f = fMAX

45 40 mA

ISB2 Automatic CE

Power-Down Current

—CMOS Inputs

Max. VCC,

CE1 > VCC – 0.3V,

or CE2 < 0.3V,

VIN > VCC – 0.3V,

or VIN < 0.3V, f = 0

10 10 mA

L2 2mA

Notes:

2. Minimum voltage is–2.0V for pulse durations of less than 20 ns.

3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

CY7C109B

CY7C1009B

Document #: 38-05038 Rev. *B Page 3 of 11

Electrical Characteristics Over the Operating Range (continu ed)

Parameter Description Test Con dition s

7C109B-20

7C1009B-20 7C109B-25

7C1009B-25 7C109B-35

7C1009B-35 UnitMin. Max. Min. Max. Min. Max.

VOH Output HIGH Voltage VCC = Min.,

IOH = –4.0 mA 2.4 2.4 2.4 V

VOL Output LOW Voltage VCC = Min.,

IOL = 8.0 mA 0.4 0.4 0.4 V

VIH Input HIGH Voltage 2.2 VCC

+ 0.3 2.2 VCC

+ 0.3 V

VIL Input LOW Voltage[2] –0.3 0.8 –0.3 0.8 –0.3 0.8 V

IIX Input Load Current GND < VI < VCC –1 +1 –1 +1 –1 +1 μA

IOZ Output Leakage

Current GND < VI < VCC,

Output Disabled –5 +5 –5 +5 –5 +5 μA

IOS Output Short

Circuit Current[3] VCC = Max.,

VOUT = GND –300 –300 –300 mA

ICC VCC Operating

Supply Current VCC = Max.,

IOUT = 0 mA,

f = fMAX = 1/tRC

75 70 60 mA

ISB1 Automatic CE

Power-Down Current

—TTL Inputs

Max. VCC, CE1 > VIH

or CE2 < VIL,

VIN > VIH or

VIN < VIL, f = fMAX

30 30 25 mA

ISB2 Automatic CE

Power-Down Current

—CMOS Inputs

Max. VCC,

CE1 > VCC – 0.3V,

or CE2 < 0.3V,

VIN > VCC – 0.3V,

or VIN < 0.3V, f = 0

10 10 10 mA

L2——mA

Capacitance[4]

Parameter Description Test Co nditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VCC = 5.0V 9pF

COUT Output Capacitance 8 pF

AC Test Loads and Waveforms

Note:

4. Tested initially and after any design or process changes that may affect these parameters.

90%

10%

3.0V

GND

90%

10%

ALL INPUT PULSES

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

OUTPUT

5 pF

INCLUDING

JIG AND

SCOPE

(a) (b)

≤ 3 ns ≤3ns

OUTPUT

R1 480ΩR1 480Ω

255ΩR2

255Ω

167Ω

Equivalent to: VENIN EQUIVALENT

1.73V

THÉ

CY7C109B

CY7C1009B

Document #: 38-05038 Rev. *B Page 4 of 11

Switching Characteristics[5] Over the Op erating Range

Parameter Description

7C109B-12

7C1009B-12 7C109B-15

7C1009B-15

UnitMin. Max. Min. Max.

Read Cycle

tRC Read Cycle Time 12 15 ns

tAA Address to Data Valid 12 15 ns

tOHA Data Hold from Address Change 3 3 ns

tACE CE1 LOW to Data Valid, CE2 HIGH to Data

Valid 12 15 ns

tDOE OE LOW to Data Valid 6 7 ns

tLZOE OE LOW to Low Z 0 0 ns

tHZOE OE HIGH to High Z[6, 7] 67ns

tLZCE CE1 LOW to Low Z, CE2 HIGH to Low Z[7] 33ns

tHZCE CE1 HIGH to High Z, CE2 LOW to High Z[6, 7] 67ns

tPU CE1 LOW to Power-Up, CE2 HIGH to

Power-Up 00ns

tPD CE1 HIGH to Power-Down, CE2 LOW to

Power-Down 12 15 ns

Write Cycle[8]

tWC Write Cycle Time[9] 12 15 ns

tSCE CE1 LOW to Write End, CE2 HIGH to Write End 10 12 ns

tAW Address Set-Up to Write End 10 12 ns

tHA Address Hold from Write End 0 0 ns

tSA Address Set-Up to Write Start 0 0 ns

tPWE WE Pulse Width 10 12 ns

tSD Data Set-Up to Write End 7 8 ns

tHD Data Hold from Write End 0 0 ns

tLZWE WE HIGH to Low Z[7] 33ns

tHZWE WE LOW to High Z[6, 7] 67ns

Notes:

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

IOL/IOH and 30-pF load capacitance.

6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from st eady-state vo ltage.

7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a

write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the

signal that terminat es the write.

9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

CY7C109B

CY7C1009B

Document #: 38-05038 Rev. *B Page 5 of 11

Switching Characteristics[5] Over the Operating Range (continued)

Parameter Description

7C109B-20

7C1009B-20 7C109B-25

7C1009B-25 7C109B-35

7C1009B-35

UnitMin. Max. Min. Max. Min. Min.

Read Cycle

tRC Read Cycle Time 20 25 35 ns

tAA Address to Data Valid 20 25 35 ns

tOHA Data Hold from Address Change 3 5 5 ns

tACE CE1 LOW to Data Valid, CE2 HIGH to Data

Valid 20 25 35 ns

tDOE OE LOW to Data Valid 8 10 15 ns

tLZOE OE LOW to Low Z 0 0 0 ns

tHZOE OE HIGH to High Z[6, 7] 81015ns

tLZCE CE1 LOW to Low Z, CE2 HIGH to Low Z[7] 355ns

tHZCE CE1 HIGH to High Z, CE2 LOW to High Z[6, 7] 81015ns

tPU CE1 LOW to Power-Up, CE2 HI GH to

Power-Up 000ns

tPD CE1 HIGH to Power-Down, CE2 LOW to

Power-Down 20 25 35 ns

Write Cycle[8]

tWC Write Cycle Time[9] 20 25 35 ns

tSCE CE1 LOW to Write End, CE2 HIGH to Write End 15 20 25 ns

tAW Address Set-Up to Write End 15 20 25 ns

tHA Address Hold from Write End 0 0 0 ns

tSA Address Set-Up to Write Start 0 0 0 ns

tPWE WE Pulse Width 121520ns

tSD Data Set-Up to Write End 10 15 20 ns

tHD Data Hold from Write End 0 0 0 ns

tLZWE WE HIGH to Low Z[7] 355ns

tHZWE WE LOW to High Z[6, 7] 81015ns

Data Retention Characteristics Over the Operating Range (Low Power version only)

Parameter Description Conditions Min. Max Unit

VDR VCC for Data Retention No input may exceed VCC + 0.5V

VCC = VDR = 2.0V,

CE1 > VCC – 0.3V or CE2 < 0.3V,

VIN > VCC – 0.3V or VIN < 0.3V

2.0 V

ICCDR Data Retention Current 150 μA

tCDR Chip Deselect to Data Retention Time 0 ns

tROperation Recovery Time 200 μs

Data Retention Waveform

4.5V4.5V

VCC

tCDR

VDR

DATA RETENTION MODE

CY7C109B

CY7C1009B

Document #: 38-05038 Rev. *B Page 6 of 11

Switching Waveforms

Read Cycle No. 1[10, 11]

Read Cycle No. 2 (OE Controlled)[11, 12]

Write Cycle No. 1 (CE1 or CE2 Controlled)[13, 14]

Notes:

10.Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.

11. WE is HIGH for read cycle.

12.Address valid prior to or coincident with CE1 transition LOW and CE2 t ransition HIGH.

PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE tHZCE

tPD

HIGH

CE1

ICC

ISB

IMPEDANCE

ADDRESS

CE2

DATA OUT

VCC

SUPPLY

CURRENT

tWC

DATA VALID

tAW

tSA

tPWE

tHA

tHD

tSD

tSCE

CE1

ADDRESS

CE2

DATA I/O

CY7C109B

CY7C1009B

Document #: 38-05038 Rev. *B Page 7 of 11

Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]

Write Cycle No. 3 (WE Controlled, OE LOW)[14]

Notes:

13.Data I/O is high impedance if OE = VIH.

14.If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.

15.During this period the I/Os are in the output state and input signals should not be applied.

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

DATAIN VALID

CE1

ADDRESS

CE2

DATA I/O

NOTE 15

DATA VALID

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

CE1

ADDRESS

CE2

DATA I/O NOTE 15

CY7C109B

CY7C1009B

Document #: 38-05038 Rev. *B Page 8 of 11

Truth Table

CE1CE2OE WE I/O0–I/O7Mode Power

H X X X High Z Power-Down Standby (ISB)

X L X X High Z Power-Down Standby (ISB)

L H L H Data Out Read Active (ICC)

L H X L Data In Write Active (ICC)

L H H H High Z Selected, Outputs Disabled Active (ICC)

Ordering Information

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

12 CY7C109B-12VC V33 32-Lead (400-Mil) Molded SOJ Commercial

CY7C1009B-12VC V32 32-Lead (300-Mil) Molded SOJ

CY7C109B-12ZC Z32 32-Lead TSOP Type I

CY7C109B-12ZXC Z32 32-Lead TSOP Type I (Pb-Free)

15 CY7C109BL-15VC V33 32-Lead (400-Mil) Molded SOJ Commerci al

CY7C109B-15VC V32 32-Lead (400-Mil) Molded SOJ

CY7C1009B-15VC V32 32-Lead (300-Mil) Molded SOJ

CY7C109B-15ZC Z32 32-Lead TSOP Type I

CY7C109B-15ZXC Z32 32-Lead TSOP Type I (Pb-Free)

CY7C109BL-15VI V33 32-Lead (400-Mil) Molded SOJ Industrial

CY7C109B-15VI V33 32-Lead (400-Mil) Molded SOJ

CY7C1009B-15VI V32 32-Lead (300-Mil) Molded SOJ

20 CY7C109B-20VC V33 32-Lead (400-Mil) Molded SOJ Commercial

CY7C1009B-20VC V32 32-Lead (300-Mil) Molded SOJ

CY7C109B-20VI V33 32-Lead (400-Mil) Molded SOJ Industrial

CY7C109B-20ZC Z32 32-Lead TSOP Type I Commercial

CY7C109B-20ZXC Z32 32-Lead TSOP Type I (Pb-Free )

25 CY7C109B-25VC V33 32-Lead (400-Mil) Molded SOJ Commercial

CY7C1009B-25VC V32 32-Lead (300-Mil) Molded SOJ

CY7C109B-25VI V33 32-Lead (400-Mil) Molded SOJ Industrial

CY7C109B-25ZC Z32 32-Lead TSOP Type I Commercial

CY7C109B-25ZI Z32 32-Lead TSOP Type I Industrial

35 CY7C109B-35VC V33 32-Lead (400-Mil) Molded SOJ Commercial

CY7C1009B-35VC V32 32-Lead (300-Mil) Molded SOJ

CY7C109B-35VI V33 32-Lead (400-Mil) Molded SOJ Industrial

Please contact loc al sales representative regarding availability of parts

CY7C109B

CY7C1009B

Document #: 38-05038 Rev. *B Page 9 of 11

Package Diagrams

32-Lead (300-Mil) Molded SOJ V32

51-85041-*A

32-Lead (400-Mil) Molded SOJ V33

51-85033-*B

CY7C109B

CY7C1009B

Document #: 38-05038 Rev. *B Page 10 of 11

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. F urthermore, Cyp ress does not a uthorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

All product and company names mentioned in this document may be the trademarks of their respective holders.

Package Diagrams (continued)

51-85056-*D

32-Lead Thin Small Outline Package Type I (8x20 mm) Z32

CY7C109B

CY7C1009B

Document #: 38-05038 Rev. *B Page 11 of 11

Document History Page

Document Title: CY7C109B, CY7C1009 128K x 8 SRAM

Document Number: 38-05038

REV. ECN NO. Issue

Date Orig. of

Change Description of Change

** 106832 09/22/01 SZV Change from Spec number: 38-00971 to 38-05038

*A 116467 09/16/02 CEA Add applications foot note to data sheet, page 1

*B 397875 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from

“3901 North First Street” to “198 Champion Court”

Updated the Ordering Information Table on page 8.