To our custo mers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corpor ation took over all the business of both
companies. Therefore, althoug h the old com pany name remains in this docum ent, it is a valid
Renesas Electronics document. W e appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
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subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
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DESCRIPTION
The 7542 Group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 7542 Group has serial interfaces, 8-bit timers, 16-bit timers,
and an A/D converter, and is useful for control of home electric ap-
pliances and office automation equipment.
FEATURES
•Basic machine-language instructions ...................................... 71
•
The minimum instruction execution time .............................
0.25 µs
(at 8 MHz oscillation frequency, double-speed mode for the
shortest instruction)
•Memory size
Flash memory version: ROM ..................... 16 to 32K + 4K bytes
RAM ..................................... 1024 bytes
Mask ROM version: ROM............................. 8K to 16K bytes
RAM ............................ 384 to 512 bytes
RSS version RAM ..................................... 1024 bytes
•Programmable I/O ports
29 (25 in 32-pin version and PWQN0036KA-A package version)
•Interrupts ................................................. 18 sources, 16 vectors
•Timers ............................................................................. 8-bit ✕ 2
...................................................................................... 16-bit ✕ 2
•Output compare............................................................ 4-channel
•Input capture ................................................................ 2-channel
•Serial interface ............ 8-bit ✕ 2 (UART or Clock-synchronized)
•A/D converter ............................................... 10-bit ✕ 8 channels
(6 channels in 32-pin version and PWQN0036KA-A package
version)
•Clock generating circuit............................................. Built-in type
(low-power dissipation by an on-chip oscillator)
(connected to external ceramic resonator or quartz-crystal
oscillator permitting RC oscillation)
•Watchdog timer ............................................................ 16-bit ✕ 1
•Power source voltage
X
IN
oscillation frequency at ceramic oscillation, in double-speed mode
At 8 MHz.................................................................... 4.5 to 5.5 V
XIN oscillation frequency at ceramic oscillation, in high-speed mode
At 8 MHz.................................................................... 4.0 to 5.5 V
At 4 MHz.................................................................... 2.4 to 5.5 V
At 2 MHz.................................................................... 2.2 to 5.5 V
XIN oscillation frequency at RC oscillation in high-speed mode or
middle-speed mode
At 4 MHz.................................................................... 4.0 to 5.5 V
At 2 MHz.................................................................... 2.4 to 5.5 V
At 1 MHz.................................................................... 2.2 to 5.5 V
•Power dissipation ................................................ 27.5 mW (Typ.)
•Operating temperature range...................................–20 to 85 °C
APPLICATION
Office automation equipment, factory automation equipment,
home electric appliances, consumer electronics, etc.
Rev.3.03 Jul 11, 2008 Page 1 of 117
REJ03B0006-0303
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0006-0303
Rev.3.03
Jul 11, 2008
7542 Group
Rev.3.03 Jul 11, 2008 Page 2 of 117
REJ03B0006-0303
Fig. 2 Pin configuration (Package type: PRSP0036GA-A)
PIN CONFIGURATION (TOP VIEW)
Fig. 1 Pin configuration (Package type: PLQP0032GB-A)
Outline PLQP0032GB-A (32P6U-A)
P07(LED07)/SRDY2
P10/RXD1/CAP0
P11/TXD1
P12/SCLK1
P13/SRDY1
P14/CNTR0
P20/AN0
P21/AN132
31
30
29
28
27
26
25 P34(LED14)
P33(LED13)/INT1
P32(LED12)/CMP3
P31(LED11)/CMP2
P30(LED10)/CAP1
VSS
XOUT
XIN
9
10
11
12
13
14
15
16
8765314
V
CC
CNV
SS
RESET
P2
2
/AN
2
P0
5
(LED
05
)/TxD
2
20 1718192124
P0
2
(LED
02
)/CMP
1
P0
4
(LED
04
)/RxD
2
P0
3
(LED
03
)/TX
OUT
P0
6
(LED
06
)/S
CLK2
23 22
P0
1
(LED
01
)/CMP
0
P0
0
(LED
00
)/CAP
0
P3
7
(LED
17
)/INT
0
M37542Mx-XXXGP
M37542FxGP
P2
3
/AN
3
P2
4
/AN
4
P2
5
/AN
5
V
REF
2
Packa
g
e t
yp
e: PRSP0036GA-A
(
36P2R-A
)
10
1
2
3
4
6
7
8
9
11
12
14
15
16
5
13
17
18
36
35
34
33
31
30
26
25
24
23
22
21
20
19
32
27
29
28
CNVSS
XOUT
XIN
VSS
P04(LED04)/RxD2
P30(LED10)/CAP1
Vcc
VREF
P05(LED05)/TxD2
P10/RXD1/CAP0
P26/AN6
P27/AN7
P11/TXD1
P12/SCLK1
P13/SRDY1
P23/AN3
P22/AN2
P21/AN1
P20/AN0
P31(LED11)/CMP2
P36(LED16)/INT1
P24/AN4
P25/AN5
P06(LED06)/SCLK2
P07(LED07)/SRDY2
RESET
M37542Mx-XXXFP
M37542FxFP
P14/CNTR0
P35(LED15)
P34(LED14)
P33(LED13)/INT1
P32(LED12)/CMP3
P37(LED17)/INT0
P00(LED00)/CAP0
P01(LED01)/CMP0
P02(LED02)/CMP1
P03(LED03)/TXOUT
7542 Group
Rev.3.03 Jul 11, 2008 Page 3 of 117
REJ03B0006-0303
Fig. 4 Pin configuration (Package type: PWQN0036KA-A)
Fig. 3 Pin configuration (Package type: PRDP0032BA-A)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CNV
SS
P1
2
/S
CLK1
P1
3
/S
RDY1
P1
4
/CNTR
0
P2
0
/AN
0
P2
1
/AN
1
P2
2
/AN
2
P2
3
/AN
3
P2
4
/AN
4
V
CC
X
IN
X
OUT
V
SS
P1
1
/T
X
D
1
P1
0
/R
X
D
1
/CAP
0
P0
7
(LED
07
)/S
RDY2
P0
6
(LED
06
)/S
CLK2
P0
5
(LED
05
)/TxD
2
P0
4
(LED
04
)/RxD
2
P3
0
(LED
10
)/CAP
1
P2
5
/AN
5
V
REF
RESET
P3
3
(LED
13
)/INT
1
P3
2
(LED
12
)/CMP
3
P3
1
(LED
11
)/CMP
2
M37542Mx-XXXSP
M37542FxSP
32
14
15
16
P3
4
(LED
14
)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Package type: PRDP0032BA-A (32P4B)
P0
3
(LED
03
)/TX
OUT
P0
2
(LED
02
)/CMP
1
P0
1
(LED
01
)/CMP
0
P0
0
(LED
00
)/CAP
0
P3
7
(LED
17
)/INT
0
Package type: PWQN0036KA-A (36PJW-A)
P07(LED07)/SRDY2
P10/RxD1/CAP0
P11/TxD1
P12/SCLK1
P13/SRDY1
P14/CNTR0
P20/AN0
P21/AN1
[N.C.]
P33(LED13)/INT1
P32(LED12)/CMP3
P31(LED11)/CMP2
P30(LED10)/CAP1
Vss
XOUT
XIN
[N.C.]
Vcc
CNVss
RESET
P06(LED06)/SCLK2
P3
4
(LED
14
)
M37542Mx-XXXHP
M37542F8HP (Note)
P2
5
/AN
5
V
REF
36
[N.C.] [N.C.]
P2
4
/AN
4
P2
3
/AN
3
P2
2
/AN
2
P0
5
(LED
05
)/TxD
2
P0
4
(LED
04
)/RxD
2
P0
3
(LED
03
)/TX
OUT
P0
2
(LED
02
)/CMP
1
P0
1
(LED
01
)/CMP
0
P0
0
(LED
00
)/CAP
0
P3
7
(LED
17
)/INT
0
27 26 25 20 192124 23 22
987653142
31
30
29
28
35
34
33
32
10
11
12
13
14
15
16
17
18
N.C.: Non Connection
Note: Only ES version
(MP: no plan)
7542 Group
Rev.3.03 Jul 11, 2008 Page 4 of 117
REJ03B0006-0303
Fig. 5 Pin configuration (Package type: 42S1M)
Packa
g
e t
yp
e 42S1M
10
1
2
3
4
6
7
8
9
11
12
14
15
16
5
13
17
18
36
35
34
33
31
30
26
25
24
23
22
32
27
29
28
19
20
21
42
41
40
39
37
38
CNV
SS
X
OUT
X
IN
V
SS
P0
4
(LED
04
)/RxD2
P3
0
(LED
10
)/CAP
1
Vcc
V
REF
P0
5
(LED
05
)/TxD2
P1
2
/SCLK1
P2
5
/AN
5
P2
6
/AN
6
P1
3
/SRDY1
P1
4
/CNTR0
NC
P2
2
/AN
2
NC
P2
1
/AN
1
P2
0
/AN
0
P3
1
(LED
11
)/CMP
2
P3
6
(LED
16
)/INT
1
P2
3
/AN
3
P2
4
/AN
4
P0
6
(LED
06
)/SCLK2
P0
7
(LED
07
)/SRDY2
RESET
M37542RSS
NC
P3
5
(LED
15
)
P3
4
(LED
14
)
P3
3
(LED
13
)/INT
1
P3
2
(LED
12
)/CMP
3
NC
P1
0
/R
X
D
1
/CAP
0
P1
1
/T
X
D
1
NC
NC
P2
7
/AN
7
P3
7
(LED
17
)/INT
0
P0
0
(LED
00
)/CAP
0
P0
1
(LED
01
)/CMP
0
P0
2
(LED
02
)/CMP
1
P0
3
(LED
03
)/TX
OUT
7542 Group
Rev.3.03 Jul 11, 2008 Page 5 of 117
REJ03B0006-0303
Table 1 Performance overview Parameter 71
0.25 µs
(Minimum instruction, oscillation frequency 8 MHz: double-speed mode)
8 MHz (max.)
8 K to 16 K bytes
384 to 512 bytes
16 K to 32 K + 4 K bytes
1024 bytes
•8-bit ✕ 3, 5-bit ✕ 1 (8-bit ✕ 1, 6-bit ✕ 2, 5-bit ✕ 1 for 32-pin version and
PWQN0036KA-A package version)
18 sources, 16 vectors
•8-bit ✕ 2, 16-bit ✕ 2
4 channel
2 channel
8-bit ✕ 2 (UART or clock synchronous)
10-bit ✕ 8 channel
(6 channel for 32-pin version and PWQN0036KA-A package version)
16-bit ✕ 1
Built-in
(external ceramic resonator or quartz-crystal oscillator, RC oscillation available)
(Low consumption current by on-chip oscillator available)
4.0 to 5.5 V
2.4 to 5.5 V
2.7 to 5.5 V
2.2 to 5.5 V
2.7 to 5.5 V
4.5 to 5.5 V
4.5 to 5.5 V
2.4 to 5.5 V
2.7 to 5.5 V
2.2 to 5.5 V
2.7 to 5.5 V
4.5 to 5.5 V
2.4 to 5.5 V
2.7 to 5.5 V
2.2 to 5.5 V
2.7 to 5.5 V
27.5 mW (Typ.)
24.0 mW (Typ.)
-20 to 85 °C
CMOS silicon gate
32-pin plastic molded SDIP/LQFP, 36-pin plastic molded SSOP/WQFN
Number of basic instructions
Instruction execution time
Oscillation frequency
Memory sizes Mask ROM ROM
RAM
FLASH ROM ROM
RAM
I/O port P0, P1, P2, P3
Interrupts
Timer
Output compare
Input capture
Serial interface
A/D converter
Watchdog timer
Clock generating circuit
Power source High-speed mode At 8MHz Mask ROM
voltage Middle-speed mode oscillation FLASH ROM
(at ceramic At 4MHz Mask ROM
resonance) oscillation FLASH ROM
At 2MHz Mask ROM
oscillation FLASH ROM
Double-speed mode At 8MHz Mask ROM
oscillation FLASH ROM
At 6.5MHz Mask ROM
oscillation FLASH ROM
At 2MHz Mask ROM
oscillation FLASH ROM
At 1MHz Mask ROM
oscillation FLASH ROM
Power source High-speed mode At 4MHz Mask ROM
voltage Middle-speed mode oscillation FLASH ROM
(at RC oscillation)
At 2MHz Mask ROM
oscillation FLASH ROM
At 1MHz Mask ROM
oscillation FLASH ROM
Power dissipation Mask ROM
FLASH ROM
Operating temperature range
Device structure
Package
Function
7542 Group
Rev.3.03 Jul 11, 2008 Page 6 of 117
REJ03B0006-0303
FUNCTIONAL BLOCK
Fig. 6 Functional block diagram (Package type: PLQP0032GB-A)
FUNCTIONAL BLOCK DIAGRAM (Package type: PLQP0032GB-A)
X
IN OUT
X
SI/O2(8)
RAM ROM
CPU
A
X
Y
S
PC
H
PC
L
PS
V
SS
11
RESET
6
V
CC
87
CNV
SS
P1(5)
30 28 26
29 27
32 31
P2(6)
P3(6)
1215 13
5
Reset input
I/O port P2 I/O port P1I/O port P3
Clock generating circuit
Clock input Clock output
910
42
31
A/D
converter
(10)
V
REF
Watchdog timer
Reset
0
14
INT
0
16
17
SI/O1(8)
CNTR
0
I/O port P0
Timer X (8)
Key-on wakeup
Prescaler X (8)
Timer B (16)
P0(8)
25 23 21 19
24 22 20 18
Timer 1 (8)
Prescaler 1 (8)
Timer A (16)
Input
Capture Output
Compare
INT
1
7542 Group
Rev.3.03 Jul 11, 2008 Page 7 of 117
REJ03B0006-0303
Fig. 7 Functional block diagram (Package type: PRSP0036GA-A)
FUNCTIONAL BLOCK DIAGRAM (Package type: PRSP0036GA-A)
X
IN OUT
X
SI/O2(8)
RAM ROM
CPU
A
X
Y
S
PC
H
PC
L
PS
V
SS
18
RESET
13
V
CC
15 14
CNV
SS
P1(5)
31
35
236
76
P2(8)
P3(8)
2124 22
12
Reset input
I/O port P2 I/O port P1I/O port P3
Clock generating circuit
Clock input Clock output
16 17
11 9
10 8
A/D
converter
(10)
V
REF
Watchdog timer
Reset
0
23
INT
0
25
26
SI/O1(8)
CNTR
0
I/O port P0
Timer X (8)
Key-on wakeup
Prescaler X (8)
Timer B (16)
P0(8)
34 32 30 28
33 31 29 27
Timer 1 (8)
Prescaler 1 (8)
Timer A (16)
INT
1
1920 54
Input
Capture Output
Compare
7542 Group
Rev.3.03 Jul 11, 2008 Page 8 of 117
REJ03B0006-0303
Fig. 8 Functional block diagram (Package type: PRDP0032BA-A)
FUNCTIONAL BLOCK DIAGRAM (Package type: PRDP0032BA-A)
X
IN OUT
X
SI/O2(8)
RAM ROM
CPU
A
X
Y
S
PC
H
PC
L
PS
V
SS
16
RESET
11
V
CC
13 12
CNV
SS
P1(5)
3131
232
P2(6)
P3(6)
17
20 18
10
Reset input
I/O port P2 I/O port P1I/O port P3
Clock generating circuit
Clock input Clock output
14 15
A/D
converter
(10)
V
REF
Watchdog timer
Reset
0
19
INT
0
2122
SI/O1(8)
CNTR
0
I/O port P0
Timer X (8)
Key-on wakeup
Prescaler X (8)
Timer B (16)
P0(8)
25 23
24
Timer 1 (8)
Prescaler 1 (8)
Timer A (16)
INT
1
28 26
27
3029
4756
8
9
Input
Capture Output
Compare
7542 Group
Rev.3.03 Jul 11, 2008 Page 9 of 117
REJ03B0006-0303
Fig. 9 Functional block diagram (Package type: PWQN0036KA-A)
FUNCTIONAL BLOCK DIAGRAM (Package type: PWQN0036KA-A)
X
IN OUT
X
SI/O2(8)
RAM ROM
CPU
A
X
Y
S
PC
H
PC
L
PS
V
SS
13
RESET
6
V
CC
87
CNV
SS
P1(5)
34 32 30
33 31
36 35
P2(6)
P3(6)
1417 15
5
Reset input
I/O port P2 I/O port P1I/O port P3
Clock generating circuit
Clock input Clock output
11 12
42
31
A/D
converter
(10)
V
REF
Watchdog timer
Reset
0
16
INT
0
20
21
SI/O1(8)
CNTR
0
I/O port P0
Timer X (8)
Key-on wakeup
Prescaler X (8)
Timer B (16)
P0(8)
25 23
24 22
Timer 1 (8)
Prescaler 1 (8)
Timer A (16)
Input
Capture Output
Compare
INT
1
29 27
28 26
7542 Group
Rev.3.03 Jul 11, 2008 Page 10 of 117
REJ03B0006-0303
PIN DESCRIPTION
Table 2 Pin description Function
Mask ROM version Apply voltage of 2.2 to 5.5 V to Vcc, and 0 V to Vss.
FLASH ROM version Apply voltage of 2.7 to 5.5 V to Vcc, and 0 V to Vss.
•Reference voltage input pin for A/D converter.
•Chip operating mode control pin, which is always connected to Vss.
•Reset input pin for active “L”
•Input and output pins for main clock generating circuit.
•Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins.
•
For using RC oscillator, short between the X
IN
and X
OUT
pins, and connect the capacitor and resistor.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
•When the on-chip oscillator is selected as the main clock, connect XIN pin to VCC and leave XOUT open.
Function expect a port function
Name
Power source
Analog refer-
ence voltage
CNVss
Reset input
Clock input
I/O port P0
I/O port P1
I/O port P2
(Note 1)
I/O port P3
(Note 2)
Pin
Vcc, Vss
VREF
CNVss
RESET
XIN
P00(LED00)/CAP0
P01(LED01)/CMP0
P02(LED02)/CMP1
P03(LED03)/TXOUT
P04(LED04)/RxD2
P05(LED05)/TxD2
P06(LED06)/SCLK2
P07(LED07)/SRDY2
P10/RxD1/CAP0
P11/TxD1
P12/SCLK1
P13/SRDY1
P14/CNTR0
P20/AN0–P27/AN7
P30(LED10)/CAP1
P31(LED11)/CMP2
P32(LED12)/CMP3
P33(LED13)/INT1
P34(LED14)
P35(LED15)
P36(LED16)/INT1
P37(LED17)/INT0
Notes1: P26/AN6 and P27/AN7 do not exist for the 32-pin version and PWQN0036KA-A package, so that Port P2 is a 6-bit I/O port.
2: P35 and P36/INT1 do not exist for the 32-pin version and PWQN0036KA-A package, so that Port P3 is a 6-bit I/O port.
• Capture function pin
• Compare function pin
• Timer X function pin
• Serial I/O2 function pin
• Serial I/O1 function pin
• Capture function pin
• Serial I/O1 function pin
• Timer X function pin
• Input pins for A/D converter
• Capture function pin
• Compare function pin
• Interrupt input pin
• Interrupt input pin
•8-bit I/O port.
•I/O direction register allows each pin to be individually pro-
grammed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
•
High drive capacity for LED drive port can be selected by program.
•5-bit I/O port
•I/O direction register allows each pin to be individually pro-
grammed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•CMOS/TTL level can be switched for P10, P12 and P13
•8-bit I/O port having almost the same function as P0
•CMOS compatible input level
•CMOS 3-state output structure
•8-bit I/O port
•I/O direction register allows each pin to be individually pro-
grammed as either input or output.
•CMOS compatible input level (CMOS/TTL level can be switched
for P36 and P37).
•CMOS 3-state output structure
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
•
High drive capacity for LED drive port can be selected by program.
XOUT Clock output
• Key-input
(key-on
wake up
interrupt
input) pin
7542 Group
Rev.3.03 Jul 11, 2008 Page 11 of 117
REJ03B0006-0303
GROUP EXPANSION
Renesas plans to expand the 7542 group as follow:
Memory type
Support for Mask ROM version, Flash memory version, and Emu-
lator MCU .
Memory size
Flash memory size ......................................16 to 32 K + 4 K bytes
Mask ROM size ................................................... 8 K to 16 K bytes
RAM size ............................................................ 384 to 1024 bytes
Package
PRDP0032BA-A ..................................32-pin plastic molded SDIP
PLQP0032GB-A .......... 0.8 mm-pitch 32-pin plastic molded LQFP
PRSP0036GA-A .......... 0.8 mm-pitch 36-pin plastic molded SSOP
PWQN0036KA-A ........ 0.5 mm-pitch 36-pin plastic molded WQFN
42S1M....................................42-pin shrink ceramic PIGGY BACK
Fig. 10 Memory expansion plan
384
32K
+4K
ROM size
(bytes)
RAM size
(bytes)
512 1024
16K
0
8K
M37542F8
M37542M2
16K
+4K M37542F4
M37542M4
7542 Group
Rev.3.03 Jul 11, 2008 Page 12 of 117
REJ03B0006-0303
Currently supported products are listed below.
Table 3 List of supported products
Product ROM size (bytes)
ROM size for User ( )
8192
(8062)
16384
(16254)
16384 + 4096
(Note 2)
32768 + 4096
(Note 2)
RAM size
(bytes)
384
512
1024
1024
1024
Package
PRDP0032BA-A
PWQN0036KA-A
PRSP0036GA-A
PLQP0032GB-A
PRDP0032BA-A
PWQN0036KA-A
PRSP0036GA-A
PLQP0032GB-A
PRDP0032BA-A
PRSP0036GA-A
PLQP0032GB-A
PRDP0032BA-A
PRSP0036GA-A
PLQP0032GB-A
PWQN0036KA-A
42S1M
Remarks
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Flash memory version
Flash memory version
Flash memory version
Flash memory version
Flash memory version
Flash memory version
Flash memory version
Emulator MCU
M37542M2-XXXSP
M37542M2-XXXHP
M37542M2-XXXFP
M37542M2-XXXGP
M37542M4-XXXSP
M37542M4-XXXHP
M37542M4-XXXFP
M37542M4-XXXGP
M37542F4SP
M37542F4FP
M37542F4GP
M37542F8SP
M37542F8FP
M37542F8GP
M37542F8HP
(Note 1)
M37542RSS
Notes 1: Only ES version (MP: no plan)
2: ROM size includes the ID code area.
7542 Group
Rev.3.03 Jul 11, 2008 Page 13 of 117
REJ03B0006-0303
b7 b0
X
b7 b0
S
b7 b0
Y
b7 b0
PCL
Processor Status Register (PS)
Carry Flag
b7 b0
b7 b0
A
b15 PCH
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Program Counter
Stack Pointer
Index Register Y
Index Register X
Accumulator
CZIDBTVN
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The MCU uses the standard 740 family instruction set. Refer to
the table of 740 family addressing modes and machine-language
instructions or the SERIES 740 <SOFTWARE> USER’S MANUAL
for details on each instruction set.
Machine-resident 740 family instructions are as follows:
1. The FST and SLW instructions cannot be used.
2. The MUL and DIV instructions can be used.
3. The WIT instruction can be used.
4. The STP instruction can be used.
Accumulator (A)
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In
the index addressing modes, the value of the OPERAND is added
to the contents of register X or register Y and specifies the real
address.
When the T flag in the processor status register is set to “1”, the
value contained in index register X becomes the address for the
second OPERAND.
Stack pointer (S)
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. The stack is used to store the current address data
and processor status when branching to subroutines or interrupt
routines.
The lower eight bits of the stack address are determined by the
contents of the stack pointer. The upper eight bits of the stack ad-
dress are determined by the Stack Page Selection Bit. If the Stack
Page Selection Bit is “0”, then the RAM in the zero page is used
as the stack area. If the Stack Page Selection Bit is “1”, then RAM
in page 1 is used as the stack area.
The Stack Page Selection Bit is located in the SFR area in the
zero page. Note that the initial value of the Stack Page Selection
Bit varies with each microcomputer type. Also some microcom-
puter types have no Stack Page Selection Bit and the upper eight
bits of the stack address are fixed. The operations of pushing reg-
ister contents onto the stack and popping them from the stack are
shown in Fig. 12.
Program counter (PC)
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
Fig. 11 740 Family CPU register structure
7542 Group
Rev.3.03 Jul 11, 2008 Page 14 of 117
REJ03B0006-0303
Execute JSR
On-going Routine
M (S) (PCH)
(S) (S – 1)
M (S) (PCL)
Execute RTS
(PCL)M (S)
(S) (S – 1)
(S) (S + 1)
(S) (S + 1)
(PCH)M (S)
Subroutine
Restore Return
Address
Store Return Address
on Stack M (S) (PS)
Execute RTI
(PS) M (S)
(S) (S – 1)
(S) (S + 1)
Interrupt
Service Routine
Restore Contents of
Processor Status Register
M (S) (PCH)
(S) (S – 1)
M (S) (PCL)
(S) (S – 1)
(PCL)M (S)
(S) (S + 1)
(S) (S + 1)
(PCH)M (S)
Restore Return
Address
I Flag “0” to “1”
Fetch the Jump Vector
Store Return Address
on Stack
Store Contents of Processor
Status Register on Stack
Interrupt request
(Note)
Note : The condition to enable the interrupt Interrupt enable bit is “1”
Interrupt disable flag is “0”
Table 4 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Fig. 12 Register push and pop at interrupt generation and subroutine call
7542 Group
Rev.3.03 Jul 11, 2008 Page 15 of 117
REJ03B0006-0303
Processor status register (PS)
The processor status register is an 8-bit register consisting of
flags which indicate the status of the processor after an arithmetic
operation. Branch operations can be performed by testing the
Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N)
flag. In decimal mode, the Z, V, N flags are not valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other
flags are undefined. Since the Index X mode (T) and Decimal
mode (D) flags directly affect arithmetic operations, they should
be initialized in the beginning of a program.
(1) Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
(2) Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
(3) Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt generated
by the BRK instruction. Interrupts are disabled when the I flag is
“1”.
When an interrupt occurs, this flag is automatically set to “1” to
prevent other interrupts from interfering until the current interrupt
is serviced.
(4) Decimal mode flag (D)
The D flag determines whether additions and subtractions are ex-
ecuted in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
(5) Break flag (B)
The B flag is used to indicate that the current interrupt was gener-
ated by the BRK instruction. The BRK flag in the processor status
register is always “0”. When the BRK instruction is used to gener-
ate an interrupt, the processor status register is pushed onto the
stack with the break flag set to “1”. The saved processor status is
the only place where the break flag is ever set.
(6) Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed be-
tween accumulator and memory, e.g. the results of an operation
between two memory locations is stored in the accumulator. When
the T flag is “1”, direct arithmetic operations and direct data trans-
fers are enabled between memory locations, i.e. between memory
and memory, memory and I/O, and I/O and I/O. In this case, the
result of an arithmetic operation performed on data in memory lo-
cation 1 and memory location 2 is stored in memory location 1.
The address of memory location 1 is specified by index register X,
and the address of memory location 2 is specified by normal ad-
dressing modes.
(7) Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location oper-
ated on by the BIT instruction is stored in the overflow flag.
(8) Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored in
the negative flag.
Table 5 Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
C flag
SEC
CLC
Z flag
–
–
I flag
SEI
CLI
D flag
SED
CLD
B flag
–
–
T flag
SET
CLT
V flag
–
CLV
N flag
–
–
7542 Group
Rev.3.03 Jul 11, 2008 Page 16 of 117
REJ03B0006-0303
[CPU mode register] CPUM
The CPU mode register contains the stack page selection bit, etc..
This register is allocated at address 003B16.
Switching method of CPU mode register
Switch the CPU mode register (CPUM) at the head of program af-
ter releasing Reset in the following method.
Fig. 14 Switching method of CPU mode register
Fig. 13 Structure of CPU mode register
After releasing reset
Switch the oscillation mode
selection bit (bit 5 of CPUM)
Switch the clock division ratio
selection bits (bits 6 and 7 of CPUM)
Main routine
Start with an on-chip oscillator
An initial value is set as a ceramic
oscillation mode. When it is switched to an
RC oscillation, its oscillation starts.
Select 1/1, 1/2, 1/8 or on-chip oscillator.
Wait by on-chip oscillator operation
until establishment of oscillator clock
When using a ceramic oscillation, wait until
establlishment of oscillation from oscillation starts.
When using an RC oscillation, wait time is not
required basically (time to execute the instruction to
switch from an on-chip oscillator meets the
requirement).
Note: After system is released from reset, an on-chip oscillator turns active automatically
and system operation is started.
7542 Group
Rev.3.03 Jul 11, 2008 Page 17 of 117
REJ03B0006-0303
Memory
Special function register (SFR) area
The SFR area in the zero page contains control registers such as
I/O ports and timers.
RAM
RAM is used for data storage and for a stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
The reserved ROM area can program/erase in the flash memory
version.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac-
cess to this area with only 2 bytes is possible in the special page
addressing mode.
Fig. 15 Memory map diagram
010016
000016
004016
044016
FF0016
FFDC16
FFFE16
FFFF16
384
512
1024
XXXX16
01BF
16
023F16
043F16
8192
16384
32768
E000
16
C00016
800016
E080
16
C08016
808016
YYYY16
ZZZZ16
RAM
ROM
Reserved area
SFR area
Not used
Interrupt vector area
ROM area
Reserved ROM area
(128 bytes)
Zero page
Special page
RAM area
RAM capacity
(bytes) address
XXXX
16
ROM capacity
(bytes) address
YYYY
16
Reserved ROM area
address
ZZZZ
16
Not used
SFR area (Note 1)
0FE016
0FFF16
Notes 1: Only flash memory version has this SFR area.
2: The reserved ROM area can program/erase in the flash memory version.
Note the difference of the mask version.
7542 Group
Rev.3.03 Jul 11, 2008 Page 18 of 117
REJ03B0006-0303
Fig. 16 Memory map of special function register (SFR)
Notes 1: Do not access to the SFR area including nothing.
2: Only flash memory version has this SFR area.
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Pull-up control register (PULL)
Transmit 1 /Receive 1 buffer register (TB1/RB1)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART1 control register (UART1CON)
Baud rate generator 1 (BRG1)
Port P1P3 control register (P1P3C)
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
Timer count source set register (TCSS)
A/D conversion register (low-order) (ADL)
Prescaler 1 (PRE1)
Timer 1 (T1)
Timer X mode register
(TXM)
Prescaler X
(PREX)
Timer X
(TX)
Serial I/O2 control register (SIO2CON)
UART2 control register (UART2CON)
A/D control register (ADCON)
A/D conversion register (high-order) (ADH)
MISRG
Watchdog timer control register (WDTCON)
Interrupt edge selection register
(INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt control register 1 (ICON1)
Timer A, B mode register (TABM)
Capture/compare port register (CCPR)
Timer source selection register (TMSR)
Capture mode register (CAPM)
Compare output mode register (CMOM)
Capture/compare status register (CCSR)
Compare interrupt source set register (CISR)
Interrupt request register 2 (IREQ2)
Interrupt control register 2 (ICON2)
On-chip oscillation division ratio selection register (RODR)
Baud rate generator 2 (BRG2)
Timer A (low-order) (TAL)
Timer A (high-order) (TAH)
Timer B (low-order) (TBL)
Timer B (high-order) (TBH)
Transmit 2 / Receive 2 buffer register (TB2/RB2)
Serial I/O2 status register (SIO2STS)
Port P0P3 drive capacity control register (DCCR)
Compare register re-load register (CMPR)
Capture software trigger register (CSTR)
Capture/compare register R/W pointer (CCRP)
Compare register (high-order) (CMPH)
Compare register (low-order) (CMPL)
Capture register 1 (high-order) (CAP1H)
Capture register 1 (low-order) (CAP1L)
Capture register 0 (high-order) (CAP0H)
Capture register 0 (low-order) (CAP0L)
Interrupt source set register (INTSET)
Interrupt source discrimination register (INTDIS)
Reserved
Reserved
Reserved
0FE0
16
0FE1
16
Flash memory control register 0 (FMCR0) (Note 2)
Flash memory control register 1 (FMCR1) (Note 2)
0FE2
16
Flash memory control register 2 (FMCR2) (Note 2)
7542 Group
Rev.3.03 Jul 11, 2008 Page 19 of 117
REJ03B0006-0303
I/O Ports
[Direction registers] PiD
The I/O ports have direction registers which determine the input/
output direction of each pin. Each bit in a direction register corre-
sponds to one pin, and each pin can be set to be input or output.
When “1” is set to the bit corresponding to a pin, this pin becomes
an output port. When “0” is set to the bit, the pin becomes an in-
put port.
When data is read from a pin set to output, not the value of the pin
itself but the value of port latch is read. Pins set to input are float-
ing, and permit reading pin values.
If a pin set to input is written to, only the port latch is written to and
the pin remains floating.
Note: P26/AN6, P27/AN7, P35 and P36 do not exist for the 32-pin version
and PWQN0036KA-A package.
Accordingly, the following settings are required;
• Select P33 for the INT1 function.
• Set direction registers of ports P26 and P27 to output.
• Set direction registers of ports P35 and P36 to output.
[Port P0P3 drive capacity control register] DCCR
By setting the Port P0P3 drive capacity control register (address
001516), the drive capacity of the N-channel output transistor for
the port P0 and port P3 can be selected.
[Pull-up control register] PULL
By setting the pull-up control register (address 001616), ports P0
and P3 can exert pull-up control by program. However, pins set to
output are disconnected from this control and cannot exert pull-up
control.
[Port P1P3 control register] P1P3C
By setting the port P1P3 control register (address 001716), a
CMOS input level or a TTL input level can be selected for ports
P10, P12, P13, P36, and P37 by program.
Fig. 19 Structure of port P1P3 control register
Fig. 18 Structure of pull-up control register
Port P1P3 control register
(P1P3C: address 0017
16
, initial value: 00
16
)
b7 b0
Note: Keep setting the P3
6
/INT
1
input level selection bit
to “0” (initial value) for 32-pin version and 36PJW-A package.
Not used
1 : TTL level
0 : CMOS level
P1
0
,P1
2
,P1
3
input level selection bit
1 : TTL level
0 : CMOS level
P3
6
/INT
1
input level selection bit
1 : TTL level
0 : CMOS level
P3
7
/INT
0
input level selection bit
Pull-up control register
(PULL: address 001616, initial value: 0016)
P
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i
t
P
o
r
t
s
P
3
1,
P
3
2
d
r
i
v
e
c
a
p
a
c
i
t
y
b
i
t
P
o
r
t
P
3
3
d
r
i
v
e
c
a
p
a
c
i
t
y
b
i
t
P
o
r
t
s
P
3
4
,
P
3
5
d
r
i
v
e
c
a
p
a
c
i
t
y
b
i
t
P
o
r
t
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P
3
6
,
P
3
7
d
r
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v
e
c
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a
c
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y
b
i
t
b
7
b
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w
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i
g
h
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e
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m
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o
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8
-
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r
t
.
Fig. 17 Structure of port P0P3 drive capacity control register
7542 Group
Rev.3.03 Jul 11, 2008 Page 20 of 117
REJ03B0006-0303
Table 6 I/O port function table
Pin
P00(LED00)/CAP0
P01(LED01)/CMP0
P02(LED02)/CMP1
P03(LED03)/TXOUT
P04(LED04)/RxD2
P05(LED05)/TxD2
P06(LED06)/SCLK2
P07(LED07)/SRDY2
P10/RxD1/CAP0
P11/TxD1
P12/SCLK1
P13/SRDY1
P14/CNTR0
P20/AN0–P27/AN7
P30(LED10)/CAP1
P31(LED11)/CMP2
P32(LED12)/CMP3
P33(LED13)/INT1
P34(LED14)
P35(LED15)
P36(LED16)/INT1
P37(LED17)/INT0
I/O format
•CMOS compatible
input level (Note 1)
•CMOS 3-state output
Non-port function
• Capture function input
• Key input interrupt
• Compare function output
• Key input interrupt
• Timer X function output
• Key input interrupt
• Serial I/O2 function input/output
• Key input interrupt
• Serial I/O1 function input
• Capture function input
• Serial I/O1 function input/output
• Timer X function input/output
• External interrupt input
• A/D conversion input
• Capture function input
• Compare function output
• External interrupt input
• External interrupt input
SFRs related each pin
Capture/Compare port register
Interrupt edge selection register
Pull-up control register
Port P0P3 drive capacity control register
Capture/Compare port register
Pull-up control register
Port P0P3 drive capacity control register
Timer X mode register
Pull-up control register
Port P0P3 drive capacity control register
Serial I/O2 control register
Interrupt edge selection register
Pull-up control register
Port P0P3 drive capacity control register
Serial I/O2 control register
Pull-up control register
Port P0P3 drive capacity control register
Serial I/O2 control register
Interrupt edge selection register
Pull-up control register
Port P0P3 drive capacity control register
Serial I/O2 control register
Pull-up control register
Port P0P3 drive capacity control register
Serial I/O1 control register
Capture/Compare port register
Port P1P3 control register
Serial I/O1 control register
Serial I/O1 control register
Port P1P3 control register
Serial I/O1 control register
Port P1P3 control register
Timer X mode register
A/D control register
Capture/Compare port register
Pull-up control register
Port P0P3 drive capacity control register
Capture/Compare port register
Pull-up control register
Port P0P3 drive capacity control register
Interrupt edge selection register
Pull-up control register
Port P0P3 drive capacity control register
Pull-up control register
Port P0P3 drive capacity control register
Interrupt edge selection register
Pull-up control register
Port P0P3 drive capacity control register
Port P1P3 control register
Diagram
No.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
Notes 1: Ports P10, P12, P13, P36, and P37 are CMOS/TTL level.
2: P26/AN6 and P27/AN7 do not exist for the 32-pin version and PWQN0036KA-A package.
3: P35 and P36/INT1 do not exist for the 32-pin version and PWQN0036KA-A package.
Name
I/O port P0
I/O port P1
I/O port P2
(Note 2)
I/O port P3
(Note 3)
7542 Group
Rev.3.03 Jul 11, 2008 Page 21 of 117
REJ03B0006-0303
Fig. 20 Block diagram of ports (1)
(1) Port P0
0
Direction
register
Data bus Port latch
Pull-up control
To key input interrupt
generating circuit
Capture 0 input
P00 key-on wakeup
selection bit
Drive capacity
control
Capture 0 input control
(2) Ports P0
1,
P0
2
Compare output
Direction
register
Data bus Port latch
Pull-up control
To key input interrupt
generating circuit
Compare output control
Drive capacity
control
(3) Port P0
3
Timer output
Direction
register
Data bus Port latch
Pull-up control
To key input interrupt
generating circuit
P03/TXOUT output valid
Drive capacity
control
(4) Port P0
4
Serial I/O2 input
Direction
register
Data bus Port latch
Pull-up control
To key input interrupt
generating circuit
Serial I/O2 enable bit
Drive capacity
control
P04 key-on wakeup
selection bit
Receive enable bit
(5) Port P0
5
Serial I/O2 output
Direction
register
Data bus Port latch
Pull-up control
To key input interrupt
generating circuit
Serial I/O2 enable bit
Drive capacity
control
Transmit enable bit
(6) Port P0
6
Serial I/O2 clock output
Direction
register
Data bus Port latch
Pull-up control
To key input interrupt
generating circuit
Serial I/O2 mode selection bit
Drive capacity
control
Serial I/O2 enable bit
Serial I/O2 synchronous
clock selection bit
Serial I/O2 clock input
P06 key-on wakeup
selection bit
Serial I/O2 enable bit
(7) Port P0
7
Serial I/O2 ready output
Direction
register
Data bus Port latch
Pull-up control
To key input interrupt
generating circuit
Serial I/O2 mode selection bit
Serial I/O2 enable bit
SRDY2 output enable bit
Drive capacity
control
7542 Group
Rev.3.03 Jul 11, 2008 Page 22 of 117
REJ03B0006-0303
Fig. 21 Block diagram of ports (2)
(8) Port P1
0
Direction
register
Data bus Port latch
Serial I/O1 enable bit
Receive enable bit
Serial I/O1 input
Capture 0 input control
P10, P12, P13
input level
selection bit
Capture 0 input
P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.
When the TTL level is selected
,
there is no h
y
steresis characteristics.
(9) Port P1
1
Data bus Port latch
Serial I/O1 output
P11/TxD1 P-channel output disable bit
Direction
register
Serial I/O1 enable bit
Transmit enable bit
(10) Port P1
2
Serial I/O1 clock output
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Serial I/O1 enable bit
Serial I/O1 synchronous
clock selection bit
Direction
register
Data bus Port latch
Serial I/O1 clock input
P10, P12, P13
input level
selection bit
*
(12) Port P14
Data bus
Serial I/O1 ready output
Port latch
Direction
register
CNTR
0
interrupt input
Timer output
P10, P12, P13
input level
selection bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
S
RDY1
output enable bit
Data bus Port latch
Direction
register
*
(11) Port P13
Data bus Port latch
Direction
register
A/D converter input Analog input pin
selection bit
(13) Ports P20–P27
*
*
Pulse output mode
7542 Group
Rev.3.03 Jul 11, 2008 Page 23 of 117
REJ03B0006-0303
Fig. 22 Block diagram of ports (3)
(14) Port P3
0
Direction
register
Data bus Port latch
Pull-up control
Capture 1 input
Drive capacity
control
Capture 1 input control
(15) Ports P3
1,
P3
2
Compare output
Direction
register
Data bus Port latch
Pull-up control
Compare output control
Drive capacity
control
(16) Port P3
3
Direction
register
Data bus Port latch
Pull-up control
INT
1
input control
Drive capacity
control
INT
1
input
(17) Ports P3
4,
P3
5
Direction
register
Data bus Port latch
Pull-up control
Drive capacity
control
(19) Port P3
7
Direction
register
Data bus Port latch
Pull-up control
Drive capacity
control
INT
0
input
P3 input level
selection bit
*
P1
0
, P1
2
, P1
3
, P3
6
, and P3
7
input level are switched to the CMOS/TTL level by the port P1P3 control register.
*
When the TTL level is selected
,
there is no h
y
steresis characteristics.
(18) Port P3
6
Direction
register
Data bus Port latch
Pull-up control
Drive capacity
control
INT
1
input
P3 input level
selection bit
*
INT
1
input control
7542 Group
Rev.3.03 Jul 11, 2008 Page 24 of 117
REJ03B0006-0303
Termination of unused pins
• Termination of common pins
I/O ports: Select an input port or an output port and follow
each processing method.
Output ports: Open.
Input ports: If the input level become unstable, through current
flow to an input circuit, and the power supply current
may increase.
Pin
P00/CAP0
P01/CMP0
P02/CMP1
P03/TXOUT
P04/RxD2
P05/TxD2
P06/SCLK2
P07/SRDY2
P10/RxD1/CAP0
P11/TxD1
P12/SCLK1
P13/SRDY1
P14/CNTR0
P20/AN0–P27/AN7
P30/CAP1
P31/CMP2
P32/CMP3
P33/INT1
P34
P35
P36/INT1
P37/INT0
VREF
XIN
XOUT
Termination 1
(recommend)
I/O port
Connect to Vss.
When only on-chip
oscillator is used, connect
to VCC through a resistor.
When external clock is
input or when on-chip
oscillator is used, open.
Termination 2
When selecting CAP function, per-
form termination of input port.
When selecting CMP0 function,
perform termination of output port.
When selecting CMP1 function,
perform termination of output port.
When selecting TXOUT function,
perform termination of output port.
When selecting RxD2 function,
perform termination of input port.
When selecting TxD2 function,
perform termination of output port.
When selecting external clock input,
perform termination of output port.
When selecting SRDY2 function,
perform termination of output port.
When selecting RxD1 function,
perform termination of input port.
When selecting TxD1 function,
perform termination of output port.
When selecting external clock input,
perform termination of input port.
When selecting SRDY1 function,
perform termination of output port.
When selecting CNTR input function,
perform termination of input port.
When selecting AN function, per-
form termination of input port.
When selecting CAP function, per-
form termination of input port.
When selecting CMP2 function,
perform termination of output port.
When selecting CMP3 function,
perform termination of output port.
When selecting INT function, per-
form termination of input port.
-
-
When selecting INT function, per-
form termination of input port.
When selecting INT function, per-
form termination of input port.
-
-
-
Termination 3
-
-
-
-
-
-
When selecting internal clock output,
perform termination of output port.
-
When selecting CAP function, per-
form termination of input port.
-
When selecting internal clock output,
perform termination of output port.
-
When selecting CNTR output function,
perform termination of output port.
-
-
-
-
-
-
-
-
-
-
-
-
Termination 4
When selecting
key-on wakeup
function, per-
form termination
of input port.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Table 7 Termination of unused pins
Especially, when expecting low consumption current
(at STP or WIT instruction execution etc.), pull-up or
pull-down input ports to prevent through current
(built-in resistor can be used).
We recommend processing unused pins through a
resistor which can secure IOH(avg) or IOL(avg).
Because, when an I/O port or a pin which have an
output function is selected as an input port, it may
operate as an output port by incorrect operation etc.
7542 Group
Rev.3.03 Jul 11, 2008 Page 25 of 117
REJ03B0006-0303
Interrupts
The 7542 Group interrupts are vector interrupts with a fixed prior-
ity scheme, and generated by 16 sources among 18 sources: 6
external, 11 internal, and 1 software.
The interrupt sources, vector addresses(1) , and interrupt priority
are shown in Table 8.
Each interrupt except the BRK instruction interrupt has the inter-
rupt request bit and the interrupt enable bit. These bits and the
interrupt disable flag (I flag) control the acceptance of interrupt re-
quests. Figure 23 shows an interrupt control diagram.
An interrupt request is accepted when all of the following condi-
tions are satisfied:
• Interrupt disable flag.................................“0”
• Interrupt request bit...................................“1”
• Interrupt enable bit....................................“1”
Though the interrupt priority is determined by hardware, priority
processing can be performed by software using the above bits
and flag.
Table 8 Interrupt vector addresses and priority
Vector addresses (Note 1)
High-order
Priority Low-order Interrupt request generating conditions RemarksInterrupt source
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
Notes 1: Vector addresses contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: Key-on wakeup interrupt and UART1 bus collision detection interrupt can be enabled by setting of interrupt source set register. The occurrence of
these interrupts are discriminated by interrupt source discrimination register.
4: A/D conversion interrupt and Timer 1 interrupt can be enabled by setting of interrupt source set register. The occurrence of these interrupts are dis-
criminated by interrupt source discrimination register.
Non-maskable
Valid only when serial I/O1 is selected
Valid only when serial I/O1 is selected
Valid only when serial I/O2 is selected
Valid only when serial I/O2 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(valid at falling edge)
When UART1 bus collision detection
interrupt is enabled.
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Compare interrupt source is selected.
STP release timer underflow
Non-maskable software interrupt
At reset input
At completion of serial I/O1 data receive
At completion of serial I/O1 transmit shift
or when transmit buffer is empty
At completion of serial I/O2 data receive
At completion of serial I/O2 transmit shift
or when transmit buffer is empty
At detection of either rising or falling edge
of INT0 input
At detection of either rising or falling edge
of INT1 input
At falling of conjunction of input logical
level for port P0 (at input)
At detection of UART1 bus collision
detection
At detection of either rising or falling edge
of CNTR0 input
At detection of either rising or falling edge
of Capture 0 input
At detection of either rising or falling edge
of Capture 1 input
At compare matched
At timer X underflow
At timer A underflow
At timer B underflow
At completion of A/D conversion
At timer 1 underflow
At BRK instruction execution
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Reset (Note 2)
Serial I/O1 receive
Serial I/O1 transmit
Serial I/O2 receive
Serial I/O2 transmit
INT0
INT1
Key-on wake-up/
UART1 bus
collision detection
(Note 3)
CNTR0
Capture 0
Capture 1
Compare
Timer X
Timer A
Timer B
A/D conversion/
Timer 1 (Note 4)
BRK instruction
7542 Group
Rev.3.03 Jul 11, 2008 Page 26 of 117
REJ03B0006-0303
Fig. 23 Interrupt control
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset Interrupt acceptance
• Interrupt Disable Flag
The interrupt disable flag is assigned to bit 2 of the processor sta-
tus register. This flag controls the acceptance of all interrupt
requests except for the BRK instruction. When this flag is set to
“1”, the acceptance of interrupt requests is disabled. When it is set
to “0”, the acceptance of interrupt requests is enabled. This flag is
set to “1” with the SEI instruction and set to “0” with the CLI in-
struction.
When an interrupt request is accepted, the contents of the proces-
sor status register are pushed onto the stack while the interrupt
disable flag remains set to “0”. Subsequently, this flag is automati-
cally set to “1” and multiple interrupts are disabled.
To use multiple interrupts, set this flag to “0” with the CLI instruc-
tion within the interrupt processing routine.
The contents of the processor status register are popped off the
stack with the RTI instruction.
• Interrupt Request Bits
Once an interrupt request is generated, the corresponding inter-
rupt request bit is set to “1” and remains “1” until the request is
accepted. When the request is accepted, this bit is automatically
set to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to
“1”, by software.
• Interrupt Enable Bits
The interrupt enable bits control the acceptance of the corre-
sponding interrupt requests. When an interrupt enable bit is set to
“0”, the acceptance of the corresponding interrupt request is dis-
abled. If an interrupt request occurs in this condition, the
corresponding interrupt request bit is set to “1”, but the interrupt
request is not accepted. When an interrupt enable bit is set to “1”,
the acceptance of the corresponding interrupt request is enabled.
Each interrupt enable bit can be set to “0” or “1” by software.
The interrupt enable bit for an unused interrupt should be set to
“0”.
• Interrupt Enable Setting
The following interrupt sources can be set to valid or invalid by the
interrupt source set register (000A16).
• Key-on wakeup
• UART1 bus collision detection interrupt
• A/D conversion
• Timer 1 interrupt
• External Interrupt Pin Selection
For the external interrupt INT1, the external input pin P33 or P36
can be selected by the INT1 input port selection bit in the interrupt
edge selection register (bit 2 of address 003A16).
However, since there is no P36/INT1 pin in the 32-pin version
PWQN0036KA-A package, select P33/INT1 pin. By the key-on
wakeup selection bit, enable/disable of a key-on wakeup of P00,
P04, and P06 pins can be selected, respectively.
7542 Group
Rev.3.03 Jul 11, 2008 Page 27 of 117
REJ03B0006-0303
b7 b0 Interrupt control register 1
Serial I/O1 receive interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
(ICON1 : address 003E16, initial value : 0016)
b7 b0 Interrupt control register 2
Capture 0 interrupt enable bit
0 : Interrupts disabled
1:Interrupts enabled
(ICON2 : address 003F16, initial value : 0016)
Interrupt request register 2
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ2 : address 003D16, initial value : 0016)
b7 b0
Capture 0 interrupt request bit
Interrupt request register 1
Serial I/O1 receive interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C16, initial value : 0016)
b7 b0
Not used (returns “0” when read)
(Do not write “1” to this bit.)
A/D conversion/Timer 1 interrupt enable bit
Timer B interrupt enable bit
Timer A interrupt enable bit
Timer X interrupt enable bit
Compare interrupt enable bit
Capture 1 interrupt enable bit
CNTR0 interrupt enable bit
Key-on wake up/UART1 bus collision
detection interrupt enable bit
INT1 interrupt enable bit
INT0 interrupt enable bit
Serial I/O2 transmit interrupt enable bit
Serial I/O2 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
A/D conversion/Timer 1 interrupt request bit
Timer B interrupt request bit
Timer A interrupt request bit
Timer X interrupt request bit
Compare interrupt request bit
Capture 1 interrupt request bit
CNTR0 interrupt request bit
Key-on wake up/UART1 bus collision detection
interrupt request bit
INT1 interrupt request bit
INT0 interrupt request bit
Serial I/O2 transmit interrupt request bit
Serial I/O2 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Interrupt source set register
(INTSET: address 000A
16
, initial value: 00
16
)
Key-on wakeup interrupt valid bit
b7 b0
Interrupt source discrimination register
(INTDIS: address 000B
16
, initial value: 00
16
)
Key-on wakeup interrupt discrimination bit
b7 b0
Interrupt edge selection register
(INTEDGE : address 003A
16
, initial value: 00
16
)
b7 b0
Not used (returns “0” when read)
Timer 1 interrupt valid bit
A/D conversion interrupt valid bit
UART1 bus collision detection interrupt valid bit
1: Interrupt valid
0: Interrupt invalid
1 : Interrupt request issued
0 : No interrupt request issued
Not used (returns “0” when read)
Timer 1 interrupt discrimination bit
A/D conversion interrupt discrimination bit
UART1 bus collision detection
interrupt discrimination bit
INT
0
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
INT
1
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
INT
1
input port selection bit (Note 1)
0 : P3
6
1 : P3
3
Not used (returns “0” when read)
P0
0
key-on wakeup selection bit
0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
P0
4
key-on wakeup selection bit
0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
P0
6
key-on wakeup selection bit
0 : Key-on wakeup enabled
1 : Ke
y
-on wakeu
p
disabled
Fig. 24 Structure of Interrupt-related registers
Note 1: P36 does not exist for the 32-pin version and
the PWQN0036KA-A package.
Select P33 for the INT1 function.
7542 Group
Rev.3.03 Jul 11, 2008 Page 28 of 117
REJ03B0006-0303
• Interrupt Request Generation, Acceptance, and Handling
Interrupts have the following three phases.
(i) Interrupt Request Generation
An interrupt request is generated by an interrupt source (ex-
ternal interrupt signal input, timer underflow, etc.) and the
corresponding request bit is set to “1”.
(ii) Interrupt Request Acceptance
Based on the interrupt acceptance timing in each instruction
cycle, the interrupt control circuit determines acceptance con-
ditions (interrupt request bit, interrupt enable bit, and interrupt
disable flag) and interrupt priority levels for accepting interrupt
requests. When two or more interrupt requests are generated
simultaneously, the highest priority interrupt is accepted. The
value of the interrupt request bit for an unaccepted interrupt
remains the same and acceptance is determined at the next
interrupt acceptance timing point.
(iii) Handling of Accepted Interrupt Request
The accepted interrupt request is processed.
Figure 25 shows the time up to execution in the interrupt process-
ing routine, and Figure 26 shows the interrupt sequence.
Figure 27 shows the timing of interrupt request generation, inter-
rupt request bit, and interrupt request acceptance.
• Interrupt Handling Execution
When interrupt handling is executed, the following operations are
performed automatically.
(1) Once the currently executing instruction is completed, an in-
terrupt request is accepted.
(2) The contents of the program counters and the processor sta-
tus register at this point are pushed onto the stack area in
order from 1 to 3.
1.High-order bits of program counter (PCH)
2.Low-order bits of program counter (PCL)
3.Processor status register (PS)
(3) Concurrently with the push operation, the jump address of the
corresponding interrupt (the start address of the interrupt pro-
cessing routine) is transferred from the interrupt vector to the
program counter.
(4) The interrupt request bit for the corresponding interrupt is set
to “0”. Also, the interrupt disable flag is set to “1” and multiple
interrupts are disabled.
(5) The interrupt routine is executed.
(6) When the RTI instruction is executed, the contents of the reg-
isters pushed onto the stack area are popped off in the order
from 3 to 1. Then, the routine that was before running interrupt
processing resumes.
As described above, it is necessary to set the stack pointer and
the jump address in the vector area corresponding to each inter-
rupt to execute the interrupt processing routine.
■ Notes on Interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
•When switching external interrupt active edge
Related registers:
Interrupt edge selection register (address 003A16)
Timer X mode register (address 002B16)
Capture mode register (address 002016)
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
➀ Set the corresponding interrupt enable bit to “0” (disabled).
➁ Set the interrupt edge select bit (active edge switch bit, trigger
mode bit).
➂ Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃ Set the corresponding interrupt enable bit to “1” (enabled).
Main routine Interrupt handling
routine
Interrupt request
generated Interrupt request
acceptance Interrupt routine
starts
Interrupt sequence
7 cycles
0 to 16* cycles
7 to 23 cycles
* When executing DIV instruction
Stack push
Vector fetch
Fig. 25 Time up to execution in interrupt routine
7542 Group
Rev.3.03 Jul 11, 2008 Page 29 of 117
REJ03B0006-0303
Fig. 27 Timing of interrupt request generation, interrupt request bit, and interrupt acceptance
Instruction cycle Push onto stack
Vector fetch Instruction cycle
Internal clock φ
SYNC
T1 IR1 T2 IR2 T3
➀➁
T1 T2 T3 : Interrupt acceptance timing points
IR1 IR2 : Timings points at which the interrupt request bit is set to “1”.
Note : Period 2 indicates the last φ cycle during one instruction cycle.
(1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1.
(2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2.
The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt
requests are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2
separately.
Fig. 26 Interrupt sequence
φ
SYNC
RD
WR
Address bus
Data bus
PC
Not used
S,SPS S-1,SPS S-2,SPS
B
L
B
H
A
L
,A
H
PC
H
PC
L
PS A
L
A
H
SYNC : CPU operation code fetch cycle
(This is an internal signal that cannot be observed from the external unit.)
B
L
, B
H
: Vector address of each interrupt
A
L
, A
H
: Jump destination address of each interrupt
SPS : “00
16
” or “01
16
”
([SPS] is a page selected by the stack page selection bit of CPU mode register.)
Push onto stack
Vector fetch Execute interrupt
routine
7542 Group
Rev.3.03 Jul 11, 2008 Page 30 of 117
REJ03B0006-0303
Key Input Interrupt (Key-On Wake-Up)
A key-on wake-up interrupt request is generated by applying “L”
level to any pin of port P0 that has been set to input mode.
In other words, it is generated when the AND of input level goes
from “1” to “0”. An example of using a key input interrupt is shown
in Figure 28, where an interrupt request is generated by pressing
one of the keys provided as an active-low key matrix which uses
ports P00 to P03 as input ports.
Fig. 28 Connection example when using key input interrupt and port P0 block diagram
Port PXx
“L” level output
PULL register
bit 3 = “0”
Port P0
7
latch
Port P0
7
Direction register = “1”
***
P0
7
output
Key input interrupt request
Port P0
Input read circuit
* P-channel transistor for pull-up
** CMOS out
p
ut buffer
PULL register
bit 3 = “0”
Port P0
6
latch
Port P0
6
Direction register = “1”
***
P0
6
output
PULL register
bit 3 = “0”
Port P0
5
latch
Port P0
5
Direction register = “1”
***
P0
5
output
PULL register
bit 3 = “0”
Port P0
4
latch
Port P0
4
Direction register = “1”
***
P0
4
output
PULL register
bit 2 = “1”
Port P0
3
latch
Port P0
3
Direction register = “0”
***
P0
3
input
PULL register
bit 2 = “1”
Port P0
2
latch
Port P0
2
Direction register = “0”
***
P0
2
input
PULL register
bit 1 = “1”
Port P0
1
latch
Port P0
1
Direction register = “0”
***
P0
1
input
PULL register
bit 0 = “1”
Port P0
0
latch
Port P0
0
Direction register = “0”
***
P0
0
input
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Port P0
0
key-on wakeup
selection bit
Port P0
6
key-on wakeup
selection bit
Port P0
4
key-on wakeup
selection bit
7542 Group
Rev.3.03 Jul 11, 2008 Page 31 of 117
REJ03B0006-0303
Timers
The 7542 Group has 4 timers: timer 1, timer X, timer A and timer
B.
The division ratio of every timer and prescaler is 1/(n+1) provided
that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches “0”, an
underflow occurs at the next count pulse, and the corresponding
timer latch is reloaded into the timer. When a timer underflows, the
interrupt request bit corresponding to each timer is set to “1”.
• Frequency divider for timer
According to the clock division selection bits (b7 and b6) of CPU
mode register (003B16), the count source of frequency divider is
set as follows;
b7b6 = “00”(high-speed), “01”(middle-speed), “11”(double-speed): X
IN
b7b6 = “10”(On-chip oscillator): On-chip oscillator
●Timer 1
Timer 1 is an 8-bit timer and counts the prescaler output.
When Timer 1 underflows, the timer 1 interrupt request bit is set to
“1”.
Prescaler 1 is an 8-bit prescaler and counts the signal which is the
oscillation frequency divided by 16.
Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1
latch to retain the reload value, respectively. The value of
prescaler 1 latch is set to Prescaler 1 when Prescaler 1
underflows. The value of timer 1 latch is set to Timer 1 when Timer
1 underflows.
When writing to Prescaler 1 (PRE1) is executed, the value is writ-
ten to both the prescaler 1 latch and Prescaler 1.
When writing to Timer 1 (T1) is executed, the value is written to
both the timer 1 latch and Timer 1.
When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is ex-
ecuted, each count value is read out.
Timer 1 always operates in the timer mode.
Prescaler 1 counts the signal which is the oscillation frequency di-
vided by 16. Each time the count clock is input, the contents of
Prescaler 1 is decremented by 1. When the contents of Prescaler
1 reach “0016”, an underflow occurs at the next count clock, and
the prescaler 1 latch is reloaded into Prescaler 1 and count contin-
ues. The division ratio of Prescaler 1 is 1/(n+1) provided that the
value of Prescaler 1 is n.
The contents of Timer 1 is decremented by 1 each time the under-
flow signal of Prescaler 1 is input. When the contents of Timer 1
reach “0016”, an underflow occurs at the next count clock, and the
timer 1 latch is reloaded into Timer 1 and count continues. The di-
vision ratio of Timer 1 is 1/(m+1) provided that the value of Timer
1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is
1/((n+1)✕(m+1)) provided that the value of Prescaler 1 is n and
the value of Timer 1 is m.
Timer 1 cannot stop counting by software.
●Timer X
Timer X is an 8-bit timer and counts the prescaler X output.
When Timer X underflows, the timer X interrupt request bit is set
to “1”.
Prescaler X is an 8-bit prescaler and counts the signal selected by
the timer X count source selection bit.
Prescaler X and Timer X have the prescaler X latch and the timer
X latch to retain the reload value, respectively. The value of
prescaler X latch is set to Prescaler X when Prescaler X
underflows. The value of timer X latch is set to Timer X when
Timer X underflows.
When writing to Prescaler X (PREX) is executed, the value is writ-
ten to both the prescaler X latch and Prescaler X.
When writing to Timer X (TX) is executed, the value is written to
both the timer X latch and Timer X.
When reading from Prescaler X (PREX) and Timer X (TX) is ex-
ecuted, each count value is read out.
Timer X can be selected in one of 4 operating modes by setting
the timer X operating mode bits of the timer X mode register.
(1) Timer mode
Prescaler X counts the count source selected by the timer X count
source selection bits. Each time the count clock is input, the con-
tents of Prescaler X is decremented by 1. When the contents of
Prescaler X reach “0016”, an underflow occurs at the next count
clock, and the prescaler X latch is reloaded into Prescaler X and
count continues. The division ratio of Prescaler X is 1/(n+1) pro-
vided that the value of Prescaler X is n.
The contents of Timer X is decremented by 1 each time the under-
flow signal of Prescaler X is input. When the contents of Timer X
reach “0016”, an underflow occurs at the next count clock, and the
timer X latch is reloaded into Timer X and count continues. The di-
vision ratio of Timer X is 1/(m+1) provided that the value of Timer
X is m. Accordingly, the division ratio of Prescaler X and Timer X is
1/((n+1)✕(m+1)) provided that the value of Prescaler X is n and
the value of Timer X is m.
(2) Pulse output mode
In the pulse output mode, the waveform whose polarity is inverted
each time timer X underflows is output from the CNTR0 pin.
The output level of CNTR0 pin can be selected by the CNTR0 ac-
tive edge switch bit. When the CNTR0 active edge switch bit is “0”,
the output of CNTR0 pin is started at “H” level. When this bit is “1”,
the output is started at “L” level.
Also, the inverted waveform of pulse output from CNTR0 pin can
be output from TXOUT pin by setting “1” to the P03/TXOUT output
valid bit.
When using a timer in this mode, set the port P14 and P03 direc-
tion registers to output mode.
(3) Event counter mode
The timer A counts signals input from the P14/CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
The active edge of CNTR0 pin input signal can be selected from
rising or falling by the CNTR0 active edge switch bit .
7542 Group
Rev.3.03 Jul 11, 2008 Page 32 of 117
REJ03B0006-0303
(4) Pulse width measurement mode
In the pulse width measurement mode, the pulse width of the sig-
nal input to P14/CNTR0 pin is measured.
The operation of Timer X can be controlled by the level of the sig-
nal input from the CNTR0 pin.
When the CNTR0 active edge switch bit is “0”, the signal selected
by the timer X count source selection bit is counted while the input
signal level of CNTR0 pin is “H”. The count is stopped while the
pin is “L”. Also, when the CNTR0 active edge switch bit is “1”, the
signal selected by the timer X count source selection bit is
counted while the input signal level of CNTR0 pin is “L”. The count
is stopped while the pin is “H”.
Timer X can stop counting by setting “1” to the timer X count stop
bit in any mode.
Also, when Timer X underflows, the timer X interrupt request bit is
set to “1”.
Note on Timer X is described below;
■ Note on Timer X
(1) CNTR0 interrupt active edge selection-1
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR0 interrupt request bit is set to “1” at the rising edge of
CNTR0 pin input signal.
(2) CNTR0 interrupt active edge selection-2
According to the setting value of CNTR0 active edge switch bit,
the interrupt request bit may be set to “1”.
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
➀ Set the corresponding interrupt enable bit to “0” (disabled).
➁ Set the active edge switch bit.
➂ Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃ Set the corresponding interrupt enable bit to “1” (enabled).
Fig. 29 Structure of timer X mode register
Fig. 30 Timer count source set register
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b7 b0
Timer X count source selection bits
b1 b0
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : f(XIN) (Note 1)
1 1 : Not available
Notes 1: f(XIN) can be used as timer X count source when using
a ceramic resonator or on-chip oscillator.
Do not use it at RC oscillation.
2: On-chip oscillator can be used when the on-chip oscillator
is enabled by bit 3 of CPUM.
Timer count source set register
(TCSS : address 002A16, initial value: 0016)
Timer B count source selection bits
b7 b6 b5
0 0 0 : f(XIN)/16
0 0 1 : f(XIN)/2
0 1 0 : f(XIN)/32
0 1 1 : f(XIN)/64
1 0 0 : f(XIN)/128
1 0 1 : f(XIN)/256
1 1 0 : Timer A underflow
1 1 1 : Not available
Timer A count source selection bits
b4 b3 b2
0 0 0 : f(XIN)/16
0 0 1 : f(XIN)/2
0 1 0 : f(XIN)/32
0 1 1 : f(XIN)/64
1 0 0 : f(XIN)/128
1 0 1 : f(XIN)/256
1 1 0 : On-chip oscillator output (Note 2)
1 1 1 : Not available
7542 Group
Rev.3.03 Jul 11, 2008 Page 33 of 117
REJ03B0006-0303
Fig. 31 Block diagram of timer 1 and timer X
Q
Q
P14/CNTR0
R
T
1/16
1/2
Timer X
interrupt
request bit
Toggle flip-flop
Timer X count stop bit
Pulse width
measurement
mode
Event
counter
mode CNTR0
interrupt
request bit
Pulse output mode
Port P14
latch
Port P14 direction
register
CNTR0 active
edge switch bit
Timer mode
Pulse output mode
CNTR0 active
edge switch bit
Timer X count
source selection bits
1/1
P03/TXOUT
Prescaler X latch (8)
Prescaler X (8)
Timer X latch (8)
Timer X (8)
Data bus
“0”
“1”
“0”
“1”
Writing to timer X latch
Pulse output mode
P0
3
/TX
OUT
output valid
Port P03 latch
Port P03
direction
register
Prescaler 1 latch (8)
Prescaler 1 (8)
Timer 1 latch (8)
Timer 1 (8)
1/16
Data bus
Timer 1 interrupt
request
Frequency
divider
XIN
On-chip
oscillator
“00”
“01”
“11”
“0”
“10”
Clock
division ratio
selection bits
CPU mode register
7542 Group
Rev.3.03 Jul 11, 2008 Page 34 of 117
REJ03B0006-0303
●Timer A,B
Timer A and Timer B are 16-bit timers and counts the signal which
is the oscillation frequency selected by setting of the timer count
source set register (TCSS). Timer A and Timer B have the same
function except of the count source clock selection.
The count source clock of Timer A is selected from among 1/2,1/
16, 1/32, 1/64, 1/128, 1/256 of f(XIN) clock and on-chip oscillator
clock.
The count source clock of Timer B is selected from among 1/2, 1/
16, 1/32, 1/64, 1/128, 1/256 of f(XIN) clock and Timer A underflow.
Timer A (B) consists of the low-order of Timer A: TAL (Timer B:
TBL) and the high-order of Timer A: TAH (Timer B: TBH). Timer A
(B) is decremented by 1 when each time of the count clock is in-
put. When the contents of Timer A (B) reach “000016”, an
underflow occurs at the next count clock, and the timer latch is re-
loaded into timer. When Timer A (B) underflows, the Timer A (B)
interrupt request bit is set to “1”.
Timer A (B) has the Timer A (B) latch to retain the load value. The
value of timer A (B) latch is set to Timer A (B) at the timing of Timer
A (B) underflow. The division ratio of Timer A (B) is 1/(n+1) pro-
vided that the value of Timer A (B) is n.
When writing to both the low-order of Timer A (B) and the high or-
der of Timer A (B) is executed, writing to “latch only” or “latch and
timer” can be selected by the setting value of the timer A (B) write
control bit.
When reading from Timer A (B) register is executed, the count
value of Timer A (B) is read out.
Be sure to write to/read out the low-order of Timer A (B) and the
high-order of Timer A (B) in the following order;
• Read
Read the high-order of Timer A (B) first, and the low-order of Timer
A (B) next and be sure to read both high-order and low-order.
• Write
Write to the low-order of Timer A (B) first, and the high-order of
Timer A (B) next and be sure to write both low-order and high or-
der.
Timer A and Timer B can be used for the timing timer of Input cap-
ture and Output compare function.
■ Notes on Timer A, B
(1) Setting of timer value
When “1: Write to only latch” is set to the timer A (B) write control
bit, written data to timer register is set to only latch even if timer is
stopped. Accordingly, in order to set the initial value for timer when
it is stopped, set “0: Write to latch and timer simultaneously” to
timer A (B) write control bit.
(2) Read/write of timer A
Stop timer A to read/write its data when the system is in the follow-
ing state;
• CPU operation clock source: XIN oscillation
• Timer A count source: On-chip oscillator output
(3) Read/write of timer B
Stop timer B to read/write its data when the system is in the fol-
lowing state;
• CPU operation clock source: XIN oscillation
• Timer B count source: Timer A underflow
• Timer A count source: On-chip oscillator output
7542 Group
Rev.3.03 Jul 11, 2008 Page 35 of 117
REJ03B0006-0303
Fig. 34 Block diagram of timer A and timer B
Timer A (low-order) latch (8)
Timer A (low-order) (8)
Timer A (high-order) latch (8)
Timer A (high-order) (8)
Data bus
Timer A interrupt
request
Compare
Capture
Timer B (low-order) latch (8)
Timer B (low-order) (8)
Timer B (high-order) latch (8)
Timer B (high-order) (8)
Data bus
Timer B interrupt
request
Compare
Capture
1/2
1/16
1/32
1/64
1/128
1/256
Timer A count
stop bit
Timer A
count source
selection bits
On-chip
oscillator
Timer A write
control bit
Timer B write
control bit
1/2
1/16
1/32
1/64
1/128
1/256
Timer B count
stop bit
Timer B count source
selection bits
Frequency
divider
On-chip
oscillator
XIN
“00”
“01”
“11”
Clock division
ratio selection
bits
“10”
Frequency
divider
CPU mode register
Fig. 32 Structure of timer A, B mode register
Fig. 33 Timer count source set register
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b7 b0
Timer X count source selection bits
b1 b0
0 0 : f(X
IN
)/16
0 1 : f(X
IN
)/2
1 0 : f(X
IN
) (Note 1)
1 1 : Not available
Notes 1: f(X
IN
) can be used as timer X count source when using
a ceramic resonator or on-chip oscillator.
Do not use it at RC oscillation.
2: On-chip oscillator can be used when the on-chip oscillator
is enabled by bit 3 of CPUM.
Timer count source set register
(TCSS : address 002A
16
, initial value: 00
16
)
Timer B count source selection bits
b7 b6 b5
0 0 0 : f(X
IN
)/16
0 0 1 : f(X
IN
)/2
0 1 0 : f(X
IN
)/32
0 1 1 : f(X
IN
)/64
1 0 0 : f(X
IN
)/128
1 0 1 : f(X
IN
)/256
1 1 0 : Timer A underflow
1 1 1 : Not available
Timer A count source selection bits
b4 b3 b2
0 0 0 : f(X
IN
)/16
0 0 1 : f(X
IN
)/2
0 1 0 : f(X
IN
)/32
0 1 1 : f(X
IN
)/64
1 0 0 : f(X
IN
)/128
1 0 1 : f(X
IN
)/256
1 1 0 : On-chip oscillator output (Note 2)
1 1 1 : Not available
7542 Group
Rev.3.03 Jul 11, 2008 Page 36 of 117
REJ03B0006-0303
Output compare
7542 group has 4-output compare channels. Each channel (0 to 3)
has the same function and can be used to output waveform by us-
ing count value of either Timer A or Timer B.
The source timer for each channel is selected by setting value of
the compare x (x = 0, 1, 2, 3) timer source bit. Timer A and Timer B
can be selected for the source timer to each channel, respectively.
To use each compare channel, set “1” to the compare x output
port bit and set the port direction register corresponding to com-
pare channel to output mode.
The compare value for each channel is set to the compare regis-
ter (low-order) and compare register (high-order).
Writing to the register for each channel is controlled by setting
value of compare register write pointer. Writing to each register is
in the following order;
1.Set the value of corresponded output compare channel to the
compare register write pointer.
2.Write a value to the compare register (low-order) and compare
register (high-order).
3.Set “1” to the compare latch y (y = 00, 01, 10, 11, 20, 21, 30, 31)
re-load bit.
When “1” is set to the compare latch y re-load bit, the value set
to the compare register is loaded to compare latch when the
next timer underflow.
When count value of timer and setting value of compare latch is
matched, compare output trigger occurs.
When “1: Enabled” is set to the compare trigger x enable bit, the
output waveform from port is inverted by compare trigger.
When “0: Disabled” is set to the compare trigger x enable bit, the out-
put waveform is not inverted, so port output can be fixed to “H” or “L”.
When “0: Positive” is set to the compare x output level latch, the
compare output waveform is turned to “H level” at compare latch
x0’s match and turned to “L level” at compare latch x1’s match.
When “1 :Negative” is set to the compare x output level latch, the
compare output waveform is turned to “L level” at compare latch
x0’s match and turned to “H level” at compare latch x1’s match.
The compare output level of each channel can be confirmed by
reading the compare x
output status bit.
Compare output interrupt is available when match of each com-
pare channel and timer count value. The interrupt request from
each channel can be disabled or enabled by setting value of com-
pare latch y interrupt source bit.
Compare 0,1 (2,3) modulation mode
In compare modulation mode, modulation waveform can be gener-
ated by using compare channel 0 and 1, or compare channel 2 and 3.
To use this mode,
• Set “1: Enabled” to the compare 0,1 (2, 3) modulation mode bit.
• Set Timer A underflow for Timer B count source.
• Set Timer A for the timer source of compare channel 0 (2).
• Set Timer B for the timer source of compare channel 1 (3).
In this mode, AND waveform of compare 0 (1) and compare 2 (3)
is generated from Port P01 and P31, respectively. Accordingly, in
order to use this mode, set “1” to the compare 0 output port bit or
compare 2 output port bit.
Fig. 35 Structure of capture/compare register R/W pointer
Fig. 36 Structure of compare register re-load register
b
7
b
0
C
o
m
p
a
r
e
r
e
g
i
s
t
e
r
R
/
W
p
o
i
n
t
e
r
b
2
b
1
b
0
000
:
C
o
m
p
a
r
e
l
a
t
c
h
0
0
001
:
C
o
m
p
a
r
e
l
a
t
c
h
0
1
010
:
C
o
m
p
a
r
e
l
a
t
c
h
1
0
011
:
C
o
m
p
a
r
e
l
a
t
c
h
1
1
100
:
C
o
m
p
a
r
e
l
a
t
c
h
2
0
101
:
C
o
m
p
a
r
e
l
a
t
c
h
2
1
110
:
C
o
m
p
a
r
e
l
a
t
c
h
3
0
111
:
C
o
m
p
a
r
e
l
a
t
c
h
3
1
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
C
a
p
t
u
r
e
r
e
g
i
s
t
e
r
0
R
/
W
p
o
i
n
t
e
r
0
:
C
a
p
t
u
r
e
l
a
t
c
h
0
0
1
:
C
a
p
t
u
r
e
l
a
t
c
h
0
1
C
a
p
t
u
r
e
r
e
g
i
s
t
e
r
1
R
/
W
p
o
i
n
t
e
r
0
:
C
a
p
t
u
r
e
l
a
t
c
h
1
0
1
:
C
a
p
t
u
r
e
l
a
t
c
h
1
1
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
C
a
p
t
u
r
e
/
c
o
m
p
a
r
e
r
e
g
i
s
t
e
r
R
/
W
p
o
i
n
t
e
r
(
C
C
R
P
:
a
d
d
r
e
s
s
0
0
1
2
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
0
1
6
)
b
7
b
0
C
o
m
p
a
r
e
l
a
t
c
h
0
0
,
0
1
r
e
-
l
o
a
d
b
i
t
0
:
R
e
-
l
o
a
d
d
i
s
a
b
l
e
d
1
:
R
e
-
l
o
a
d
a
t
n
e
x
t
u
n
d
e
r
f
l
o
w
C
o
m
p
a
r
e
l
a
t
c
h
1
0
,
1
1
r
e
-
l
o
a
d
b
i
t
0
:
R
e
-
l
o
a
d
d
i
s
a
b
l
e
d
1
:
R
e
-
l
o
a
d
a
t
n
e
x
t
u
n
d
e
r
f
l
o
w
C
o
m
p
a
r
e
l
a
t
c
h
2
0
,
2
1
r
e
-
l
o
a
d
b
i
t
0
:
R
e
-
l
o
a
d
d
i
s
a
b
l
e
d
1
:
R
e
-
l
o
a
d
a
t
n
e
x
t
u
n
d
e
r
f
l
o
w
C
o
m
p
a
r
e
l
a
t
c
h
3
0
,
3
1
r
e
-
l
o
a
d
b
i
t
0
:
R
e
-
l
o
a
d
d
i
s
a
b
l
e
d
1
:
R
e
-
l
o
a
d
a
t
n
e
x
t
u
n
d
e
r
f
l
o
w
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
C
o
m
p
a
r
e
r
e
g
i
s
t
e
r
r
e
-
l
o
a
d
r
e
g
i
s
t
e
r
(
C
M
P
R
:
a
d
d
r
e
s
s
0
0
1
41
6,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
01
6)
■ Notes on Output Compare
• When the selected source timer of each compare channel is
stopped, written data to compare register is loaded to the com-
pare latch simultaneously.
• Do not write the same data to both of compare latch x0 and x1.
• When setting value of the compare latch is larger than timer set-
ting value, compare match signal is not generated. Accordingly,
the output waveform is fixed to “L” or “H” level.
However, when setting value of another compare latch is
smaller than timer setting value, this compare match signal is
generated. Accordingly, compare match interrupt occurs.
• When the compare x trigger enable bit is cleared to “0” (dis-
abled), the match trigger to the waveform output circuit is
disabled, and the output waveform can be fixed to “L” or “H”
level.
However, in this case, the compare match signal is generated.
Accordingly, compare match interrupt occurs.
7542 Group
Rev.3.03 Jul 11, 2008 Page 37 of 117
REJ03B0006-0303
Fig. 38 Structure of timer source selection register
Fig. 39 Structure of compare output mode register
Fig. 40 Structure of capture/compare status register
Fig. 41 Structure of compare interrupt source register
b
7
b
0
C
o
m
p
a
r
e
0
t
i
m
e
r
s
o
u
r
c
e
b
i
t
C
o
m
p
a
r
e
1
t
i
m
e
r
s
o
u
r
c
e
b
i
t
C
o
m
p
a
r
e
2
t
i
m
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r
s
o
u
r
c
e
b
i
t
C
o
m
p
a
r
e
3
t
i
m
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r
s
o
u
r
c
e
b
i
t
C
a
p
t
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r
e
0
t
i
m
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r
s
o
u
r
c
e
b
i
t
C
a
p
t
u
r
e
1
t
i
m
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r
s
o
u
r
c
e
b
i
t
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
0
:
T
i
m
e
r
A
1
:
T
i
m
e
r
B
T
i
m
e
r
s
o
u
r
c
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s
e
l
e
c
t
i
o
n
r
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g
i
s
t
e
r
(
T
M
S
R
:
a
d
d
r
e
s
s
0
0
1
F
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
0
1
6
)
b
7
b
0
C
o
m
p
a
r
e
0
o
u
t
p
u
t
l
e
v
e
l
l
a
t
c
h
0
:
P
o
s
i
t
i
v
e
1
:
N
e
g
a
t
i
v
e
C
o
m
p
a
r
e
1
o
u
t
p
u
t
l
e
v
e
l
l
a
t
c
h
0
:
P
o
s
i
t
i
v
e
1
:
N
e
g
a
t
i
v
e
C
o
m
p
a
r
e
2
o
u
t
p
u
t
l
e
v
e
l
l
a
t
c
h
0
:
P
o
s
i
t
i
v
e
1
:
N
e
g
a
t
i
v
e
C
o
m
p
a
r
e
3
o
u
t
p
u
t
l
e
v
e
l
l
a
t
c
h
0
:
P
o
s
i
t
i
v
e
1
:
N
e
g
a
t
i
v
e
C
o
m
p
a
r
e
0
t
r
i
g
g
e
r
e
n
a
b
l
e
b
i
t
0
:
D
i
s
a
b
l
e
d
1
:
E
n
a
b
l
e
d
C
o
m
p
a
r
e
1
t
r
i
g
g
e
r
e
n
a
b
l
e
b
i
t
0
:
D
i
s
a
b
l
e
d
1
:
E
n
a
b
l
e
d
C
o
m
p
a
r
e
2
t
r
i
g
g
e
r
e
n
a
b
l
e
b
i
t
0
:
D
i
s
a
b
l
e
d
1
:
E
n
a
b
l
e
d
C
o
m
p
a
r
e
3
t
r
i
g
g
e
r
e
n
a
b
l
e
b
i
t
0
:
D
i
s
a
b
l
e
d
1
:
E
n
a
b
l
e
d
C
o
m
p
a
r
e
o
u
t
p
u
t
m
o
d
e
r
e
g
i
s
t
e
r
(
C
M
O
M
:
a
d
d
r
e
s
s
0
0
2
1
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
0
1
6
)
b
7
b
0
C
o
m
p
a
r
e
0
o
u
t
p
u
t
s
t
a
t
u
s
b
i
t
0
:
“
L
”
l
e
v
e
l
o
u
t
p
u
t
1
:
“
H
”
l
e
v
e
l
o
u
t
p
u
t
C
o
m
p
a
r
e
1
o
u
t
p
u
t
s
t
a
t
u
s
b
i
t
0
:
“
L
”
l
e
v
e
l
o
u
t
p
u
t
1
:
“
H
”
l
e
v
e
l
o
u
t
p
u
t
C
o
m
p
a
r
e
2
o
u
t
p
u
t
s
t
a
t
u
s
b
i
t
0
:
“
L
”
l
e
v
e
l
o
u
t
p
u
t
1
:
“
H
”
l
e
v
e
l
o
u
t
p
u
t
C
o
m
p
a
r
e
3
o
u
t
p
u
t
s
t
a
t
u
s
b
i
t
0
:
“
L
”
l
e
v
e
l
o
u
t
p
u
t
1
:
“
H
”
l
e
v
e
l
o
u
t
p
u
t
C
a
p
t
u
r
e
0
s
t
a
t
u
s
b
i
t
0
:
l
a
t
c
h
0
0
c
a
p
t
u
r
e
d
1
:
l
a
t
c
h
0
1
c
a
p
t
u
r
e
d
C
a
p
t
u
r
e
1
s
t
a
t
u
s
b
i
t
0
:
l
a
t
c
h
1
0
c
a
p
t
u
r
e
d
1
:
l
a
t
c
h
1
1
c
a
p
t
u
r
e
d
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
C
a
p
t
u
r
e
/
C
o
m
p
a
r
e
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
C
C
S
R
:
a
d
d
r
e
s
s
0
0
2
21
6,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
01
6)
b
7
b
0
C
o
m
p
a
r
e
l
a
t
c
h
0
0
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
b
i
t
C
o
m
p
a
r
e
l
a
t
c
h
0
1
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
b
i
t
C
o
m
p
a
r
e
l
a
t
c
h
1
0
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
b
i
t
C
o
m
p
a
r
e
l
a
t
c
h
1
1
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
b
i
t
C
o
m
p
a
r
e
l
a
t
c
h
2
0
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
b
i
t
C
o
m
p
a
r
e
l
a
t
c
h
2
1
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
b
i
t
C
o
m
p
a
r
e
l
a
t
c
h
3
0
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
b
i
t
C
o
m
p
a
r
e
l
a
t
c
h
3
1
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
b
i
t
0
:
D
i
s
a
b
l
e
d
1
:
E
n
a
b
l
e
d
C
o
m
p
a
r
e
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
s
e
t
r
e
g
i
s
t
e
r
(
C
I
S
R
:
a
d
d
r
e
s
s
0
0
2
3
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
0
1
6
)
Fig. 37 Structure of capture/compare port register
b
7
b
0
C
a
p
t
u
r
e
0
i
n
p
u
t
p
o
r
t
b
i
t
s
b
1
b
0
00
:
C
a
p
t
u
r
e
f
r
o
m
P
0
0
01
:
C
a
p
t
u
r
e
f
r
o
m
P
1
0
10
:
R
i
n
g
/
5
1
2
11
:
N
o
t
a
v
a
i
l
a
b
l
e
C
o
m
p
a
r
e
0
o
u
t
p
u
t
p
o
r
t
b
i
t
0
:
P
0
1
i
s
I
/
O
p
o
r
t
1
:
P
0
1
i
s
C
o
m
p
a
r
e
0
C
o
m
p
a
r
e
1
o
u
t
p
u
t
p
o
r
t
b
i
t
0
:
P
0
2
i
s
I
/
O
p
o
r
t
1
:
P
0
2
i
s
C
o
m
p
a
r
e
1
C
a
p
t
u
r
e
1
i
n
p
u
t
p
o
r
t
b
i
t
0
:
C
a
p
t
u
r
e
f
r
o
m
P
3
0
1
:
R
i
n
g
/
5
1
2
C
o
m
p
a
r
e
2
o
u
t
p
u
t
p
o
r
t
b
i
t
0
:
P
3
1
i
s
I
/
O
p
o
r
t
1
:
P
3
1
i
s
C
o
m
p
a
r
e
2
C
o
m
p
a
r
e
3
o
u
t
p
u
t
p
o
r
t
b
i
t
0
:
P
3
2
i
s
I
/
O
p
o
r
t
1
:
P
3
2
i
s
C
o
m
p
a
r
e
3
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
C
a
p
t
u
r
e
/
C
o
m
p
a
r
e
p
o
r
t
r
e
g
i
s
t
e
r
(
C
C
P
R
:
a
d
d
r
e
s
s
0
0
1
E
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
0
1
6
)
7542 Group
Rev.3.03 Jul 11, 2008 Page 38 of 117
REJ03B0006-0303
Fig. 42 Block diagram of output compare
Fig. 43 Block diagram of compare channel 0
Timer A latch
Timer A counter
Timer B counter
Timer B latch
Compare latch 00
Compare latch 01
Wave latch channel 0
Compare 0 timer source bit
Compare channel 0
Compare channel 1
Compare channel 2
Compare channel 3
P0
1
/CMP
0
P0
2
/CMP
1
P3
1
/CMP
2
P3
2
/CMP
3
Compare buffer 00 (16)
Compare latch 00 (16)
Compare buffer 01 (16)
Compare latch 01 (16)
Data bus
Compare interrupt
Compare register
write pointer
(001216, bits 0 to 2)
Compare latch 00, 01
re-load bit
(001416, bit 0)
Timer A counter (16)
Compare 0 timer
source bit
(001F16, bit 0)
Compare 0 trigger
enable bit
(002116, bit 4)
Output latch
Compare 0 output
level latch
(002116, bit 0)
Compare 0 output
status bit
(002216, bit 0)
Compare 0 output
port bit
(001E16, bit 2)
P01/CMP0
Timer B counter (16)
I/O port
Compare latch 00
interrupt source
bit (002316, bit 0)
Compare latch 01
interrupt source
bit (002316, bit 1)
Compare register
7542 Group
Rev.3.03 Jul 11, 2008 Page 39 of 117
REJ03B0006-0303
Fig. 44 Block diagram at modulation mode
Compare buffer 00 (16)
Compare latch 00 (16)
Compare buffer 01 (16)
Compare latch 01 (16)
Data bus
Compare register
Compare register
write pointer
(001216, bits 0 to 2)
Compare latch 00, 01
re-load bit
(001416, bit 0)
Timer A counter (16)
Compare 0 (1)
timer source bits
(001F16, bit 0 (bit 1)
Compare 0 trigger
enable bit
(002116, bit 4)
Output latch
Compare 0 output
level latch
(002116, bit 0)
Compare 0 output
status bit
(002216, bit 0)
Compare 0 output
port bit
(001E16, bit 2)
P01/CMP0
Timer B counter (16)
Compare 1 trigger
enable bit
(002116, bit 5)
Output latch
Compare 1 output
level latch
(002116, bit 1)
Compare 1 output
status bit
(002216, bit 1)
Underflow
Compare latch 10 (16)
Compare buffer 10 (16)
Compare latch 11 (16)
Compare buffer 11 (16)
Data bus
Compare register
Compare latch 10, 11
re-load bit
(001416, bit 1)
Compare register
write pointer
(001216, bits 0 to 2)
I/O
port
7542 Group
Rev.3.03 Jul 11, 2008 Page 40 of 117
REJ03B0006-0303
Fig. 45 Output compare mode (general waveform)
Fig. 46 Output compare mode (compare register write timing)
000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 000F 000E 000D 000C 000B0000
000B
0005
0 1 0
Timer underflow
Timer count value
Compare latch 00
Compare latch 01
Compare 00 match
Compare 01 match
Compare output
Compare interrupt
Compare status bit
Timer count clock
Note: Compare interrupt occurs only for the interrupt source selected by Compare interrupt source register.
Re-load the count value
000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 000F 000E 000D 000C 000B0000
000B
0005
0 1 10
000E
000C
0
Timer underflow
Timer count value
Compare latch 00
Compare latch 01
Compare latch 00 write
Compare latch 01 write
Compare latch 00, 01 re-load bit
Compare latch 00, 01 re-load signal
Compare 00 match
Compare 01 match
Compare output
Compare interrupt
Compare status bit
Timer count clock
Re-load the count value
7542 Group
Rev.3.03 Jul 11, 2008 Page 41 of 117
REJ03B0006-0303
Fig. 47 Output compare mode (compare 0, 1 modulation mode)
0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 0002 0001 0007 0006 0005 0004 00030000
0006
0002
0 1 101
0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 0002 0001 0007 0006 0005 0004 00030000
0004
0001
0 1 1010
Timer A underflow
Timer A count value
Compare latch 00
Compare latch 01
Compare 00 match
Compare 01 match
Compare 0 output
Compare 0 output status bit
Timer A count clock
Carrier wave generated by Compare 0
Compare 0 output
Timer B count value
Compare latch 10
Compare latch 11
Compare 10 match
Compare 11 match
Compare 1 output
Compare interrupt
Compare 1 output status bit
Timer A underflow
Modulation of output waveform generated by Compare 1
Modulation output
Note: Compare interrupt occurs only for the interrupt source selected by Compare interrupt source register.
Port outptu wavefowm
7542 Group
Rev.3.03 Jul 11, 2008 Page 42 of 117
REJ03B0006-0303
Fig. 48 Output compare mode (compare 0, 1 modulation mode: effect of output level latch)
Modulation output
Compare 1 output
Compare 0 output
1. When Compare 0 output level latch is “Positive”, Compare 1 output level latch is “Positive”.
Modulation output
Compare 1 output
Compare 0 output
2. When Compare 0 output level latch is “Negative”, Compare 1 output level latch is “Positive”.
Modulation output
Compare 1 output
Compare 0 output
3. When Compare 0 output level latch is “Positive”, Compare 1 output level latch is “Negative”.
Modulation output
Compare 1 output
Compare 0 output
4. When Compare 0 output level latch is “Negative”, Compare 1 output level latch is “Negative”.
7542 Group
Rev.3.03 Jul 11, 2008 Page 43 of 117
REJ03B0006-0303
Input capture
7542 group has 2-input capture channels. Each channel (0 and 1)
has the same function and can be used to capture count value of
either Timer A or Timer B.
The source timer for each channel is selected by setting value of
the capture x (x = 0, 1) timer source bit. Timer A and Timer B can
be selected for the source timer to each channel, respectively.
To use each capture channel, set the capture x input port bits and
set the port direction register corresponding to capture channel to
input mode.
The input capture circuit retains the count value of selected timer
when external trigger is input. The timer count value is retained to
the capture latch x0 when rising edge is input and is retained to
the capture latch x1 when falling edge is input.
The count value of timer can be retained by software by capture y
(y = 00, 01, 10, 11) software trigger bit too. When “1” is set to this
bit, count value of timer is retained to the corresponded capture
latch.
When reading from the capture y
software trigger bit is executed,
“0” is read out.
The latest status of capture latch can be confirmed by reading of
the capture x status bit. This bit indicates the capture latch which
latest data is in.
The valid trigger edge for capture interrupt is set by the capture x
interrupt edge selection bits. (Regardless of the setting value of
capture x interrupt edge selection bits, timer count values for both
edges are retained to the capture latch.)
Each capture input has the noise filter circuit that judges continu-
ous 4-time same level with sampling clock to be valid. The
sampling clock of noise filter is set by the capture x noise filter
clock selection bits.
Reading from the register for each channel is controlled by setting
value of the capture register read pointer. Reading from each reg-
ister is in the following order;
1.Set the value of the corresponded input capture channel to the
capture register read pointer.
2.Read from the capture register (low-order) and capture register
(high-order).
■ Notes on Input Capture
• If the capture trigger is input while the capture register (low-order
and high-order) is in read, captured value is changed between
high-order reading and low-order reading. Accordingly, some
countermeasure by software is recommended, for example
comparing the values that twice of read.
• When the on-chip-oscillator is selected for Timer A count source,
Timer A cannot be used for the capture source timer.
Timer B cannot be used for the capture source timer when the
system is in the following state;
• CPU operation clock source: XIN oscillation
• Timer B count source: Timer A underflow
• Timer A count source: On-chip oscillator output
• When writing “1” to capture latch x0 (x1) software trigger bit of
capture latch x0 and x1 at the same time, or external trigger and
software trigger occur simultaneously, the set value of capture x
status bit is undefined.
• When setting the interrupt active edge selection bit and noise fil-
ter clock selection bit of external interrupt CAP0, CAP1, the
interrupt request bit may be set to “1”.
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
➀ Set the corresponding interrupt enable bit to “0” (disabled).
➁ Set the interrupt edge selection bit or noise filter clock selection bit.
➂ Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃ Set the corresponding interrupt enable bit to “1” (enabled).
• When the capture interrupt is used as the interrupt for return
from stop mode, set the capture x noise filter clock selection bits
to “00 (Filter stop)”.
7542 Group
Rev.3.03 Jul 11, 2008 Page 44 of 117
REJ03B0006-0303
Fig. 49 Structure of capture software trigger register
b
7
b
0C
a
p
t
u
r
e
r
e
g
i
s
t
e
r
0
(
L
o
w
-
o
r
d
e
r
)
(
C
A
P
0
L
:
a
d
d
r
e
s
s
0
0
0
C1
6)
b
7
b
0C
a
p
t
u
r
e
r
e
g
i
s
t
e
r
0
(
H
i
g
h
-
o
r
d
e
r
)
(
C
A
P
0
H
:
a
d
d
r
e
s
s
0
0
0
D1
6)
b7 b0 C
a
p
t
u
r
e
r
e
g
i
s
t
e
r
1
(
L
o
w
-
o
r
d
e
r
)
(
C
A
P
1
L
:
a
d
d
r
e
s
s
0
0
0
E1
6)
b
7
b
0C
a
p
t
u
r
e
r
e
g
i
s
t
e
r
1
(
H
i
g
h
-
o
r
d
e
r
)
(
C
A
P
1
H
:
a
d
d
r
e
s
s
0
0
0
F1
6)
b
7
b
0
C
a
p
t
u
r
e
0
i
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
s
b
1
b
0
00
:
R
i
s
i
n
g
a
n
d
f
a
l
l
i
n
g
e
d
g
e
01
:
R
i
s
i
n
g
e
d
g
e
10
:
F
a
l
l
i
n
g
e
d
g
e
11
:
N
o
t
a
v
a
i
l
a
b
l
e
C
a
p
t
u
r
e
1
i
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
s
b
3
b
2
00
:
R
i
s
i
n
g
a
n
d
f
a
l
l
i
n
g
e
d
g
e
01
:
R
i
s
i
n
g
e
d
g
e
10
:
F
a
l
l
i
n
g
e
d
g
e
11
:
N
o
t
a
v
a
i
l
a
b
l
e
C
a
p
t
u
r
e
0
n
o
i
s
e
f
i
l
t
e
r
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
s
b
5
b
4
00
:
F
i
l
t
e
r
s
t
o
p
01
:
f
(
X
I
N
)
10
:
f
(
X
I
N
)
/
8
11
:
f
(
X
I
N
)
/
3
2
C
a
p
t
u
r
e
1
n
o
i
s
e
f
i
l
t
e
r
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
s
b
7
b
6
00
:
F
i
l
t
e
r
s
t
o
p
01
:
f
(
X
I
N
)
10
:
f
(
X
I
N
)
/
8
11
:
f
(
X
I
N
)
/
3
2
C
a
p
t
u
r
e
m
o
d
e
r
e
g
i
s
t
e
r
(
C
A
P
M
:
a
d
d
r
e
s
s
0
0
2
0
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
0
1
6
)
b
7
b
0
C
a
p
t
u
r
e
l
a
t
c
h
0
0
s
o
f
t
w
a
r
e
t
r
i
g
g
e
r
b
i
t
C
a
p
t
u
r
e
l
a
t
c
h
0
1
s
o
f
t
w
a
r
e
t
r
i
g
g
e
r
b
i
t
C
a
p
t
u
r
e
l
a
t
c
h
1
0
s
o
f
t
w
a
r
e
t
r
i
g
g
e
r
b
i
t
C
a
p
t
u
r
e
l
a
t
c
h
1
1
s
o
f
t
w
a
r
e
t
r
i
g
g
e
r
b
i
t
E
a
c
h
so
f
t
w
a
r
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t
r
i
g
g
e
r
o
c
c
u
r
s
b
y
s
e
t
t
i
n
g
“
1
”
t
o
c
o
r
r
e
s
p
o
n
d
i
n
g
b
i
t
.
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
C
a
p
t
u
r
e
s
o
f
t
w
a
r
e
t
r
i
g
g
e
r
r
e
g
i
s
t
e
r
(
C
S
T
R
:
a
d
d
r
e
s
s
0
0
1
3
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
0
1
6
)
Fig. 50 Structure of capture software trigger register/capture
mode register
7542 Group
Rev.3.03 Jul 11, 2008 Page 45 of 117
REJ03B0006-0303
Fig. 51 Block diagram of input capture
Fig. 52 Block diagram of capture channel 0
P1
0
/CAP
0
P0
0
/CAP
0
Timer A latch
Timer A counter
Timer B counter
Timer B latch
Capture latch 00
Capture latch 01
Trigger input channel 0
Capture 0 timer source bit
Capture channel 0
Capture channel 1
Ring
/512
Ring
/512
P3
0
/CAP
1
Capture pointer
(001316, bits 4, 5)
Capture latch 00 (16) Capture latch 01 (16)
Data bus
Capture interrupt
Capture register 0
read pointer
(001216, bit 4)
Timer A counter (16)
Capture 0 timer
source bit
(001F16, bit 4)
Capture
trigger
Capture 0
status bit
(002216, bit 4)
Digital filter
Ring/512
Capture latch 00
software trigger bit
(001316, bit 0)
Capture 0 input
port bits
(001E16, bits 0, 1) Timer B counter (16)
Capture 0
interrupt edge
selection bits
(002016, bits 0, 1)
P10/CAP0
Capture register
Capture latch 0 (16)
Capture 0 noise
filter clock
selection bits
(002016, bits 4, 5)
P00/CAP0
Rising Falling
7542 Group
Rev.3.03 Jul 11, 2008 Page 46 of 117
REJ03B0006-0303
Fig. 53 Capture interrupt edge selection = “rising edge”
Fig. 54 Capture interrupt edge selection = “rising and falling edge”
000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 000F 000E 000D 000C 000B0000
XXXX 000A 000C
XXXX 0005
0001
000F
1 0 1 010
Timer underflow
Capture input wave
Timer count value
Capture latch 00
Capture latch 01
Capture interrupt
Capture x (x=0, 1) status bit
Re-load the timer count value
Overwrite
000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 000F 000E 000D 000C 000B0000
1 0 1 010
XXXX 000A 000C
XXXX 0005
0001
000F
Timer underflow
Capture input wave
Timer count value
Capture latch 00
Capture latch 01
Capture interrupt
Capture x (x=0, 1) status bit
Re-load the timer count value
Overwrite
7542 Group
Rev.3.03 Jul 11, 2008 Page 47 of 117
REJ03B0006-0303
Fig. 55 Block diagram of clock synchronous serial I/O1
Fig. 56 Operation of clock synchronous serial I/O1 function
Serial Interface
The 7542 Group has Serial I/O1 and Serial I/O2. Except that Serial
I/O1 has the bus collision detection function and the TXD2 output
structure for Serial I/O2 is CMOS only, they have the same function.
●Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
(1) Clock Synchronous Serial I/O1 Mode
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control register
(bit 6) to “1”.
For clock synchronous serial I/O1, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
1
/
4
1
/
4
F
/
F
P
12/
SC
L
K
1
S
e
r
i
a
l
I
/
O
1
s
t
a
t
u
s
r
e
g
i
s
t
e
r
Serial I/O1 control register
P
13/
SR
D
Y
1
P
10/
RXD1/
C
A
P0
P
11/
TXD1
XIN
Receive buffer register 1
A
d
d
r
e
s
s
0
0
1
81
6
R
e
c
e
i
v
e
s
h
i
f
t
r
e
g
i
s
t
e
r
1
R
e
c
e
i
v
e
b
u
f
f
e
r
f
u
l
l
f
l
a
g
(
R
B
F
)
Receive interru pt request (RI)
Clock control circui
t
S
h
i
f
t
c
l
o
c
k
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator 1
Address 001C16
BRG count source selection bit
C
l
o
c
k
c
o
n
t
r
o
l
c
i
r
c
u
i
t
Falling-edge det ector
T
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
1
Data bus A
d
d
r
e
s
s
0
0
1
81
6
Shift cloc
k
T
r
a
n
s
m
i
t
s
h
i
f
t
c
o
m
p
l
e
t
i
o
n
f
l
a
g
(
T
S
C
)
T
r
a
n
s
m
i
t
b
u
f
f
e
r
e
m
p
t
y
f
l
a
g
(
T
B
E
)
T
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
(
T
I
)
Transmit interrupt source selection bit
Address 001916
Data bus
A
d
d
r
e
s
s
0
0
1
A1
6
Transmit shift register 1
D7
D7
D0D1D2D3D4D5D6
D0D1D2D3D4D5D6
RBF = 1
TSC = 1
TBE = 0 TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD1
Serial input RxD1
Write pulse to receive/transmit
buffer register 1 (address 001816)
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after
the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O1 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD1 pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Receive enable signal SRDY1
7542 Group
Rev.3.03 Jul 11, 2008 Page 48 of 117
REJ03B0006-0303
Fig. 57 Block diagram of UART serial I/O1
(2) Asynchronous Serial I/O1 (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit of the serial I/O1 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Fig. 58 Operation of UART serial I/O1 function
XI
N
1/4
OE
PE FE
1/16
1
/
1
6
D
a
t
a
b
u
s
R
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
1
A
d
d
r
e
s
s
0
0
1
81
6
R
e
c
e
i
v
e
s
h
i
f
t
r
e
g
i
s
t
e
r
1
R
e
c
e
i
v
e
b
u
f
f
e
r
f
u
l
l
f
l
a
g
(
R
B
F
)
R
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
(
R
I
)
Baud rate generator 1
F
r
e
q
u
e
n
c
y
d
i
v
i
s
i
o
n
r
a
t
i
o
1
/
(
n
+
1
)
A
d
d
r
e
s
s
0
0
1
C1
6
S
T
/
S
P
/
P
A
g
e
n
e
r
a
t
o
r
Transmit buffer register 1
Data bus
T
r
a
n
s
m
i
t
s
h
i
f
t
r
e
g
i
s
t
e
r
1
Address 001816
Transmit shift completion f lag (T SC)
T
r
a
n
s
m
i
t
b
u
f
f
e
r
e
m
p
t
y
f
l
a
g
(
T
B
E
)
T
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
(
T
I
)
Address 001916
ST detector
SP detector U
A
R
T
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
Address 001B16
Character length selection bit
A
d
d
r
e
s
s
0
0
1
A1
6
B
R
G
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
Transmit interrupt source selection bit
S
e
r
i
a
l
I
/
O
1
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
C
l
o
c
k
c
o
n
t
r
o
l
c
i
r
c
u
i
t
C
h
a
r
a
c
t
e
r
l
e
n
g
t
h
s
e
l
e
c
t
i
o
n
b
i
t
7
b
i
t
s
8
b
i
t
s
S
e
r
i
a
l
I
/
O
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
P
12/
SC
L
K
1
Serial I/O1 status register
P
10/
RXD1/
C
A
P0
P11/TXD1
TSC=0
TBE=1
RBF=0
TBE=0 TBE=0
RBF=1 RBF=1
STD
0
D
1
SP D
0
D
1
ST SP
TBE=1 TSC=1
STD
0
D
1
SP D
0
D
1
ST SP
Transmit or receive clock
Transmit buffer 1
write signal
Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Notes
✽
✽
Serial output T
X
D
1
Serial input R
X
D
1
Receive buffer 1
read signal
7542 Group
Rev.3.03 Jul 11, 2008 Page 49 of 117
REJ03B0006-0303
[Transmit buffer register 1/receive buffer register 1 (TB1/
RB1)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[Serial I/O1 status register (SIO1STS)] 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O1 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit of the serial I/O1 control regis-
ter has been set to “1”, the transmit shift completion flag (bit 2)
and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O1 control register (SIO1CON)] 001A16
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[UART1 control register (UART1CON)] 001B16
The UART1 control register consists of four control bits (bits 0 to
3) which are valid when asynchronous serial I/O is selected and
set the data format of an data transfer and one bit (bit 4) which is
always valid and sets the output structure of the P11/TxD1 pin.
[Baud rate generator 1 (BRG1)] 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
■ Notes on Serial I/O1
• Serial I/O interrupt
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission en-
abled, take the following sequence.
➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁ Set the transmit enable bit to “1”.
➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➃ Set the serial I/O transmit interrupt enable bit to “1” (enabled).
• I/O pin function when serial I/O1 is enabled.
The functions of P12 and P13 are switched with the setting values
of a serial I/O1 mode selection bit and a serial I/O1 synchronous
clock selection bit as follows.
(1) Serial I/O1 mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
Setup of a serial I/O1 synchronous clock selection bit
“0” : P12 pin turns into an output pin of a synchronous clock.
“1” : P12 pin turns into an input pin of a synchronous clock.
Setup of a SRDY1 output enable bit (SRDY)
“0” : P13 pin can be used as a normal I/O pin.
“1” : P13 pin turns into a SRDY1 output pin.
(2) Serial I/O1 mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O1 synchronous clock selection bit
“0”: P12 pin can be used as a normal I/O pin.
“1”: P12 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is
P13 pin. It can be used as a normal I/O pin.
7542 Group
Rev.3.03 Jul 11, 2008 Page 50 of 117
REJ03B0006-0303
Fig. 59 Structure of serial I/O1-related registers
T
r
a
n
s
m
i
t
b
u
f
f
e
r
e
m
p
t
y
f
l
a
g
(
T
B
E
)
0
:
B
u
f
f
e
r
f
u
l
l
1
:
B
u
f
f
e
r
e
m
p
t
y
R
e
c
e
i
v
e
b
u
f
f
e
r
f
u
l
l
f
l
a
g
(
R
B
F
)
0
:
B
u
f
f
e
r
e
m
p
t
y
1
:
B
u
f
f
e
r
f
u
l
l
T
r
a
n
s
m
i
t
s
h
i
f
t
c
o
m
p
l
e
t
i
o
n
f
l
a
g
(
T
S
C
)
0
:
T
r
a
n
s
m
i
t
s
h
i
f
t
i
n
p
r
o
g
r
e
s
s
1
:
T
r
a
n
s
m
i
t
s
h
i
f
t
c
o
m
p
l
e
t
e
d
O
v
e
r
r
u
n
e
r
r
o
r
f
l
a
g
(
O
E
)
0
:
N
o
e
r
r
o
r
1
:
O
v
e
r
r
u
n
e
r
r
o
r
P
a
r
i
t
y
e
r
r
o
r
f
l
a
g
(
P
E
)
0
:
N
o
e
r
r
o
r
1
:
P
a
r
i
t
y
e
r
r
o
r
F
r
a
m
i
n
g
e
r
r
o
r
f
l
a
g
(
F
E
)
0
:
N
o
e
r
r
o
r
1
:
F
r
a
m
i
n
g
e
r
r
o
r
S
u
m
m
i
n
g
e
r
r
o
r
f
l
a
g
(
S
E
)
0
:
(
O
E
)
U
(
P
E
)
U
(
F
E
)
=
0
1
:
(
O
E
)
U
(
P
E
)
U
(
F
E
)
=
1
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
1
”
w
h
e
n
r
e
a
d
)
b
7
b
7
S
e
r
i
a
l
I
/
O
1
s
t
a
t
u
s
r
e
g
i
s
t
e
r
S
e
r
i
a
l
I
/
O
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
b
0b
0
B
R
G
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
C
S
S
)
0
:
f
(
X
I
N
)
1
:
f
(
X
I
N
)
/
4
S
e
r
i
a
l
I
/
O
1
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
(
S
C
S
)
0
:
B
R
G
o
u
t
p
u
t
d
i
v
i
d
e
d
b
y
4
w
h
e
n
c
l
o
c
k
s
y
n
c
h
r
o
n
o
u
s
s
e
r
i
a
l
I
/
O
i
s
s
e
l
e
c
t
e
d
,
B
R
G
o
u
t
p
u
t
d
i
v
i
d
e
d
b
y
1
6
w
h
e
n
U
A
R
T
i
s
s
e
l
e
c
t
e
d
.
1
:
E
x
t
e
r
n
a
l
c
l
o
c
k
i
n
p
u
t
w
h
e
n
c
l
o
c
k
s
y
n
c
h
r
o
n
o
u
s
s
e
r
i
a
l
I
/
O
i
s
s
e
l
e
c
t
e
d
,
e
x
t
e
r
n
a
l
c
l
o
c
k
i
n
p
u
t
d
i
v
i
d
e
d
b
y
1
6
w
h
e
n
U
A
R
T
i
s
s
e
l
e
c
t
e
d
.
S
R
D
Y
1
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
(
S
R
D
Y
)
0
:
P
1
3
p
i
n
o
p
e
r
a
t
e
s
a
s
o
r
d
i
n
a
r
y
I
/
O
p
i
n
1
:
P
1
3
p
i
n
o
p
e
r
a
t
e
s
a
s
S
R
D
Y
1
o
u
t
p
u
t
p
i
n
T
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
T
I
C
)
0
:
I
n
t
e
r
r
u
p
t
w
h
e
n
t
r
a
n
s
m
i
t
b
u
f
f
e
r
h
a
s
e
m
p
t
i
e
d
1
:
I
n
t
e
r
r
u
p
t
w
h
e
n
t
r
a
n
s
m
i
t
s
h
i
f
t
o
p
e
r
a
t
i
o
n
i
s
c
o
m
p
l
e
t
e
d
T
r
a
n
s
m
i
t
e
n
a
b
l
e
b
i
t
(
T
E
)
0
:
T
r
a
n
s
m
i
t
d
i
s
a
b
l
e
d
1
:
T
r
a
n
s
m
i
t
e
n
a
b
l
e
d
R
e
c
e
i
v
e
e
n
a
b
l
e
b
i
t
(
R
E
)
0
:
R
e
c
e
i
v
e
d
i
s
a
b
l
e
d
1
:
R
e
c
e
i
v
e
e
n
a
b
l
e
d
S
e
r
i
a
l
I
/
O
1
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
(
S
I
O
M
)
0
:
C
l
o
c
k
a
s
y
n
c
h
r
o
n
o
u
s
(
U
A
R
T
)
s
e
r
i
a
l
I
/
O
1
:
C
l
o
c
k
s
y
n
c
h
r
o
n
o
u
s
s
e
r
i
a
l
I
/
O
S
e
r
i
a
l
I
/
O
1
e
n
a
b
l
e
b
i
t
(
S
I
O
E
)
0
:
S
e
r
i
a
l
I
/
O
1
d
i
s
a
b
l
e
d
(
p
i
n
s
P
1
0
t
o
P
1
3
o
p
e
r
a
t
e
a
s
o
r
d
i
n
a
r
y
I
/
O
p
i
n
s
)
1
:
S
e
r
i
a
l
I
/
O
1
e
n
a
b
l
e
d
(
p
i
n
s
P
1
0
t
o
P
1
3
o
p
e
r
a
t
e
a
s
s
e
r
i
a
l
I
/
O
p
i
n
s
)
b7
U
A
R
T
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P1
1
/T
X
D
1
P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
b0
(
S
I
O
1
S
T
S
:
a
d
d
r
e
s
s
0
0
1
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7542 Group
Rev.3.03 Jul 11, 2008 Page 51 of 117
REJ03B0006-0303
Bus collision detection (SIO1)
SIO1 can detect a bus collision by setting UART1 bus collision de-
tection interrupt enable bit.
When transmission is started in the clock synchronous or asyn-
chronous (UART) serial I/O mode, the transmit pin TxD1 is
compared with the receive pin RxD1 in synchronization with rising
edge of transmit shift clock. If they do not coincide with each other,
a bus collision detection interrupt request occurs.
When a transmit data collision is detected between LSB and MSB
of transmit data in the clock synchronous serial I/O mode or be-
tween the start bit and stop bit of transmit data in UART mode, a
bus collision detection can be performed by both the internal clock
and the external clock.
A block diagram is shown in Fig. 61.
A timing diagram is shown in Fig. 62.
Note: Bus collision detection can be used when SIO1 is operating
at full-duplex communication. When SIO1 is operating at
half-duplex communication, set bus collision detection inter-
rupt to be disabled.
Fig. 61 Block diagram of bus collision detection interrupt circuit
Fig. 62 Timing diagram of bus collision detection interrupt
D
TxD1
RxD1
Shift clock
UART1 bus collision detection
interrupt valid bit
(Address 000A16, bit 1)
UART1 bus collision detection
interrupt discrimination bit
(Address 000B16, bit 1)
Key-on wakeup/
UART1 bus collision detection
interrupt request bit
(Address 003C16, bit 6)
Key-on wakeup interrupt request
Q
0 : No interrupt request issued
Interrupt source set register
(INTSET: address 000A16, initial value: 0016)
Key-on wakeup interrupt valid bit
b7 b0
0: Interrupt invalid
Interrupt source discrimination register
(INTDIS: address 000B16, initial value: 0016)
Key-on wakeup interrupt discrimination bit
b7 b0
Interrupt request register 1
(IREQ1 : address 003C16, initial value : 0016)
Serial I/O1 receive interrupt request bit
b7 b0
Serial I/O1 receive interrupt enable bit
0 : Interrupts disabled
Interrupt control register 1
(ICON1 : address 003E16, initial value : 0016)
b7 b0
1 : Interrupts enabled
CNTR0 interrupt enable bit
Key-on wake up/UART1 bus collision
INT1 interrupt enable bit
INT0 interrupt enable bit
Serial I/O2 transmit interrupt enable bit
Serial I/O2 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
detection interrupt enable bit
1 : Interrupt request issued
CNTR0 interrupt request bit
detection interrupt request bit
Key-on wake up/UART1 bus collision
INT1 interrupt request bit
INT0 interrupt request bit
Serial I/O2 transmit interrupt request bit
Serial I/O2 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
1: Interrupt occurs
0: Interrupt does not occur
Not used (returns “0” when read)
Timer 1 interrupt discrimination bit
A/D conversion interrupt discrimination bit
discrimination bit
UART1 bus collision detection interrupt
1: Interrupt valid
Not used (returns “0” when read)
Timer 1 interrupt valid bit
A/D conversion interrupt valid bit
UART1 bus collision detection
interrupt valid bit
Fig. 60 Bus collision detection circuit related registers
Bus collision detection
interrupt generation
Data collision
Transmit shift clock
Transmit pin TxD1
Receive pin RxD1
7542 Group
Rev.3.03 Jul 11, 2008 Page 52 of 117
REJ03B0006-0303
Fig. 63 Block diagram of clock synchronous serial I/O2
Fig. 64 Operation of clock synchronous serial I/O2 function
●Serial I/O2
Serial I/O2 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
(1) Clock Synchronous Serial I/O2 Mode
Clock synchronous serial I/O2 mode can be selected by setting
the serial I/O2 mode selection bit of the serial I/O2 control register
(bit 6) to “1”.
For clock synchronous serial I/O2, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
D7
D7
D0D1D2D3D4D5D6
D0D1D2D3D4D5D6
RBF = 1
TSC = 1
TBE = 0 TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD2
Serial input RxD2
Write pulse to receive/transmit
buffer register 2 (address 002E
16
)
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after
the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O2 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD
2
pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Receive enable signal SRDY2
1
/
4
1
/
4
F
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7542 Group
Rev.3.03 Jul 11, 2008 Page 53 of 117
REJ03B0006-0303
Fig. 65 Block diagram of UART serial I/O2
(2) Asynchronous Serial I/O2 (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O2 mode selection bit of the serial I/O2 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Fig. 66 Operation of UART serial I/O2 function
X
IN
1/4
OE
PE FE
1/16
1/16
Data bus
Receive buffer register 2
Address 002E
16
Receive shift register 2
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator 2
Frequency division ratio 1/(n+1)
Address 0032
16
ST/SP/PA generator
Transmit buffer register 2
Data bus
Transmit shift register 2
Address
002E
16
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Address
002F
16
ST detector
SP detector UART2 control register
Address 0031
16
Character length selection bit
Address 0030
16
BRG count source selection bit
Transmit interrupt source selection bit
Serial I/O2 synchronous clock selection bit
Clock control circuit
Character length selection bit
7 bits
8 bits
Serial I/O2 control register
P0
6
/S
CLK2
Serial I/O2 status register
P0
4
/R
X
D
2
P0
5
/T
X
D
2
TSC=0
TBE=1
RBF=0
TBE=0 TBE=0
RBF=1 RBF=1
STD
0
D
1
SP D
0
D
1
ST SP
TBE=1 TSC=1
STD
0
D
1
SP D
0
D
1
ST SP
Transmit or receive clock
Transmit buffer 2
write signal
Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O2 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Notes
✽
✽
Serial output T
X
D
2
Serial input R
X
D
2
Receive buffer 2
read signal
7542 Group
Rev.3.03 Jul 11, 2008 Page 54 of 117
REJ03B0006-0303
[Transmit buffer register 2/receive buffer register 2 (TB2/
RB2)] 002E16
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[Serial I/O2 status register (SIO2STS)] 002F16
The read-only serial I/O2 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O2
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O2 enable bit SIOE
(bit 7 of the serial I/O2 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O2 status register are initialized to “0” at
reset, but if the transmit enable bit of the serial I/O2 control regis-
ter has been set to “1”, the transmit shift completion flag (bit 2)
and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O2 control register (SIO2CON)] 003016
The serial I/O2 control register consists of eight control bits for the
serial I/O2 function.
[UART2 control register (UART2CON)] 003116
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer.
[Baud rate generator 2 (BRG2)] 003216
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
■ Notes on Serial I/O2
• Serial I/O interrupt
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission en-
abled, take the following sequence.
➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁ Set the transmit enable bit to “1”.
➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➄ Set the serial I/O transmit interrupt enable bit to “1” (enabled).
• I/O pin function when serial I/O2 is enabled.
The functions of P06 and P07 are switched with the setting values
of a serial I/O2 mode selection bit and a serial I/O2 synchronous
clock selection bit as follows.
(1) Serial I/O2 mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
Setup of a serial I/O2 synchronous clock selection bit
“0” : P06 pin turns into an output pin of a synchronous clock.
“1” : P06 pin turns into an input pin of a synchronous clock.
Setup of a SRDY2 output enable bit (SRDY)
“0” : P07 pin can be used as a normal I/O pin.
“1” : P07 pin turns into a SRDY2 output pin.
(2) Serial I/O2 mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O2 synchronous clock selection bit
“0”: P06 pin can be used as a normal I/O pin.
“1”: P06 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is
P07 pin. It can be used as a normal I/O pin.
7542 Group
Rev.3.03 Jul 11, 2008 Page 55 of 117
REJ03B0006-0303
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t
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n
t
e
r
r
u
p
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s
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r
c
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l
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t
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n
b
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t
(
T
I
C
)
0
:
I
n
t
e
r
r
u
p
t
w
h
e
n
t
r
a
n
s
m
i
t
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f
f
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r
h
a
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p
t
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d
1
:
I
n
t
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r
r
u
p
t
w
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t
r
a
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s
m
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f
t
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o
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i
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c
o
m
p
l
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d
T
r
a
n
s
m
i
t
e
n
a
b
l
e
b
i
t
(
T
E
)
0
:
T
r
a
n
s
m
i
t
d
i
s
a
b
l
e
d
1
:
T
r
a
n
s
m
i
t
e
n
a
b
l
e
d
R
e
c
e
i
v
e
e
n
a
b
l
e
b
i
t
(
R
E
)
0
:
R
e
c
e
i
v
e
d
i
s
a
b
l
e
d
1
:
R
e
c
e
i
v
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n
a
b
l
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d
S
e
r
i
a
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I
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O
2
m
o
d
e
s
e
l
e
c
t
i
o
n
b
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t
(
S
I
O
M
)
0
:
C
l
o
c
k
a
s
y
n
c
h
r
o
n
o
u
s
(
U
A
R
T
)
s
e
r
i
a
l
I
/
O
1
:
C
l
o
c
k
s
y
n
c
h
r
o
n
o
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s
s
e
r
i
a
l
I
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O
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r
i
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l
I
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2
e
n
a
b
l
e
b
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t
(
S
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E
)
0
:
S
e
r
i
a
l
I
/
O
2
d
i
s
a
b
l
e
d
(
p
i
n
s
P
0
4
t
o
P
0
7
o
p
e
r
a
t
e
a
s
o
r
d
i
n
a
r
y
I
/
O
p
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n
s
)
1
:
S
e
r
i
a
l
I
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O
2
e
n
a
b
l
e
d
(
p
i
n
s
P
0
4
t
o
P
0
7
o
p
e
r
a
t
e
a
s
s
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r
i
a
l
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p
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n
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)
b
7
U
A
R
T
2
c
o
n
t
r
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l
r
e
g
i
s
t
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r
C
h
a
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l
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n
g
t
h
s
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l
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c
t
i
o
n
b
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t
(
C
H
A
S
)
0
:
8
b
i
t
s
1
:
7
b
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t
s
P
a
r
i
t
y
e
n
a
b
l
e
b
i
t
(
P
A
R
E
)
0
:
P
a
r
i
t
y
c
h
e
c
k
i
n
g
d
i
s
a
b
l
e
d
1
:
P
a
r
i
t
y
c
h
e
c
k
i
n
g
e
n
a
b
l
e
d
P
a
r
i
t
y
s
e
l
e
c
t
i
o
n
b
i
t
(
P
A
R
S
)
0
:
E
v
e
n
p
a
r
i
t
y
1
:
O
d
d
p
a
r
i
t
y
S
t
o
p
b
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t
l
e
n
g
t
h
s
e
l
e
c
t
i
o
n
b
i
t
(
S
T
P
S
)
0
:
1
s
t
o
p
b
i
t
1
:
2
s
t
o
p
b
i
t
s
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
i
s
b
i
t
.
)
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
1
”
w
h
e
n
r
e
a
d
)
b
0
(
S
I
O
2
S
T
S
:
a
d
d
r
e
s
s
0
0
2
F
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e
:
8
0
1
6
)
(
S
I
O
2
C
O
N
:
a
d
d
r
e
s
s
0
0
3
0
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
0
1
6
)
(UART2CON : address 0031
16
, initial value: E0
16
)
Fig. 67 Structure of serial I/O2-related registers
7542 Group
Rev.3.03 Jul 11, 2008 Page 56 of 117
REJ03B0006-0303
A/D Converter
The functional blocks of the A/D converter are described below.
[A/D conversion register] AD
The A/D conversion register is a read-only register that stores the
result of A/D conversion. Do not read out this register during an A/
D conversion.
[A/D control register] ADCON
The A/D control register controls the A/D converter.
Bit 2 to 0 are analog input pin selection bits.
Bit 3 is the A/D conversion clock selection bit. When “0” is set to this
bit, the A/D conversion clock is f(XIN)/2 and the A/D conversion time
is 122 cycles of f(XIN). When “1” is set to this bit, the A/D conversion
clock is f(XIN) and the A/D conversion time is 61 cycles of f(XIN).
Bit 4 is the A/D conversion completion bit. The value of this bit re-
mains at “0” during A/D conversion, and changes to “1” at
completion of A/D conversion.
A/D conversion is started by setting this bit to “0”.
[Comparison voltage generator]
The comparison voltage generator divides the voltage between
AVSS and VREF by 1024, and outputs the divided voltages.
[Channel selector]
The channel selector selects one of ports P27/AN7 to P20/AN0,
and inputs the voltage to the comparator.
[Comparator and control circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores its result into the A/D
conversion register. When A/D conversion is completed, the con-
trol circuit sets the A/D conversion completion bit and the A/D
interrupt request bit to “1”. Because the comparator is constructed
linked to a capacitor, set f(XIN) in order that the A/D conversion
clock is 250 kHz or over during A/D conversion.
■ Notes on A/D converter
As for AD translation accuracy, on the following operating condi-
tions, accuracy may become low.
(1) Since the analog circuit inside a microcomputer becomes sen-
sitive to noise when VREF voltage is set up lower than Vcc
voltage, accuracy may become low rather than the case
where VREF voltage and Vcc voltage are set up to the same
value..
(2) When VREF voltage is lower than [ 3.0 V ], the accuracy at the
low temperature may become extremely low compared with
that at room temperature. When the system would be used at
low temperature, the use at VREF=3.0 V or more is recom-
mended.
Fig. 68 Structure of A/D control register
Fig. 69 Structure of A/D conversion register
Read 8-bit (Read only address 0035
16
)
b7 b0
b9 b8 b7 b6 b5 b4 b3 b2
(Address 0035
16
)
Read 10-bit (read in order address 0036
16
, 0035
16
)
b7 b0
b9 b8
(Address 0036
16
)
b7 b0
b7 b6 b5 b4 b3 b2 b1 b0
(Address 0035
16
)
Note: High-order 6-bit of address 0036
16
returns “0” when read.
Not used (returns “0” when read)
A/D conversion completion bit
0 : Conversion in progress
1 : Conversion completed
b7 b0
Analog input pin selection bits
000 : P20/AN0
001 : P21/AN1
010 : P22/AN2
011 : P23/AN3
100 : P24/AN4
101 : P25/AN5
110 : P26/AN6 (Note 1)
111 : P27/AN7 (Note 1)
Notes 1: These can be used only for 36 pin version.
2: A/D conversion clock=f(XIN) can be used
only when ceramic oscillation or on-chip oscillator is used.
Select f(XIN)/2 when RC oscillation is used.
A/D control register
(ADCON : address 003416, initial value: 1016)
A/D conversion clock selection bit (Note 2)
0 : f(XIN)/2
1 : f(XIN)
7542 Group
Rev.3.03 Jul 11, 2008 Page 57 of 117
REJ03B0006-0303
Fig. 70 Block diagram of A/D converter
A/D control register
(Address 0034
16
)
Channel selector
A/D control circuit
Resistor ladder
V
REF
Comparator
A/D interrupt request
b7 b0
Data bus
3
10
P2
0
/AN
0
P2
1
/AN
1
P2
2
/AN
2
P2
3
/AN
3
P2
4
/AN
4
P2
5
/AN
5
P2
6
/AN
6
P2
7
/AN
7
A/D conversion register (low-order) (Address 0036
16
)
(Address 0035
16
)
A/D conversion register (high-order)
V
SS
f(X
IN
)
f(X
IN
)/2
7542 Group
Rev.3.03 Jul 11, 2008 Page 58 of 117
REJ03B0006-0303
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an
8-bit watchdog timer L, being a 16-bit counter.
Standard operation of watchdog timer
The watchdog timer stops when the watchdog timer control regis-
ter (address 003916) is not set after reset. Writing an optional
value to the watchdog timer control register (address 003916)
causes the watchdog timer to start to count down. When the
watchdog timer H underflows, an internal reset occurs. Accord-
ingly, it is programmed that the watchdog timer control register
(address 003916) can be set before an underflow occurs.
When the watchdog timer control register (address 003916) is
read, the values of the high-order 6-bit of the watchdog timer H,
STP instruction function selection bit and watchdog timer H count
source selection bit are read.
Initial value of watchdog timer
By a reset or writing to the watchdog timer control register (ad-
dress 003916), the watchdog timer H is set to “FF16” and the
watchdog timer L is set to “FF16”.
Operation of watchdog timer H count source selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 003916). When this bit is
“0”, the count source becomes a watchdog timer L underflow sig-
nal. The detection time is 131.072 ms at f(XIN)=8 MHz.
When this bit is “1”, the count source becomes f(XIN)/16. In this
case, the detection time is 512 µs at f(XIN)=8 MHz.
This bit is cleared to “0” after reset.
Operation of STP instruction function selection bit
When “0” is set to STP instruction function selection bit, system
enters into the stop mode at the STP instruction execution.
When “1” is set to this bit, internal reset occurs at the STP instruc-
tion execution.
This bit is set to “1” by program, but it cannot be changed to “0” .
This bit is cleared to “0” after reset.
■ Notes on Watchdog Timer
1.
The watchdog timer is operating during the wait mode. Write data
to the watchdog timer control register to prevent timer underflow.
2.
The watchdog timer stops during the stop mode. However, the
watchdog timer is running during the oscillation stabilizing time
after the STP instruction is released. In order to avoid the under-
flow of the watchdog timer, the watchdog timer control register
must be written just before executing the STP instruction.
3. The STP instruction function selection bit (bit 6 of watchdog
timer control register (address 003916)) can be rewritten only
once after releasing reset. After rewriting it is disable to write
any data to this bit.
4. A count source of watchdog timer is affected by the clock divi-
sion selection bit of the CPU mode register.
The f(XIN) clock is supplied to the watchdog timer when select-
ing f(XIN) as the CPU clock.
The on-chip oscillator output is supplied to the watchdog timer
when selecting the on-chip oscillator output as the CPU clock.
Fig. 71 Block diagram of watchdog timer
Fig. 72 Structure of watchdog timer control register
Watchdog timer control register
(WDTCON: address 003916, initial value: 3F16)
Watchdog timer H (read only for high-order 6-bit)
STP instruction function selection bit
0 : System enters into the stop mode
at the STP instruction execution
1 : Internal reset occurs at the STP instruction execution
Watchdog timer H count source selection bit
0 : Watchdog timer L underflow
1 : f(XIN)/16 or on-chip oscillator/16
b7 b0
XIN clock
On-chip oscillator
Source clock selection
(auto-switch depending on setting of CPUM)
Data bus
“0”
“1”
1/16
Watchdog timer H count
source selection bit
Reset
circuit
STP Instruction function selection bit
Watchdog timer H (8)
Write "FF
16
" to the
watchdog timer
control register
Internal
reset
RESET
Watchdog timer L (8)
STP Instruction
Write “FF
16
” to the
watchdog timer
control register
7542 Group
Rev.3.03 Jul 11, 2008 Page 59 of 117
REJ03B0006-0303
Reset Circuit
The 7542 group starts operation by the on-chip oscillator after sys-
tem is released from reset.
Accordingly, when the rising of power supply voltage passes 2.2V,
set the reset input voltage to become below 0.2Vcc (0.44V).
Moreover, switch CPU clock to the external oscillator after the ris-
ing of power supply voltage passes the minimum operation
voltage and after an oscillation is stabilized.
Note: The minimum operation voltage is decided by the division
ratio of an external oscillator's frequency and a CPU clock.
Decide on an external oscillator's oscillation stabilizing time
after fully evaluating an oscillator's stabilizing time used.
Fig. 73 Example of reset circuit
Fig. 74 Timing diagram at reset
(Note)
0.2 VCC
0 V
0 V
Poweron
VCCRESET
VCC
RESET
Power source
voltage
detection circuit
Power source
voltage
Reset input
voltage
Note : Reset release voltage Vcc = 2.2 V
Data
Address
8-13 clock cycles
Reset address from the
vector table
1 : An on-chip oscillator applies about RING•2 MHz, φ•250 kHz frequency clock
at average of Vcc = 5 V.
2 : The mark “?” means that the address is changeable depending on the previous state.
3 : These are all internal signals except RESET.
Notes
?? FFFC FFFD
AD
H
,AD
L
???
?? AD
L
AD
H
???
Clock from
on-chip oscillator
RING φ
RESET
RESET
OUT
SYNC
7542 Group
Rev.3.03 Jul 11, 2008 Page 60 of 117
REJ03B0006-0303
Fig. 75 Internal status of microcomputer at reset
Prescaler 1 (PRE1)
Timer 1 (T1)
Timer X mode register (TXM)
Prescaler X (PREX)
Timer X (TX)
Timer count source set register (TCSS)
Serial I/O2 status register (SIO2STS)
A/D control register (ADCON)
MISRG
Watchdog timer control register (WDTCON)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt control register 1 (ICON1)
(18)
(19)
(20)
(21)
(22)
(23)
(29)
(30)
(31)
(32)
(33)
(34)
FF16
0116
0016
0016
FF16
FF16
0016
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002F
16
0030
16
0034
16
0037
16
0039
16
003A
16
003B
16
003C
16
003E
16
00111111
0016
0016
0016
10000000
Processor status register
Program counter
Contents of address FFFC
16
(PC
H
)
(PC
L
)
(PS)
Notes 1: X : Undefined
2:The content of other registers is undefined when the microcomputer is reset.
The initial values must be surely set before you use it.
3:Only flash memory version has this register.
Contents of address FFFD
16
XXXXX1XX
Port P0 direction register (P0D)
Port P1 direction register (P1D)
Port P2 direction register (P2D)
Port P3 direction register (P3D)
Pull-up control register (PULL)
(1)
(2)
(3)
(4)
(13)
Register contents
0016
0016
0016
0016
0001
16
0003
16
0005
16
0007
16
0016
16
Serial I/O1 control register (SIO1CON)
UART1 control register (UART1CON)
(16)
(17)
Serial I/O1 status register (SIO1STS)
(15)
001A
16
001B
16
0016
11100000
0019
16 10000000
XXX0 0000
Address
Port P1P3 control register (P1P3C)
(14) 0017
16 0016
Timer A, B mode register (TABM)
Capture/Compare port register (CCPR)
Timer source selection register (TMSR)
0016
0016
0016
001D
16
001E
16
001F
16
0016
0016
0016
0020
16
0021
16
0022
16
0016
0023
16
(35)
(36)
(37)
(38)
(39)
(41)
(42)
(43)
(44)
(45)
Serial I/O2 control register (SIO2CON) 0031
16
Interrupt request register 2 (IREQ2) 003D
16 0016
Interrupt control register 2 (ICON2) 003F
16 0016
(46)
(47)
(48)
(49)
UART2 control register (UART2CON)
On-chip oscillation division ratio selection register (RODR)
0016
0038
16
(40)
00000010
00010000
11100000
10000000
Capture mode register (CAPM)
Compare output mode register (CMOM)
(25)
(26)
(27)
(28)
FF16
0024
16
FF16
FF16
0025
16
0026
16
0027
16 FF16
Timer A (low-order) (TAL)
Timer A (high-order) (TAH)
Timer B (low-order) (TBL)
Timer B (high-order) (TBH)
(24)
Capture/Compare status register (CCSR)
Compare interrupt source register (CISR)
(8)
(9)
(10)
(11)
(12)
Interrupt source discrimination register (INTDIS)
Compare register (low-order) (CMPL)
(6)
(7)
Interrupt source set register (INTSET)
(5)
000B
16
0010
16
0016
000A
16
Compare register (high-order) (CMPH)
Capture/Compare register R/W pointer (CCRP)
Capture software trigger register (CSTR)
0016
0016
0016
0011
16
0012
16
0013
16
0016
0016
0014
16
0015
16
Compare register re-load register (CMPR)
Port P0P3 drive capacity control register (DCCR)
0016
0016
(51)
(52)
Flash memory control register 0 (FMCR0) (Note 3)
Flash memory control register 1 (FMCR1) (Note 3)
0FE0
16
0FE1
16
00000001
01000000
(50) Flash memory control register 2 (FMCR2) (Note 3) 0FE2
16 00000001
7542 Group
Rev.3.03 Jul 11, 2008 Page 61 of 117
REJ03B0006-0303
Fig. 77 External circuit of ceramic resonator
Fig. 78 External circuit of RC oscillation
Fig. 79 External clock input circuit
Fig. 76 Processing of XIN and XOUT pins at on-chip oscillator
operation
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator be-
tween XIN and XOUT, and an RC oscillation circuit can be formed
by connecting a resistor and a capacitor.
Use the circuit constants in accordance with the resonator
manufacturer's recommended values.
No external resistor is needed between XIN and XOUT since a
feed-back resistor exists on-chip. (An external feed-back resistor
may be needed depending on conditions.)
(1) On-chip oscillator operation
When the MCU operates by the on-chip oscillator for the main
clock, connect XIN pin to VCC through a resistor and leave XOUT
pin open.
The clock frequency of the on-chip oscillator depends on the sup-
ply voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
(2) Ceramic resonator
When the ceramic resonator is used for the main clock, connect
the ceramic resonator and the external circuit to pins XIN and
XOUT at the shortest distance. A feedback resistor is built in be-
tween pins XIN and XOUT.
(3) RC oscillation
When the RC oscillation is used for the main clock, connect the
XIN pin and XOUT pin to the external circuit of resistor R and the
capacitor C at the shortest distance.
The frequency is affected by a capacitor, a resistor and a micro-
computer.
So, set the constants within the range of the frequency limits.
(4) External clock
When the external signal clock is used for the main clock, connect
the XIN pin to the clock source and leave XOUT pin open.
Select “0” (ceramic oscillation) to oscillation mode selection bit of
CPU mode register (003B16).
Insert a damping resistor if required.
The resistance will vary depending on the oscillator and
the oscillation drive capacity setting.
Use the value recommended by the maker of the oscillator.
Also, if the oscillator manufacturer ’s data sheet specifies
that a feedback resistor be added external to the chip
though a feedback resistor exists on-chip, insert a feed-
back resistor between XIN and XOUT following the
instruction.
Note:
Connect the external
circuit of resistor R
and the capacitor C at
the shortest distance.
The frequency is af-
fected by a capacitor,
a resistor and a micro-
computer.
So, set the constants
within the range of the
frequency limits.
Note:
The clock frequency of the
on-chip oscillator depends
on the supply voltage and
the operation temperature
range.
Be careful that variable
frequencies and obtain
the sufficient margin.
Note:
X
IN
X
OUT
External oscillation
circuit
V
C
C
V
SS
O
p
e
n
M37542
X
I
N
X
O
U
T
C
R
M
3
7
5
4
2
X
IN
C
O
U
T
C
I
N
X
OUT
M
3
7
5
4
2
R
d
X
I
N
X
O
U
T
M
3
7
5
4
2
O
p
e
n
R
7542 Group
Rev.3.03 Jul 11, 2008 Page 62 of 117
REJ03B0006-0303
(1) Oscillation control
• Stop mode
When the STP instruction is executed, the internal clock φ stops at
an “H” level and the XIN oscillator stops. At this time, timer 1 is set
to “0116” and prescaler 1 is set to “FF16” when the oscillation sta-
bilization time set bit after release of the STP instruction is “0”. On
the other hand, timer 1 and prescaler 1 are not set when the
above bit is “1”. Accordingly, set the wait time fit for the oscillation
stabilization time of the oscillator to be used. f(XIN)/16 is forcibly
connected to the input of prescaler 1. When an external interrupt
is accepted, oscillation is restarted but the internal clock φ remains
at “H” until timer 1 underflows. As soon as timer 1 underflows, the
internal clock φ is supplied. This is because when a ceramic oscil-
lator is used, some time is required until a start of oscillation. In
case oscillation is restarted by reset, no wait time is generated. So
apply an “L” level to the RESET pin while oscillation becomes
stable, or set the wait time by on-chip oscillator operation after
system is released from reset until the oscillation is stabled.
With the FLASH version, the internal power supply circuit is
changed to low power consumption mode for consumption current
reduction at the time of STP instruction execution.
Although an internal power supply circuit is usually changed to the
normal operation mode at the time of the return from an STP in-
struction, since a certain time is required to start the power supply
to FLASH and operation of FLASH to be enabled, set wait time
100 µs or more with the FLASH version by the oscillation stabiliza-
tion time set function after release of the STP instruction which
used the timer 1.
• Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock re-
starts if a reset occurs or when an interrupt is received. Since the
oscillator does not stop, normal operation can be started immedi-
ately after the clock is restarted. To ensure that interrupts will be
received to release the STP or WIT state, interrupt enable bits
must be set to “1” before the STP or WIT instruction is executed.
■ Notes on Clock Generating Circuit
For use with the oscillation stabilization set bit after release of the
STP instruction set to “1”, set values in timer 1 and prescaler 1 af-
ter fully appreciating the oscillation stabilization time of the
oscillator to be used.
• Switch of ceramic and RC oscillations
After releasing reset the operation starts by starting an on-chip os-
cillator. Then, a ceramic oscillation or an RC oscillation is selected
by setting bit 5 of the CPU mode register.
• Double-speed mode
When a ceramic oscillation is selected, a double-speed mode can
be used. Do not use it when an RC oscillation is selected.
Fig. 80 Structure of CPU mode register
O
s
c
i
l
l
a
t
i
o
n
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
(
N
o
t
e
1
)
0
:
C
e
r
a
m
i
c
o
s
c
i
l
l
a
t
i
o
n
1
:
R
C
o
s
c
i
l
l
a
t
i
o
n
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
(
C
P
U
M
:
a
d
d
r
e
s
s
0
0
3
B
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e
:
8
0
1
6
)
S
t
a
c
k
p
a
g
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
0
p
a
g
e
1
:
1
p
a
g
e
C
l
o
c
k
d
i
v
i
s
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r
a
t
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l
e
c
t
i
o
n
b
i
t
s
b
7
b
6
0
0
:
f
(φ)
=
f
(
X
I
N
)
/
2
(
H
i
g
h
-
s
p
e
e
d
m
o
d
e
)
0
1
:
f
(φ)
=
f
(
X
I
N
)
/
8
(
M
i
d
d
l
e
-
s
p
e
e
d
m
o
d
e
)
1
0
:
a
p
p
l
i
e
d
f
r
o
m
on
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
1
1
:
f
(φ)
=
f
(
X
I
N
)
(
D
o
u
b
l
e
-
s
p
e
e
d
m
o
d
e
)
(
N
o
t
e
2
)
O
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
o
s
c
i
l
l
a
t
i
o
n
c
o
n
t
r
o
l
b
i
t
0
:
O
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
o
s
c
i
l
l
a
t
i
o
n
e
n
a
b
l
e
d
1
:
O
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
o
s
c
i
l
l
a
t
i
o
n
s
t
o
p
X
IN
oscillation control bit
0 : Ceramic or RC oscillation enabled
1 : Ceramic or RC oscillation stop
P
r
o
c
e
s
s
o
r
m
o
d
e
b
i
t
s
(
N
o
t
e
1
)
b
1
b
0
0
0
S
i
n
g
l
e
-
c
h
i
p
m
o
d
e
0
1
1
0
1
1
N
o
t
a
v
a
i
l
a
b
l
e
b7 b0
2: These bit s ar e us ed only when a ceram ic oscillation is select ed.
Notes 1: The bit c an be rew r itten on ly once af ter r eleasing rese t. Aft er r ewriting
i
t
i
s
d
i
s
a
b
l
e
t
o
w
r
i
t
e
a
n
y
d
a
t
a
t
o
t
h
e
b
i
t
.
H
o
w
e
v
e
r
,
b
y
r
e
s
e
t
t
h
e
b
i
t
i
s
i
n
i
t
i
a
l
i
z
e
d
a
n
d
c
a
n
b
e
r
e
w
r
i
t
t
e
n
,
a
g
a
i
n
.
(
I
t
i
s
n
o
t
d
i
s
a
b
l
e
t
o
w
r
i
t
e
a
n
y
d
a
t
a
t
o
t
h
e
b
i
t
f
o
r
e
m
u
l
a
t
o
r
M
C
U
“
M
3
7
5
4
2
R
S
S
”
.
)
Do not use these when an RC oscillation is selected.
• CPU mode register
Bits 5, 1 and 0 of CPU mode register are used to select oscillation
mode and to control operation modes of the microcomputer. In or-
der to prevent the dead-lock by error-writing (ex. program
run-away), these bits can be rewritten only once after releasing re-
set. After rewriting it is disable to write any data to the bit. (The
emulator MCU “M37542RSS” is excluded.)
Also, when the read-modify-write instructions (SEB, CLB) are ex-
ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
•
Clock division ratio, X
IN
oscillation control, on-chip oscillator control
The state transition shown in Fig. 84 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), XIN oscillation
control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of
CPU mode register. Be careful of notes on use in Fig. 84.
• Count source (Timer 1, Timer A, Timer B, Timer X, Serial I/O,
Serial I/O2, A/D converter, Watchdog timer)
A count source of watchdog timer is affected by the clock divi-
sion selection bit of the CPU mode register.
The f(XIN) clock is supplied to the watchdog timer when select-
ing f(XIN) as the CPU clock.
The on-chip oscillator output is supplied to the watchdog timer
when selecting the on-chip oscillator output as the CPU clock.
7542 Group
Rev.3.03 Jul 11, 2008 Page 63 of 117
REJ03B0006-0303
● On-chip oscillation division ratio
At on-chip oscillator mode, division ratio of on-chip oscillator for
CPU clock is selected by setting value of on-chip oscillation divi-
sion ratio selection register. The division ratio of on-chip oscillation
for CPU clock is selected from among 1/1, 1/2, 1/8, 1/128. The op-
eration clock for the peripheral function block is not changed by
setting value of this register.
■ Notes on On-chip Oscillation Division Ratio
• When system is released from reset, ROSC/8 (on-chip oscillator
middle-speed mode) is selected for CPU clock.
• When state transition from the ceramic or RC oscillation to on-
chip oscillator, ROSC/8 (on-chip oscillator middle-speed mode)
is selected for CPU clock.
• When the MCU operates by on-chip oscillator for the main clock
without external oscillation circuit, connect XIN pin to VCC
through a resistor and leave XOUT pin open.
Set “10010x002” (x = 0 or 1) to CPUM.
Fig. 81
Structure of on-chip oscillation division ratio selection register
On-chip oscillation division ratio selection register
(RODR: address 0037
16
, initial value: 02
16
)
On-chip oscillator division ratio
b1 b0
00: On-chip oscillator double-speed mode (R
OSC
/1)
01: On-chip oscillator high-speed mode (R
OSC
/2)
10: On-chip oscillator middle-speed mode (R
OSC
/8)
11: On-chip oscillator low-speed mode (R
OSC
/128)
Not used (returns “0” when read)
b7 b0
7542 Group
Rev.3.03 Jul 11, 2008 Page 64 of 117
REJ03B0006-0303
Fig. 82 Block diagram of internal clock generating circuit (for ceramic resonator)
Fig. 83 Block diagram of internal clock generating circuit (for RC oscillation)
S
R
QS
R
Q
1/2
R
S
Q
(Note)
1/4 1/2
WIT
instruction STP instruction
Timing φ
(Internal
clock)
STP instruction
Interrupt request
Reset
Interrupt disable flag l
High-speed mode
Middle-speed mode
Prescaler 1 Timer 1
Clock division
ratio selection bits
Double-speed mode
On-chip oscillator
mode
On-chip oscillator
XOUTXIN
1/16
Clock division ratio selection bits
Middle-, high-, double-speed mode
On-chip oscillator mode
1/4
1/2 On-chip oscillator division
ratio selection bits
R
OSC
/128
R
OSC
/8
R
OSC
/2
R
OSC
/1
RESET
Although a feed-back resistor exists on-chip, an external feed-back resistor
may be needed depending on conditions.
Note:
S
R
QS
R
Q
1/2
R
S
Q
1/4 1/2
WIT
instruction STP instruction
Timing φ
(Internal clock)
STP instruction
Interru
p
t re
q
uest
Reset
Interrupt disable flag l
High-speed mode
Middle-speed mode
Prescaler 1 Timer 1
Clock division
ratio selection bits
Double-speed mode
RING
XOUT XIN
Delay
Clock division ratio selection bits
Middle-, high-, double-speed mode
On-chip
oscillator
mode
RESET
On-chip oscillator
mode
On-chip oscillator division
ratio selection bits
On-chip oscillator 1/16
1/4
1/2 ROSC/128
ROSC/8
ROSC/2
ROSC/1
7542 Group
Rev.3.03 Jul 11, 2008 Page 65 of 117
REJ03B0006-0303
Fig. 84 State transition
STP mode
f(X
IN
) oscillation: stop
On-chip oscillator: stop
WAIT mode 1 WAIT mode 2 WAIT mode 3
WAIT mode 3’
Operation clock source: On-chip oscillator (Note 2)Operation clock source: f(X
IN
) (Note 1)
Notes on switch of clock
(1) In operation clock = f(X
IN
), the following can be selected for the CPU clock division ratio.
f(X
IN
)/2 (high-speed mode)
f(X
IN
)/8 (middle-speed mode)
f(X
IN
) (double-speed mode, only at a ceramic oscillation)
(2) In operation clock = On-chip oscillator, the following can be selected for the CPU clock division ratio.
R
OSC
/1 (On-chip oscillator double-speed mode)
R
OSC
/2 (On-chip oscillator high-speed mode)
R
OSC
/8 (On-chip oscillator middle-speed mode)
R
OSC
/128 (On-chip oscillator low-speed mode)
(3) After system is released from reset, and state transition of state 2 → state 3 and state transition of state 2’ → state 3’,
ROSC/8 (On-chip oscillator middle-speed mode) is selected for CPU clock.
(4) Executing the state transition state 3 to 2 or state 3 to 3’ after stabilizing X
IN
oscillation.
(5) When the state 2 → state 3 → state 4 is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
1. CPUM
76
= 10
2
(state 2 → state 3)
2. NOP instruction
Transition from Double-speed mode: NOP ✕ 3
Transition from High-speed mode: NOP ✕ 1
Transition from Middle-speed mode: NOP ✕ 0
3. CPU
4
= 1
2
(state 3 → state 4)
(6) When the state 3 → state 2 → state 1 is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
1. CPUM
76
= 00
2
or 01
2
or 11
2
(state 3 → state 2)
2. NOP instruction
Transition from On-chip oscillator double-speed mode: NOP ✕ 4
Transition from On-chip oscillator high-speed mode: NOP ✕ 2
Transition from On-chip oscillator middle-speed mode: NOP ✕ 0
Transition from On-chip oscillator low-speed mode: NOP ✕ 0
3. CPUM
3
= 1
2
(state 2 → state 1)
WAIT mode 4
State 4
RESET state
f(X
IN
) oscillation: enabled
On-chip oscillator: enabled
State 3
State 3’
WAIT mode 2’
State 2’
State 2State 1
Interrupt STP
instruction
Interrupt WIT
instruction Interrupt
CPUM
3
=0
2
CPUM
3
=1
2
CPUM
76
=10
2
(Note 3)
CPUM
76
=00
2
01
2
11
2
(Note 4)
CPUM
76
=10
2
(Note 3)
CPUM
76
=00
2
01
2
11
2
MISRG
1
=1
2
MISRG
1
=0
2
MISRG
1
=1
2
(Note 4)MISRG
1
=0
2
Reset
released
(Note 3)
CPUM
4
=0
2
CPUM
4
=1
2
Interrupt
WIT
instruction
WIT
instruction Interrupt
WIT
instruction
Interrupt WIT
instruction Interrupt WIT
instruction
STP
instruction STP
instruction
STP
instruction
Interrupt
Interrupt
Interrupt
f(X
IN
) oscillation: enabled
On-chip oscillator: stop f(X
IN
) oscillation: enabled
On-chip oscillator: enabled f(X
IN
) oscillation: enabled
On-chip oscillator: enabled
f(X
IN
) oscillation: enabled
On-chip oscillator: enabled f(X
IN
) oscillation: enabled
On-chip oscillator: enabled
Oscillation stop detection circuit valid
f(X
IN
) oscillation: stop
On-chip oscillator: enabled
7542 Group
Rev.3.03 Jul 11, 2008 Page 66 of 117
REJ03B0006-0303
Fig. 85 Structure of MISRG
● Oscillation stop detection circuit
The oscillation stop detection circuit is used to detect an oscilla-
tion stop when a ceramic resonator or oscillation circuit stops due
to disconnection. To use the oscillation stop detection circuit, set
the on-chip oscillator to start operating.
The oscillation stop detection circuit is enabled by setting the Ce-
ramic or RC oscillation stop detection function active bit to 1.
While this circuit is enabled, the operating status of the Ceramic or
RC oscillation circuit is monitored using the on-chip oscillator. If an
oscillation stop is detected, the oscillation stop detection status bit
is set to 1. If the oscillation stop detection reset enable bit is also
set to 1, an internal reset is triggered at oscillation stop detection.
The Ceramic or RC oscillation stop detection function active bit
and the oscillation stop detection status bit are not initialized if an
oscillation stop detection reset is triggered and these bits retain
their value of 1. Since these bits are initialized to 0 by an external
reset, an oscillation stop detection reset can be determined by
checking the oscillation stop status bit.
The oscillation stop detection status bit is set to 0 by writing 0 to
the Ceramic or RC oscillation stop detection function active bit.
To enable the oscillation detection circuit, first write 0 to the Ce-
ramic or RC oscillation stop detection function active bit and set
the oscillation stop detection status bit to 0. Then set the Ceramic
or RC oscillation stop detection function active bit to 1.
The Ceramic oscillation, RC oscillation, and external clock input
are set as the clocks for oscillation stop detection. Refer to the
electrical characteristics for the frequencies for oscillation stop de-
tection.
■ Notes on Oscillation Stop Detection Circuit
(1) Do not execute the transition to “state 2’a” shown in Figure 86
State transition of oscillation stop detection circuit. In this state,
no reset is triggered and the MCU is stopped even when the
XIN oscillation is stopped.
(2) After an oscillation stop detection reset, if this reset is enabled
while bits Ceramic or RC oscillation stop detection function ac-
tive and oscillation stop detection status are retained, a reset
is triggered again.
(3) The oscillation stop detection status bit is initialized under the
following conditions:
• External reset, power-on reset, low-voltage detection reset,
watchdog timer reset, and reset by the STP instruction func-
tion.
• Write 0 to the Ceramic or RC oscillation stop detection func-
tion active Bit.
(4) While the oscillation stop detection function is in active, the os-
cillation stop detection status bit may set to 1 when the
watchdog timer underflow.
When an oscillation stop detection reset is triggered, reconfirm
that oscillation is stopped.
(5) The oscillation stop detection circuit is not included in the emu-
lator MCU “M37542RSS”.
MISRG(address 003816, initial value: 0016)
b7 b0
Oscillation stabilization time set bit after
release of the STP instruction
0: Set “0116” in timer1, and “FF16”
in prescaler 1 automatically
1: Not set automatically
Reserved bits
(
D
o
n
ot
wri
te
“1”
to
t
h
ese
b
i
ts)
Not used (return “0” when read)
Oscillation stop detection status bit
0: Oscillation stop not detected
1: Oscillation stop detected
Oscillation stop reset bit
0: Oscillation stop reset disabled
1: Oscillation stop reset enabled
Ceramic or RC oscillation stop
detection function active bit
0: Detection function inactive
1: Detection function active
7542 Group
Rev.3.03 Jul 11, 2008 Page 67 of 117
REJ03B0006-0303
Fig. 86 State transition 2
Operation clock source: On-chip oscillator (Note 2)Operation clock source: f(XIN) (Note 1)
Notes on switch of clock
(1) In operation clock = f(XIN), the following can be selected for the CPU clock division ratio.
f(XIN)/2 (High-speed mode)
f(XIN)/8 (Middle-speed mode)
f(XIN) (Double-speed mode, only at a ceramic oscillation)
(2) In operation clock = On-chip oscillator, the following can be selected for the CPU clock division ratio.
ROSC/1 (On-chip oscillator double-speed mode)
ROSC/2 (On-chip oscillator high-speed mode)
ROSC/8 (On-chip oscillator middle-speed mode)
ROSC/128 (On-chip oscillator low-speed mode)
(3) Executing the state transition state 3 to 2 or state 3 to 3’ after stabilizing XIN oscillation.
(4) After system is released from reset, and state transition of state 2 → state 3 and state transition of state 2’ → state 3’,
R
OSC
/8 (On-chip oscillator middle-speed mode) is selected for CPU clock.
(5) MCU cannot be returned by On-chip oscillator and its operation is stopped since internal reset does not occur at oscillation stop detected.
Accordingly, do not execute the transition to state 2'a.
(6) STP instruction cannot be used when oscillation stop detection circuit is in active.
RESET state 2
f(X
IN) oscillation: enabled
On-chip oscillator: enabled
RESET state 1
f(XIN) oscillation: enabled
On-chip oscillator: enabled
Oscillation stop detection circuit is in active. (Note 6)
Applied “L” to RESET pin
(external reset)
MISRG
3
is cleared to “0”.
MISRG
2
=1
2
MISRG
2
=0
2
MISRG
2
=1
2
MISRG
2
=0
2
MISRG
1
=1
2
MISRG
1
=0
2
(MISRG
3
is cleared to “0”.) MISRG
1
=1
2
(Note 3)MISRG
1
=0
2
(MISRG
3
is cleared to “0”.)
State 3
State 2
f(XIN) oscillation: enabled
On-chip oscillator: enabled f(XIN) oscillation: enabled
On-chip oscillator: enabled
State 3’
State 2’
f(XIN) oscillation: enabled
On-chip oscillator: enabled
State 2’a (Note 5)
Oscillation stop reset disabled
When oscillation stop is detected;
MISRG3 is set to “1”.
Internal RESET does not occur.
Prohibitive state
MUC will be locked when Ceramic
or RC oscillation is stopped.
State 3’a
Oscillation stop reset disabled
When oscillation stop is detected;
MISRG3 is set to “1”.
Internal RESET does not occur.
Oscillation stop reset enabled
When oscillation stop is detected;
MISRG3 is set to “1”.
Internal RESET occurs.
Oscillation stop reset enabled
When oscillation stop is detected;
MISRG3 is set to “1”.
Internal RESET occurs.
State 3’c
Release from internal reset
MISRG3 is set to “1”.
Oscillation status can be
confirmed by reading MISRG3.
f(XIN) oscillation: enabled
On-chip oscillator: enabled
State 3’b
State 2’b
CPUM
76
=10
2
(Note 4)
CPUM
76
=00
2
01
2
11
2
(Note 3)
CPUM
76
=10
2
CPUM
76
=00
2
01
2
11
2
CPUM
76
=10
2
(Note 4)
CPUM
76
=00
2
01
2
11
2
Reset
released
(Note 4)
Reset
released
(Note 4)
Oscillation stop is detected
(internal reset)
7542 Group
Rev.3.03 Jul 11, 2008 Page 68 of 117
REJ03B0006-0303
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after reset are
undefined except for the interrupt disable flag I which is “1”. After
reset, initialize flags which affect program execution. In particular,
it is essential to initialize the T flag and the D flag because of their
effect on calculations.
Interrupts
The contents of the interrupt request bit do not change even if the
BBC or BBS instruction is executed immediately after they are
changed by program because this instruction is executed for the
previous contents. For executing the instruction for the changed
contents, execute one instruction before executing the BBC or
BBS instruction.
Decimal Calculations
• For calculations in decimal notation, set the decimal mode flag
D to “1”, then execute the ADC instruction or SBC instruction. In
this case, execute SEC instruction, CLC instruction or CLD in-
struction after executing one instruction before the ADC instruction
or SBC instruction.
• In the decimal mode, the values of the N (negative), V (overflow)
and Z (zero) flags are invalid.
Ports
• The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory opera-
tion instruction when the T flag is “1”, addressing mode using
direction register values as qualifiers, and bit test instructions such
as BBC and BBS.
It is also impossible to use bit operation instructions such as CLB
and SEB and read/modify/write instructions of direction registers
for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA in-
struction, etc.
A/D Conversion
Do not execute the STP instruction during A/D conversion.
Instruction Execution Timing
The instruction execution time can be obtained by multiplying the
frequency of the internal clock φ by the number of cycles men-
tioned in the machine-language instruction table.
The frequency of the internal clock φ is the same as that of the XIN
in double-speed mode, twice the XIN cycle in high-speed mode
and 8 times the XIN cycle in middle-speed mode.
CPU Mode Register
The oscillation mode selection bit and processor mode bits can be
rewritten only once after releasing reset. However, after rewriting it
is disable to write any value to the bit. (Emulator MCU is ex-
cluded.)
When a ceramic oscillation is selected, a double-speed mode of
the clock division ratio selection bits can be used. Do not use it
when an RC oscillation is selected.
State transition
Do not stop the clock selected as the operation clock because of
setting of CM3, 4.
NOTES ON HARDWARE
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suit-
able for high frequencies as bypass capacitor between power
source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the
capacitor to as close as possible. For bypass capacitor which
should not be located too far from the pins to be connected, a ce-
ramic capacitor of 0.01 µF to 0.1 µF is recommended.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
1.Mask ROM Order Confirmation Form *
2.Mark Specification Form *
For the mask ROM confirmation and the mark specifications,
refer to the "Renesas Technology Corp." Homepage
(http://www.renesas.com/en/rom).
7542 Group
Rev.3.03 Jul 11, 2008 Page 69 of 117
REJ03B0006-0303
NOTES ON USE
Countermeasures against noise
1. Shortest wiring length
(1) Package
Select the smallest possible package to make the total wiring
length short.
<Reason>
The wiring length depends on a microcomputer package. Use of a
small package, for example QFP and not DIP, makes the total wir-
ing length short to reduce influence of noise.
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as
short as possible.
• Make the length of wiring (within 20 mm) across the grounding
lead of a capacitor which is connected to an oscillator and the
VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS pat-
terns.
<Reason>
If noise enters clock I/O pins, clock waveforms may be deformed.
This may cause a program failure or program runaway. Also, if a
potential difference is caused by the noise between the VSS level
of a microcomputer and the VSS level of an oscillator, the correct
clock will not be input in the microcomputer.
(2) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as
short as possible. Especially, connect a capacitor across the
RESET pin and the VSS pin with the shortest possible wiring
(within 20mm).
<Reason>
The width of a pulse input into the RESET pin is determined by the
timing necessary conditions. If noise having a shorter pulse width
than the standard is input to the RESET pin, the reset is released
before the internal state of the microcomputer is completely initial-
ized. This may cause a program runaway.
Fig. 89 Wiring for clock I/O pins
Fig. 87 Selection of packages
DIP
SDIP
SOP
QFP
Fig. 88 Wiring for the RESET pin
RESET
Reset
circuit
Noise
VSSVSS
Reset
circuit
VSS
RESET
VSS
N.G.
O.K.
Noise
XIN
XOUT
VSS
XIN
XOUT
VSS
N.G. O.K.
(4) Wiring to CNVss pin
Connect the CNVss pin to the Vss pin with the shortest possible
wiring.
In the normal microcomputer mode, disconnect a wiring of a serial
rewrite circuit, which is for the flash memory version, from the
MCU by a jumper switch.
<Reason>
The processor mode of a microcomputer is influenced by a poten-
tial at the CNVss pin. If a potential difference is caused by the
noise between pins CNVss and Vss, the processor mode may be-
come unstable. This may cause a microcomputer malfunction or a
program runaway.
A wiring of a serial rewrite circuit may function as an antenna
which feeds noise into the microcomputer.
Fig. 90 Wiring for CNVss pin
N
o
i
s
e
CNV
SS
V
SS
N
.
G
.
C
N
V
S
S
V
S
S
O.K.
C
N
V
S
S
V
S
S
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7542 Group
Rev.3.03 Jul 11, 2008 Page 70 of 117
REJ03B0006-0303
Fig. 91 Bypass capacitor across the VSS line and the VCC line
2. Connection of bypass capacitor across VSS line and VCC line
Connect an approximately 0.1
µ
F bypass capacitor across the VSS
line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin and the VCC pin
at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin
with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS
line and VCC line.
• Connect the power source wiring via a bypass capacitor to the
VSS pin and the VCC pin.
VSS
VCC






VSS
VCC












N.G. O.K.
3. Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog
signal line which is connected to an analog input pin in series.
Besides, connect the resistor to the microcomputer as close as
possible.
• Connect an approximately 1000 pF capacitor across the Vss pin
and the analog input pin. Besides, connect the capacitor to the
Vss pin as close as possible. Also, connect the capacitor across
the analog input pin and the Vss pin at equal length.
<Reason>
Signals which is input in an analog input pin (such as an A/D con-
verter/comparator input pin) are usually output signals from
sensor. The sensor which detects a change of event is installed far
from the printed circuit board with a microcomputer, the wiring to
an analog input pin is longer necessarily. This long wiring func-
tions as an antenna which feeds noise into the microcomputer,
which causes noise to an analog input pin.
Fig. 92 Analog signal line and a resistor and a capacitor
Analog
input pin
VSS
Noise
Thermistor
Microcomputer
N.G. O.K.
(Note)
Note : The resistor is used for dividing
resistance with a thermistor.
• The analog input pin is connected to the capacitor of a voltage
comparator. Accordingly, sufficient accuracy may not be ob-
tained by the charge/discharge current at the time of A/D
conversion when the analog signal source of high-impedance is
connected to an analog input pin. In order to obtain the A/D con-
version result stabilized more, please lower the impedance of an
analog signal source, or add the smoothing capacitor to an ana-
log input pin.
7542 Group
Rev.3.03 Jul 11, 2008 Page 71 of 117
REJ03B0006-0303
4. Oscillator concerns
Take care to prevent an oscillator that generates clocks for a mi-
crocomputer operation from being affected by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as
possible from signal lines where a current larger than the toler-
ance of current value flows.
<Reason>
In the system using a microcomputer, there are signal lines for
controlling motors, LEDs, and thermal heads or others. When a
large current flows through those signal lines, strong noise occurs
because of mutual inductance.
(2) Installing oscillator away from signal lines where potential lev-
els change frequently
Install an oscillator and a connecting pattern of an oscillator away
from signal lines where potential levels change frequently. Also, do
not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
<Reason>
Signal lines where potential levels change frequently (such as the
CNTR pin signal line) may affect other lines at signal rising edge
or falling edge. If such lines cross over a clock line, clock wave-
forms may be deformed, which causes a microcomputer failure or
a program runaway.
➀ Keeping oscillator away from large current signal lines
➁ Installing oscillator away from signal lines where potential lev-
els change frequently
Fig. 93 Wiring for a large current signal line/Writing of signal
lines where potential levels change frequently
XI
N
XO
U
T
VS
S
M
Microcomputer
Mutual inductance
Large
current
GND
XIN
XOUT
VS
S
CNTR
D
o
n
o
t
c
r
o
s
s
N.G.
(3) Oscillator protection using Vss pattern
As for a two-sided printed circuit board, print a Vss pattern on the
underside (soldering side) of the position (on the component side)
where an oscillator is mounted.
Connect the Vss pattern to the microcomputer Vss pin with the
shortest possible wiring. Besides, separate this Vss pattern from
other Vss patterns.
Fig. 94 Vss pattern on the underside of an oscillator







XIN
XOUT
VSS
An example of VSS patterns on the
underside of a printed circuit board
Oscillator wiring
pattern example
Separate the VSS line for oscillation from other VSS lines
7542 Group
Rev.3.03 Jul 11, 2008 Page 72 of 117
REJ03B0006-0303
5. Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program for
checking whether input levels are equal or not.
• As for an output port, since the output data may reverse because
of noise, rewrite data to its port latch at fixed periods.
• Rewrite data to direction registers and pull-up control registers at
fixed periods.
Fig. 95 Setup for I/O ports
6. Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can
be detected by a software watchdog timer and the microcomputer
can be reset to normal operation. This is equal to or more effective
than program runaway detection by a hardware watchdog timer.
The following shows an example of a watchdog timer provided by
software.
In the following example, to reset a microcomputer to normal op-
eration, the main routine detects errors of the interrupt processing
routine and the interrupt processing routine detects errors of the
main routine.
This example assumes that interrupt processing is repeated mul-
tiple times in a single main routine processing.
Fig. 96 Watchdog timer by software
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer
(SWDT) and writes the initial value N in the SWDT once at each
execution of the main routine. The initial value N should satisfy
the following condition:
N+1 ≥ (Counts of interrupt processing executed in each main
routine)
As the main routine execution cycle may change because of an
interrupt processing or others, the initial value N should have a
margin.
• Watches the operation of the interrupt processing routine by
comparing the SWDT contents with counts of interrupt process-
ing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and de-
termines to branch to the program initialization routine for
recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt process-
ing.
• Determines that the main routine operates normally when the
SWDT contents are reset to the initial value N at almost fixed
cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to
branch to the program initialization routine for recovery process-
ing in the following case:
If the SWDT contents are not initialized to the initial value N but
continued to decrement and if they reach 0 or less.
Main routine
(SWDT)← N
CLI
Main processing
(SWDT)
Interrupt processing
routine errors
N
Interrupt processing routine
(SWDT) ← (SWDT)—1
Interrupt processing
(SWDT)
Main routine
errors
>0
≤0RTI
Return
=N?
≤0?
≠N
Direction register
Port latch
Data bus
I/O port
pins
Noise
Noise
N.G.
O.K.
7542 Group
Rev.3.03 Jul 11, 2008 Page 73 of 117
REJ03B0006-0303
Table 9 Summary of 7542 group’s flash memory version
FLASH MEMORY MODE
The 7542 group’s flash memory version has the flash memory that
can be rewritten with a single power source.
For this flash memory, three flash memory modes are available in
which to read, program, and erase: the parallel I/O and standard
serial I/O modes in which the flash memory can be manipulated
using a programmer and the CPU rewrite mode in which the flash
memory can be manipulated by the Central Processing Unit
(CPU).
● Summary
Table 9 lists the summary of the 7542 Group (flash memory ver-
sion).
This flash memory version has some blocks on the flash memory
as shown in Figure 97 and each block can be erased.
In addition to the ordinary User ROM area to store the MCU op-
eration control program, the flash memory has a Boot ROM area
that is used to store a program to control rewriting in CPU rewrite
and standard serial I/O modes. This Boot ROM area has had a
standard serial I/O mode control program stored in it when
shipped from the factory. However, the user can write a rewrite
control program in this area that suits the user ’s application sys-
tem. This Boot ROM area can be rewritten in only parallel I/O
mode.
Item
Power source voltage (Vcc)
Temperature at program/erase
Program/Erase VPP voltage (VPP)
Flash memory mode
Erase block division User ROM area/Data ROM area
Boot ROM area (Note)
Program method
Erase method
Program/Erase control method
Number of commands
Number of program/Erase times
ROM code protection
Specifications
VCC = 2.7 to 5.5 V
Ta = 0 to 60 °C
VCC = 2.7 to 5.5 V
3 modes; Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode
Refer to Fig. 97.
Not divided (4K bytes)
In units of bytes
Block erase
Program/Erase control by software command
5 commands
100
Available in parallel I/O mode and standard serial I/O mode
Note: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory.
This Boot ROM area can be erased and written in only parallel I/O mode.
7542 Group
Rev.3.03 Jul 11, 2008 Page 74 of 117
REJ03B0006-0303
Fig. 97 Block diagram of built-in flash memory
● Boot Mode
The control program for CPU rewrite mode must be written into
the User ROM or Boot ROM area in parallel I/O mode beforehand.
(If the control program is written into the Boot ROM area, the stan-
dard serial I/O mode becomes unusable.)
See Figure 97 for details about the Boot ROM area.
Normal microcomputer mode is entered when the microcomputer
is reset with pulling CNVSS pin low. In this case, the CPU starts
operating using the control program in the User ROM area.
When the microcomputer is reset and the CNVSS pin high after
pulling the P37(RP) pin low, P32(CE) pin high, P06/SCLK pin low
and P05/TxD2 pin high, the CPU starts operating (start address of
program is stored into addresses FFFC16 and FFFD16) using the
control program in the Boot ROM area. This mode is called the
“Boot mode”. Also, User ROM area can be rewritten using the con-
trol program in the Boot ROM area.
● Block Address
Block addresses refer to the maximum address of each block.
These addresses are used in the block erase command.
Notes 1: The boot ROM area can be rewritten in a parallel I/O mode. (Access to except boot ROM area is disablrd.)
2: To specify a block, use the maximum address in the block.
3: The mask ROM version has the reserved ROM area. Note the difference of the area.
SFR area
SFR area
Internal RAM area
(1K bytes)
Internal flash memory
area
(4K bytes) (Note 3)
Internal flash memory
area
(32K bytes) (Note 3)
0000
16
0040
16
043F
16
0FE0
16
RAM
8000
16
0FFF
16
FFFF
16
7000
16
User ROM area
7000
16
7800
16
8000
16
E000
16
C000
16
FFFF
16
F000
16
FFFF
16
32K bytes ROM Product
Data block B :
2K bytes
Boot ROM area
4K bytes
Data block A :
2K bytes
block 2 : 16K bytes
block 1 : 8K bytes
block 0 : 8K bytes
SFR area
SFR area
Internal RAM area
(1K bytes)
Internal flash memory
area
(4K bytes) (Note 3)
Internal flash memory
area
(16K bytes) (Note 3)
0000
16
0040
16
043F
16
0FE0
16
RAM
C000
16
0FFF
16
7FFF
16
FFFF
16
7000
16
SFR area
7000
16
7800
16
7FFF
16
E000
16
C000
16
FFFF
16
16K bytes ROM Product
Data block B :
2K bytes
Data block A :
2K bytes
block 1 : 8K bytes
block 0 : 8K bytes
● CPU Rewrite Mode
In CPU rewrite mode, the internal flash memory can be operated
on (read, program, or erase) under control of the Central Process-
ing Unit (CPU).
In CPU rewrite mode, only the User ROM area shown in Figure 97
can be rewritten; the Boot ROM area cannot be rewritten. Make
sure the program and block erase commands are issued for only
the User ROM area and each block area.
The control program for CPU rewrite mode can be stored in either
User ROM or Boot ROM area. In the CPU rewrite mode, because
the flash memory cannot be read from the CPU, the rewrite con-
trol program must be transferred to internal RAM area before it
can be executed.
• Outline Performance
CPU rewrite mode is usable in the single-chip or Boot mode. The
only User ROM area can be rewritten.
In CPU rewrite mode, the CPU erases, programs and reads the in-
ternal flash memory as instructed by software commands. This
rewrite control program must be transferred to internal RAM area
before it can be executed.
The MCU enters CPU rewrite mode by setting “1” to the CPU re-
write mode select bit (bit 1 of address 0FE016). Then, software
commands can be accepted.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or
in error can be verified by reading the status register.
7542 Group
Rev.3.03 Jul 11, 2008 Page 75 of 117
REJ03B0006-0303
Fig. 98 Structure of flash memory control register 0
b7 b0 Flash memory control register 0
(FMCR0: address : 0FE0
16
: initial value: 01
16
)
RY/BY status flag
0 : Busy (being written or erased)
1 : Ready
CPU rewrite mode select bit (Note 1)
0 : CPU rewrite mode invalid
1 : CPU rewrite mode valid
8KB user block E/W mode enable bit (Note 1, 2)
0 : E/W disabled
1 : E/W enabled
Flash memory reset bit (Note 3)
0 : Normal operation
1 : reset
Not used (do not write “1” to this bit.)
User ROM area select bit (Note 4)
0 : Boot ROM area is accessed
1 : User ROM area is accessed
Program status flag
0: Pass
1: Error
Erase status flag
0: Pass
1: Error
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
2: This bit can be written only when CPU rewrite mode select bit is “1”.
3: Effective only when the CPU rewrite mode select bit = “1”. Fix this
bit to “0” when the CPU rewrite mode select bit is “0”.
4: Write to this bit in program on RAM
[Flash memory control registers (FMCR0 to FMCR2)]
0FE016 to 0FE216
Figure 98 shows the flash memory control register 0.
Bit 0 of the flash memory control register 0 is the RY/BY status
flag used exclusively to read the operating status of the flash
memory. During programming and erase operations, it is “0”
(busy). Otherwise, it is “1” (ready).
Bit 1 of the flash memory control register 0 is the CPU rewrite
mode select bit. When this bit is set to “1”, the MCU enters CPU
rewrite mode. And then, software commands can be accepted. In
CPU rewrite mode, the CPU becomes unable to access the inter-
nal flash memory directly. Therefore, use the control program in
the internal RAM for write to bit 1. To set this bit 1 to “1”, it is nec-
essary to write “0” and then write “1” in succession to bit 1. The bit
can be set to “0” by only writing “0”.
Bit 2 of the flash memory control register 0 is the 8KB user block
E/W mode enable bit. By setting this bit in combination with bit 4
(all user block E/W enable bit) of flash memory control register 2
(address 0FE016), Erase/Write to user block in CPU rewrite mode
is disabled.
Bit 3 of the flash memory control register 0 is the flash memory re-
set bit used to reset the control circuit of internal flash memory.
This bit is used when exiting CPU rewrite mode and when flash
memory access has failed. When the CPU rewrite mode select bit
is “1”, setting “1” for this bit resets the control circuit. To release
the reset, it is necessary to set this bit to “0”.
Bit 5 of the flash memory control register 0 is the User ROM area
select bit and is valid only in the boot mode. Setting this bit to “1”
in the boot mode switches an accessible area from the boot ROM
area to the user ROM area. To use the CPU rewrite mode in the
boot mode, set this bit to “1”. Note that when the microcomputer is
booted up in the user ROM area, only the user ROM area is ac-
cessible and bit 5 is invalid; on the other hand, when the
microcomputer is in the boot mode, bit 5 is valid independent of
the CPU rewrite mode. To rewrite bit 5, execute the user-original
reprogramming control software transferred to the internal RAM in
advance.
Bit 6 of the flash memory control register 0 is the program status
flag. This bit is set to “1” when writing to flash memory is failed.
When program error occurs, the block cannot be used.
Bit 7 of the flash memory control register 0 is the erase status flag.
This bit is set to “1” when erasing flash memory is failed. When
erase error occurs, the block cannot be used.
7542 Group
Rev.3.03 Jul 11, 2008 Page 76 of 117
REJ03B0006-0303
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
2: Effective only when the suspend enable bit = “1”.
b7 b0
Erase Suspend enble bit (Notes 1)
0 : Suspend invalid
1 : Suspend valid
Erase Suspend request bit (Notes 2)
0 : Erase restart
1 : Suspend request
Erase Suspend flag
0 : Erase active
1 : Erase inactive (Erase Suspend mode)
Not used (do not write “1” to this bit.)
Not used (do not write “1” to this bit.)
Flash memory control register 1
(FMCR1: address : 0FE116: initial value: 4016)
Figure 99 shows the flash memory control register 1.
Bit 0 of the flash memory control register 1 is the Erase suspend
enable bit. By setting this bit to “1”, the erase suspend mode to
suspend erase processing temporarily when block erase com-
mand is executed can be used. In order to set this bit to “1”,
writing “0” and “1” in succession to bit 0. In order to set this bit to
“0”, write “0” only to bit 0.
Bit 1 of the flash memory control register 1 is the erase suspend
request bit. By setting this bit to “1” when erase suspend enable
bit is “1”, the erase processing is suspended.
Bit 6 of the flash memory control register 1 is the erase suspend
flag. This bit is cleared to “0” at the flash erasing.
Figure 100 shows the flash memory control register 2.
Bit 0 of the flash memory control register 1 is the all user block E/
W enable bit. By setting this bit to “0”, Erase/Write to all user block
(blocks 0, 1, 2) is disabled. As a result, error writing in program to
write only to data block can be prevented. Fig. 99 Structure of flash memory control register 1
Fig. 100 Structure of flash memory control register 2
Table 10 Erase/Write disable setting
CPU rewrite
mode select bit
0
0
0
0
1
1
1
1
All user block
E/W enable bit
0
0
1
1
0
0
1
1
8KB user block
E/W enable bit
0
1
0
1
0
1
0
1
Block 0: 8KB
Block 1: 8KB
E/W disabled (RESET)
E/W disabled
E/W disabled
E/W disabled
E/W disabled
E/W disabled
E/W disabled
E/W enabled
Block 2: 16KB
E/W disabled (RESET)
E/W disabled
E/W disabled
E/W disabled
E/W disabled
E/W disabled
E/W enabled
E/W enabled
Data block A: 2KB
Data block B: 2KB
E/W disabled (RESET)
E/W disabled
E/W disabled
E/W disabled
E/W enabled
E/W enabled
E/W enabled
E/W enabled
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
2: Effective only when the CPU rewrite mode select bit = “1”.
b7 b0
Reserved bit (returns “1” when read)
Reserved bits (do not write “1” to this bit.)
All user block E/W enable bit (Notes 1, 2)
0 : E/W disabled
1 : E/W enabled
Not used (do not write “1” to this bit.)
Flash memory control register 2
(FMCR2: address : 0FE2
16
: initial value: 01
16
)
7542 Group
Rev.3.03 Jul 11, 2008 Page 77 of 117
REJ03B0006-0303
■ Notes on CPU Rewrite Mode
Take the notes described below when rewriting the flash memory
in CPU rewrite mode.
●Operation speed
During CPU rewrite mode, set the system clock φ to 4.0 MHz or
less using the clock division ratio selection bits (bits 6 and 7 of ad-
dress 003B16).
●Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode.
●Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode because
they refer to the internal data of the flash memory.
●Watchdog timer
If the watchdog timer has been already activated, internal reset
due to an underflow will not occur because the watchdog timer is
surely cleared during program or erase.
●Reset
Reset is always valid. The MCU is activated using the boot mode
at release of reset in the condition of CNVss = “H”, so that the pro-
gram will begin at the address which is stored in addresses
FFFC16 and FFFD16 of the boot ROM area.
Fig. 101 CPU rewrite mode set/release flowchart
End
Start
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession ) (Note 3)
Single-chip mode or Boot mode
Set CPU mo de register (Note 1)
Using software command executes erase,
program, or other operation
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R
A
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s1:
S
e
t
t
h
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m
a
i
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c
l
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r
a
t
i
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e
l
e
c
t
i
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n
b
i
t
s
o
f
Write “0” to CPU rewrite mode select bit
S
e
t
C
P
U
r
e
w
r
i
t
e
m
o
d
e
s
e
l
e
c
t
b
i
t
t
o
“
1
”
(
b
y
w
r
i
t
i
n
g
“
0
”
a
n
d
t
h
e
n
“
1
”
i
n
s
u
c
c
e
s
s
i
o
n
)
CPU mode register (bits 6, 7 of address 003B16).
2: As for setting of these bits, refer to Table 10.
3: Before exiting the CPU rewrite mode after completing erase or program operation,
S
e
t
a
l
l
u
s
e
r
b
l
o
c
k
E
/
W
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a
b
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b
i
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t
8
K
B
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b
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k
E
/
W
m
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n
a
b
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b
i
t
(f
o
r
s
e
t
t
i
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t
o
“
1
”,
b
y
w
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t
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n
g
“
0
”
a
n
d
t
h
e
n
“
1
”
i
n
s
u
c
c
e
s
s
i
o
n
)
(Note 2)
S
e
t
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l
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r
b
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c
k
E
/
W
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n
a
b
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b
i
t
t
o
“
0
”
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e
t
8
K
B
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/
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m
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n
a
b
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b
i
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t
o
“
0
”
a
l
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o
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x
e
c
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r
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a
d
a
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y
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r
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e
s
e
t
t
h
e
f
l
a
s
h
m
e
m
o
r
y
.
Figure 101 shows a flowchart for setting/releasing CPU rewrite mode.
7542 Group
Rev.3.03 Jul 11, 2008 Page 78 of 117
REJ03B0006-0303
● Software Commands
Table 11 lists the software commands.
After setting the CPU rewrite mode select bit to “1”, execute a soft-
ware command to specify an erase or program operation.
Each software command is explained below.
• Read Array Command (FF16)
The read array mode is entered by writing the command code
“FF16” in the first bus cycle. When an address to be read is input
in one of the bus cycles that follow, the contents of the specified
address are read out at the data bus (D0 to D7).
The read array mode is retained until another command is written.
• Read Status Register Command (7016)
When the command code “7016” is written in the first bus cycle,
the contents of the status register are read out at the data bus (D0
to D7) by a read in the second bus cycle.
The status register is explained in the next section.
• Clear Status Register Command (5016)
This command is used to clear the bits SR4 and SR5 of the status
register after they have been set. These bits indicate that opera-
tion has ended in an error. To use this command, write the
command code “5016” in the first bus cycle.
• Program Command (4016)
Program operation starts when the command code “4016” is writ-
ten in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, program operation (data program-
ming and verification) will start.
Whether the write operation is completed can be confirmed by
_____
read status register or the RY/BY status flag. When the program
starts, the read status register mode is entered automatically and
the contents of the status register is read at the data bus (D0 to
D7). The status register bit 7 (SR7) is set to “0” at the same time
the write operation starts and is returned to “1” upon completion of
the write operation. In this case, the read status register mode re-
mains active until the read array command (FF16) is written.
Table 11 List of software commands (CPU rewrite mode)
The RY/BY status flag of the flash memory control register is “0”
during write operation and “1” when the write operation is com-
pleted as is the status register bit 7.
At program end, program results can be checked by reading the
status register.
Fig. 102 Program flowchart
S
t
a
r
t
W
r
i
t
e
“
4
0
1
6
”
R
e
a
d
s
t
a
t
u
s
r
e
g
i
s
t
e
r
P
r
o
g
r
a
m
c
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m
p
l
e
t
e
d
N
O
Y
E
S
W
r
i
t
e
a
d
d
r
e
s
s
W
r
i
t
e
d
a
t
a
SR4 = “0”? P
r
o
g
r
a
m
e
r
r
o
r
N
O
Y
E
S
S
R
7
=
“
1
”
?
o
r
R
Y
/
B
Y
=
“
1
”
?
W
r
i
t
e
Command
Read array
Read status register
Clear status register
Program
Block erase
Mode
First bus cycle Second bus cycle
Address Data
(D
0
to D
7
)Mode Address Data
(D
0
to D
7
)
Write
Write
Write
Write
Write
✕ (Note 4)
✕
✕
✕
✕
FF
16
70
16
50
16
40
16
20
16
Read
Write
Write
✕
WA (Note 2)
BA (Note 3)
SRD (Note 1)
WD (Note 2)
D0
16
SRD = Status Register Data
WA = Write Address, WD = Write Data
BA = Block Address to be erased (Input the maximum address of each block.)
✕ = ✕ denotes a given address in the user ROM area.
7542 Group
Rev.3.03 Jul 11, 2008 Page 79 of 117
REJ03B0006-0303
• Block Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “D016” and the block address in the
second bus cycle that follows, the block erase (erase and erase
verify) operation starts for the block address of the flash memory
to be specified.
Whether the block erase operation is completed can be confirmed
by read status register or the RY/BY status flag of flash memory
control register. At the same time the block erase operation starts,
the read status register mode is automatically entered, so that the
contents of the status register can be read out. The status register
bit 7 (SR7) is set to “0” at the same time the block erase operation
starts and is returned to “1” upon completion of the block erase
operation. In this case, the read status register mode remains ac-
tive until the read array command (FF16) is written.
The RY/BY status flag is “0” during block erase operation and “1”
when the block erase operation is completed as is the status reg-
ister bit 7.
After the block erase ends, erase results can be checked by read-
ing the status register. For details, refer to the section where the
status register is detailed.
Fig. 103 Erase flowchart
Write “20
16
”
“D0
16
”
Block address
Erase completed
(write read command “
FF
16
”
)
NO
YES
Start
Write
SR5 = “0” ? Erase error
YES
NO
SR7 = “1”?
or
RY/BY = “1”?
Read status register
7542 Group
Rev.3.03 Jul 11, 2008 Page 80 of 117
REJ03B0006-0303
Table 12 Definition of each bit in status register
● Status Register
The status register shows the operating status of the flash
memory and whether erase operations and programs ended suc-
cessfully or in error. It can be read in the following ways:
(1) By reading an arbitrary address from the User ROM area after
writing the read status register command (7016)
(2) By reading an arbitrary address from the User ROM area in the
period from when the program starts or erase operation starts
to when the read array command (FF16) is input.
Also, the status register can be cleared by writing the clear status
register command (5016).
After reset, the status register is set to “8016”.
Table 12 shows the status register. Each bit in this register is ex-
plained below.
•Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. This bit is set to “0” (busy) during write or erase operation
and is set to “1” when these operations ends.
After power-on, the sequencer status is set to “1” (ready).
•Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is reset to “0”.
•Program status (SR4)
The program status indicates the operating status of write opera-
tion. When a write error occurs, it is set to “1”.
The program status is reset to “0” when it is cleared.
If “1” is written for any of the SR5 and SR4 bits, the read array,
program, and block erase commands are not accepted. Before ex-
ecuting these commands, execute the clear status register
command (5016) and clear the status register.
Also, if any commands are not correct, both SR5 and SR4 are set
to “1”.
Each bit of
SRD bits
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Sequencer status
Reserved
Erase status
Program status
Reserved
Reserved
Reserved
Reserved
Status name “1”
Ready
-
Terminated in error
Terminated in error
-
-
-
-
“0”
Busy
-
Terminated normally
Terminated normally
-
-
-
-
Definition
7542 Group
Rev.3.03 Jul 11, 2008 Page 81 of 117
REJ03B0006-0303
● Full Status Check
By performing full status check, it is possible to know the execu-
tion results of erase and program operations. Figure 104 shows a
full status check flowchart and the action to be taken when each
error occurs.
Fig. 104 Full status check flowchart and remedial procedure for errors
Read status register
S
R
4
=
“
1
”
a
n
d
S
R5
=
“
1
”
?
NO
Y
E
S
SR5 = “0” ?
Y
E
S
Er
a
s
e
e
r
r
o
r
NO
SR4 = “0” ?
Y
E
S
N
O
Command
sequence error
Program error
End (block erase, program)
E
x
e
c
u
t
e
t
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e
c
l
e
a
r
s
t
a
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g
i
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r
c
o
m
m
a
n
d
(
5
0
1
6
)
t
o
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e
a
r
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s
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.
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r
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t
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d
c
o
r
r
e
c
t
l
y
.
S
h
o
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l
d
a
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r
a
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r
r
o
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c
c
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,
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r
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c
a
n
n
o
t
b
e
u
s
e
d
.
Note: When one of SR5 and SR4 is set to “1”, none of the read array, program,
and block erase commands is accepted. Execute the clear status register
command (5016) before executing these commands.
S
h
o
u
l
d
a
p
r
o
g
r
a
m
e
r
r
o
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o
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n
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t
b
e
u
s
e
d
.
7542 Group
Rev.3.03 Jul 11, 2008 Page 82 of 117
REJ03B0006-0303
● Functions To Inhibit Rewriting Flash
Memory Version
To prevent the contents of internal flash memory from being read
out or rewritten easily, this MCU incorporates a ROM code protect
function for use in parallel I/O mode and an ID code check func-
tion for use in standard serial I/O mode.
(1) ROM Code Protect Function
The ROM code protect function is the function to inhibit reading
out or modifying the contents of internal flash memory by using
the ROM code protect control address (address FFDB16) in paral-
lel I/O mode. Figure 105 shows the ROM code protect control
address (address FFDB16). (This address exists in the User ROM
area.)
If one or both of the pair of ROM code protect bits is set to “0”, the
ROM code protect is turned on, so that the contents of internal
flash memory are protected against readout and modification. The
ROM code protect is implemented in two levels. If level 2 is se-
lected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to
select both level 1 and level 2, level 2 is selected by default.
If both of the two ROM code protect reset bits are set to “00”, the
ROM code protect is turned off, so that the contents of internal
flash memory can be readout or modified. Once the ROM code
protect is turned on, the contents of the ROM code protect reset
bits cannot be modified in parallel I/O mode. Use the serial I/O or
CPU rewrite mode to rewrite the contents of the ROM code protect
reset bits.
Rewriting of only the ROM code protect control address (address
FFDB16) cannot be performed. When rewriting the ROM code pro-
tect reset bit, rewrite the whole user ROM area (block 0)
containing the ROM code protect control address.
Fig. 105 Structure of ROM code protect control address
R
O
M
c
o
d
e
p
r
o
t
e
c
t
c
o
n
t
r
o
l
a
d
d
r
e
s
s
(
a
d
d
r
e
s
s
F
F
D
B
1
6
)
R
O
M
C
P
(
F
F
1
6
w
h
e
n
s
h
i
p
p
e
d
)
Reserved bits (“1” at read/write)
ROM code protect level 2 set bits (ROMCP2) (Notes 1, 2)
b3b2
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
ROM code protect reset bits (Note 3)
b5b4
0 0: Protect removed
0 1: Protect set bits effective
1 0: Protect set bits effective
1 1: Protect set bits effective
ROM code protect level 1 set bits (ROMCP1) (Note 1)
b7b6
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
b
0b
7
N
o
t
e
s1:
W
h
e
n
R
O
M
c
o
d
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p
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c
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d
o
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,
t
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i
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t
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n
a
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f
l
a
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m
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a
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a
i
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t
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a
d
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t
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n
i
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p
a
r
a
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e
l
I
/
O
m
o
d
e
.
2:
W
h
e
n
R
O
M
c
o
d
e
p
r
o
t
e
c
t
l
e
v
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l
2
i
s
t
u
r
n
e
d
o
n
,
R
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c
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e
a
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b
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t
i
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L
S
I
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s
t
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r
,
e
t
c
.
a
l
s
o
i
s
i
n
h
i
b
i
t
e
d
.
3:
T
h
e
R
O
M
c
o
d
e
p
r
o
t
e
c
t
r
e
s
e
t
b
i
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s
c
a
n
b
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u
s
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d
t
o
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u
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n
o
f
f
R
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c
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p
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c
t
l
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v
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l
1
a
n
d
R
O
M
c
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p
r
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t
e
c
t
l
e
v
e
l
2
.
H
o
w
e
v
e
r
,
s
i
n
c
e
t
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e
s
e
b
i
t
s
c
a
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o
t
b
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f
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p
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I
/
O
m
o
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e
,
t
h
e
y
n
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d
t
o
b
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r
e
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r
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n
i
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r
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a
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I
/
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P
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w
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m
o
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e
.
11
7542 Group
Rev.3.03 Jul 11, 2008 Page 83 of 117
REJ03B0006-0303
(2) ID Code Check Function
Use this function in standard serial I/O mode. When the contents
of the flash memory are not blank, the ID code sent from the pro-
grammer is compared with the ID code written in the flash memory
to see if they match. If the ID codes do not match, the commands
sent from the programmer are not accepted. The ID code consists
of 8-bit data, and its areas are FFD416 to FFDA16. Write a pro-
gram which has had the ID code preset at these addresses to the
flash memory.
Fig. 106 ID code store addresses
ROM code protect control
ID7
ID6
ID5
ID4
ID3
ID2
ID1
FFDB16
FFDA16
FFD916
FFD816
FFD716
FFD616
FFD516
FFD416
Address
Interrupt vector area
7542 Group
Rev.3.03 Jul 11, 2008 Page 84 of 117
REJ03B0006-0303
● Parallel I/O Mode
The parallel I/O mode is used to input/output software commands,
address and data in parallel for operation (read, program and
erase) to internal flash memory.
Use the external device (writer) only for 7542 Group (flash
memory version). For details, refer to the user ’s manual of each
writer manufacturer.
• User ROM and Boot ROM Areas
In parallel I/O mode, the User ROM and Boot ROM areas shown
in Figure 97 can be rewritten. Both areas of flash memory can be
operated on in the same way.
The Boot ROM area is 4 Kbytes in size and located at addresses
F00016 through FFFF16. Make sure program and block erase op-
erations are always performed within this address range. (Access
to any location outside this address range is prohibited.)
In the Boot ROM area, an erase block operation is applied to only
one 4 Kbyte block. The boot ROM area has had a standard serial
I/O mode control program stored in it when shipped from the fac-
tory. Therefore, using the MCU in standard serial I/O mode, do not
rewrite to the Boot ROM area.
7542 Group
Rev.3.03 Jul 11, 2008 Page 85 of 117
REJ03B0006-0303
● Standard serial I/O Mode
The standard serial I/O mode inputs and outputs the software
commands, addresses and data needed to operate (read, pro-
gram, erase, etc.) the internal flash memory. This I/O is clock
synchronized serial. This mode requires a purpose-specific pe-
ripheral unit.
The standard serial I/O mode is different from the parallel I/O
mode in that the CPU controls flash memory rewrite (uses the
CPU rewrite mode), rewrite data input and so forth. The standard
serial I/O mode is started when the microcomputer is reset and
the CNVSS pin high after pulling the P37(RP) pin low, P32(CE) pin
high, P06/SCLK2 pin low and P05/TxD2 pin high. (In the ordinary
microcomputer mode, set CNVss pin to “L” level.)
This control program is written in the Boot ROM area when the
product is shipped from Renesas. Accordingly, make note of the
fact that the standard serial I/O mode cannot be used if the Boot
ROM area is rewritten in parallel I/O mode.
The standard serial I/O mode has standard serial I/O mode 1 of
the clock synchronous serial and the standard serial I/O mode 2 of
the clock asynchronous serial.
Table 13 lists the description of pin function (standard serial I/O
mode 1). Figures 107 to 109 show the pin connections for the
standard serial I/O mode 1.
Table 14 lists the description of pin function (standard serial I/O
mode 2). Figures 112 to 114 show the pin connections for the
standard serial I/O mode 2.
In standard serial I/O mode, only the User ROM area shown in
Figure 97 can be rewritten. The Boot ROM area cannot be written.
In standard serial I/O mode, a 7-byte ID code is used. When there
is data in the flash memory, this function determines whether the
ID code sent from the peripheral unit (programmer) and those writ-
ten in the flash memory match.The commands sent from the
peripheral unit (programmer) are not accepted unless the ID code
matches.
7542 Group
Rev.3.03 Jul 11, 2008 Page 86 of 117
REJ03B0006-0303
Pin name Signal name I/O
VCC,VSS Power supply I
CNVSS CNVSS I
RESET Reset input I
XIN Clock input I
XOUT Clock output O
VREF Reference voltage input I
P00–P03I/O port P0 I/O
P04RxD input I
P05TxD output O
P06SCLK input I
P07BUSY output O
P10–P14I/O port P1 I/O
P20–P27I/O port P2 I/O
P30, P31, P33–P36I/O port P3 I/O
P32CE input I
P37RP input I
(1) Standard serial I/O mode 1
Table 13 Description of pin function (standard serial I/O mode 1) Function
Apply 2.7 to 5.5 V to the Vcc pin and 0 V to the Vss pin.
After input of port is set, input “H” level.
Reset input pin. System operates when RESET pin is set to “H” level after
CNVss pin is set to “H” level.
Connect an oscillation circuit between the XIN and XOUT pins.
As for the connection method, refer to the “clock generating circuit”.
(When system operates only by the on-chip oscillator, an external circuit is not
required.)
Apply reference voltage of A/D to this pin.
Input “L” or “H” level, or keep open.
Serial data input pin.
Serial data output pin.
Serial clock input pin.
BUSY signal output pin.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
Input “H” level.
Input “L” level.
7542 Group
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REJ03B0006-0303
Fig. 107 Pin connection diagram in standard serial I/O mode 1 (PLQP0032GB-A package)
P07(LED07)/SRDY2
P10/RXD1/CAP0
P11/TXD1
P12/SCLK1
P13/SRDY1
P14/CNTR0
P20/AN0
P21/AN132
31
30
29
28
27
26
25 P34(LED14)
P33(LED13)/INT1
P32(LED12)/CMP3
P31(LED11)/CMP2
P30(LED10)/CAP1
VSS
XOUT
XIN
9
10
11
12
13
14
15
16
8765314
V
CC
CNV
SS
RESET
P2
2
/AN
2
P0
5
(LED
05
)/TxD
2
20 1718192124
P0
2
(LED
02
)/CMP
1
P0
4
(LED
04
)/RxD
2
P0
3
(LED
03
)/TX
OUT
P0
6
(LED
06
)/S
CLK2
23 22
P0
1
(LED
01
)/CMP
0
P0
0
(LED
00
)/CAP
0
P3
7
(LED
17
)/INT
0
M37542FxGP
P2
3
/AN
3
P2
4
/AN
4
P2
5
/AN
5
V
REF
2
Vss
BUSY
"H" input
Vcc
CNVSS
RESET
RxD
TxD
SCLK "L" input
Note
Note. Connect the oscillation circuit to XIN and XOUT.
(Package type: PLQP0032GB-A)
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REJ03B0006-0303
Fig. 108 Pin connection diagram in standard serial I/O mode 1 (PRSP0036GA-A package)
Fig. 109 Pin connection diagram in standard serial I/O mode 1 (PRDP0032BA-A package)
10
1
2
3
4
6
7
8
9
11
12
14
15
16
5
13
17
18
36
35
34
33
31
30
26
25
24
23
22
21
20
19
32
27
29
28
CNV
SS
X
OUT
X
IN
V
SS
P0
4
(LED
04
)/RxD
2
P3
0
(LED
10
)/CAP
1
Vcc
V
REF
P0
5
(LED
05
)/TxD
2
P1
0
/R
X
D
1
/CAP
0
P2
6
/AN
6
P2
7
/AN
7
P1
1
/T
X
D
1
P1
2
/S
CLK1
P1
3
/S
RDY1
P2
3
/AN
3
P2
2
/AN
2
P2
1
/AN
1
P2
0
/AN
0
P3
1
(LED
11
)/CMP
2
P3
6
(LED
16
)/INT
1
P2
4
/AN
4
P2
5
/AN
5
P0
6
(LED
06
)/S
CLK2
P0
7
(LED
07
)/S
RDY2
RESET
M37542FxFP
P1
4
/CNTR
0
P3
5
(LED
15
)
P3
4
(LED
14
)
P3
3
(LED
13
)/INT
1
P3
2
(LED
12
)/CMP
3
P3
7
(LED
17
)/INT
0
P0
0
(LED
00
)/CAP
0
P0
1
(LED
01
)/CMP
0
P0
2
(LED
02
)/CMP
1
P0
3
(LED
03
)/TX
OUT
BUSY
S
CLK
T
X
D
R
X
D
L input
H input
RESET
Vcc
Vss
CNV
SS
Note
Note. Connect the oscillation circuit to X
IN
and X
OUT
.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CNVSS
P12/SCLK1
P13/SRDY1
P14/CNTR0
P20/AN0
P21/AN1
P22/AN2
P23/AN3
P24/AN4
VCC
XIN
XOUT
VSS
P11/TXD1
P10/RXD1/CAP0
P07(LED07)/SRDY2
P06(LED06)/SCLK2
P05(LED05)/TxD2
P04(LED04)/RxD2
P30(LED10)/CAP1
P25/AN5
VREF
RESET
P33(LED13)/INT1
P32(LED12)/CMP3
P31(LED11)/CMP2
M37542FxSP
32
14
15
16
P34(LED14)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
P03(LED03)/TXOUT
P02(LED02)/CMP1
P01(LED01)/CMP0
P00(LED00)/CAP0
P37(LED17)/INT0
BUSY
SCLK
TXD
RXD
L input
H input
RESET
Vcc
Vss
CNVSS
Note
Note. Connect the oscillation circuit to X
IN
and X
OUT
.
(Package type: PRSP0036GA-A)
(Package type: PRDP0032BA-A)
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REJ03B0006-0303
Fig. 110 Handling example of control pins in standard serial I/O mode 1
M37542 flash memory version
Target board
RESET
XIN XOUT
User reset circuit
To user system circuit
TXD(P05)
SCLK(P06)
RXD(P04)
BUSY(P07)
VSS
(P32)
VCC
Note 1
(P37)
CNVSS Note 2
Connect the user reset circuit to the RESET pin with the shortest possible wiring.
In the normal microcomputer mode, disconnect a wiring of a serial rewrite circuit,
which is for the flash memory version, from the MCU by a jumper switch.
Connect the CNVss pin to the Vss pin with the shortest possible wiring.
In the normal microcomputer mode, disconnect a wiring of a serial rewrite circuit,
which is for the flash memor
y
version
,
from the MCU b
y
a
j
um
p
er switch.
Notes 1:
2:
• Standard serial I/O mode 1
Figure 110 shows the handling example of control pins on the user
system board when the standard serial I/O mode 1 is used.
Refer to the serial programmer manual of your programmer to
handle pins controlled by the programmer.
7542 Group
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REJ03B0006-0303
Fig. 111 Timing diagram in standard serial I/O mode 1
Power source
RESET
CNVSS
P37(RP)
P32(CEB)
P07(BUSY)
P06(SCLK2)
P05(TxD2)
P04(RxD2)
td(port-CNVSS)
th(CNVSS-RESET)
th(CNVSS-port)
td(CNVSS-RESET)
td(RESET-SCLK)
Symbol
td(port-CNVss)
td(CNVss-RESET)
td(RESET-SCLK)
th(RESET-CNVss)
th(CNVss-port)
Ratings Unit
ms
ms
ms
ms
ms
Min.
1
1
0.05
1
1
Typ.
-
-
-
-
-
Max.
-
-
0.5
-
-
Note: Keep input of P06 “H” until P07 turns “L”.
(Note)
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REJ03B0006-0303
Pin name Signal name I/O
VCC,VSS Power supply I
CNVSS CNVSS I
RESET Reset input I
XIN Clock input I
XOUT Clock output O
VREF Reference voltage input I
P00–P03I/O port P0 I/O
P04RxD input I
P05TxD output O
P06SCLK input I
P07BUSY output O
P10–P14I/O port P1 I/O
P20–P27I/O port P2 I/O
P30, P31, P33–P36I/O port P3 I/O
P32CE input I
P37RP input I I
(2) Standard serial I/O mode 2
Table 14 Description of pin function (standard serial I/O mode 2)
Function
Apply 2.7 to 5.5 V to the Vcc pin and 0 V to the Vss pin.
After input of port is set, input “H” level.
Reset input pin. System operates when RESET pin is set to “H” level after
CNVss pin is set to “H” level.
Connect an oscillation circuit between the XIN and XOUT pins.
As for the connection method, refer to the “clock generating circuit”.
(When system operates only by the on-chip oscillator, an external circuit is not
required.)
Apply reference voltage of A/D to this pin.
Input “L” or “H” level, or keep open.
Serial data input pin.
Serial data output pin.
Input “L” level.
BUSY signal output pin.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
Input “H” level.
Input “L” level.
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REJ03B0006-0303
P0
7
(LED
07
)/S
RDY2
P1
0
/R
X
D
1
/CAP
0
P1
1
/T
X
D
1
P1
2
/S
CLK1
P1
3
/S
RDY1
P1
4
/CNTR
0
P2
0
/
AN
0
P2
1
/
AN
1
32
31
30
29
28
27
26
25
P3
4
(LED
14
)
P3
3
(LED
13
)/INT
1
P3
2
(LED
12
)/CMP
3
P3
1
(LED
11
)/CMP
2
P3
0
(LED
10
)/CAP
1
V
SS
X
OUT
X
IN
9
10
11
12
13
14
15
16
8765314
V
CC
CNV
SS
RESET
P2
2
/AN
2
P0
5
(LED
05
)/TxD
2
20 1718192124
P0
2
(LED
02
)/CMP
1
P0
4
(LED
04
)/RxD
2
P0
3
(LED
03
)/TX
OUT
P0
6
(LED
06
)/S
CLK2
23 22
P0
1
(LED
01
)/CMP
0
P0
0
(LED
00
)/CAP
0
P3
7
(LED
17
)/INT
0
M37542FxGP
P2
3
/AN
3
P2
4
/AN
4
P2
5
/AN
5
V
REF
2
Vss
“H” input
Vcc
CNV
SS
RESET
RxD
TxD
BUSY
"L"
input “L” input
Note. Connect the oscillation circuit to XIN and XOUT.
Note
Fig. 112 Pin connection diagram in standard serial I/O mode 2 (PLQP0032GB-A package)
(Package type: PLQP0032GB-A)
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REJ03B0006-0303
Fig. 113 Pin connection diagram in standard serial I/O mode 2 (PRSP0036GA-A package)
Fig. 114 Pin connection diagram in standard serial I/O mode 2 (PRDP0032BA-A package)
10
1
2
3
4
6
7
8
9
11
12
14
15
16
5
13
17
18
36
35
34
33
31
30
26
25
24
23
22
21
20
19
32
27
29
28
CNVSS
XOUT
XIN
VSS
P04(LED04)/RxD2
P30(LED10)/CAP1
Vcc
VREF
P05(LED05)/TxD2
P10/RXD1/CAP0
P26/AN6
P27/AN7
P11/TXD1
P12/SCLK1
P13/SRDY1
P23/AN3
P22/AN2
P21/AN1
P20/AN0
P31(LED11)/CMP2
P36(LED16)/INT1
P24/AN4
P25/AN5
P06(LED06)/SCLK2
P07(LED07)/SRDY2
RESET
M37542FxFP
P14/CNTR0
P35(LED15)
P34(LED14)
P33(LED13)/INT1
P32(LED12)/CMP3
P37(LED17)/INT0
P00(LED00)/CAP0
P01(LED01)/CMP0
P02(LED02)/CMP1
P03(LED03)/TXOUT
“L” input
BUSY
T
X
D
R
X
D
“L” input
“H” input
RESET
Vcc
Vss
CNV
SS
Note. Connect the oscillation circuit to XIN and XOUT.
Note
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CNVSS
P12/SCLK1
P13/SRDY1
P14/CNTR0
P20/AN0
P21/AN1
P22/AN2
P23/AN3
P24/AN4
VCC
XIN
XOUT
VSS
P11/TXD1
P10/RXD1/CAP0
P07(LED07)/SRDY2
P06(LED06)/S
CLK
2
P05(LED05)/TxD2
P04(LED04)/RxD2
P30(LED10)/CAP1
P25/AN5
VREF
RESET
P33(LED13)/INT1
P32(LED12)/CMP3
P31(LED11)/CMP2
M37542FxSP
32
14
15
16
P34(LED14)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
P03(LED03)/TXOUT
P02(LED02)/CMP1
P01(LED01)/CMP0
P00(LED00)/CAP0
P37(LED17)/INT0
“L” input
BUSY
TXD
RXD
“L” input
“H” input
RESET
Vcc
Vss
CNVSS
Note. Connect the oscillation circuit to X
IN
and X
OUT
.
Note
(Package type: PRSP0036GA-A)
(Package type: PRDP0032BA-A)
7542 Group
Rev.3.03 Jul 11, 2008 Page 94 of 117
REJ03B0006-0303
M37542 flash memory version
Target board
RESET
X
IN
X
OUT
User reset circuit
To user system circuit
T
X
D(P0
5
)
S
CLK
(P0
6
)
R
X
D(P0
4
)
BUSY(P0
7
)
V
SS
(P3
2
)
V
CC
Note 1
Note 2
(P3
7
)
CNV
SS
Connect the user reset circuit to the RESET pin with the shortest possible wiring.
In the normal microcomputer mode, disconnect a wiring of a serial rewrite circuit,
which is for the flash memory version, from the MCU by a jumper switch.
Connect the CNVss pin to the Vss pin with the shortest possible wiring.
In the normal microcomputer mode, disconnect a wiring of a serial rewrite circuit,
which is for the flash memor
y
version
,
from the MCU b
y
a
j
um
p
er switch.
Notes 1:
2:
Fig. 115 Handling example of control pins in standard serial I/O mode 2
• Standard serial I/O mode 2
Figure 115 shows the handling example of control pins on the user
system board when the standard serial I/O mode 2 is used.
Refer to the serial programmer manual of your programmer to
handle pins controlled by the programmer.
7542 Group
Rev.3.03 Jul 11, 2008 Page 95 of 117
REJ03B0006-0303
Fig. 116 Timing diagram in standard serial I/O mode 2
Power source
RESET
CNVSS
P37(RP)
P32(CEB)
P06(SCLK2)
P05(TxD2)
P04(RxD2)
td(port-CNVSS)
th(CNVSS-RESET)
th(CNV
SS
-port)
td(CNVSS-RESET)
Symbol
td(port-CNVss)
td(CNVss-RESET)
th(RESET-CNVss)
th(CNVss-port)
Ratings Unit
ms
ms
ms
ms
Min.
1
1
1
1
Typ.
-
-
-
-
Max.
-
-
-
-
Note: In the standard serial I/O2, set P06 and P07 as follows;
P06: input “L” level.
P07: BUSY signal output pin. Keep open.
7542 Group
Rev.3.03 Jul 11, 2008 Page 96 of 117
REJ03B0006-0303
ELECTRICAL CHARACTERISTICS
1.Absolute Maximum Ratings
Table 15 Absolute maximum ratings
–0.3 to 6.5
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
300 (Note)
–20 to 85
–40 to 125
Power source voltage
Input voltage
P00–P07, P10–P14, P20–P27, P30–P37, VREF
Input voltage RESET, XIN
Input voltage CNVSS
Output voltage
P00–P07, P10–P14, P20–P27, P30–P37, XOUT
Power dissipation
Operating temperature
Storage temperature
V
V
V
V
V
mW
°C
°C
VCC
VI
VI
VI
VO
Pd
Topr
Tstg
Conditions
Symbol Ratings Unit
Parameter
All voltages are
based on VSS.
When an input
voltage is
measured, output
transistors are cut
off.
Ta = 25°C
Note: 200 mW for the PLQP0032GB-A package product.
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Rev.3.03 Jul 11, 2008 Page 97 of 117
REJ03B0006-0303
Recommended Operating Conditions
Table 16 Recommended operating conditions (1)
(FLASH ROM version: V
CC
= 2.7 to 5.5V, Mask ROM version: V
CC
= 2.2 to 5.5 V, V
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
VCC
VCC
VCC
VCC
0.2VCC
0.8
0.2VCC
0.16VCC
–80
80
80
–40
40
40
4.0
2.4
2.7
2.2
2.7
4.5
4.0
2.4
2.7
2.2
2.7
4.0
2.4
2.7
2.2
2.7
2.0
0.8VCC
2.0
0.8VCC
0
0
0
0
Min. Typ. Max.
Symbol Parameter Unit
Power source voltage (High-, Middle-speed mode)
(ceramic)
(Double-speed mode)
Power source voltage (High-, Middle-speed mode)
(RC)
Power source voltage
Analog reference voltage
“H” input voltage
P00–P07, P10–P14, P20–P27, P30–P37
“H” input voltage (TTL input level selected)
P10, P12, P13, P36, P37 (Note 1)
“H” input voltage
RESET, XIN
“L” input voltage
P00–P07, P10–P14, P20–P27, P30–P37
“L” input voltage (TTL input level selected)
P10, P12, P13, P36, P37 (Note 1)
“L” input voltage
RESET, CNVSS
“L” input voltage
XIN
“H” total peak output current (Note 2)
P00–P07, P10–P14, P20–P27, P30–P37
“L” total peak output current (Note 2)
P10–P14, P20–P27
“L” total peak output current (Note 2)
P00–P07, P30–P37
“H” total average output current (Note 2)
P0
0
–P0
7
, P1
0
–P1
4
, P2
0
–P2
7
, P3
0
–P3
7
“L” total average output current (Note 2)
P10–P14, P20–P27
“L” total average output current (Note 2)
P00–P07, P30–P37
f(XIN) = 8 MHz Mask ROM
FLASH ROM
f(XIN) = 4 MHz Mask ROM
FLASH ROM
f(XIN) = 2 MHz Mask ROM
FLASH ROM
f(XIN) = 8 MHz Mask ROM
FLASH ROM
f(XIN) = 6.5 MHz Mask ROM
FLASH ROM
f(XIN) = 2 MHz Mask ROM
FLASH ROM
f(XIN) = 1 MHz Mask ROM
FLASH ROM
f(XIN) = 4 MHz Mask ROM
FLASH ROM
f(XIN) = 2 MHz Mask ROM
FLASH ROM
f(XIN) = 1 MHz Mask ROM
FLASH ROM
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
0
Limits
VCC
VSS
VREF
VIH
VIH
VIH
VIL
VIL
VIL
VIL
∑IOH(peak)
∑IOL(peak)
∑IOL(peak)
∑IOH(avg)
∑IOL(avg)
∑IOL(avg)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
Note 1: Vcc = 4.0 to 5.5V
2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
7542 Group
Rev.3.03 Jul 11, 2008 Page 98 of 117
REJ03B0006-0303
Recommended Operating Conditions (continued)
Table 17 Recommended operating conditions (2)
(FLASH ROM version: V
CC
= 2.7 to 5.5V, Mask ROM version: V
CC
= 2.2 to 5.5 V, V
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
“H” peak output current (Note 1) P00–P07, P10–P14, P20–P27, P30–P37
“L” peak output current (Note 1) P00–P07, P30–P37 (Drive capacity = “L”)
P10–P14, P20–P27
“L” peak output current (Note 1)
P0
0
–P0
7
, P3
0
–P3
7
(Drive capacity = “H”)
“H” average output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37
“L” average output current (Note 2) P00–P07, P30–P37 (Drive capacity = “L”)
P10–P14, P20–P27
“L” average output current (Note 2)
P0
0
–P0
7
, P3
0
–P3
7
(Drive capacity = “H”)
Oscillation frequency (Note 3) Mask ROM: VCC = 4.5 to 5.5 V
at ceramic oscillation or external clock input FLASH ROM: VCC = 4.5 to 5.5 V
Double-speed mode
Oscillation frequency (Note 3) Mask ROM: VCC = 4.0 to 5.5 V
at ceramic oscillation or external clock input FLASH ROM: VCC = 4.0 to 5.5 V
Double-speed mode
Oscillation frequency (Note 3) Mask ROM: VCC = 2.4 to 5.5 V
at ceramic oscillation or external clock input FLASH ROM: VCC = 2.7 to 5.5 V
Double-speed mode
Oscillation frequency (Note 3) Mask ROM: VCC = 2.2 to 5.5 V
at ceramic oscillation or external clock input
Double-speed mode
Oscillation frequency (Note 3) Mask ROM: VCC = 4.0 to 5.5 V
at ceramic oscillation or external clock input FLASH ROM: VCC = 4.0 to 5.5 V
High-, Middle-speed mode
Oscillation frequency (Note 3) Mask ROM: VCC = 2.4 to 5.5 V
at ceramic oscillation or external clock input FLASH ROM: VCC = 2.7 to 5.5 V
High-, Middle-speed mode
Oscillation frequency (Note 3) Mask ROM: VCC = 2.2 to 5.5 V
at ceramic oscillation or external clock input
High-, Middle-speed mode
Oscillation frequency (Note 3) Mask ROM: VCC = 4.0 to 5.5 V
at RC oscillation FLASH ROM: VCC = 4.0 to 5.5 V
High-, Middle-speed mode
Oscillation frequency (Note 3) Mask ROM: VCC = 2.4 to 5.5 V
at RC oscillation FLASH ROM: VCC = 2.7 to 5.5 V
High-, Middle-speed mode
Oscillation frequency (Note 3) Mask ROM: VCC = 2.2 to 5.5 V
at RC oscillation
High-, Middle-speed mode
Symbol Parameter Limits Max.Typ.Min. –10
10
30
–5
5
15
8
6.5
2
1
8
4
2
4
2
1
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50 %.
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOL(avg)
IOL(avg)
f(XIN)
mA
mA
mA
mA
mA
mA
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
7542 Group
Rev.3.03 Jul 11, 2008 Page 99 of 117
REJ03B0006-0303
Electrical Characteristics
Table 18 Electrical characteristics (1)
(FLASH ROM version: V
CC
= 2.7 to 5.5V, Mask ROM version: V
CC
= 2.2 to 5.5 V, V
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
IOH = –5 mA
VCC = 4.0 to 5.5 V
IOH = –1.0 mA
Mask ROM: V
CC
= 2.2 to 5.5 V
FLASH ROM: VCC = 2.7 to 5.5 V
IOL = 5 mA
VCC = 4.0 to 5.5 V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
IOL = 1.0 mA
Mask ROM: V
CC
= 2.2 to 5.5 V
FLASH ROM: VCC = 2.7 to 5.5 V
IOL = 15 mA
VCC = 4.0 to 5.5 V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
IOL = 1.0 mA
Mask ROM: V
CC
= 2.2 to 5.5 V
FLASH ROM: VCC = 2.7 to 5.5 V
VI = VCC
(Pin floating. Pull up transistors
“off”)
VI = VCC
VI = VCC
VI = VSS
(Pin floating. Pull up transistors
“off”)
VI = VSS
VI = VSS
VI = VSS
(Pull up transistors “on”)
When clock stopped
VCC = 5.0 V, Ta = 25 °C
VCC = 5.0 V, Ta = 25 °C
Test conditions
VCC–1.5
VCC–1.0
2.0
1000
62.5
“H” output voltage
P00–P07, P10–P14, P20–P27, P30–P37 (Note 1)
“L” output voltage
P00–P07, P30–P37 (Drive capacity = “L”)
P10–P14, P20–P27
“L” output voltage
P00–P07, P30–P37 (Drive capacity = “H”)
Hysteresis
CNTR0, INT0, INT1, CAP0, CAP1 (Note 2)
P00–P07 (Note 3)
Hysteresis
RXD0, SCLK0, RXD1, SCLK1
Hysteresis
RESET
“H” input current
P00–P07, P10–P14, P20–P27, P30–P37
“H” input current
RESET
“H” input current
XIN
“L” input current
P00–P07, P10–P14, P20–P27, P30–P37
“L” input current
RESET
“L” input current
XIN
“L” input current
P00–P07, P30–P37
RAM hold voltage
On-chip oscillator oscillation frequency
Oscillation stop detection circuit detection frequency
1.5
0.3
1.0
2.0
0.3
1.0
5.0
5.0
–5.0
–5.0
–0.5
5.5
3000
187.5
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
V
kHz
kHz
VOH
VOL
VOL
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIH
IIL
IIL
IIL
IIL
VRAM
ROSC
DOSC
0.4
0.5
0.5
4.0
–4.0
–0.2
2000
125
Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”.
2: RXD1, SCLK1, INT0, and INT1 (P36 selected) have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level).
3: It is available only when operating key-on wake up.
7542 Group
Rev.3.03 Jul 11, 2008 Page 100 of 117
REJ03B0006-0303
Electrical Characteristics (continued)
Table 19 Electrical characteristics (2)
(FLASH ROM version: V
CC
= 2.7 to 5.5V, Mask ROM version: V
CC
= 2.2 to 5.5 V, V
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits UnitTest conditions
Power source
current 9.0
7.5
6.5
5.5
5.0
4.2
1.2
2.8
3.2
2.4
2.2
1.9
1.0
1.3
0.6
1.0
3.2
2.6
0.6
0.4
1.0
3.0
10
10
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
ICC 5.5
4.8
3.5
3.0
2.0
1.7
0.4
1.0
1.5
1.4
0.9
1.0
0.35
0.65
0.2
0.55
1.6
1.2
0.2
0.6
0.2
0.12
0.5
0.5
0.1
0.55
f(XIN) = 8 MHz
Output transistors “off”
f(XIN) = 2 MHz,
Mask ROM: VCC = 2.2 V
FLASH ROM: VCC = 2.7 V
Output transistors “off”
On-chip oscillator
operation mode,
Output transistors “off”
f(XIN) = 8 MHz (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
f(XIN) = 2 MHz,
Mask ROM: VCC = 2.2 V
FLASH ROM: VCC = 2.7 V
(in WIT state),
functions except timer 1 disabled,
Output transistors “off”
On-chip oscillator operation mode,
(in WIT state),
functions except timer 1 disabled,
Output transistors “off”
Increment when A/D conversion is executed
f(XIN) = 8 MHz, VCC = 5 V
All oscillation stopped
(in STP state)
Output transistors “off”
Double-speed mode Mask ROM
FLASH ROM
High-speed mode Mask ROM
FLASH ROM
Middle-speed mode Mask ROM
FLASH ROM
High-speed mode Mask ROM
FLASH ROM
Frequency/1 Mask ROM
FLASH ROM
Frequency/2 Mask ROM
FLASH ROM
Frequency/8 Mask ROM
FLASH ROM
Frequency/128 Mask ROM
FLASH ROM
Mask ROM
FLASH ROM
Mask ROM
FLASH ROM
Mask ROM
FLASH ROM
Mask ROM
FLASH ROM
Ta = 25 °C Mask ROM
FLASH ROM
Ta = 85 °C Mask ROM
FLASH ROM
Note: Increment when A/D conversion is executed includes the reference power source input current (IVREF).
7542 Group
Rev.3.03 Jul 11, 2008 Page 101 of 117
REJ03B0006-0303
A/D Converter Characteristics
Table 20 A/D Converter characteristics
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Resolution
Absolute accuracy
Conversion time
Ladder resistor
Reference power source input current
A/D port input current
Min. Typ. Max.
Symbol Parameter Limits UnitTest conditions
Ta = 25 °C Mask ROM
VCC = VREF = 2.7 to 5.5 V FLASH ROM
AD conversion clock = f(XIN)/2
AD conversion clock = f(XIN)
VREF = 5.0 V
VREF = 3.0 V
Bits
LSB
tc(XIN)
kΩ
µA
µA
10
± 3
± 4
122
61
200
120
5.0
—
—
tCONV
RLADDER
IVREF
II(AD)
55
150
90
50
30
Note: AD conversion accuracy may be low under the following conditions;
(1) When the VREF voltage is set to be lower than the VCC voltage, an analog circuit in this microcomputer is affected by noise.
The accuracy is lower than the case the VREF voltage is the same as VCC voltage.
(2) When the VREF voltage is 3.0 V or less at the low temperature, the AD conversion accuracy may be very lower than at room temperature.
When system is used at low temperature, that VREF is 3.0 V or more is recommended.
Electrical Characteristics of 7542 Group Flash Memory
Table 21 Electrical Characteristics of 7542 Group Flash Memory
Symbol Parameter
Program/Erase endurance (Note 1)
Byte program time
2Kbyte-block
Block erase time 8Kbyte-block
16Kbyte-block
Time delay from suspend request until erase suspend
Erase suspend request interval
Program, erase voltage
Read voltage
Program, erase temperature
Data hold time
td(SR-ES)
Note 1. Definition of program and erase
The program and erase endurance shows an erase endurance for every block.
If the program and erase endurance is “n” times (n = 100), “n” times erase can be performed for every block.
For example, if performing 1-byte write to the distinct addresses on Block A of 2Kbyte block 2048 times and then erasing that block,
program and erase endurance is counted as one time.
However, do not perform multiple programs to the same address for one time erase. (disable overwriting).
Limits Unit
Min.
100
10
2.7
2.7
0
20
Typ.
50
0.2
0.4
0.7
Max.
400
9
9
9
8
5.5
5.5
60
times
µs
s
s
s
ms
ms
V
V
°C
year
Test
conditions
Ta = 55 °C
Fig. 117 Time delay from suspend request until erase suspend
t
d(SR-ES)
Erase-suspend request
(interrupt request)
Erase suspend flag
7542 Group
Rev.3.03 Jul 11, 2008 Page 102 of 117
REJ03B0006-0303
Timing Requirements
Table 22 Timing requirements (1)
(FLASH ROM version: V
CC
= 4.0 to 5.5V, Mask ROM version: V
CC
= 4.0 to 5.5 V, V
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1, CAP0, CAP1 input “H” pulse width (Note 1)
CNTR0, INT0, INT1, CAP0, CAP1 input “L” pulse width (Note 1)
Serial I/O1, serial I/O2 clock input cycle time (Note 2)
Serial I/O1, serial I/O2 clock input “H” pulse width (Note 2)
Serial I/O1, serial I/O2 clock input “L” pulse width (Note 2)
Serial I/O1, serial I/O2 input set up time
Serial I/O1, serial I/O2 input hold time
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD1–SCLK1)
th(SCLK1–RxD1)
2
125
50
50
200
80
80
800
370
370
220
100
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 23 Timing requirements (2)
(
FLASH ROM version: V
CC
= 2.7 to 5.5V, Mask ROM version: V
CC
= 2.4 to 5.5 V
, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1, CAP0, CAP1 input “H” pulse width (Note 1)
CNTR0, INT0, INT1, CAP0, CAP1 input “L” pulse width (Note 1)
Serial I/O1, serial I/O2 clock input cycle time (Note 2)
Serial I/O1, serial I/O2 clock input “H” pulse width (Note 2)
Serial I/O1, serial I/O2 clock input “L” pulse width (Note 2)
Serial I/O1, serial I/O2 input set up time
Serial I/O1, serial I/O2 input hold time
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD1–SCLK1)
th(SCLK1–RxD1)
2
250
100
100
500
230
230
2000
950
950
400
200
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: As for CAP0, CAP1, it is the value when noise filter is not used.
2: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.
In this time, bit 6 of the serial I/O2 control register (address 003016) is set to “1” (clock synchronous serial I/O is selected).
When bit 6 of the serial I/O2 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.
Notes 1: As for CAP0, CAP1, it is the value when noise filter is not used.
2: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
In this time, bit 6 of the serial I/O2 control register (address 003016) is set to “1” (clock synchronous serial I/O is selected).
When bit 6 of the serial I/O2 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.
7542 Group
Rev.3.03 Jul 11, 2008 Page 103 of 117
REJ03B0006-0303
Table 24 Timing requirements (3)
(Mask ROM version: V
CC
= 2.2 to 5.5 V, V
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted) (This is only for the mask ROM version.)
Min. Typ. Max.
Symbol Parameter Limits Unit
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1, CAP0, CAP1 input “H” pulse width (Note 1)
CNTR0, INT0, INT1, CAP0, CAP1 input “L” pulse width (Note 1)
Serial I/O1, serial I/O2 clock input cycle time (Note 2)
Serial I/O1, serial I/O2 clock input “H” pulse width (Note 2)
Serial I/O1, serial I/O2 clock input “L” pulse width (Note 2)
Serial I/O1, serial I/O2 input set up time
Serial I/O1, serial I/O2 input hold time
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD1–SCLK1)
th(SCLK1–RxD1)
2
500
200
200
1000
460
460
4000
1900
1900
800
400
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: As for CAP0, CAP1, it is the value when noise filter is not used.
2: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
In this time, bit 6 of the serial I/O2 control register (address 003016) is set to “1” (clock synchronous serial I/O is selected).
When bit 6 of the serial I/O2 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.
7542 Group
Rev.3.03 Jul 11, 2008 Page 104 of 117
REJ03B0006-0303
Switching Characteristics
Table 25 Switching characteristics (1)
(
FLASH ROM version: V
CC
= 4.0 to 5.5V, Mask ROM version: V
CC
= 4.0 to 5.5 V
, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
tC(SCLK1)/2–30
tC(SCLK1)/2–30
–30
Min. Typ. Max.
Symbol Parameter Limits Unit
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tr(CMOS)
tf(CMOS)
Serial I/O1, serial I/O2 clock output “H” pulse width
Serial I/O1, serial I/O2 clock output “L” pulse width
Serial I/O1, serial I/O2 output delay time
Serial I/O1, serial I/O2 output valid time
Serial I/O1, serial I/O2 clock output rising time
Serial I/O1, serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
Note 1: Pin XOUT is excluded.
Table 26 Switching characteristics (2)
(
FLASH ROM version: V
CC
= 2.7 to 5.5V, Mask ROM version: V
CC
= 2.4 to 5.5 V,
VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
350
50
50
50
50
Note 1: Pin XOUT is excluded.
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tr(CMOS)
tf(CMOS)
Serial I/O1, serial I/O2 clock output “H” pulse width
Serial I/O1, serial I/O2 clock output “L” pulse width
Serial I/O1, serial I/O2 output delay time
Serial I/O1, serial I/O2 output valid time
Serial I/O1, serial I/O2 clock output rising time
Serial I/O1, serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
tC(SCLK1)/2–50
tC(SCLK1)/2–50
–30
20
20
ns
ns
ns
ns
ns
ns
ns
ns
10
10
140
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
Table 27 Switching characteristics (3)
(
V
CC
= 2.2 to 5.5 V
, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
450
70
70
70
70
Note 1: Pin XOUT is excluded.
Switching characteristics measurement circuit diagram
/ / /
Measured
output pin
CMOS output
100 pF
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tr(CMOS)
tf(CMOS)
Serial I/O1, serial I/O2 clock output “H” pulse width
Serial I/O1, serial I/O2 clock output “L” pulse width
Serial I/O1, serial I/O2 output delay time
Serial I/O1, serial I/O2 output valid time
Serial I/O1, serial I/O2 clock output rising time
Serial I/O1, serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
tC(SCLK1)/2–70
tC(SCLK1)/2–70
–30
25
25
ns
ns
ns
ns
ns
ns
ns
ns
7542 Group
Rev.3.03 Jul 11, 2008 Page 105 of 117
REJ03B0006-0303
Fig. 118 Timing chart
0.2VCC
td(SCLK1-TxD1)
tf
0.2
VCC
0.8VCC
0.8VCC
tr
tsu(RxD1-SCLK1)th(SCLK1-RxD1)
tv(SCLK1-TxD1)
tC(SCLK1)
tWL(SCLK1) tWH(SCLK1)
R
X
D
1
(at receive)
S
CLK1
0.2VCC
tWL(XIN)
0.8VCC
tWH(XIN)tC(XIN)
X
IN
0.2VCC 0.8
VCC
tW(RESET)
RESET
0.2VCC
tWL(CNTR0)
0.8VCC
tWH(CNTR0)
tC(CNTR0)
T
X
D
1
(at transmit)
CNTR0
0.2VCC
tWL(CNTR0)
0.8VCC
tWH(CNTR0)
INT0, INT1
CAP0, CAP1
7542 Group
Rev.3.03 Jul 11, 2008 Page 106 of 117
REJ03B0006-0303
PACKAGE OUTLINE
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
y
Index mark
*3
F
32
25
24 17
16
9
81
*1
*2
x
b
p
e
H
E
E
D
H
D
Z
D
Z
E
Detail F
L
1
L
A
c
A
2
A
1
Previous CodeJEITA Package Code RENESAS Code
PLQP0032GB-A 32P6U-A
MASS[Typ.]
0.2gP-LQFP32-7x7-0.80
1.0
0.125
0.35
0.7
0.7
0.20
0.200.1450.09
0.420.370.32
MaxNomMin
Dimension in Millimeters
Symbol
Reference
7.17.06.9D
7.17.06.9E
1.4A
2
9.29.08.8
9.29.08.8
1.7A
0.20.10
0.70.50.3L
x
8
°
0
°
c
0.8e
0.10y
H
D
H
E
A
1
b
p
b
1
c
1
Z
D
Z
E
L
1
Terminal cross section
b
1
c
1
bp
c
y
Index mark
118
1936
F
*1
*2
*3
E
H
E
D
ebp
A
c
Detail F
A2
L
A1
INCLUDE TRIM OFFSET.
DIMENSION "*3" DOES NOT
NOTE)
DO NOT INCLUDE MOLD FLASH.
DIMENSIONS "*1" AND "*2"1.
2.
Previous CodeJEITA Package Code RENESAS Code
PRSP0036GA-A 36P2R-A
MASS[Typ.]
0.5gP-SSOP36-8.4x15-0.80
0.20.150.13
0.50.40.35
MaxNomMin
Dimension in Millimeters
Symbol
Reference
15.215.014.8D
8.68.48.2E
2.0A2
12.2311.9311.63
2.4A
0.05
0.70.50.3L
10
°
0
°
c
0.8e
0.15y
HE
A1
bp
0.65 0.95
7542 Group
Rev.3.03 Jul 11, 2008 Page 107 of 117
REJ03B0006-0303
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
16
17
32
1
SEATING PLANE
*1
*2
*3*3
E
LA
A
1
A
2
D
eb
3
b
2
b
p
c
5.08
A
1
b
3
15
°
e1.778
c
L3.0
0.51
0.9 1.0 1.3
A
E8.758.9 9.05
D27.828.0 28.2
Reference
Symbol
Dimension in Millimeters
Min Nom Max
0.22 0.27 0.34
P-SDIP32-8.9x28-1.78 2.2g
MASS[Typ.]
32P4BPRDP0032BA-A
RENESAS CodeJEITA Package Code Previous Code
b
p
0.35 0.45 0.55
10.169.86 10.46
b
2
0.63 0.73 1.03
A
2
3.8
0
°
1.528 2.028
e
1
e
1
Previous CodeJEITA Package Code RENESAS Code
PWQN0036KA-A 36PJW-A
MASS[Typ.]
0.07gP-HWQFN36-6x6-0.50
0.70.60.5
0.250.20.15
MaxNomMin
Dimension in Millimeters
Symbol
Reference
6.16.05.9D
6.16.05.9E
0.75A2
0.8A
0.0500
4.26E1
Lp
0.5e
0.05x
A1
bp
y0.05
D24.26
Detail F
A
1
A
2
A
9
19
27
1
10
36
18
28
9
19 27
1
10 36
18 28
F
x
y
E
D
bp
Lp
D2
E
1
e
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APPENDIX
NOTES ON PROGRAMMING
1. Processor Status Register
(1) Initializing of processor status register
Flags which affect program execution must be initialized after a re-
set.
In particular, it is essential to initialize the T and D flags because
they have an important effect on calculations.
<Reason>
After a reset, the contents of the processor status register (PS) are
undefined except for the I flag which is “1”.
Reset
↓
Initializing of flags
↓
Main program
Fig. 2 Stack memory contents after PHP instruction execution
Fig. 1 Initialization of processor status register
(2) How to reference the processor status register
To reference the contents of the processor status register (PS), ex-
ecute the PHP instruction once then read the contents of (S+1). If
necessary, execute the PLP instruction to return the PS to its origi-
nal status.
(S)
(S)+1 Stored PS
3. JMP instruction
When using the JMP instruction in indirect addressing mode, do
not specify the last address on a page as an indirect address.
4.Multiplication and Division Instructions
(1) The index X mode (T) and the decimal mode (D) flags do not
affect the MUL and DIV instruction.
(2) The execution of these instructions does not change the con-
tents of the processor status register.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig. 3 Status flag at decimal calculations
2. Decimal calculations
(1) Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper
decimal notation, set the decimal mode flag (D) to “1” with the
SED instruction. After executing the ADC or SBC instruction, ex-
ecute another instruction before executing the SEC, CLC, or CLD
instruction.
(2) Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in
the status register (the N, V, and Z flags) are invalid after a ADC or
SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of
the calculation, or is cleared to “0” if a borrow is generated. To de-
termine whether a calculation has generated a carry, the C flag
must be initialized to “0” before each calculation. To check for a
borrow, the C flag must be initialized to “1” before each calcula-
tion.
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5. Read-modify-write instruction
Do not execute a read-modify-write instruction to the read invalid
address (SFR).
The read-modify-write instruction operates in the following se-
quence: read one-byte of data from memory, modify the data,
write the data back to original memory. The following instructions
are classified as the read-modify-write instructions in the 740
Family.
(1) Bit management instructions: CLB, SEB
(2) Shift and rotate instructions: ASL, LSR, ROL, ROR, RRF
(3) Add and subtract instructions: DEC, INC
(4) Logical operation instructions (1’s complement): COM
Add and subtract/logical operation instructions (ADC, SBC, AND,
EOR, and ORA) when T flag = “1” operate in the way as the read-
modify-write instruction. Do not execute the read invalid SFR.
<Reason>
When the read-modify-write instruction is executed to read invalid
SFR, the instruction may cause the following consequence: the in-
struction reads unspecified data from the area due to the read
invalid condition. Then the instruction modifies this unspecified
data and writes the data to the area. The result will be random
data written to the area or some unexpected event.
NOTES ON PERIPHERAL FUNCTIONS
Notes on I/O Ports
1. Setting of 32-pin version and PWQN0036KA-A package version
(1) Set direction registers of ports P2
6
, P2
7
, P3
5
and P3
6
to output.
(2) Select P33 for the INT1 function by the INT1 input port selec-
tion bit (bit 2 of interrupt edge selection register (address
3A16)).
(3) Be sure to set P36/INT1 input level selection bit (bit 1 of port
P1P3 control register (address 1716)) to “0”.
2. Port P0P3 drive capacity control register
The number of LED drive port (drive capacity is HIGH) is 8.
3. Pull-up control register
When using each port which built in pull-up resistor as an output
port, the pull-up control bit of corresponding port becomes invalid,
and pull-up resistor is not connected.
<Reason>
Pull-up control is effective only when each direction register is set
to the input mode.
4. Notes in stand-by state
In stand-by state*1 for low-power dissipation, do not make input
levels of an input port and an I/O port “undefined”.
Pull-up (connect the port to Vcc) or pull-down (connect the port to
Vss) these ports through a resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using a built-in pull-up resistor, note on varied current val-
ues:
• When setting as an input port : Fix its input level
•When setting as an output port : Prevent current from flowing out
to external.
<Reason>
The output transistor becomes the OFF state, which causes the
ports to be the high-impedance state. Note that the level becomes
“undefined” depending on external circuits.
Accordingly, the potential which is input to the input buffer in a mi-
crocomputer is unstable in the state that input levels of an input
port and an I/O port are “undefined”. This may cause power
source current.
*1 stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
5. Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit manag-
ing instruction*2, the value of the unspecified bit may be changed.
<Reason>
The bit managing instructions are read-modify-write form instruc-
tions for reading and writing data by a byte unit. Accordingly, when
these instructions are executed on a bit of the port latch of an I/O
port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port :
The pin state is read in the CPU, and is written to this bit after bit
managing.
• As for a bit which is set for an output port :
The bit value of the port latch is read in the CPU, and is written to
this bit after bit managing.
Note the following :
• Even when a port which is set as an output port is changed for
an input port, its port latch holds the output data.
• As for a bit of the port latch which is set for an input port, its
value may be changed even when not specified with a bit man-
aging instruction in case where the pin state differs from its port
latch contents.
*2 bit managing instructions : SEB, and CLB instructions
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6. Direction register
The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory opera-
tion instruction when the T flag is “1”, addressing mode using
direction register values as qualifiers, and bit test instructions such
as BBC and BBS.
It is also impossible to use bit operation instructions such as CLB
and SEB and read-modify-write instructions of direction registers
for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA in-
struction, etc.
Termination of Unused Pins
1. Terminate unused pins
Perform the following wiring at the shortest possible distance (20
mm or less) from microcomputer pins.
(1) I/O ports
Set the I/O ports for the input mode and connect each pin to VCC
or VSS through each resistor of 1 kΩ to 10 kΩ. The port which can
select a built-in pull-up resistor can also use the built-in pull-up re-
sistor.
When using the I/O ports as the output mode, open them at “L” or
“H”.
• When opening them in the output mode, the input mode of the
initial status remains until the mode of the ports is switched over
to the output mode by the program after reset. Thus, the poten-
tial at these pins is undefined and the power source current may
increase in the input mode. With regard to an effects on the sys-
tem, thoroughly perform system evaluation on the user side.
• Since the direction register setup may be changed because of a
program runaway or noise, set direction registers by program
periodically to increase the reliability of program.
2. Termination remarks
(1) I/O ports setting as input mode
[1] Do not open in the input mode.
<Reason>
• The power source current may increase depending on the first-
stage circuit.
• An effect due to noise may be easily produced as compared with
proper termination (1) shown on the above “1. Terminate unused
pins”.
[2] Do not connect to VCC or VSS directly.
<Reason>
If the direction register setup changes for the output mode be-
cause of a program runaway or noise, a short circuit may occur.
[3] Do not connect multiple ports in a lump to VCC or VSS through
a resistor.
<Reason>
If the direction register setup changes for the output mode be-
cause of a program runaway or noise, a short circuit may occur
between ports.
Notes on Interrupts
1. Change of relevant register settings
When not requiring for the interrupt occurrence synchronous with
the following case, take the sequence shown in Figure 4.
• When switching external interrupt active edge
• When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Fig. 4 Sequence of changing relevant register
<Reason>
When setting the followings, the interrupt request bit of the corre-
sponding interrupt may be set to “1”.
• When switching external interrupt active edge
INT0 interrupt edge selection bit
(bit 0 of Interrupt edge selection register (address 3A16))
INT1 interrupt edge selection bit
(bit 1 of Interrupt edge selection register)
CNTR0 active edge switch bit
(bit 2 of timer X mode register (address 2B16))
Capture 0 interrupt edge selection bit
(bits 1 and 0 of capture mode register (address 2016))
Capture 1 interrupt edge selection bit
(bits 3 and 2 of capture mode register)
2. Check of interrupt request bit
When executing the BBC or BBS instruction to determine an in-
terrupt request bit immediately after this bit is set to “0”, take the
following sequence.
<Reason>
If the BBC or BBS instruction is executed immediately after an in-
terrupt request bit is cleared to “0”, the value of the interrupt
request bit before being cleared to “0” is read.
Set the corresponding interrupt enable bit to “0” (disabled) .
↓
Set the interrupt edge selection bit, active edge switch bit, or
the interrupt source selection bit.
↓
NOP (One or more instructions)
↓
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
↓
Set the corresponding interrupt enable bit to “1” (enabled).
Set the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Fig. 5 Sequence of check of interrupt request bit
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3. Interrupt discrimination bit
Use an LDM instruction to clear to “0” an interrupt discrimination
bit.
LDM #%0000XXXX, $0B
Set the following values to “X”
“0”: an interrupt discrimination bit to clear
“1”: other interrupt discrimination bits
Ex.) When a key-on wakeup interrupt discrimination bit is cleared;
LDM #%00001110 and $0B.
4. Interrupt discrimination bit and interrupt request bit
For key-on wakeup, UART1 bus collision detection, A/D conver-
sion and Timer 1 interrupt, even if each interrupt valid bit (interrupt
source set register (address 0A16)) is set “0: Invalid”, each inter-
rupt discrimination bit (interrupt source discrimination register
(address 0B16)) is set to “1: interrupt occurs” when corresponding
interrupt request occurs.
But corresponding interrupt request bit (interrupt request registers
1, 2 (addresses 3C16, 3D16) is not affected.
Notes on Timers
1. When n (0 to 255) is written to a timer latch, the frequency divi-
sion ratio is 1/(n+1).
2. When a count source of timer X, timer A or timer B is switched,
stop a count of the timer.
Notes on Timer X
1. CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit (bit 2 of timer X mode register (address 2B16)).
When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR0 interrupt request bit is set to “1” at the rising edge of
CNTR0 pin input signal.
2. Timer X count source selection
The f(XIN) (frequency not divided) can be selected by the timer X
count source selection bits (bits 1 and 0 of timer count source set
register (address 2A16)) only when the ceramic oscillation or the
on-chip oscillator is selected.
Do not select it for the timer X count source at the RC oscillation.
3. Pulse output mode
Set the direction register of port P14, which is also used as CNTR0
pin, to output.
When the TXOUT pin is used, set the direction register of port P03,
which is also used as TXOUT pin, to output.
4. Pulse width measurement mode
Set the direction register of port P14, which is also used as CNTR0
pin, to input.
Notes on Timer A, B
1. Setting of timer value
When “1: Write to only latch” is set to the timer A (B) write control
bit, written data to timer register is set to only latch even if timer is
stopped or operating. Accordingly, in order to set the initial value
for timer when it is stopped, set “0: Write to latch and timer simul-
taneously” to timer A (B) write control bit.
2. Read/write of timer A
Stop timer A to read/write its data in the following state;
XIN oscillation selected by clock division ratio selection bits (bits 7
and 6 of CPU mode register (address 3B16)), and the on-chip os-
cillator output is selected as the timer A count source.
3. Read/write of timer B
Stop timer B to read/write its data in the following state;
XIN oscillation selected by clock division ratio selection bits, the
timer A underflow is selected as the timer B count source, and the
on-chip oscillator output is selected as the timer A count source.
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Notes on Output Compare
1. When the selected source timer of each compare channel is
stopped, written data to compare register is loaded to the com-
pare latch simultaneously.
2. Do not write the same data to both of compare latch x0 (x=0, 1,
2, 3) and x1.
3. When setting value of the compare register is larger than timer
setting value, compare match signal is not generated. Accord-
ingly, the output waveform is fixed to “L” or “H” level.
However, when setting value of another compare register is
smaller than timer setting value, this compare match signal is
generated. Accordingly, if the corresponding compare latch y
(y=00, 01, 10, 11, 20, 21, 30, 31) interrupt source bit is set to “1”
(valid), compare match interrupt request occurs.
4. When the compare x trigger enable bit is cleared to “0” (dis-
abled), the match trigger to the waveform output circuit is
disabled. Accordingly, the output waveform can be fixed to “L”
or “H” level.
However, in this case, the compare match signal is generated.
Accordingly, if the corresponding compare latch y (y=00, 01, 10,
11, 20, 21, 30, 31) interrupt source bit is set to “1”
(valid),compare match interrupt request occurs.
Notes on Input Capture
1. If the capture trigger is input while the capture register (low-or-
der and high-order) is in read, captured value is changed
between high-order reading and low-order reading. Accordingly,
some countermeasure by software is recommended, for ex-
ample comparing the values that twice of read.
2. Timer A cannot be used for the capture source timer in the fol-
lowing state;
• XIN oscillation selected by clock division ratio selection bits
(bits 7 and 6 of CPU mode register (address 3B16))
• Timer A count source: On-chip oscillator output.
Timer B cannot be used for the capture source timer in the fol-
lowing state;
• XIN oscillation selected by clock division ratio selection bits
• Timer B count source: Timer A underflow
• Timer A count source: On-chip oscillator output.
3. As shown below, when the capture input is performed to both
capture latch 00 and 01 at the same time, the value of capture
0 status bit (bit 4 of capture/compare status register (address
2216)) is undefined (same as capture 1).
• When “1” is written to capture latch 00 software trigger bit (bit 0
of capture software trigger register (address 1316)) and capture
latch 01 software trigger bit (bit 1 of capture software trigger reg-
ister) at the same time
• When external trigger of capture latch 00 and software trigger of
capture latch 01 occur at the same time
• When external trigger of capture latch 01 and software trigger of
capture latch 00 occur at the same time
4. When the capture interrupt is used as the interrupt for return
from stop mode, set the capture 0 noise filter clock selection
bits (bits 5 and 4 of capture mode register (address 2016)) to
“00 (Filter stop)” (same as capture 1).
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3. Notes common to clock synchronous serial I/O and UART
(1) Set the serial I/Oi (i=1, 2) control register again after the trans-
mission and the reception circuits are reset by clearing both
the transmit enable bit and the receive enable bit to “0.”
Fig. 6 Sequence of setting serial I/Oi control register again
Clear both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
Set the bits 0 to 3 and bit 6 of the
serial I/Oi control register
Set both the transmit enable bit (TE)
and the receive enable bit (RE), or
one of them to “1”
Notes on Serial I/Oi (i=1, 2)
1. Clock synchronous serial I/O
(1) When the transmit operation is stopped, clear the serial I/Oi
enable bit and the transmit enable bit to “0” (serial I/Oi and
transmit disabled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/Oi enable bit is cleared to “0”
(serial I/Oi disabled), the internal transmission is running (in this
case, since pins TxDi, RxDi, SCLKi, and SRDYi function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/Oi enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxDi pin and an operation failure occurs.
(2) When the receive operation is stopped, clear the receive en-
able bit to “0” (receive disabled), or clear the serial I/Oi enable
bit to “0” (serial I/Oi disabled).
(3) When the transmit/receive operation is stopped, clear both the
transmit enable bit and receive enable bit to “0” (transmit and
receive disabled) simultaneously. (any one of data transmis-
sion and reception cannot be stopped.)
<Reason>
In the clock synchronous serial I/O mode, the same clock is used
for transmission and reception.
If any one of transmission and reception is disabled, a bit error oc-
curs because transmission and reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also oper-
ates for data reception. Accordingly, the transmission circuit does
not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit cannot be initialized even
if the serial I/Oi enable bit is cleared to “0” (serial I/Oi disabled)
(same as (1)).
(4) When signals are output from the SRDYi pin on the reception
side by using an external clock, set all of the receive enable
bit, the SRDYi output enable bit, and the transmit enable bit to
“1”.
(5) When the SRDYi signal input is used, set the using pin to the in-
put mode before data is written to the transmit/receive buffer
register.
2. UART
When the transmit operation is stopped, clear the transmit enable
bit to “0” (transmit disabled).
<Reason>
Same as (1) shown on the above “1. Clock synchronous serial I/O“.
When the receive operation is stopped, clear the receive enable
bit to “0” (receive disabled).
When the transmit/receive operation is stopped, clear the transmit
enable bit to “0” (transmit disabled) and receive enable bit to “0”
(receive disabled).
(2) The transmit shift completion flag changes from “1” to “0” with
a delay of 0.5 to 1.5 shift clocks. When data transmission is
controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(3) When data transmission is executed at the state that an exter-
nal clock input is selected as the synchronous clock, set “1” to
the transmit enable bit while the SCLKi is “H” state. Also, write
to the transmit buffer register while the SCLKi is “H” state.
(4) When the transmit interrupt is used, set as the following se-
quence.
➀ Serial I/Oi transmit interrupt enable bit is set to “0” (disabled).
➁ Serial I/Oi transmit enable bit is set to “1”.
➂ Serial I/Oi transmit interrupt request bit is set to “0” after 1 or
more instructions have been executed.
➃ Serial I/Oi transmit interrupt enable bit is set to “1” (enabled).
<Reason>
When the transmit enable bit is set to “1”, the transmit buffer
empty flag and transmit shift completion flag are set to “1”.
Accordingly, even if the timing when any of the above flags is set
to “1” is selected for the transmit interrupt source, interrupt request
occurs and the transmit interrupt request bit is set.
(5) Write to the baud rate generator (BRGi) while the transmit/re-
ceive operation is stopped.
Can be set
with the LDM
instruction at
the same time
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Notes on Serial I/O1
1. I/O pin function when serial I/O1 is enabled.
The pin functions of P12/SCLK1 and P13/SRDY1 are switched to as
follows according to the setting values of a serial I/O1 mode selec-
tion bit (bit 6 of serial I/O1 control register (address 1A16)) and a
serial I/O1 synchronous clock selection bit (bit 1 of serial I/O1 con-
trol register).
(1) Serial I/O1 mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
• Setup of a serial I/O1 synchronous clock selection bit
“0” : P12 pin turns into an output pin of a synchronous clock.
“1” : P12 pin turns into an input pin of a synchronous clock.
• Setup of a SRDY1 output enable bit (SRDY)
“0” : P13 pin can be used as a normal I/O pin.
“1” : P13 pin turns into a SRDY1 output pin.
(2) Serial I/O1 mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
• Setup of a serial I/O1 synchronous clock selection bit
“0”: P12 pin can be used as a normal I/O pin.
“1”: P12 pin turns into an input pin of an external clock.
• When clock asynchronous (UART) type serial I/O is selected, it
functions P13 pin. It can be used as a normal I/O pin.
Note on Bus Collision Detection
When serial I/O1 is operating at half-duplex communication, set
bus collision detection interrupt to be disabled.
Notes on Serial I/O2
1. I/O pin function when serial I/O2 is enabled
The pin functions of P06/SCLK2 and P07/SRDY2 are switched to as
follows according to the setting values of a serial I/O2 mode selec-
tion bit (bit 6 of serial I/O2 control register (address 3016)) and a
serial I/O2 synchronous clock selection bit (bit 2 of serial I/O2 con-
trol register).
(1) Serial I/O2 mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
• Setup of a serial I/O2 synchronous clock selection bit
“0” : P06 pin turns into an output pin of a synchronous clock.
“1” : P06 pin turns into an input pin of a synchronous clock.
• Setup of a SRDY2 output enable bit (SRDY)
“0” : P07 pin can be used as a normal I/O pin.
“1” : P07 pin turns into a SRDY2 output pin.
(2) Serial I/O2 mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
• Setup of a serial I/O2 synchronous clock selection bit
“0”: P06 pin can be used as a normal I/O pin.
“1”: P06 pin turns into an input pin of an external clock.
• When clock asynchronous (UART) type serial I/O is selected, it
functions P07 pin. It can be used as a normal I/O pin.
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6. A/D conversion accuracy
As for AD translation accuracy, on the following operating condi-
tions, accuracy may become low.
(1) Since the analog circuit inside a microcomputer becomes sen-
sitive to noise when VREF voltage is set up lower than Vcc
voltage, accuracy may become low rather than the case
where VREF voltage and Vcc voltage are set up to the same
value..
(2) When VREF voltage is lower than [ 3.0 V ], the accuracy at the
low temperature may become extremely low compared with
that at room temperature. When the system would be used at
low temperature, the use at VREF=3.0 V or more is recom-
mended.
Notes on Watchdog Timer
1. The watchdog timer is operating during the wait mode. Write
data to the watchdog timer control register to prevent timer un-
derflow.
2. The watchdog timer stops during the stop mode. However, the
watchdog timer is running during the oscillation stabilizing time
after the STP instruction is released. In order to avoid the un-
derflow of the watchdog timer, the watchdog timer control
register must be written just before executing the STP instruc-
tion.
3. The STP instruction function selection bit (bit 6 of watchdog
timer control register (address 003916)) can be rewritten only
once after releasing reset. After rewriting it is disable to write
any data to this bit.
4. A count source of watchdog timer is affected by the clock divi-
sion selection bit of the CPU mode register.
The f(XIN) clock is supplied to the watchdog timer when select-
ing f(XIN) as the CPU clock.
The on-chip oscillator output is supplied to the watchdog timer
when selecting the on-chip oscillator output as the CPU clock.
Notes on RESET pin
1. Connecting capacitor
In case where the RESET signal rise time is long, connect a ce-
ramic capacitor or others across the RESET pin and the Vss pin.
And use a 1000 pF or more capacitor for high frequency use.
When connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor
as short as possible.
• Be sure to verify the operation of application products on the
user side.
<Reason>
If the several nanosecond or several ten nanosecond impulse
noise enters the RESET pin, it may cause a microcomputer fail-
ure.
Notes on A/D conversion
1. Analog input pin
Make the signal source impedance for analog input low, or equip
an analog input pin with an external capacitor of 0.01µF to 1µF.
Further, be sure to verify the operation of application products on
the user side.
<Reason>
An analog input pin includes the capacitor for analog voltage com-
parison. Accordingly, when signals from signal source with high
impedance are input to an analog input pin, charge and discharge
noise generates. This may cause the A/D conversion/comparison
precision to be worse.
2. Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of
the capacity will be lost if the clock frequency is too low. This may
cause the A/D conversion precision to be worse. Accordingly, set
f(XIN) in order that the A/D conversion clock is 250 kHz or over
during A/D conversion.
3. A/D conversion clock selection
Select f(XIN)/2 as an A/D conversion clock by setting the A/D con-
version clock selection bit (bit 3 of A/D control register (address
3416)) when RC oscillation is used.
The f(XIN) can be also used as an A/D conversion clock only when
ceramic oscillation or on-chip oscillator is used.
4. Analog input pin selection
P26/AN6 and P27/AN7 can be used only for PRSP0036GA-A pack-
age version.
5. Read A/D conversion register
• 8-bit read
Read only the A/D conversion low-order register (address 3516).
•10-bit read
Read the A/D conversion high-ordrer register (address 3616) first,
and then, read the A/D conversion low-order register (address
3516).
In this case, the high-order 6 bits of address 3616 returns “0”
when read.
7542 Group
Rev.3.03 Jul 11, 2008 Page 116 of 117
REJ03B0006-0303
Notes on Clock Generating Circuit
1. Switch of ceramic and RC oscillations
After releasing reset, the oscillation mode selection bit (bit 5 of
CPU mode register (address 3B16)) is “0” (ceramic oscillation se-
lected). When the RC oscillation is used, after releasing reset, set
this bit to “1”.
2. Double-speed mode
The double-speed mode can be used only when a ceramic oscilla-
tion is selected. Do not use it when an RC oscillation is selected.
3. CPU mode register
Oscillation mode selection bit (bit 5), processor mode bits (bits 1
and 0) of CPU mode register (address 3B16) are used to select os-
cillation mode and to control operation modes of the
microcomputer. In order to prevent the dead-lock by erroneously
writing (ex. program run-away), these bits can be rewritten only
once after releasing reset. After rewriting, it is disabled to write any
data to the bit. (The emulator MCU “M37542RSS” is excluded.)
Also, when the read-modify-write instructions (SEB, CLB, etc.) are
executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
4. Clock division ratio, XIN oscillation control, on-chip oscillator
control
The state transition shown in Fig. 84 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), XIN oscillation
control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of
CPU mode register. Be careful of notes on use in Fig. 84.
5. On-chip oscillator operation
When the MCU operates by the on-chip oscillator for the main
clock, connect XIN pin to VCC through a 1 kΩ to 10 kΩ resistor and
leave XOUT pin open.
The clock frequency of the on-chip oscillator depends on the sup-
ply voltage and the operation temperature range.
Be careful that this margin of frequencies when designing applica-
tion products.
6. Ceramic resonator
When the ceramic resonator is used for the main clock, connect
the ceramic resonator and the external circuit to pins XIN and
XOUT at the shortest distance. Externally connect a damping resis-
tor Rd depending on the oscillation frequency. A feedback resistor
is built-in.
Use the resonator manufacturer ’s recommended value because
constants such as capacitance depend on the resonator.
7. RC oscillation
When the RC oscillation is used for the main clock, connect the
XIN pin and XOUT pin to the external circuit of resistor R and the
capacitor C at the shortest distance.
The frequency is affected by a capacitor, a resistor and a micro-
computer.
So, set the constants within the range of the frequency limits.
8. External clock
When the external signal clock is used for the main clock, connect
the XIN pin to the clock source and leave XOUT pin open.
Select “0” (ceramic oscillation) to oscillation mode selection bit.
9. Count source (Timer 1, Timer A, Timer B, Timer X, Serial I/O,
Serial I/O2, A/D converter, Watchdog timer)
A count source of watchdog timer is affected by the clock divi-
sion selection bit of the CPU mode register.
The f(XIN) clock is supplied to the watchdog timer when select-
ing f(XIN) as the CPU clock.
The on-chip oscillator output is supplied to the watchdog timer
when selecting the on-chip oscillator output as the CPU clock.
Notes on Oscillation Control
1. Oscillation stop detection circuit
(1) When the stop mode is used, set the oscillation stop detection
function to “invalid”.
(2) When the ceramic or RC oscillation is stopped by the XIN oscil-
lation control bit (bit 4 of CPU mode register (address 3B16)),
set the oscillation stop detection function to “invalid”.
2. Stop mode
(1) When the stop mode is used, set the oscillation stop detection
function to “invalid”.
(2) When the stop mode is used, set “0” (STP instruction enabled)
to the STP instruction function selection bit of the watchdog
timer control register (bit 6 of watchdog timer control register
(address 3916)).
(3) The oscillation stabilizing time after release of STP instruction
can be selected from “set automatically ”/“not set automati-
cally” by the oscillation stabilizing time set bit after release of
the STP instruction (bit 0 of MISRG (address 3816)). When “0”
is set to this bit, “0116” is set to timer 1 and “FF16” is set to
prescaler 1 automatically at the execution of the STP instruc-
tion. When “1” is set to this bit, set the wait time to timer 1 and
prescaler 1 according to the oscillation stabilizing time of the
oscillation. Also, when timer 1 is used, set values again to
timer 1 and prescaler 1 after system is returned from the stop
mode.
(4) Do not execute the STP instruction during the A/D conversion.
7542 Group
Rev.3.03 Jul 11, 2008 Page 117 of 117
REJ03B0006-0303
Notes on On-chip Oscillation Division Ratio
• When the clock division ratio is switched from f(XIN) to on-chip
oscillator by the clock division ratio selection bits (bits 7 and 6 of
CPU mode register (address 3B16)), the on-chip oscillator divi-
sion ratio (bits 1 and 0 of on-chip oscillation division ratio
selection register (address 3716)) is “102” (on-chip oscillator
middle-speed mode (ROSC/8)).
Notes on Oscillation Stop Detection Circuit
1. After the reset by the oscillation stop detection, the value of fol-
lowing bits are retained, not initialized.
• Ceramic or RC oscillation stop detection function active bit
Bit 1 of MISRG (address 3B16)
• Oscillation stop detection status bit
Bit 3 of MISRG
2. Oscillation stop detection status bit is initialized (“0”) by the fol-
lowing operation.
• External reset
• Write “0” data to the ceramic or RC oscillation stop detection
function active bit.
3. The oscillation stop detection circuit is not included in the emu-
lator MCU “M37542RSS”.
Notes on CPU Rewrite Mode
Take the notes described below when rewriting the flash memory
in CPU rewrite mode.
1. Operation speed
During CPU rewrite mode, set the system clock φ to 4.0 MHz or
less using the clock division ratio selection bits (bits 6 and 7 of
CPU mode register).
2. Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode.
3. Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode because
they refer to the internal data of the flash memory.
4. Watchdog timer
If the watchdog timer has been already activated, internal reset
due to an underflow will not occur because the watchdog timer is
surely initialized during program or erase.
5. Reset
Reset is always valid. The MCU is activated using the boot mode
at release of reset in the condition of CNVss = “H”, so that the pro-
gram will begin at the address which is stored in addresses
FFFC16 and FFFD16 of the boot ROM area.
Electric Characteristic Differences Between
Mask ROM, Flash Memory MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation among mask ROM and flash
memory version MCUs due to the differences in the manufacturing
processes.
When manufacturing an application system with the flash memory
and then switching to use of the mask ROM version, perform suffi-
cient evaluations for the commercial samples of the mask ROM
version.
Note on Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the supply voltage is less than the
recommended operating conditions and design a system not to
cause errors to the system by this unstable operation.
NOTES ON HARDWARE
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suit-
able for high frequencies as bypass capacitor between power
source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the
capacitor to as close as possible. For bypass capacitor which
should not be located too far from the pins to be connected, a ce-
ramic capacitor of 0.01 µF to 0.1 µF is recommended.
REVISION HISTORY
Rev. Date Description
Page Summary
7542 Group Datasheet
1.00 Nov 27, 2002
2.00 Apr 21, 2003
2.01 Dec 03, 2003
2.02 Jan 06, 2004
First edition issued
FEATURES; Memory size revised.
Memory size; Flash memory size revised.
Fig.8; ROM size revised.
Table 2; ROM size revised.
Central Processing Unit (CPU); Description revised.
Fig.26; Port P03 direction register revised.
Fig.42; Modulation output revised.
Fig.43; Modulation output revised.
Reset Circuit; Description revised.
(3) RC oscillation; Description revised.
(1) Oscillation control
• Stop mode
Description about FLASH added.
Fig.77; revised.
FLASH MEMORY MODE added.
ELECTRICAL CHARACTERISTICS added.
FEATURES: Interrupt, Power source voltage, Power dissipation revised.
Fig. 8: Development schedule revised.
Table 2: ROM size for Flash memory version revised.
Fig. 12: Note added.
Fig. 14: Flash memory control register 2 added.
Fig. 26:
“CPU mode register” added, description for timer 1 interrupt request revised.
Fig. 29: “CPU mode register” added.
Fig. 37 and Fig. 38: Pin name added.
Fig. 39: Pin name added.
Fig. 46 and Fig. 47: Pin name added.
A-D Converter revised.
Fig. 70 Flash memory control register 2 added.
Fig. 79 (5), (6) revised.
■ A-D Converter revised.
DATA REQUIRED FOR MASK ORDERS revised.
Description of flash memory control register 0 (bit 2), Fig. 83 revised.
Description of flash memory control register 2, Fig. 85 and Table 8 added.
Fig. 86 revised.
Table 9 revised.
ELECTRICAL CHARACTERISTICS;
General purpose revised.
Extended operating temperature version added.
FEATURES: The minimum instruction execution time revised.
Note 2 eliminated.
Stack pointer (S): Reference number of Figure in description revised.
Table 12: P07 (BUSY output) added.
Fig. 95: “BUSY” added to P07.
Fig. 96, Fig. 97: “BUSY” added to P07.
Fig. 98, Fig. 99: CNVSS revised.
Table 19, Table 20 Timing requirements (General purpose)
Vcc for FLASH ROM version and Mask ROM version revised.
Table 22, Table 23 Switching characteristics (General purpose)
Vcc for FLASH ROM version and Mask ROM version revised.
–
1
8
9
10
28
36
37
53
55
56
57
65 to 72
73 to 82
1
8
9
13
15
28
30
33
34
40
51
54
59
64
65
68
69
70
71
85 to103
1
10
79
82
83
84
91
93
A - 1
REVISION HISTORY
Rev. Date Description
Page Summary
7542 Group Datasheet
2.03 Feb 10, 2004
2.04 Apr 14, 2004
2.05 Jun 08, 2004
2.06 Aug 24, 2004
Information about 36PJW-A package version added.
- Fig.4 Pin configuration added.
- Fig.9 Functional block diagram added.
- Table 1: Notes 2, 3 revised.
- 36PJW-A package added.
- Table 2 List of supported products revised.
- I/O Ports description and Fig. 19: Note revised.
- Table 5: Notes 2, 3 revised.
- INTEDGE revised.
- Fig.24: Note revised.
Table 12: P00–P03, P07 → P00–P03
Fig.100, Fig.101: td(CNVss-port) → th(CNVss-port)
Table 17: ICC data for FLASH ROM added.
Table 18: Absolute accuracy for FLASH ROM added.
Table 29: ICC data for FLASH ROM added.
Table 30: Absolute accuracy for FLASH ROM added.
Package: Description of 36PJW-A revised.
Table 2: M37542M2-XXXHP added.
Fig. 79, Fig. 80 a bit name revised.
Countermeasure against noise added.
(NOTES ON PERIPHERAL FUNCTIONS are included in APPENDIX at the end of
this data sheet.)
Part name revised.
36PJW-A package added.
APPENDIX added.
FEATURES • Programmable I/O ports, • A/D converter: Description added.
Fig.4: Pin 1 to Pin 3 revised. M37542F8HP: Note added.
Table 2: M37542F8HP: Note added.
Notes on A/D conversion added.
Table 7: Number of program/erase times revised.
Fig. 110: Figure title and table in figure revised, and Note added.
M37542F8HP: Note added.
Notes on A/D accuracy added.
Notes on Oscillation Stop Detection Circuit
1: • Each bit of Port register Pi eliminated.
Note on Power Source Voltage added.
Words standardized: On-chip oscillator, A/D converter
Fig. 97: Bits 0 to 3 revised.
(1) ROM Code Protect Function: Some description added.
● Standard serial I/O Mode: Some description revised.
Description of standard serial I/O mode 1 and standard serial I/O mode 2 separated.
Fig. 107 Handling example of control pins in standard serial I/O mode 1 added.
Fig. 112 Handling example of control pins in standard serial I/O mode 2 added.
3
8
9
10
11
18
19
23
26
81
86
91
92
101
102
10
11
60
65 to 68
88
108
109 to 118
1
3
11
53
70
88
89
117
119
All pages
73
79
82
83 to 92
86
91
A - 2
REVISION HISTORY
Rev. Date Description
Page Summary
7542 Group Datasheet
3.00 Jun 01, 2005
3.01 Nov 02, 2005
ROM size of Flash memory version revised.
Fig.1 M37542F8GP → M37542FxGP
Fig.2 M37542F8FP → M37542FxFP
Fig.3 M37542F8SP → M37542FxSP
Table 1 Performance overview added.
Table 2 Function of Vcc, Vss revised.
Flash memory size revised, and Fig.10 M37542F4 added.
Table 3 M37542F4GP,M37542F4FP,M37542F4SP added.
Fig. 20 (5) Port P05 revised.
Table 7 Termination of unused pins added.
Description of Serial I/O revised.
[UART2 control register (UART2CON)] revised.
Fig. 64 UART2 contorl register revised.
Description of Clock Generating Circuit revised. Fig. 74 revised.
Fig. 79 revised.
Table 9 Temperature at program/erase added.
Fig.94 16 Kbyte ROM Product added.
Table 11 List of software commands (CPU rewrite mode) revised.
Fig.104 M37542F8GP → M37542FxGP
Fig.105 M37542F8SP → M37542FxSP
Fig.106 M37542F8FP → M37542FxFP
Fig.109 M37542F8GP → M37542FxGP
Fig.110 M37542F8SP → M37542FxSP
Fig.111 M37542F8FP → M37542FxFP
M37542F4GP,M37542F4FP,M37542F4SP added.
Table 15 Conditions: Description added.
Table 18 Note 1 added.
Table 20, Fig. 104 added.
Table 28 Conditions: Description added.
Table 31 Note 1 added.
Table 34, Fig. 106 added.
Extended operating temperature 125 °C version added.
(2) How to reference the processor status register revised.
Fig. 2 revised.
Package revised.
Bit name revised: STP instruction disable bit → STP instruction function selection bit
- Description for “Operation of STP instruction function selection bit” revised.
- Notes on Watchdog Timer added.
- Fig.68: Blodk diagram of watchdog timer revised.
- Fig.69: Bit 6 and Bit 7 of WDTCON revised.
Bit 6: Bit name and its description revised. (Bit function is not changed.)
→ STP instruction function selection bit
0 : System enters into the stop mode at the STP instruction execution
1 : Internal reset occurs at the STP instruction execution
-Notes on Clock Generating Circuit : Note on Count source added.
Notes on Watchdog Timer : Note on Count source added.
Notes on Clock Generating Circuit : Note on Count source added.
1
2
3
5
10
11
12
21
24
46
53
54
60
63
72
73
77
86
87
91
92
95
98
100
105
108
110
114-122
125
-
-
57
61
132
133
A - 3
REVISION HISTORY
Rev. Date Description
Page Summary
7542 Group Datasheet
A - 4
3.02 Oct 31, 2006
3.03 Jul 11, 2008
Table 3 : ROM size revised and note 2 added.
ROM : Description added.
Fig. 15 : Note 2 added.
Table 7 : XIN and XOUT added.
Notes on Watchdog Timer : Note 3 revised.
5. Setup for I/O ports : Note eliminated.
Fig 94 : Block diagram revised and note 3 added.
4. BRK instruction eliminated.
1. Analog input pin : Description revised.
FEATURES: Description revised.
DESCRIPTION, FEATURES: “serial I/O” → “serial interface”
APPLICATION: “car” deleted.
Fig. 1, Fig. 2 revised.
Table 1: Parameter revised, Note 1 deleted.
Table 2: Note 1 deleted.
Fig. 10 revised.
Table 3 revised.
Fig. 20 revised.
Fig. 21 revised.
Interrupts revised.
“Serial I/O” → “Serial interface”
• Oscillation stop detection circuit: Description revised
Fig. 101: Note 2, Note 3 revised.
Fig. 107 revised.
Fig. 108, Fig. 109 revised.
Fig. 112 revised.
Fig. 113 revised.
ELECTRICAL CHARACTERISTICS:
1.7542Group (General purpose); Description revised, “(General purpose)” deleted
2.7542Group (Extended operating temperature version),
3.7542Group (Extended operating temperature 125 °C version) deleted.
Notes on Timer A, B: “(bit 0 (bit 2 of timer .... (address 1D16))” deleted.
12
17
24
57, 132
71
73
125
132
1
2
5
10
11
12
21
22
25 to 29
47
66
77
87
88
92
93
96 to 105
111
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