W49F002U
256K × 8 CMOS FLASH MEMORY
Publication Release Date: April 2000
- 1 - Revision A2
GENERAL DESCRIPTION
The W49F002U is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W49F002U results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory
products). The device can also be programmed and erased using standard EPROM programmers.
FEATURES
• Single 5-volt operations:
− 5-volt Read
− 5-volt Erase
− 5-volt Program
• Fast Program operation:
− Byte-by-Byte programming: 35 µS (typ.)
• Fast Erase operation: 100 mS (typ.)
• Fast Read access time: 70/90/120 nS
• Endurance: 10K cycles (typ.)
• Ten-year data retention
• Hardware data protection
• One 16K byte Boot Block with Lockout
protection
• Two 8K byte Parameter Blocks
• Two Main Memory Blocks (96K, 128K) Bytes
• Low power consumption
− Active current: 25 mA (typ.)
− Standby current: 20 µA (typ.)
• Automatic program and erase timing with
internal VPP generation
• End of program or erase detection
− Toggle bit
− Data polling
• Latched address and data
• TTL compatible I/O
• JEDEC standard byte-wide pinouts
• Available packages: 32-pin DIP and 32-pin
TSOP and 32-pin-PLCC
W49F002U
- 2 -
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DQ0
DQ1
DQ2
GND
A7
A6
A5
A4
A3
A2
A1
A0
A16
A15
A12
V
WE
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DD
A17
32-pin
DIP
RESET
5
6
7
9
10
11
12
13
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
29
28
27
26
25
24
23
22
21
3031
32
12
3
4
8
20191817161514
D
Q
1
D
Q
2
G
N
D
D
Q
3
D
Q
4
D
Q
5
D
Q
6
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
A
1
2
A
1
6
V
D
D
/
W
E
A
1
5
32-pin
PLCC
A
1
7
/
R
E
S
E
T
32-pin
TSOP
1
2
3
4
5
6
7
8
9
10
11
14
15
16
A15
A12
A7
A6
A5
A4
V
WE
A14
A13
A8
DD
A11
A9
A16
A17
RESET
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BLOCK DIAGRAM
CONTROL OUTPUT
BUFFER
DECODER
CE
OE
WE
A0
.
.
A17
.
.
DQ0
VDD
VSS
DQ7
3FFFF
20000
1FFFF
38000
37FFF
3A000
39FFF
00000
3C000
3BFFF
RESET
PARAMETER
BLOCK2
8K BYTES
BOOT BLOCK
16K BYTES
PARAMETER
BLOCK1
8K BYTES
MAIN MEMORY
BLOCK2
128K BYTES
MAIN MEMORY
BLOCK1
96K BYTES
PIN DESCRIPTION
SYMBOL PIN NAME
RESET Reset
A0−A17 Address Inputs
DQ0−DQ7 Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
VDD Power Supply
GND Ground
W49F002U
Publication Release Date: April 2000
- 3 - Revision A2
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W49F002U is controlled by
CE
and
OE
, both of which have to be low for
the host to obtain data from the outputs.
CE
is used for device selection. When
CE
is high, the chip
is de-selected and only standby power will be consumed.
OE
is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either
CE
or
OE
is high.
Refer to the timing waveforms for further details.
Reset Operation
The reset input pin can be used in some application. When RESET pin is at high state, the device is
in normal operation mode. When RESET pin is at low state, it will halts the device and all outputs are
at high impedance state. As the high state re-asserted to the RESET pin, the device will return to
read or standby mode, it depends on the control signals. When the system drives the RESET pin low
for at least a period of 500 nS, the device immediately terminates any operation in progress duration
of the RESET pulse. The other function for RESET pin is temporary reset the boot block. By
applying the 12V to RESET pin, the boot block can be reprogrammed even though the boot block
lockout function is enabled.
Boot Block Operation
There is one 16K-byte boot block in this device, which can be used to store boot code. It is located in
the last 16K bytes with the address range of the boot block is 3C000(hex) to 3FFFF(hex).See
Command Code sequence for Boot Block Lockout Enable for the specific code. Once this feature is
set the data for the designated block cannot be erased or programmed (programming lockout); other
memory locations can be changed with the regular programming method. Once the boot block
programming lockout feature is activated, the chip erase function can no longer erase the boot block.
There is one condition that the lockout feature can be overridden. Just apply 12V to RESET pin, the
lockout feature will temporarily be inactivated and the block can be erased/programmed. Once the
RESET pin return to TTL level, the lockout feature will be activated again.
In order to detect whether the boot block feature is set on the 16K-bytes block, users can perform
software command code sequence: enter the product identification mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address "0002
(hex)". If the DQ0 of output data is "1," the boot block programming lockout feature is activated; if the
DQ0 of output data is "0 ," the lockout feature is inactivated and the block can be
erased/programmed.
To return to normal operation, perform a three-byte command code sequence (or an alternate single-
byte command) to exit the identification mode. For the specific code, see Command Code for
Identification/Boot Block Lockout Detection.
Chip Erase Operation
The chip-erase mode can be initiated by a six-byte command code sequence. After the command
loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed as fast as 100 mS (typical). The host system is not required to provide any control or
timing during this operation. The entire memory array will be erased to FF hex. by the chip erase
W49F002U
- 4 -
operation if the boot block programming lockout feature is not activated. Once the boot block lockout
feature is activated, the whole chip erase function will erase the two main memory blocks and the two
parameter blocks but not the boot block. The device will automatically return to normal read mode
after the erase operation. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
Sector Erase Operation
There are four sectors: two main memory blocks and two parameters blocks which can be erased
individually by initiating a six-byte command code sequence. Sector address is latched on the falling
edge of
WE
signal in the sixth cycle while the data input "30(hex)" is latched at the rising edge of
WE
in this cycle. After the command loading cycle, the device enters the internal sector erase mode,
which is automatically timed and will be completed as fast as 100 mS (typical). The host system does
not require to provide any control or timing during this operation. The device will automatically return
to normal read mode after the erase operation. Data polling and/or Toggle Bits can be used to detect
the end of erase cycle.
When different sector address is loaded in the sixth cycle for sector erase command, the
correspondent sectors will be erased automatically; that these sections will be erased independedntly.
For detail sector to be erased information, please refer to the Table of Command Definition.
Program Operation
The W49F002U is programmed on a byte-by-byte basis. Program operation can only change logical
data "1" to logical data "0". The erase operation (changed entire data in two main memory blocks and
two parameter blocks and/or boot block from "0" to "1") is needed before programming.
The program operation is initiated by a 4-byte command code sequence (see Command Codes for
Byte Programming). The device will internally enter the program operation immediately after the byte-
program command is entered. The internal program timer will automatically time-out (50 µS max. -
TBP). Once completed, the device returns to normal read mode. Data polling and/or Toggle Bits can
be used to detect end of program cycle.
Hardware Data Protection
The integrity of the data stored in the W49F002U is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A
WE
pulse of less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than
2.5V typical.
(3) Write Inhibit Mode: Forcing
OE
low,
CE
high, or
WE
high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out
5 mS before any write (erase/program) operation.
Data Polling (DQ7)- Write Status Detection
The W49F002U includes a data polling feature to indicate the end of a program or erase cycle.
When the W49F002U is in the internal program or erase cycle, any attempt to read DQ7 of the last
byte loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle,
and become logical "1" or true data when the erase cycle has been completed.
W49F002U
Publication Release Date: April 2000
- 5 - Revision A2
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W49F002U provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will
produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between
0's and 1's will stop. The device is then ready for the next operation.
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a three-byte (or JEDEC 3-byte) command sequence can be used to access
the product ID. A read from address 0000H outputs the manufacturer code DA(hex). A read from
address 0001H outputs the device code 0B(hex). The product ID operation can be terminated by a
three-byte command code sequence or an alternate one-byte command code sequence (see
Command Definition table).
In the hardware access mode, access to the product ID is activated by forcing
CE
and
OE
low,
WE
high, and raising A9 to 12 volts.
TABLE OF OPERATING MODES
Operating Mode Selection
(VHH = 12V ± 5%)
MODE PINS
RESET
CE
OE
WE
ADDRESS DQ.
Read VIH VIL VIL VIH AIN Dout
Write VIH VIL VIH VIL AIN Din
Standby VIH VIH X X X High Z
Write Inhibit VIH X VIL X X High Z/DOUT
VIH X X VIH X High Z/DOUT
Output Disable VIH X VIH X X High Z
Reset Mode VIL X X X X High Z
Product ID VIH VIL VIL VIH A0 = VIL; A1−A17 = VIL;
A9 = VHH Manufacturer Code DA (Hex)
VIH VIL VIL VIH A0 = VIH; A1−A17 = VIL;
A9 = VHH Device Code 0B (Hex)
W49F002U
- 6 -
TABLE OF COMMAND DEFINITION(1)
COMMAND NO.
OF 1ST
CYCLE 2ND
CYCLE 3RD
CYCLE 4TH
CYCLE 5TH
CYCLE 6TH
CYCLE
DESCRIPTION Cycles
Addr. Data
Addr. Data
Addr. Data
Addr. Data
Addr. Data
Addr. Data
Read 1 AIN DOUT
Chip Erase 6 5555 AA
2AAA 55
5555 80 5555 AA
2AAA 55 5555 10
Sector Erase 6 5555 AA
2AAA 55
5555 80 5555 AA
2AAA 55 SA(3) 30
Byte Program 4 5555 AA
2AAA 55
5555 A0 AIN DIN
Boot Block Lockout 6 5555 AA
2AAA 55
5555 80 5555 AA
2AAA 55 5555 40
Product ID Entry 3 5555 AA
2AAA 55
5555 90
Product ID Exit (2) 3 5555 AA
2AAA 55
5555 F0
Product ID Exit (2) 1 XXXX F0
Notes:
1. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex)
2. Either one of the two Product ID Exit commands can be used.
3. SA means: Sector Address
If SA is within 3C000 to 3FFFF (Boot Block address range), and the Boot Block programming lockout feature is activated,
nothing will happen and the device will go back to read mode after 100nS.
If the Boot Block programming lockout feature is not activated, this command will erase Boot Block.
If SA is within 3A000 to 3BFFF (Parameter Block1 address range), this command will erase PB1.
If SA is within 38000 to 39FFF (Parameter Block2 address range), this command will erase PB2.
If SA is within 20000 to 37FFF (Main Memory Block1 address range), this command will erase MMB1.
If SA is within 00000 to 1FFFF (Main Memory Block2 address range), this command will erase MMB2.
W49F002U
Publication Release Date: April 2000
- 7 - Revision A2
Command Codes for Byte Program
COMMAND SEQUENCE ADDRESS DATA
0 Write 5555H AAH
1 Write 2AAAH 55H
2 Write 5555H A0H
3 Write Programmed-address Programmed-data
Byte Program Flow Chart
Byte Program
Command Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data A0
to
address 5555
Load data Din
to
programmed-
address
Exit
Pause TBP
Notes for software program code:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)
W49F002U
- 8 -
Command Codes for Chip Erase
BYTE SEQUENCE ADDRESS DATA
1 Write 5555H AAH
2 Write 2AAAH 55H
3 Write 5555H 80H
4 Write 5555H AAH
5 Write 2AAAH 55H
6 Write 5555H 10H
Chip Erase Acquisition Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Exit
Load data 10
to
address 5555
Pause TEC
Notes for chip erase:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)
W49F002U
Publication Release Date: April 2000
- 9 - Revision A2
Command Codes for Sector Erase
BYTE SEQUENCE ADDRESS DATA
1 Write 5555H AAH
2 Write 2AAAH 55H
3 Write 5555H 80H
4 Write 5555H AAH
5 Write 2AAAH 55H
6 Write SA* 30H
Sector Erase Acquisition Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 30
to
address SA*
Exit
Pause TEC
Notes for chip erase:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)
SA : For details, see the page 6 .
W49F002U
- 10 -
Command Codes for Product Identification and Boot Block Lockout Detection
BYTE
SEQUENCE SOFTWARE PRODUCT
IDENTIFICATION/BOOT BLOCK
LOCKOUT DETECTION ENTRY
SOFTWARE PRODUCT
IDENTIFICATION/BOOT BLOCK
LOCKOUT DETECTION EXIT(6)
ADDRESS DATA ADDRESS DATA
1 Write 5555 AA 5555H AAH
2 Write 2AAA 55 2AAAH 55H
3 Write 5555 90 5555H F0H
Pause 10 µS Pause 10 µS
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
Product
Identification
Entry (1)
Load data 55
to
address 2AAA
Load data 90
to
address 5555
Pause 10 S
Product
Identification
and Boot Block
Lockout Detection
Mode (3)
Read address = 0000
data = DA
Read address = 0001
Read address = 0002
data =in DQ0= "1" / "0"
(4)
Product
Identification Exit(6)
Load data 55
to
address 2AAA
Load data F0
to
address 5555
Normal Mode (5)
(2)
(2)
Load data AA
to
address 5555
µµ
Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex)
(2) A1−A17 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
(3) The device does not remain in identification and boot block lockout detection mode if power down.
(4) If the output data in DQ0= " 1 " the boot block programming lockout feature is activated; if the output data in DQ0 = " 0 ,"
the lockout feature is inactivated and the boot block can be programmed.
(5) The device returns to standard operation mode.
(6) Optional 1-byte cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout
detection.
W49F002U
Publication Release Date: April 2000
- 11 - Revision A2
Command Codes for Boot Block Lockout Enable
BYTE SEQUENCE ADDRESS DATA
0 Write 5555H AAH
1 Write 2AAAH 55H
2 Write 5555H 80H
3 Write 5555H AAH
4 Write 2AAAH 55H
5 Write 5555H 40H
Pause TBP
Boot Block Lockout Enable Acquisition Flow
Boot Block Lockout
Feature Set Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 40
to
address 5555
Exit
Pause TBP
Notes for boot block lockout enable:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)
W49F002U
- 12 -
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Power Supply Voltage to Vss Potential -0.5 to +7.0 V
Operating Temperature 0 to +70 °C
Storage Temperature -65 to +150 °C
D.C. Voltage on Any Pin to Ground Potential except
OE
-0.5 to VDD +1.0 V
Transient Voltage (<20 nS ) on Any Pin to Ground Potential -1.0 to VDD +1.0 V
Voltage on
OE
Pin to Ground Potential -0.5 to 12.5 V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
DC Operating Characteristics
(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)
PARAMETER SYM.
TEST CONDITIONS LIMITS UNIT
MIN.
TYP.
MAX.
Power Supply
Current ICC
CE
=
OE
= VIL,
WE
= VIH, all DQs open
Address inputs = VIL/VIH, at f = 5 MHz
- 25 50 mA
Standby VDD
Current (TTL input) ISB1
CE
= VIH, all DQs open
Other inputs = VIL/VIH
- 2 3 mA
Standby VDD
Current
(CMOS input)
ISB2
CE
= VDD -0.3V, all DQs open
Other inputs = VDD -0.3V/GND
- 20 100 µA
Input Leakage
Current ILI VIN = GND to VDD - - 10 µA
Output Leakage
Current ILO VOUT = GND to VDD - - 10 µA
Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.0 - VDD +0.5
V
Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage VOH IOH = -0.4 mA 2.4 - - V
W49F002U
Publication Release Date: April 2000
- 13 - Revision A2
Power-up Timing
PARAMETER SYMBOL TYPICAL UNIT
Power-up to Read Operation TPU. READ 100 µS
Power-up to Write Operation TPU. WRITE 5 mS
CAPACITANCE
(VDD = 5.0V, TA = 25° C, f = 1 MHz)
PARAMETER SYMBOL CONDITIONS MAX. UNIT
I/O Pin Capacitance CI/O VI/O = 0V 12 pf
Input Capacitance CIN VIN = 0V 6 pf
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise/Fall Time < 5 nS
Input/Output Timing Level 1.5V/1.5V
Output Load 1 TTL Gate and CL = 100 pF for 120 nS;
CL = 30 pF for 70 nS /90 nS
AC Test Load and Waveform
+5V
1.8K
1.3K
DOUT
Ω
Ω
30 pF for 70nS / 90nS
(Including Jig and Scope)
Input
3V
0V
Test Point Test Point
1.5V 1.5V
Output
100 pF for 120nS
W49F002U
- 14 -
AC Characteristics, continued
Read Cycle Timing Parameters
(VCC = 5.0V ±10%, VCC = 0V, TA = 0 to 70° C)
PARAMETER SYM.
W49F002U-70
W49F002U-90
W49F002U-120
UNIT
MIN. MAX.
MIN. MAX.
MIN. MAX.
Read Cycle Time TRC 70 - 90 - 120 - nS
Chip Enable Access Time TCE - 70 - 90 - 120 nS
Address Access Time TAA - 70 - 90 - 120 nS
Output Enable Access Time TOE - 35 - 40 - 50 nS
CE Low to Active Output TCLZ 0 - 0 - 0 - nS
OE Low to Active Output TOLZ 0 - 0 - 0 - nS
CE
High to High-Z Output TCHZ - 25 - 25 - 30 nS
OE
High to High-Z Output TOHZ - 25 - 25 - 30 nS
Output Hold from Address Change TOH 0 - 0 - 0 - nS
Write Cycle Timing Parameters
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Address Setup Time TAS 0 - - nS
Address Hold Time TAH 50 - - nS
WE and CE Setup Time TCS 0 - - nS
WE and CE Hold Time TCH 0 - - nS
OE High Setup Time TOES 0 - - nS
OE High Hold Time TOEH 0 - - nS
CE Pulse Width TCP 100 - - nS
WE Pulse Width TWP 100 - - nS
WE High Width TWPH 100 - - nS
Data Setup Time TDS 50 - - nS
Data Hold Time TDH 10 - - nS
Byte Programming Time TBP - 35 50 µS
Erase Cycle Time TEC - 0.1 0.2 S
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
W49F002U
Publication Release Date: April 2000
- 15 - Revision A2
AC Characteristics, continued
Data Polling and Toggle Bit Timing Parameters
PARAMETER SYM.
W49F002U-70
W49F002U-90
W49F002U-120
UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
OE
to Data Polling Output Delay TOEP - 35 - 40 - 50 nS
CE
to Data Polling Output Delay TCEP - 70 - 90 - 120 nS
OE
to Toggle Bit Output Delay TOET - 35 - 40 - 50 nS
CE
to Toggle Bit Output Delay TCET - 70 - 90 - 120 nS
TIMING WAVEFORMS
Read Cycle Timing Diagram
Address A17-0
DQ7-0 Data Valid
Data Valid
High-Z
CE
OE
WE
TRC
VIH
TCLZ
TOLZ
TOE
TCE
TOH
TAA
TCHZ
TOHZ
High-Z
W49F002U
- 16 -
Timing Waveforms, continued
WE
Controlled Command Write Cycle Timing Diagram
Address A17-0
DQ7-0 Data Valid
CE
OE
WE
TAS
TCS
TOES
TAH
TCH
TOEH
TWPH
TWP
TDS
TDH
CE
Controlled Command Write Cycle Timing Diagram
High Z Data Valid
CE
OE
WE
DQ7-0
TAS TAH
TCPH
TOEH
TDH
TDS
TCP
TOES
Address A17-0
W49F002U
Publication Release Date: April 2000
- 17 - Revision A2
Timing Waveforms, continued
Program Cycle Timing Diagram
Address A17-0
Byte 0 Byte 1
Byte 2 Internal Write Start
DQ7-0
CE
OE
WE
Byte Program Cycle
TBP
TWPH
TWP
5555 55552AAA
AA A055
Address
Data-In
Byte 3
DATA
Polling Timing Diagram
Address A17-0
DQ7
WE
OE
CE
X X X X
TCEP
TOEH
TOEP
TOES
TECTBP or
An An An An
W49F002U
- 18 -
Timing Waveforms, continued
Toggle Bit Timing Diagram
Address A17-0
DQ6
CE
OE
WE
TOEH TOES
TBP orTEC
Boot Block Lockout Enable Timing Diagram
SB2
SB1
SB0
Address A17-0
DQ7-0
CE
OE
WE
SB3 SB4 SB5
Six byte code for Boot Block
Lockout Feature Enable
TEC
TWP
TWPH
5555 2AAA 5555 5555 2AAA 5555
AA 55 80 AA 55 40
W49F002U
Publication Release Date: April 2000
- 19 - Revision A2
Timing Waveforms, continued
Chip Erase Timing Diagram
SB2
SB1
SB0
Address A17-0
DQ7-0
CE
OE
WE
SB3 SB4 SB5 Internal Erase starts
Six-byte code for 5V-only software
chip erase
TWP
TWPH
TEC
5555 2AAA 5555 5555 2AAA 5555
AA 55 80 AA 55 10
Sector Erase Timing Diagram
SB2
SB1
SB0
Address A17-0
DQ7-0
CE
OE
WE
SB3 SB4 SB5 Internal Erase starts
Six-byte code for 5V-only software
Main Memory Erase
TWP
TWPH
TEC
5555 2AAA 5555 5555 2AAA SA
AA 55 80 AA 55 30
SA = Sector Address
W49F002U
- 20 -
ORDERING INFORMATION
PART NO.
ACCESS
TIME
(n
S)
POWER
SUPPLY
CURRENT
MAX.
(mA)
STANDBY
VDD
CURRENT
MAX.
(
µ
A)
PACKAGE CYCLE
W49F002U-70B 70 50 100 (CMOS) 32-pin DIP 10K
W49F002U-90B 90 50 100 (CMOS) 32-pin DIP 10K
W49F002U-12B 120 50 100 (CMOS) 32-pin DIP 10K
W49F002UT70B 70 50 100 (CMOS) 32-pin TSOP (8 mm × 20 mm) 10K
W49F002UT90B 90 50 100 (CMOS) 32-pin TSOP (8 mm × 20 mm) 10K
W49F002UT12B 120 50 100 (CMOS) 32-pin TSOP (8 mm × 20 mm) 10K
W49F002UP70B 70 50 100 (CMOS) 32-pin PLCC 10K
W49F002UP90B 90 50 100 (CMOS) 32-pin PLCC 10K
W49F002UP12B 120 50 100 (CMOS) 32-pin PLCC 10K
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
3. Winbond withholds a Boot Block options for Bottom Boot use. Please contact Winbond FAEs for detail information.
W49F002U
Publication Release Date: April 2000
- 21 - Revision A2
PACKAGE DIMENSIONS
32-pin P-DIP
1.Dimensions D Max. & S include mold flash or
tie bar burrs.
2.Dimension E1 does not include interlead flash.
3.Dimensions D & E1 include mold mismatch and
are determined at the mold parting line.
6.General appearance spec. should be based on
final visual inspection spec.
.
1.371.22
0.0540.048
Notes:
Symbol Min. Nom. Max. Max.Nom.Min.
Dimension in inches Dimension in mm
A
B
c
D
e
A
L
S
A
A1
2
E
0.050 1.27
0.210 5.33
0.010
0.150
0.016
0.155
0.018
0.160
0.022
3.81
0.41
0.25
3.94
0.46
4.06
0.56
0.008
0.120
0.670
0.010
0.130
0.014
0.140
0.20
3.05
0.25
3.30
0.36
3.56
0.555
0.550
0.545 14.10
13.9713.84
17.02
15.24
14.99 15.49
0.6000.590 0.610
2.29 2.54 2.790.090 0.100 0.110
B1
1
e
E1
a
1.650 1.660 41.91 42.16
0 15
0.085 2.16
0.6500.630 16.00 16.51
protrusion/intrusion.
4.Dimension B1 does not include dambar
5.Controlling dimension: Inches
150
Seating Plane
eA
2
A
a
c
E
Base Plane
1A
1
e
L
A
S
1E
D
1
B
B
32
116
17
32-pin PLCC
Notes:
L
c
1b
2A
H
E
E
eb
DHD
y
A
A1
Seating Plane
E
G
GD
1
13
14 20
29
324
5
21
30
1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches
4. General appearance spec. should be based on final
visual inspection sepc.
Symbol Min. Nom. Max. Max.Nom.Min.
Dimension in Inches Dimension in mm
A
b
c
D
e
HE
L
y
A
A1
2
E
b1
GD
3.56
0.50
2.802.67 2.93
0.71
0.66 0.81
0.41 0.46 0.56
0.20 0.25 0.35
13.89 13.97 14.05
11.35 11.43 11.51
1.27
HD
GE
12.45 12.9
5
13.46
9.91 10.41 10.92
14.86 14.99 15.11
12.32 12.45 12.57
1.91 2.29
0.004
0.095
0.090
0.075
0.495
0.49
0
0.485
0.595
0.590
0.585
0.430
0.410
0.390
0.5300.51
0
0.490
0.050
0.453
0.450
0.447
0.553
0.550
0.547
0.014
0.010
0.008
0.022
0.018
0.016
0.0320.026 0.028
0.1150.105 0.110
0.020
0.140
1.12 1.420.044 0.056
0°10°10°
0°
0.10
2.41
θ
θ
W49F002U
- 22 -
Package Dimensions, continued
32-pin TSOP
A
A
A
2
1
L
L1Y
c
E
H
D
D
b
e
M
0.10(0.004)
θ
Min. Nom. Max. Min. Nom. Max.
Symbol
A
A
b
c
D
E
e
L
L
Y
1
1
2
A
HD
Note:
Controlling dimension: Millimeters
Dimension in Inches
0.047
0.006
0.041
0.039
0.037
0.007 0.008 0.009
0.005 0.006 0.007
0.720 0.724 0.728
0.311 0.315 0.319
0.780 0.787 0.795
0.020
0.016 0.020 0.024
0.031
0.000 0.004
13 5
0.002
1.20
0.05 0.15
1.051.00
0.95
0.17
0.12
18.30
7.90
19.80
0.40
0.00
1
0.20 0.23
0.15 0.17
18.40 18.50
8.00 8.10
20.00 20.20
0.50
0.50 0.60
0.80
0.10
35
Dimension in mm
θ
__ __ __ __
__ __
__ __
__ __
__
__
__
__
__
__
W49F002U
Publication Release Date: April 2000
- 23 - Revision A2
VERSION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 Nov. 1999 - Renamed from W49F002/B/U/N
A2 Apr. 2000 1, 13−15, 20 Add the 120 nS bin
14 Change Tbp(typ.) from 10 µS to 35 µS
Change Tec(max.) from 1 Sec to 0.2 Sec
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Note: All data and specifications are subject to change without notice.