W49F002U 256K x 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W49F002U is a 2-megabit, 5-volt only CMOS flash memory organized as 256K x 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49F002U results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. FEATURES * Single 5-volt operations: - 5-volt Read - 5-volt Erase - 5-volt Program * Two Main Memory Blocks (96K, 128K) Bytes * Low power consumption - Active current: 25 mA (typ.) - Standby current: 20 A (typ.) * Automatic program and erase timing with internal VPP generation * End of program or erase detection * Fast Program operation: - Byte-by-Byte programming: 35 S (typ.) * Fast Erase operation: 100 mS (typ.) * Fast Read access time: 70/90/120 nS * Endurance: 10K cycles (typ.) * Ten-year data retention * Latched address and data * Hardware data protection * TTL compatible I/O * One 16K byte Boot Block with Lockout protection * JEDEC standard byte-wide pinouts * * Available packages: 32-pin DIP and 32-pin Two 8K byte Parameter Blocks - Toggle bit - Data polling TSOP and 32-pin-PLCC -1- Publication Release Date: April 2000 Revision A2 W49F002U PIN CONFIGURATIONS BLOCK DIAGRAM VDD RESET 1 32 VDD A16 2 31 WE A15 3 30 A17 A12 4 29 A14 CE A7 5 28 A13 OE 27 A8 A6 6 A5 7 A4 8 26 A9 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 GND 16 17 DQ3 32-pin DIP VSS CONTROL WE / R E S E T 4 3 1 32 31 30 2 V / D W D E . DECODER PARAMETER BLOCK1 8K BYTES PARAMETER BLOCK2 8K BYTES A 1 7 MAIN MEMORY BLOCK1 96K BYTES A7 5 29 A14 A6 6 28 A13 A5 7 27 A8 A4 8 26 A9 32-pin PLCC DQ7 BOOT BLOCK 16K BYTES A0 A17 A A 1 1 5 6 DQ0 . . RESET . A 1 2 OUTPUT BUFFER MAIN MEMORY BLOCK2 128K BYTES A3 9 25 A11 A2 10 24 OE A1 11 23 A10 A0 12 22 DQ0 13 21 CE DQ7 14 15 16 17 18 19 20 D D G Q Q N 1 2 D D Q 3 D Q 4 D Q 5 D Q 6 PIN DESCRIPTION SYMBOL A11 A9 A8 A13 A14 A17 WE V DD RESET A16 A15 A12 A7 A6 A5 A4 1 2 32 31 30 3 4 5 6 7 8 9 10 11 12 13 14 15 16 29 28 27 32-pin TSOP 26 25 24 23 22 21 20 19 18 17 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 RESET Reset A0-A17 Address Inputs DQ0-DQ7 -2- PIN NAME Data Inputs/Outputs CE Chip Enable OE Output Enable WE VDD Write Enable GND Ground Power Supply 3FFFF 3C000 3BFFF 3A000 39FFF 38000 37FFF 20000 1FFFF 00000 W49F002U FUNCTIONAL DESCRIPTION Read Mode The read operation of the W49F002U is controlled by CE and OE, both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the timing waveforms for further details. Reset Operation The reset input pin can be used in some application. When RESET pin is at high state, the device is in normal operation mode. When RESET pin is at low state, it will halts the device and all outputs are at high impedance state. As the high state re-asserted to the RESET pin, the device will return to read or standby mode, it depends on the control signals. When the system drives the RESET pin low for at least a period of 500 nS, the device immediately terminates any operation in progress duration of the RESET pulse. The other function for RESET pin is temporary reset the boot block. By applying the 12V to RESET pin, the boot block can be reprogrammed even though the boot block lockout function is enabled. Boot Block Operation There is one 16K-byte boot block in this device, which can be used to store boot code. It is located in the last 16K bytes with the address range of the boot block is 3C000(hex) to 3FFFF(hex).See Command Code sequence for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed with the regular programming method. Once the boot block programming lockout feature is activated, the chip erase function can no longer erase the boot block. There is one condition that the lockout feature can be overridden. Just apply 12V to RESET pin, the lockout feature will temporarily be inactivated and the block can be erased/programmed. Once the RESET pin return to TTL level, the lockout feature will be activated again. In order to detect whether the boot block feature is set on the 16K-bytes block, users can perform software command code sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address "0002 (hex)". If the DQ0 of output data is "1," the boot block programming lockout feature is activated; if the DQ0 of output data is "0 ," the lockout feature is inactivated and the block can be erased/programmed. To return to normal operation, perform a three-byte command code sequence (or an alternate singlebyte command) to exit the identification mode. For the specific code, see Command Code for Identification/Boot Block Lockout Detection. Chip Erase Operation The chip-erase mode can be initiated by a six-byte command code sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed as fast as 100 mS (typical). The host system is not required to provide any control or timing during this operation. The entire memory array will be erased to FF hex. by the chip erase -3- Publication Release Date: April 2000 Revision A2 W49F002U operation if the boot block programming lockout feature is not activated. Once the boot block lockout feature is activated, the whole chip erase function will erase the two main memory blocks and the two parameter blocks but not the boot block. The device will automatically return to normal read mode after the erase operation. Data polling and/or Toggle Bits can be used to detect end of erase cycle. Sector Erase Operation There are four sectors: two main memory blocks and two parameters blocks which can be erased individually by initiating a six-byte command code sequence. Sector address is latched on the falling edge of WE signal in the sixth cycle while the data input "30(hex)" is latched at the rising edge of WE in this cycle. After the command loading cycle, the device enters the internal sector erase mode, which is automatically timed and will be completed as fast as 100 mS (typical). The host system does not require to provide any control or timing during this operation. The device will automatically return to normal read mode after the erase operation. Data polling and/or Toggle Bits can be used to detect the end of erase cycle. When different sector address is loaded in the sixth cycle for sector erase command, the correspondent sectors will be erased automatically; that these sections will be erased independedntly. For detail sector to be erased information, please refer to the Table of Command Definition. Program Operation The W49F002U is programmed on a byte-by-byte basis. Program operation can only change logical data "1" to logical data "0". The erase operation (changed entire data in two main memory blocks and two parameter blocks and/or boot block from "0" to "1") is needed before programming. The program operation is initiated by a 4-byte command code sequence (see Command Codes for Byte Programming). The device will internally enter the program operation immediately after the byteprogram command is entered. The internal program timer will automatically time-out (50 S max. TBP). Once completed, the device returns to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle. Hardware Data Protection The integrity of the data stored in the W49F002U is also hardware protected in the following ways: (1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than 2.5V typical. (3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5 mS before any write (erase/program) operation. Data Polling (DQ7)- Write Status Detection The W49F002U includes a data polling feature to indicate the end of a program or erase cycle. When the W49F002U is in the internal program or erase cycle, any attempt to read DQ7 of the last byte loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and become logical "1" or true data when the erase cycle has been completed. -4- W49F002U Toggle Bit (DQ6)- Write Status Detection In addition to data polling, the W49F002U provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a three-byte (or JEDEC 3-byte) command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code DA(hex). A read from address 0001H outputs the device code 0B(hex). The product ID operation can be terminated by a three-byte command code sequence or an alternate one-byte command code sequence (see Command Definition table). In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE high, and raising A9 to 12 volts. TABLE OF OPERATING MODES Operating Mode Selection (VHH = 12V 5%) MODE PINS ADDRESS DQ. RESET CE OE WE Read VIH VIL VIL VIH AIN Dout Write VIH VIL VIH VIL AIN Din Standby VIH VIH X X X High Z Write Inhibit VIH X VIL X X High Z/DOUT VIH X X VIH X High Z/DOUT Output Disable VIH X VIH X X High Z Reset Mode VIL X X X X High Z Product ID VIH VIL VIL VIH A0 = VIL; A1-A17 = VIL; Manufacturer Code DA (Hex) A9 = VHH VIH VIL VIL VIH A0 = VIH; A1-A17 = VIL; A9 = VHH -5- Device Code 0B (Hex) Publication Release Date: April 2000 Revision A2 W49F002U TABLE OF COMMAND DEFINITION(1) COMMAND DESCRIPTION NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Read 1 AIN DOUT Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA Byte Program 4 5555 AA 2AAA 55 5555 A0 AIN Boot Block Lockout 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit (2) 3 5555 AA 2AAA 55 5555 F0 Product ID Exit (2) 1 XXXX F0 (3) DIN 5555 40 Notes: 1. Address Format: A14-A0 (Hex); Data Format: DQ7-DQ0 (Hex) 2. Either one of the two Product ID Exit commands can be used. 3. SA means: Sector Address If SA is within 3C000 to 3FFFF (Boot Block address range), and the Boot Block programming lockout feature is activated, nothing will happen and the device will go back to read mode after 100nS. If the Boot Block programming lockout feature is not activated, this command will erase Boot Block. If SA is within 3A000 to 3BFFF (Parameter Block1 address range), this command will erase PB1. If SA is within 38000 to 39FFF (Parameter Block2 address range), this command will erase PB2. If SA is within 20000 to 37FFF (Main Memory Block1 address range), this command will erase MMB1. If SA is within 00000 to 1FFFF (Main Memory Block2 address range), this command will erase MMB2. -6- 30 W49F002U Command Codes for Byte Program COMMAND SEQUENCE ADDRESS DATA 0 Write 5555H AAH 1 Write 2AAAH 55H 2 Write 5555H A0H 3 Write Programmed-address Programmed-data Byte Program Flow Chart Byte Program Command Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data A0 to address 5555 Load data Din to programmedaddress Pause TBP Exit Notes for software program code: Data Format: DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex) -7- Publication Release Date: April 2000 Revision A2 W49F002U Command Codes for Chip Erase BYTE SEQUENCE ADDRESS 1 Write 5555H AAH 2 Write 2AAAH 55H 3 Write 5555H 80H 4 Write 5555H AAH 5 Write 2AAAH 55H 6 Write 5555H 10H Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Pause TEC Exit Notes for chip erase: Data Format: DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex) -8- DATA W49F002U Command Codes for Sector Erase BYTE SEQUENCE ADDRESS DATA 1 Write 5555H AAH 2 Write 2AAAH 55H 3 Write 5555H 80H 4 Write 5555H AAH 5 Write 2AAAH 55H 6 Write SA* 30H Sector Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 30 to address SA* Pause TEC Exit Notes for chip erase: Data Format: DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex) SA : For details, see the page 6 . -9- Publication Release Date: April 2000 Revision A2 W49F002U Command Codes for Product Identification and Boot Block Lockout Detection SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION EXIT(6) ADDRESS DATA ADDRESS DATA 1 Write 5555 AA 5555H AAH 2 Write 2AAA 55 2AAAH 55H 3 Write 5555 90 5555H BYTE SEQUENCE Pause 10 S F0H Pause 10 S Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 Load data 55 to address 2AAA Load data 90 to address 5555 Pause 10 S Product Identification and Boot Block Lockout Detection Mode (3) Product Identification Exit(6) (2) Read address = 0000 data = DA Read address = 0001 (2) (4) Read address = 0002 data =in DQ0= "1" / "0" Load data 55 to address 2AAA Load data F0 to address 5555 (5) Normal Mode Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7-DQ0 (Hex); Address Format: A14-A0 (Hex) (2) A1-A17 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the output data in DQ0= " 1 " the boot block programming lockout feature is activated; if the output data in DQ0 = " 0 ," the lockout feature is inactivated and the boot block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-byte cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection. - 10 - W49F002U Command Codes for Boot Block Lockout Enable BYTE SEQUENCE ADDRESS 0 Write 5555H DATA AAH 1 Write 2AAAH 55H 2 Write 5555H 80H 3 Write 5555H AAH 4 Write 2AAAH 55H 5 Write 5555H 40H Pause TBP Boot Block Lockout Enable Acquisition Flow Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 40 to address 5555 Pause T BP Exit Notes for boot block lockout enable: Data Format: DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex) - 11 - Publication Release Date: April 2000 Revision A2 W49F002U DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +7.0 V 0 to +70 C -65 to +150 C D.C. Voltage on Any Pin to Ground Potential except OE -0.5 to VDD +1.0 V Transient Voltage (<20 nS ) on Any Pin to Ground Potential -1.0 to VDD +1.0 V -0.5 to 12.5 V Power Supply Voltage to Vss Potential Operating Temperature Storage Temperature Voltage on OE Pin to Ground Potential Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC Operating Characteristics (VDD = 5.0V 10%, VSS = 0V, TA = 0 to 70 C) PARAMETER SYM. TEST CONDITIONS LIMITS MIN. TYP. Power Supply Current ICC Standby VDD ISB1 MAX. - 25 50 mA - 2 3 mA - 20 100 A Address inputs = VIL/VIH, at f = 5 MHz Current (TTL input) Standby VDD Current CE = OE = VIL, WE = VIH, all DQs open UNIT CE = VIH, all DQs open Other inputs = VIL/VIH ISB2 CE = VDD -0.3V, all DQs open Other inputs = VDD -0.3V/GND (CMOS input) Input Leakage Current ILI VIN = GND to VDD - - 10 A Output Leakage Current ILO VOUT = GND to VDD - - 10 A Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.0 - VDD +0.5 V Output Low Voltage VOL - - 0.45 V Output High Voltage VOH IOH = -0.4 mA 2.4 - - V IOL = 2.1 mA - 12 - W49F002U Power-up Timing PARAMETER SYMBOL TYPICAL UNIT Power-up to Read Operation TPU. READ 100 S Power-up to Write Operation TPU. WRITE 5 mS CAPACITANCE (VDD = 5.0V, TA = 25 C, f = 1 MHz) PARAMETER SYMBOL I/O Pin Capacitance Input Capacitance CONDITIONS CI/O CIN VI/O = 0V VIN = 0V MAX. UNIT 12 6 pf pf AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0V to 3.0V Input Rise/Fall Time Input/Output Timing Level Output Load < 5 nS 1.5V/1.5V 1 TTL Gate and CL = 100 pF for 120 nS; CL = 30 pF for 70 nS /90 nS AC Test Load and Waveform +5V 1.8K DOUT 30 pF for 70nS / 90nS 100 pF for 120nS (Including Jig and Scope) 1.3K Input Output 3V 1.5V 1.5V 0V Test Point - 13 - Test Point Publication Release Date: April 2000 Revision A2 W49F002U AC Characteristics, continued Read Cycle Timing Parameters (VCC = 5.0V 10%, VCC = 0V, TA = 0 to 70 C) PARAMETER SYM. W49F002U-70 W49F002U-90 W49F002U-120 UNIT MIN. MAX. MIN. MAX. MIN. MAX. Read Cycle Time TRC 70 - 90 - 120 - nS Chip Enable Access Time TCE - 70 - 90 - 120 nS Address Access Time TAA - 70 - 90 - 120 nS Output Enable Access Time TOE - 35 - 40 - 50 nS CE Low to Active Output TCLZ 0 - 0 - 0 - nS OE Low to Active Output TOLZ 0 - 0 - 0 - nS CE High to High-Z Output TCHZ - 25 - 25 - 30 nS OE High to High-Z Output TOHZ - 25 - 25 - 30 nS Output Hold from Address Change TOH 0 - 0 - 0 - nS Write Cycle Timing Parameters PARAMETER SYMBOL MIN. TYP. MAX. UNIT Address Setup Time TAS 0 - - nS Address Hold Time TAH 50 - - nS WE and CE Setup Time TCS 0 - - nS WE and CE Hold Time TCH 0 - - nS OE High Setup Time TOES 0 - - nS OE High Hold Time TOEH 0 - - nS CE Pulse Width TCP 100 - - nS WE Pulse Width TWP 100 - - nS WE High Width TWPH 100 - - nS Data Setup Time TDS 50 - - nS Data Hold Time TDH 10 - - nS Byte Programming Time TBP - 35 50 S Erase Cycle Time TEC - 0.1 0.2 S Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL. - 14 - W49F002U AC Characteristics, continued Data Polling and Toggle Bit Timing Parameters PARAMETER SYM. W49F002U-70 W49F002U-90 W49F002U-120 UNIT MIN. MAX. MIN. MAX. MIN. MAX. OE to Data Polling Output Delay TOEP - 35 - 40 - 50 nS CE to Data Polling Output Delay TCEP - 70 - 90 - 120 nS OE to Toggle Bit Output Delay TOET - 35 - 40 - 50 nS CE to Toggle Bit Output Delay TCET - 70 - 90 - 120 nS TIMING WAVEFORMS Read Cycle Timing Diagram TRC Address A17-0 TCE CE TOE OE VIH TOHZ TOLZ WE TCLZ TOH TCHZ High-Z High-Z DQ7-0 Data Valid Data Valid TAA - 15 - Publication Release Date: April 2000 Revision A2 W49F002U Timing Waveforms, continued WE Controlled Command Write Cycle Timing Diagram TAS TAH Address A17-0 TCS CE TCH TOES TOEH OE TWP WE TWPH TDS DQ7-0 Data Valid TDH CE Controlled Command Write Cycle Timing Diagram TAS TAH Address A17-0 TCPH TCP CE TOES TOEH OE WE TDS DQ7-0 High Z Data Valid TDH - 16 - W49F002U Timing Waveforms, continued Program Cycle Timing Diagram Byte Program Cycle Address A17-0 2AAA 5555 55 AA DQ7-0 5555 Address A0 Data-In CE OE T WPH TBP TWP WE Byte 1 Byte 0 Byte 2 Byte 3 Internal Write Start DATA Polling Timing Diagram Address A17-0 An An An An WE TCEP CE TOEH TOES OE TOEP DQ7 X X X X TBP or TEC - 17 - Publication Release Date: April 2000 Revision A2 W49F002U Timing Waveforms, continued Toggle Bit Timing Diagram Address A17-0 WE CE TOES TOEH OE DQ6 TBP orTEC Boot Block Lockout Enable Timing Diagram Six byte code for Boot Block Lockout Feature Enable Address A17-0 DQ7-0 5555 2AAA 5555 AA 55 80 5555 AA 2AAA 55 5555 40 CE OE TWP TEC WE TWPH SB0 SB1 SB2 - 18 - SB3 SB4 SB5 W49F002U Timing Waveforms, continued Chip Erase Timing Diagram Six-byte code for 5V-only software chip erase Address A17-0 5555 DQ7-0 2AAA 55 AA 5555 5555 80 2AAA AA 55 5555 10 CE OE TWP TEC WE TWPH SB0 SB1 SB2 SB3 SB4 SB5 Internal Erase starts Sector Erase Timing Diagram Six-byte code for 5V-only software Main Memory Erase Address A17-0 DQ7-0 5555 2AAA 55 AA 5555 5555 80 AA 2AAA 55 SA 30 CE OE TWP TEC WE TWPH SB0 SB1 SB2 SB3 SB4 SB5 Internal Erase starts SA = Sector Address - 19 - Publication Release Date: April 2000 Revision A2 W49F002U ORDERING INFORMATION (nS) POWER SUPPLY CURRENT MAX. (mA) STANDBY VDD CURRENT MAX. (A) W49F002U-70B 70 50 100 (CMOS) 32-pin DIP 10K W49F002U-90B 90 50 100 (CMOS) 32-pin DIP 10K W49F002U-12B 120 50 100 (CMOS) 32-pin DIP 10K W49F002UT70B 70 50 100 (CMOS) 32-pin TSOP (8 mm x 20 mm) 10K W49F002UT90B 90 50 100 (CMOS) 32-pin TSOP (8 mm x 20 mm) 10K W49F002UT12B 120 50 100 (CMOS) 32-pin TSOP (8 mm x 20 mm) 10K W49F002UP70B 70 50 100 (CMOS) 32-pin PLCC 10K W49F002UP90B 90 50 100 (CMOS) 32-pin PLCC 10K W49F002UP12B 120 50 100 (CMOS) 32-pin PLCC 10K PART NO. ACCESS TIME PACKAGE Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 3. Winbond withholds a Boot Block options for Bottom Boot use. Please contact Winbond FAEs for detail information. - 20 - CYCLE W49F002U PACKAGE DIMENSIONS 32-pin P-DIP Symbol A A1 A2 B B1 c D E E1 e1 L D 17 32 E1 16 E A1 L Base Plane Seating Plane B e1 a 5.33 0.25 0.150 0.155 0.160 3.81 3.94 4.06 0.016 0.018 0.022 0.41 0.46 0.56 0.048 0.050 0.054 1.22 1.27 1.37 0.008 0.010 0.014 0.20 0.25 0.590 1.650 1.660 0.600 0.610 14.99 15.24 0.36 41.91 42.16 15.49 13.97 14.10 0.545 0.550 0.555 13.84 0.090 0.100 0.110 2.29 2.54 2.79 0.120 0.130 0.140 3.05 3.30 3.56 15 0 16.51 17.02 0 0.630 0.650 0.670 16.00 15 0.085 2.16 1.Dimensions D Max. & S include mold flash or tie bar burrs. 2.Dimension E1 does not include interlead flash. 3.Dimensions D & E1. include mold mismatch and are determined at the mold parting line. 4.Dimension B1 does not include dambar protrusion/intrusion. 5.Controlling dimension: Inches 6.General appearance spec. should be based on final visual inspection spec. c A A2 Min. Nom. Max. 0.010 eA S Notes: S Dimension in mm Min. Nom. Max. 0.210 a 1 Dimension in inches eA B1 32-pin PLCC Symbol HE E 4 1 32 30 5 29 GD D HD A A1 A2 b1 b c D E e GD GE HD HE L y Dimension in Inches Min. Nom. Max. Dimension in mm Min. Nom. Max. 3.56 0.140 0.50 0.020 0.105 0.110 0.115 2.67 2.80 2.93 0.026 0.028 0.032 0.66 0.71 0.81 0.016 0.46 0.018 0.022 0.41 0.008 0.010 0.014 0.20 0.25 0.35 0.547 0.550 0.553 13.89 13.97 14.05 0.56 11.51 0.447 0.450 0.453 11.35 11.43 0.044 0.050 0.056 1.12 1.27 1.42 0.490 0.530 12.45 0.430 9.91 12.9 5 10.41 13.46 0.390 0.51 0 0.410 0.585 0.590 0.595 14.86 14.99 15.11 0.485 0.49 0 0.090 0.495 12.32 12.45 12.57 0.095 1.91 2.29 2.41 0.075 0.004 0 10 10.92 0.10 0 10 21 13 Notes: 14 20 1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection sepc. c L A2 e b b1 Seating Plane GE A A1 y - 21 - Publication Release Date: April 2000 Revision A2 W49F002U Package Dimensions, continued 32-pin TSOP HD Dimension in Inches Dimension in mm Symbol D A c e E Nom. __ __ Max. Min. Nom. __ __ 0.047 A1 M Min. 0.002 __ 0.006 0.05 __ Max. 1.20 0.15 A2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.007 0.008 0.009 0.17 0.20 0.23 c 0.005 0.006 0.007 0.12 0.15 0.17 D 0.720 0.724 0.728 18.30 18.40 18.50 E 0.311 0.315 0.319 7.90 8.00 8.10 HD 0.780 0.787 0.795 19.80 20.00 20.20 __ __ 0.024 0.40 __ __ 0.10(0.004) b __ e L L A L 0.016 __ 1 A2 Y 0.000 A1 1 L1 0.020 0.020 0.031 __ 3 0.004 0.00 5 1 Y Note: Controlling dimension: Millimeters - 22 - 0.50 0.50 0.80 __ 3 __ 0.60 __ 0.10 5 W49F002U VERSION HISTORY VERSION DATE PAGE A1 Nov. 1999 - A2 Apr. 2000 1, 13-15, 20 14 DESCRIPTION Renamed from W49F002/B/U/N Add the 120 nS bin Change Tbp(typ.) from 10 S to 35 S Change Tec(max.) from 1 Sec to 0.2 Sec Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 23 - Publication Release Date: April 2000 Revision A2