CYV15G0104EQ
Multi Rate Video Cable Equalizer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-07425 Rev. ** Revised October 25, 2007
Features
■Multi rate adaptive equalization
■Operates from 143 to 1485 Mbps serial data rate
■SMPTE 292M, SMP TE 344M, and SMPTE 259M compliant
■Supports DVB-ASI at 270 Mbps
■Maximum cable length adju s tment for HD-SDI and SD-SDI
data rates
■Carrier detect and mute functionality for HD-SDI an d SD-SDI
data rates
■Equalizer bypass mode
■Seamless connection with HOTLink II™ family
■Equalizes up to 350m of Belden 16 94A and Canare L-5CFB
coaxial cable at 270 Mbps
■Typically equalizes up to 200m of Belden 1694A and Canare
L-5CFB coaxial cable at 1.485 Gbps
■Low power: 160 mW at 3.3V
■Single 3.3V supply
■16-pin Quad Flat No Lead (QFN) package
■0.18 μm CMOS technology
■Pb-free and RoHS compliant
■Pin compatible to existing QFN equalizer devices
■Uses Cypress CLEANLink™ technology
Functional Description
The CYV15G0104EQ is a multi rate adaptive equalizer designed
to equalize and restore signals received over 75Ω coaxial cable.
The equalizer meets SMPTE 292M, SMP TE 344M, and SMPTE
259M data rates. The CYV15G0104EQ is optimized to equalize
up to 350m of Canare L-5CFB and Belden 1694A coaxial cable
at 270 Mbps and typically up to 200m of Canare L-5CFB and
Belden 1694A coaxial cable at 1.485 Gbps. The
CYV15G0104EQ connects seamlessly to the HOTLi nk II family
of transceiver devices.
The CYV15G0104EQ has DC restoration to compensate for the
DC content of the SMPTE pathological patterns. The maximum
cable length adjust (MCLADJ) sets the approximate maximum
cable length to equalize at SD and HD data rates. The
CYV15G0104EQ’s differential serial outputs (SDO, SDO) mute,
when the approximate ca ble leng th set b y MCLADJ is reache d,
and carrier detect (CD) is tied to MUTE. MUTE pin controls
muting the outputs of the equalizer at HD and SD data rates.
Power consumption is typically 160 mW at 3.3V.
Serial Links
Copper Cable
CYV15G0104EQ
Multi Rate
Cable
Equalizer
Connections
Equalizer System Connection Diagram
Cable
Driver
HOTLink II
Serializer
HOTLink II
Deserializer
[+] Feedback [+] Feedback
CYV15G0104EQ
Document Number: 001-07425 Rev. ** Page 2 of 9
Pinouts
Figure 1. Pin Diagram - 16 Pin QFN (Top View)
CYV15G01 0 4 E Q M u lti-Ra te V id eo C able E qu a lizer B loc k D iag ra m
CYV 15 G 0 10 4 E Q Multi-Ra te Vide o C ab le E qua lize r B loc k D iagra m
Differential Output
Cable Len gth An alog
Adjustor an d Mute
Threshold Bloc k
Carrier Detect an d
Mute Contro l B lo ck
DC Restore
Equalizer
MUTE
BYPASS
SDO, SDO
SDI, S D I
MCLADJ CD
2
3
4
5678
CYV15G0104EQ
(Marked CY21EQ
On Package)
SDO
GND
MCLADJ
BYPASS
SDI
AGC
GND
SDI SDO
GND
AGC
GND
VCC
MUTE
VCC
CD
Center Pad
(bottom of package)
1
16 15 14 13
11
10
9
12
Equalizer Block Diagram
[+] Feedback [+] Feedback
CYV15G0104EQ
Document Number: 001-07425 Rev. ** Page 3 of 9
Table 1. Pin Descriptions - CYV15G0104EQ Single Channel Cable Equalizer
Name IO Characteristics Signal Description
Control Signals
MUTE LVTTL Input Mute.
When the MUTE pin is set LOW, the equalizer’s differential serial outputs are not muted.
When the MUTE pin is set HIGH, the equalizer’s differential serial outputs are muted.
BYPASS setting is ignored when MUTE is HIGH.
Connecting CD to MUTE pin enables automatic muting of the equalizer upon loss of signal.
Do not leave unused MUTE pin floating. Always drive it to a known state.
CD LVTTL Output Carrier Detect.
When the incoming da ta stream is present and maximum cable length does not exceed
that set by MCLADJ, CD outputs a voltage less than 0.8V.
When the incoming data stream is not present or maximum cable length exceeds that set
by MCLADJ, CD outputs a voltage greater than 2.8V.
Connecting CD to MUTE pin enables automatic muting of the equalizer upon loss of signal.
MCLADJ Analog Input Maximum Cable Length Adjust.
The maximum equalized cable len gth is set b y th e vol tage applied to the MCLADJ i npu t.
When the maximum cable length set by MCLADJ is reached, the CD indicator is
deasserted.
If MCLADJ functionality is not needed, this pin should be left floating or tied to ground to
allow maximum equalized cable len gth.
MCLADJ works at both SD and HD data rates.
BYPASS LV TTL Input Equalizer Bypass. When BYPASS is set HIGH, the signal presented at the equalizer ’s
differential serial inputs (SDI, SDI) is routed to the equalizer ’s differential serial outputs
(SDO, SDO) without equalizing.
When BYPASS is set LOW, the incoming video data stream is equalized and presented
at the equalizer‘s serial differential outputs (SDO, SDO).
When MUTE pin is set HIGH, BYP ASS setting is ignored and the serial outputs are muted.
AGC, AGC Analog Automatic Gain Control. Place a capacitor of 1 μF between the AGC and AGC pi n s .
SDO, SDO Differential
Output Differential Serial Ou tputs. The equalized serial video data stream is presented at the
SDO/SDO differential serial CML output.
SDI, SDI Differential
Input Differential Serial Inputs. SDI/SDI accepts either a single-ended or differential serial
video data stream over 75Ω coaxial cable.
Power
VCC Power Power Supply for Device. Connect to +3.3V DC.
GND Gnd Connect to Ground.
Center Pad –Connect to PCB Ground for Maximum Thermal Dissipation.
[+] Feedback [+] Feedback
CYV15G0104EQ
Document Number: 001-07425 Rev. ** Page 4 of 9
Equalizer Operation
The CYV15G0104EQ is a high speed adaptive cable equ alizer
designed to equalize standard definition (SD) and high definition
(HD) serial digital interface (SDI) video data streams..The
CYV15G0104EQ equal izer is optimized to equalize up to 350 m
of Belden 1694A cable and Canare L-5C FB cable at 270 Mbps
and typically up to 200m of Belden 1694A cable and Canare
L-5CFB cable at 1.485 Gbps. The CYV15G0104EQ equalizer
contains one power supply and typically consumes 160 mW
power at 3.3V. The multi rate equalizer meets the SMP TE 259M,
SMPTE 292M, SMPTE 344M, and DVB-ASI vi deo standards. It
meets all pathological requirements for SMPTE 292M as defined
by RP198 and for SMPTE 259M as defined by RP178. The
CYV15G0104EQ multi rate cable equalizer operates from 143
Mbps to 1.485 Gbps serial data rate.
The CYV15G0104EQ equalizer has multiple variable gain equal-
ization stages that reverse the attenuation effects of the cable.
This equalization is achieved by separate regulation of the lower
and higher frequency components in the signal to give a clean
output eye diagram. The CYV15G0104EQ has DC restoration to
compensate for the DC content of the SMPTE pathological
patterns.
SDI, SDI
CYV15G0104EQ accepts single-ended or differential serial
video data streams over 75Ω coaxia l cable. It is recommended
to AC couple the SDI, SDI input s as th ey are in ternally biased t o
1.2V.
SDO, SDO
The CYV15G0104EQ has differential serial output interface
drivers that use Current Mode Logic (CML) drivers to provide
source matching for the transmission line. These outputs are
either AC coupled or DC coupled to HOTLink II receivers.
MCLADJ
Maximum Cable Length Adjust (MCLADJ) sets the approximate
maximum amount of cable to be equalized. When the maximum
cable length set by MCLADJ is reached, the CD pin is
deasserted. To enable automatic muting of the device upon loss
of signal, C D should be tied directly to MUTE. MCLADJ works at
SD and HD data rates.
Figure 2 on page 7 illustrates the voltage required at MCLADJ
input to equalize various Belden 1694A cable lengths. If
MCLADJ functionality is not required, this pin should be left
floating or tied to ground to enable maximum equalized cable
length.
MUTE
MUTE is an input pin that controls the muting of the equalizer ’s
output. MUTE operates for both HD and SD data rates.
If MUTE is set LOW, the equalizer serial outputs are not muted.
If MUTE is set HIGH, then the equalizer serial outputs are muted.
When MUTE is active, BYPASS setting is also ignored.
Connecting CD to MUTE pin enables automatic muting of the
equalizer upon loss of signal.
Do not leave the MUTE pin floating. Always drive it to a known
state.
Carrier Detect (CD)
Carrier Detect is an active LOW output pin that indicates the
presence of a valid incoming data signal. When the incoming
data signal is present, and maximum cable length does not
exceed that set by MCLADJ, CD outputs a voltage less than
0.8V.
When the incoming data stream is not present, or maximum
cable length exceeds that set by MCLADJ, CD outputs a voltage
greater than 2.8V.
Connecting CD to MUTE pin enables automatic muting of the
equalizer upon loss of signal.
BYPASS
The CYV15G0104EQ has a bypass mode that enables the user
to bypass the equalizer’s equalization and DC restoration
functions. When BYPASS is set HIGH, the signal presented at
the equalizer’s differential serial inputs (SDI, SDI) is routed to the
equalizer’s differential serial outputs (SDO, SDO) without equal-
izing.
When BYPASS is set LOW, the incoming video data stream is
equalized and presented at the equalizer‘s differential serial
outputs (SDO, SDO).
AGC
Place a capacitor of 1 μF between the AGC and AGC pins of the
CYV15G0104EQ equalizer
[+] Feedback [+] Feedback
CYV15G0104EQ
Document Number: 001-07425 Rev. ** Page 5 of 9
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature.................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............ ................................ –55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +3.8V
DC Voltage Applied to Outputs
in High Z State........................ ... ............–0.5V to VCC + 0.5V
DC Input Voltage ........ ... ................. ... ... ...–0.5V to V CC+0.5V
Electro Static Discharge (ESD) HBM.......................> 2000 V
(JEDEC EIA/JESD-A114A)
Latch Up Current.................................. ................. .> 200 mA
Power Up Requirements
The CYV15G0104EQ contains one power supply. The voltage
on any input or IO pin must not exceed the power pin during
power up.
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C +3.3V ±5%
Notes
1. Production test.
2. Calculated results from production test.
DC Electrical Characteristics
Parameter Description Test Conditions Min Typ Max Unit
VCC Supply Voltage[1] –3.135 3.3 3.465 V
PDPower Consumption[2] –125 160 190 mW
ISSupply Current[1] –38 48 60 mA
VCMOUT Output Common Mode Voltage[1] Load = 50Ω– VCC – ΔVSDO/2
= 2.9 – V
VCMIN Input Common Mode Voltage[1]
(Bypass = High) – 1 1.4 V
Input Common Mode Voltage[1]
(Bypass = Low) – 0 2.9 V
–Floating MCLADJ DC Voltage[1] –1.3 V
–MCLADJ Range[2] –0.4 0.72 1.02 V
VCD(OH) CD Output Voltage[1] Carrier Not Present 2.8 – – V
VCD(OL) Carrier Present – – 0.8 V
VMUTE MUTE Input Voltage Required to Force
Outputs to Mute[1] Min to Mute 2.5 – V
VMUTE MUTE Input Voltage Required to Force
Active[1] Max to Activate – – 1 V
[+] Feedback [+] Feedback
CYV15G0104EQ
Document Number: 001-07425 Rev. ** Page 6 of 9
Notes
3. Not tested. Based on characterization.
4. Not tested. Guarant eed by design simulations.
5. Based on characterization across temperature and voltage with 140m of Belden 1694A cable, transmitting SMPTE Equalizer Pathological Test Pattern.
6. Based on characterization across temperature and voltage with 350m of Belden 1694A cable, transmitting SMPTE Equalizer Pathological Test Pattern.
7. Based on characterization at TA = 25°C, VCC = 3.3V
AC Electrical Characteristics
Parameter Description Test Conditions Min Typ Max Unit
–Serial Input Data Rate[1] –143 –1485 Mbps
VSDI Input Voltage Swing Single-ended, at the transmitter ,
HD data rate 500[5] 1200 mV
VSDI Input Voltage Swing Single-ended, at the transmitter ,
SD data rate 500[6] 1200 mV
ΔVSDO Output Voltage Swing[1] Differentialp-p, 50Ω load 450 700 950 mV
–Output Jitter for Various Cable
Lengths and Data Rates 270 Mbps
Belden 1694A: 0-350m
Canare L-5CFB: 0-350m
800 mV transmit amplitude
Equalizer pathological pattern
–0.2[1] –UI
1.485 Gbps
Belden 1694A: 0-140m
Canare L-5CFB: 0-140m
800 mV transmit amplitude
Equalizer pathological pattern
–0.25[1] –UI
1.485 Gbps
Belden 1694A: 140-200m
Canare L-5CFB: 140-200m
800 mV transmit amplitude
Equalizer pathological pattern
–0.3[7] –UI
–Output Rise/Fall Time[3, 4] 20% - 80%, HD data rate 80 120 220 ps
Output Rise/Fall Time[3, 4] 20% - 80%, SD data rate 80 120 350 ps
–Mismatch in Rise/Fall T ime[3, 4] – – – 30 ps
–Duty Cycle Distortion[3, 4] HD color bar pattern –20 –ps
–Overshoot[3, 4] – – – 10 %
–Input Return Loss[3] –-15 – – dB
–Input Resistance[3, 4] Single-ended –2.5 – kΩ
–Input Capacitance[3, 4] Single-ended – 1 – pF
–Output Resistance[3, 4] Single-ended –50 –Ω
[+] Feedback [+] Feedback
CYV15G0104EQ
Document Number: 001-07425 Rev. ** Page 7 of 9
Typical Performance Graphs
(Unless otherwise stated, VCC = 3.3V, TA = 25°C)
Figure 2. MCLADJ Input Voltage vs Belden 1694A Cable Length at SD-SDI and HD-S DI Data Rates
Typical Application Circuit
Figure 3. Interfacing CYV15G0104EQ to the HOTLink II SerDes
CABLE LENG T H (m )
VOLTAGE (V)
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
0 50 100 150 200 250 300 350
[+] Feedback [+] Feedback
CYV15G0104EQ
Document Number: 001-07425 Rev. ** Page 8 of 9
Ordering Information
Ordering Code Package
Marking Package Name Package Type Operating
Range
CYV15G0104EQ-LXC CY21EQ LY16A Pb-free 16-Pi n QFN 0 to 70°C
Package Dimension
Figure 4. 16-Pin QFN Package LY16A
E-PAD
C
1.00 MAX.
N
SEATING
PLANE
N
2
2
0.35±0.05
0.65
11
0.05
0°-12°
0.30-0.50
1.90
0.05 MAX.
C
0.80 MAX.
0.20 REF.
PIN1 ID
0.45
0.20 R.
SIDE VIEW
3.90
4.10
3.70
3.80
4.10
3.70
3.80
3.90
0.42±0.18
2.00
2.00
1.90
(4X)
DIMENSION IN mm MIN.
MAX.
TOP VIEW
BOTTOM VIEW
2.50 REF.
REF.
2.50
REFERENCE JEDEC MO-220
PKG. WEIGHT 0.04gms
PART #
LF16A STANDARD PKG.
LY16A LEAD FREE PKG.
001-04468-*A
[+] Feedback [+] Feedback
Document Number: 001-07425 Rev. ** Revised October 25, 2007 Page 9 of 9
PSoC Designer™, Programmable System-on-Chip™, an d PS oC Exp re ss™ are tra demarks a nd PSo C® is a registe red t rade mark of Cypress S emi conductor Corp. All o the r tr a dem a rks o r re gi ster e d
trademar ks refere nced herei n are prop erty of the respe ctive corp orations. Purchas e of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard S pecification as defined by Philips. HOTLink is a registered trademark and
HOTLink II and CLEANLink are trademarks of Cypress Semiconductor. All other trademarks or registered trademarks referenced herein are property of the respective corporations. All products and
company names mentioned in this document may be the trademarks of their resp ective holders.
CYV15G0104EQ
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products a re not warranted no r intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Further more, Cypr ess does not author ize its produc ts for use as critic al
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protectio n (United States and fore ign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee pr oduct to be used only in conjunction with a Cyp ress
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described h erein. Cypres s does not
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfuncti on or failure may reason ably be expected to res ult in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document History Page
Document Title: CYV15G0104EQ Multi Rate Video Cable Equalizer
Document Number: 001-07425
Rev. Ecn No. Issue Date Orig. Of
Change Description Of Change
** 1396423 SEE ECN UKK/AESA New datasheet
[+] Feedback [+] Feedback