93LC56BTI/SNG - Microchip Technology, Inc.

 2003 Microchip Technology Inc. DS21794B-page 1

93AA56A/B/C, 93LC56A/B/C,

93C56A/B/C

Device Selection Table

Features

• Low-power CMOS technology

• ORG pin to select word size for ‘56C version

• 256 x 8-bit organization ‘A’ ver. devices (no ORG)

• 128 x 16-bit organization ‘B’ ver. devices (no

ORG)

• Self-timed ERASE/WRITE cycles (including

auto-erase)

• Automatic ERAL before WRAL

• Power on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device Status signal (READ Y/BUSY)

• Seque nti al REA D functi on

• 1,000,000 E/W cycles

• Data retention > 200 y ears

• Temperature ranges supported:

Pin Function Table

Description

The Microchip Technology Inc. 93XX56A/B/C devices

are 2K bit low voltage serial Electrically Erasable

PROMs (EEPROM). Word-selectable devices such as

the 93AA56C, 93LC56C or 93C56C are dependent

upon external logic levels driving the ORG pin to set

word size. For dedicated 8-bit communication, the

93AA56A, 93LC56A or 93C56A devices are available,

while the 93AA56B, 93LC56B and 93C56B devices

provide dedicated 16-bit communication. Advanced

CMOS technology makes these devices ideal for low

power, nonvolatile memory applications. The entire

93XX Series is available in standard packages includ-

ing 8-lead PDIP and SOIC, and advanced packaging

including 8-lead MSOP, 6-lead SOT-23, and 8-lead

TSSOP. Pb-free (Pure Matte Sn) finish is also

available.

Package Types (not to scale)

Part Number VCC Range ORG Pin Word Size Temp Ranges Packages

93AA56A 1.8-5.5 No 8-bit I P, SN, ST, MS, OT

93AA56B 1.8-5-5 No 16-bit I P, SN, ST, MS, OT

93LC56A 2.5-5.5 No 8-bit I, E P, SN, ST, MS, OT

93LC56B 2.5-5.5 No 16-bit I, E P, SN, ST, MS, OT

93C56A 4.5-5.5 No 8-bit I, E P, SN, ST, MS, OT

93C56B 4.5-5.5 No 16-bit I, E P, SN, ST, MS, OT

93AA56C 1.8-5.5 Yes 8 or 16-bit I P, SN, ST, MS

93LC56C 2.5-5.5 Yes 8 or 16-bit I, E P, SN, ST, MS

93C56C 4.5-5.5 Yes 8 or 16-bit I, E P, SN, ST, MS

- Industrial (I) -40°C to +85°C

- Automotive (E) -40°C to +125°C

Name Function

CS Chip Select

CLK Serial Data Clock

DI Serial Data Input

DO Serial Data Output

VSS Ground

NC No internal connec tio n

ORG Memory Configuration

VCC Power Supply

CLK

ORG*

PDIP/SOIC

(P, SN)

CLK DI

NC ORG*

ROTATED SOIC

(ex: 93LC56BX)

TSSOP/MSOP

CLK

ORG*

(ST, M S) SOT-23

CLK

(OT)

* ORG pin is NC on A/B devices

2K Micr owire Compatible Serial EEPROM

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

DS21794B-page 2  2003 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins......................................................................................................................................................≥ 4kV

TABLE 1-1: DC CHARACTERISTICS

†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This is a stress rating only and fun ction al ope rati on of th e dev ice at tho se or a ny oth er con dition s abov e thos e

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

All parameters apply ov er the specified

ranges unless otherwise noted.

VCC = range by device (see Table on Page 1)

Industrial (I): TA = -40°C to +85°C

Automotive (E): TA = -40°C to +125°C

Param.

No. Symbol Parameter Min Typ Max Units Conditions

D1 VIH1

VIH2High-lev el inp ut vol t ag e 2.0

0.7 VCC —

—VCC +1

VCC +1 V

VVCC ≥ 2.7V

VCC < 2.7V

D2 VIL1

VIL2Low-level input voltage -0.3

-0.3 —

—0.8

0.2 VCC V

VVCC ≥ 2.7V

VCC < 2.7V

D3 Vol1

Vol2 Low-level ou tput voltage —

——

—0.4

0.2 V

VIOL = 2.1 mA, VCC = 4.5V

IOL = 100 µA, VCC = 2.5V

D4 VOH1

VOH2High-lev el outp ut vol tage 2.4

VCC - 0.2 —

——

—V

VIOH = -400 µA, VCC = 4.5V

IOH = -100 µA, VCC = 2.5V

D5 ILI Input leakage current — — ±1 µAVIN = VSS to VCC

D6 ILO Output lea ka ge cur r ent — — ±1 µAVOUT = VSS to VCC

D7 CIN,

COUT Pin capacitance (all inputs/

outputs) ——7pFVIN/VOUT = 0V (Note 1)

TA = 25°C, FCLK = 1 MHz

D8 ICC write Write current —

——

500 2

—mA

µAFCLK = 3 MHz, Vcc = 5.5V

FCLK = 2 MHz, Vcc = 2.5V

D9 ICC read Read current —

—

100

500

—

µA

FCLK = 3 MHz, VCC = 5.5V

FCLK = 2 MHz, VCC = 3.0V

FCLK = 2 MHz, VCC = 2.5V

D10 ICCS Standby current —

——

—1

5µA

µAI – Temp

E – Temp

CLK = Cs = 0V

ORG = DI = VSS or VCC

(Note 2) (Note 3)

D11 VPOR VCC voltage detect

93AA56A/B/C, 93L C56A/B/C

93C56A/B/C —

—1.5V

3.8V —

—V

V(Note 1)

Note 1: This parameter is periodically sampled and not 100% tested.

2: ORG pin not available on ‘A’ or ‘B’ versions.

3: READY/BUSY status must be cleared from DO, see Section 3.4 "Data Out (DO)".

 2003 Microchip Technology Inc. DS21794B-page 3

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

TABLE 1-2: AC CHARACTERISTICS

All parameters apply over the specified

ranges unless otherwise noted.

VCC = range by device (see Table on Page 1)

Industrial (I): TA = -40°C to +85°C

Automotive (E): TA = -40°C to +125°C

Param.

No. Symbol Parameter Min Max Units Conditions

A1 FCLK Clock frequency — 3

MHz

4.5V ≤ VCC < 5.5V, 93XX56C only

2.5V ≤ VCC < 5.5V

1.8V ≤ VCC < 2.5V

A2 TCKH Clock high time 200

250

450

—ns

4.5V ≤ VCC < 5.5V, 93XX56C only

2.5V ≤ VCC < 5.5V

1.8V ≤ VCC < 2.5V

A3 TCKL Clock low time 100

200

450

—ns

4.5V ≤ VCC < 5.5V, 93XX56C only

2.5V ≤ VCC < 5.5V

1.8V ≤ VCC < 2.5V

A4 TCSS Chip Sele ct setup time 50

100

250

—ns

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

A5 TCSH Chip Sele ct hold time 0 — ns 1.8V ≤ VCC < 5.5V

A6 TCSL Chip Sele ct low tim e 250 — ns 1.8V ≤ VCC < 5.5V

A7 TDIS Data input setup time 50

100

250

—ns

4.5V ≤ VCC < 5.5V, 93XX56C only

2.5V ≤ VCC < 5.5V

1.8V ≤ VCC < 2.5V

A8 TDIH Data input hold time 50

100

250

—ns

4.5V ≤ VCC < 5.5V, 93XX56C only

2.5V ≤ VCC < 5.5V

1.8V ≤ VCC < 2.5V

A9 TPD Data output delay time — 200

250

400

4.5V ≤ VCC < 5.5V, CL = 100 pF

2.5V ≤ VCC < 4.5V, CL = 100 pF

1.8V ≤ VCC < 2.5V, CL = 100 pF

A10 TCZ Data output disable time — 100

200 ns

ns 4.5V ≤ VCC < 5.5V, (Note 1)

1.8V ≤ VCC < 4.5V, (Note 1)

A11 TSV Status valid time — 200

300

500

4.5V ≤ VCC < 5.5V, CL = 100 pF

2.5V ≤ VCC < 4.5V, CL = 100 pF

1.8V ≤ VCC < 2.5V, CL = 100 pF

A12 TWC P rogram cycle t ime — 6 ms Erase/Write mode (AA and LC

versions)

A13 TWC — 2 ms Erase/Write mode

(93C versions)

A14 TEC — 6 ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V

A15 TWL — 15 ms WRAL mode, 4.5V ≤ VCC ≤ 5.5V

A16 — Endurance 1M — cycles 25°C, VCC = 5.0V, (Note 2)

Note 1: This parameter is periodically sampled and not 100% tested.

2: This application is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which may be obtained from

www.microchip.com.

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

DS21794B-page 4  2003 Microchip Technology Inc.

FIGU RE 1-1 : SYN CH R ONO US DA TA TIMI NG

TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX56B OR 93XX56C WITH ORG = 1)

TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX56A OR 93XX56C WITH ORG = 0)

Instruct ion SB Opcode Address Data In Dat a Ou t R eq. C LK C yc les

ERASE 1 11 X A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)11

ERAL 1 00 10XXXXXX — (RDY/BSY

)11

EWDS 1 00 00XXXXXX — HIGH-Z 11

EWEN 1 00 11XXXXXX — HIGH-Z 11

READ 1 10 X A6 A5 A4 A3 A2 A1 A0 — D15 – D0 27

WRITE 1 01 X A6 A5 A4 A3 A2 A1 A0 D15 – D0 (RDY/BSY)27

WRAL 1 00 01XXXXXXD15 – D0(RDY/BSY

)27

Instruction SB Opcode Address Data In Data Out Req. CLK

Cycles

ERASE 1 11 X A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)12

ERAL 1 00 10XXXXXXX — (RDY/BSY

)12

EWDS 1 00 00XXXXXXX — HIGH-Z 12

EWEN 1 00 11XXXXXXX — HIGH-Z 12

READ 1 10 X A7 A6 A5 A4 A3 A2 A1 A0 — D7 – D0 20

WRITE 1 01 X A7 A6 A5 A4 A3 A2 A1 A0 D7 – D0 (RDY/BSY)20

WRAL 1 00 0 1 X X X X X X X D7 – D0 (RDY/BSY)20

CS VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

CLK

(READ)

(PROGRAM)

TCSS

TDIS

TCKH TCKL

TDIH

TPD

TCSH

TPD

TCZ

STATUS VALID

TSV

TCZ

Note: TSV is relative to CS.

 2003 Microchip Technology Inc. DS21794B-page 5

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

2.0 FUNCTIONAL DESCRIPTION

When the ORG* pin is connected to VCC, the (x16)

organization is selected. When it is connected to

ground, the (x8) organization is selected. Instructions,

address es and wri te data a re cloc ked into the DI pin on

the rising edge of the clock (CLK). The DO pin is

normally held in a HIGH-Z state except when reading

data from the device, or when checking the READY/

BUSY status during a programming operation. The

READY/BUSY status can be verified during an Erase/

Wr ite operat ion by pol ling the DO pin; DO lo w indicate s

that programming is still in progress, while DO high

indica tes the devi ce is rea dy. DO will ente r th e H IG H-Z

state on the falling edge of CS.

2.1 START Condition

The START bit is detected by the device if CS and DI

are both high with respect to the positive edge of CLK

for the first time.

Before a ST AR T condition is detected, CS, CLK, and DI

may change in any combination (except to that of a

START condition), without resulting in any device

operation (READ, WRITE, ERASE, EWEN, EWDS,

ERAL, or WRAL). As soon as CS is high, the device is

no longer in Standby mode.

An instruction following a START condition will only be

execut ed if the requi r ed op co de, address and data bits

for any particular instruction are clocked in.

2.2 Data In/Data Out (DI/DO)

It is possible to connect the Data In and Data Out pins

together. However, with this configuration it is possible

for a “bus conflict” to occur during the “dummy zero”

that pre ced es the Re ad ope ra tio n, if A0 i s a l ogi c high

level. Under such a condition the voltage level seen at

Dat a Out is undefined a nd will dep end upon the relativ e

impedances of Data Out and the signal source driving

A0. The higher the current sourcing capability of A0,

the higher the voltage at the Data Out pin. In order to

limit this current, a resistor should be connected

between DI and DO.

2.3 Data Protecti on

All modes of operation ar e inhibited when VCC is below

a typical voltage of 1.5V for '93AA' and '93LC' devices

or 3.8V for '93C' devices.

The EWEN and EWDS commands give additional

protection against accidentally programming during

normal operation.

Note: For added protection, an EWDS command

should be performed after every write

operation.

After power-up, the device is automatically in the

EWDS mode. Therefore, an EWEN instruction must be

performed before the initial ERASE or WRITE instruction

can be execu ted .

Block Diagram

Memory

Array

Data Register

Mode

Decode

Logic

Clock

Address

Decoder

Address

Counter

Output

Buffer DO

ORG*

CLK

VCC VSS

*ORG input is not available on A/B devices

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

DS21794B-page 6  2003 Microchip Technology Inc.

2.4 ERASE

The ERASE instruction forces all data bits of the speci-

fied address to the logical ‘1’ state. CS is brought low

follow ing the l oading o f the las t address b it. This f alling

edge of the CS pin initiates the self-timed program-

ming cycle, except on ‘93C’ devices where the rising

edge of CLK before the last address bit initiates the

write cycle.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL). DO at logical ‘0’ indicates that programming

is still in progress. DO at logical ‘1’ indicates that the

the device is ready for another instruction.

Note: Issuing a START bit and then taking CS low

will clear the READY/BUSY status from

DO.

FIGU RE 2-1 : ERAS E TIMI NG FO R 93AA AN D 93L C D EVI CE S

FIGURE 2-2: ERASE TIMING FOR 93C DEVICES

CLK

TCSL

CHECK STATUS

111A

NAN-1 AN-2 ••• A0

TSV TCZ

BUSY READY HIGH-Z

TWC

HIGH-Z

CLK

TCSL

CHECK STATUS

111A

NAN-1 AN-2 ••• A0

TSV TCZ

BUSY READY HIGH-Z

TWC

HIGH-Z

 2003 Microchip Technology Inc. DS21794B-page 7

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

2.5 ERASE ALL (ERAL)

The Erase All (ERAL) instruction will erase the entire

memory array to the logical ‘1’ state. The ERAL cycle is

identical to the ERASE cycle, except for the different

opcode. The ERAL cycle is completely self-timed and

commences at the falling edge of the CS, except on

‘93C’ devices where the rising edge of CLK before the

last data bit initiates the write cycle. Clocking of the

CLK pin is not necessary after the device has entered

the ERAL cycle.

The DO pin indicates the READY/BUSY status of the

device , if CS is brough t high a fter a mi nimum of 250 n s

low ( TCSL).

Note: Issuing a START bit and then taking CS low

will clear the READY/BUSY status from

DO.

VCC must be ≥ 4.5V for proper operation of ERAL.

FIGU RE 2- 3 : ER AL TIM IN G F O R 93 AA AND 9 3 LC DE VI C ES

FIGU RE 2-4: ERAL T IM ING FOR 93 C DEVICE S

CLK

TCSL

CHECK STATUS

10010X

••• X

TSV TCZ

BUSY READY HIGH-Z

TEC

HIGH-Z

VCC must be ≥ 4.5V for proper operation of ERAL.

CLK

TCSL

CHECK STATUS

10010X

••• X

TSV TCZ

BUSY READY HIGH-Z

TEC

HIGH-Z

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

DS21794B-page 8  2003 Microchip Technology Inc.

2.6 ERASE/WRITE DISABLE And ENABLE (EWDS/EWEN)

The 93XX56A/B/C powers up in the ERASE/WRITE

Disable (EWDS) state. All Programming modes must be

precede d by an ERASE/WRITE En able (EWEN) instruc-

tion. Once the EWEN instruction is executed, program-

ming remains enabled until an EWDS instruction is

executed or Vcc is removed from the device.

To protect against accidental data disturbance, the

EWDS instruction can be used to disable all ERASE/

WRITE functions and should follow all programming

operatio ns. Executio n of a READ instruct ion i s ind epen-

dent of both the EWEN and EWDS instructions.

FIGURE 2-5: EWDS TIMING

FIGURE 2-6: EWEN TIMING

2.7 READ

The READ instruction outputs the serial data of the

addressed memory location on the DO pin. A dummy

zero bit prece des the 8-bit (If ORG pin is low or A-V ersion

devices) or 16-bit (If ORG pin is high or B-version

devic es) ou tput st ring. The ou tput dat a bi ts will toggle on

the rising edge of the CLK and are stable after the spec-

ified time dela y (TPD). S equ entia l rea d is possi ble wh en

CS is held high. The memory data will automatically cycle

to t he ne xt re gi ster an d o utput s eq ue nt ia ll y.

FIGU RE 2- 7 : RE AD TIMING

CLK

DI 10

000X ••• X

TCSL

CLK

DI 00 1 1X

TCSL

•••

CLK

110An ••• A0

HIGH-Z 0Dx

••• D0 Dx ••• D0 •••

Dx D0

 2003 Microchip Technology Inc. DS21794B-page 9

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

2.8 WRITE

The WRITE instruction is followed by 8 bits (If ORG is

low or A-v ersi on device s) or 16 b its (If OR G pi n is hig h

or B-versi on devices) of data whi ch are writt en into th e

specified address. For 93AA56A/B/C and 93LC56A/B/C

devices, after the last data bit is clocked into DI, the

falling edge of CS initiates the self-timed auto-erase and

programmin g c ycle. F or 93 C56A/ B/C d evices , the se lf-

timed auto-erase and programming cycle is initiated by

the rising edge of CLK on the last data bit.

The DO pin indicates the READY/BUSY status of the

device , if CS is brough t high a fter a mi nimum of 250 n s

low (TCSL). DO at logical ‘0’ indicates that programming

is still in progress. DO at logical ‘1’ indicates that the

the data specified and the device is ready for another

instruction.

Note: Issuing a START bit and then taking CS low

will clear the READY/BUSY status from

DO.

FIGURE 2-8: WRITE TIMING FOR 93AA AND 93LC DEVICES

FIGU RE 2-9: WRITE TIM IN G FOR 93 C DEVICE S

CLK

101An

••• A0 Dx ••• D0

BUSY READY HIGH-Z

HIGH-Z

Twc

TCSL

TCZ

TSV

CLK

101An

••• A0 Dx ••• D0

BUSY READY HIGH-Z

HIGH-Z

Twc

TCSL

TCZ

TSV

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

DS21794B-page 10  2003 Microchip Technology Inc.

2.9 WRITE ALL (WRAL)

The Write All (WRAL) instruction will write the entire

memory array with the data specified in the command.

For 93AA56A/ B/C and 93LC56 A/B/C de vices, after th e

last data bit is clocked into DI, the falling edge of CS

initiates the self-timed auto-erase and programming

cycle. For 93C56A/B/C devices, the self-timed auto-

erase and programming cycle is initiated by the rising

edge of CLK on the last data bit. Clocking of the CLK

pin is not necessary after the device has entered the

WRAL cycle. The WRAL command does include an

automatic ERAL cycle for the device. Therefore, the

WRAL instruction does not require an ERAL instruct ion

but the chip must be in the EWEN status.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low ( TCSL).

Note: Issuing a START bit and then taking CS low

will clear the READY/BUSY status from

DO.

VCC must be ≥ 4.5V for proper operation of WRAL.

FIGURE 2-10: WRAL TIMING FOR 93AA AND 93LC DEVICES

FIGU RE 2-11: WRAL TIM IN G FOR 93C DE VICE S

CLK

DO HIGH-Z

10001X

••• XDx ••• D0

HIGH-Z BUSY READY

TWL

VCC must be ≥ 4.5V for proper operation of WRAL.

TCSL

TSV TCZ

CLK

DO HIGH-Z

10001X

••• XDx ••• D0

HIGH-Z BUSY READY

TWL

TCSL

TSV TCZ

 2003 Microchip Technology Inc. DS21794B-page 11

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

3.0 PIN DESCRIPTIONS

TABLE 3-1: PIN DESCRIPTIONS

3.1 Chip Select (CS)

A high level selects the device; a low level deselects

the dev ice and fo rces it i nto S t andby mode. H owever , a

progra mmin g c yc le which is al read y i n pro gres s wi ll be

completed, regardless of the Chip Select (CS) input

signal . I f C S is brou gh t low duri ng a p r ogra m cyc le, th e

device will go into Standby mode as soon as the

programming cycle is completed.

CS must be low for 250 ns minimum (TCSL) between

consecutive instructions. If CS is low, the internal

control logic is held in a Reset status.

3.2 Serial Clock (CLK)

The Serial Clock is used to synchronize the communi-

cation between a master device and the 93XX series

device. Opcodes, address and data bits are clocked in

on the pos itive edge of CL K. Dat a bit s are also c locke d

out on the positive edge of CLK.

CLK can be stopped anywhere in the transmission

sequence (at high or low level) and can be continued

anytime with respect to clock high time (TCKH) and

clock low time (TCKL). This gives the controlling master

freedom in preparing opcode, address and data.

CLK is a “Don't Care” if CS is low (device deselected).

If CS is high, but the START condition has not been

detected (DI = 0), any number of clock cyc les can be

received by the device without changing its status (i.e.,

waiting for a START condition).

CLK cycles are not required during the self-timed

WRITE (i.e., auto ERASE/WRITE) cycle.

After detection of a START condition the specified

number o f clock c ycle s (re spe ctively low to hi gh transi-

tions of CLK) must be provided. These clock cycles are

required to clock in all required opcode, address and

dat a bits before an in stru ct ion is ex ec ute d. C L K and D I

then become don't care inp uts waiting for a new START

condition to be detected.

3.3 Data In (DI)

Data In (DI) is used to clock in a START bit, opcode,

address and data synchronously with the CLK input.

3.4 Data Out (DO)

Dat a Out (DO) is used in the Re ad mode to ou tput dat a

synchronously with the CLK input (TPD after the posi-

tive edge of CLK).

This pin also provides READY/BUSY status informa-

tion during ERASE and WRITE cycles. READY/BUSY

status information is available on the DO pin if CS is

brought high after being low for minimum Chip Select

low time (TCSL) and an ERASE or WRITE operation

has been initi ated.

The Status signal is not available on DO, if CS is held

low during the entire ERASE or WRITE cycle. In this

case, DO is in the HIGH-Z mode. If status is checked

after the ERASE/W RITE cycle, the data line will be high

to indicate the device is ready.

Note: Issuing a START bit and then taking CS low

will clear the READY/BUSY status from

DO.

3.5 Organization (ORG)

When the ORG pin i s connected to VCC or Logic HI, the

(x16) mem ory organi zation is selected . When the ORG

pin is tied to VSS or Logic LO, the (x8) memory

organization is selected. For proper operation, ORG

must be tied to a valid logic level.

93XX56A devices are always x8 organization and

93XX56B devices are always x16 organization.

Name SOIC/PDIP/

MSOP/TSSOP SOT-23 Rotated SOIC Function

CS 1 5 3 Chip Select

CLK 2 4 4 Serial Clock

DI 3 3 5 Data In

DO 4 1 6 Data Out

VSS 527Ground

ORG/NC 6 N/A 8 Or ganization / 93XX56C

No Internal Connection / 93XX56A/B

NC 7 N/A 1 No Internal Connecti on

VCC 8 6 2 Power Supply

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

DS21794B-page 12  2003 Microchip Technology Inc.

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

Legend: XX...X Part number

T Temperature

Blank Commercial

I Industrial

E Extended

YY Year code (last 2 digits of calendar year) except TSSOP

and MSOP which use only the last 1 digit

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Note: Custom marking available.

Example:

6-Lead SOT-23

8-Lead MSOP (150 mil) Example:

XXXXXXT

YWWNNN 3L56BI

2281L7

XXNN 2EL7

XXXXXNNN

XXXXXXXX

YYWW

8-Lead PDIP

8-Lead SOIC

XXXXYYWW

XXXXXXXX

NNN

XXXX

TYWW

8-Lead TSSOP

NNN

I/P 1L7

93LC56B

0228

Example:

I/SN 0228

93LC56B

1L7

L56B

I228

Example:

MSOP 1st Line Marking Codes

Device

93AA56A

93AA56B

93AA56C

93LC56A

93LC56B

93LC56C

93C56A

93C56B

93C56C

std mark

3A56AT

3A56BT

3A56CT

3L56AT

3L56BT

3L56CT

3C56AT

3C56BT

3C56CT

Pb-free

mark

GA56AT

GA56BT

GA56CT

GL56AT

GL56BT

GL56CT

GC56AT

GC56BT

GC56CT

T = blank for commercial, “I” for Industrial,

“E” for Extended.

TSSOP 1st Line Marking Codes

Device

93AA56A

93AA56B

93AA56C

93LC56A

93LC56B

93LC56C

93C56A

93C56B

93C56C

std mark

A56A

A56B

A56C

L56A

L56B

L56C

C56A

C56B

C56C

Pb-free

mark

GABA

GABB

GABC

GLBA

GLBB

GLBC

GCBA

GCBB

GCBC

Temperature grade is marked on line 2.

SOT23 Marking Codes

Device

93AA56A

93AA56B

93LC56A

93LC56B

93C56A

93C56B

I-temp

2BNN

2LNN

2ENN

2PNN

2HNN

2TNN

E-temp

–

2FNN

2RNN

2JNN

2UNN

Pb-free topside mark is same; Pb-free

noted only on carton label.

 2003 Microchip Technology Inc. DS21794B-page 13

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

(F)

n 1

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

.037 REFFFootprint (Reference)

exceed .010" (0.254mm) per side.

Notes:

Drawing No. C04-111

*Controlling Parameter

Mold Draft Angle Top

Mold Draft Angle Bottom

Foot Angle

Lead Width

Lead Thickness

.003

.009

.006

.012

Dimension Limits

Overall Height

Molded Package Thickness

Molded Package Width

Overall Length

Foot Length

Standoff

Overall Width

Number of Pins

Pitch

.016 .024

.118 BSC

.000

.030

.193 TYP.

.033

MIN

Units

.026 BSC

NOM

INCHES

0.95 REF

.009

.016

0.08

0.22

0°

0.23

0.40

8°

MILLIMETERS*

0.65 BSC

0.85

3.00 BSC

0.60

4.90 BSC

.043

.031

.037

.006

0.40

0.00

0.75

MIN

MAX NOM

1.10

0.80

0.15

0.95

MAX

15°5° -

JEDEC Equivalent: MO-187

0° - 8°

5°

5° -

15°

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

DS21794B-page 14  2003 Microchip Technology Inc.

6-Lead Plastic Small Outline Transistor (OT) (SOT-23)

10501050

Mold Draft Angle Bottom

10501050

Mold Draft Angle Top

0.500.430.35.020.017.014BLead Width

0.200.150.09.008.006.004

Lead Thickness

10501050

Foot Angle

0.550.450.35.022.018.014LFoot Length

3.102.952.80.122.116.110DOverall Length

1.751.631.50.069.064.059

Molded Package Width

3.002.802.60.118.110.102EOverall Width

0.150.080.00.006.003.000

Standoff

1.301.100.90.051.043.035

Molded Package Thickness

1.451.180.90.057.046.035AOverall Height

1.90.075

Outside lead pitch (basic)

0.95.038

Pitch

Number of Pins

MAX

NOM

MINMAX

NOM

MINDimension Limits

MILLIMETERSINCHES*Units

exceed .005" (0.127mm) per side.

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

Notes:

JEITA (formerly EIAJ) equivalent: SC-74A

Drawing No. C04-120

*Controlling Parameter

 2003 Microchip Technology Inc. DS21794B-page 15

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Units INCHES* MILLIMETERS

Dime nsion Limits MIN NOM MAX MIN NOM MAX

Number of Pins n88

Pitch p.100 2.54

Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32

Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68

Base to Seating Plane A1 .015 0.38

Shoulder to Shoulder W idt h E .300 .313 .325 7.62 7.94 8. 26

Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60

Overall Length D .360 .373 .385 9.14 9.46 9.78

Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43

Lead Thickness c.008 .012 .015 0.20 0.29 0.38

Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78

Lower Lead Width B .014 .018 .022 0.36 0.46 0.56

Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92

Mold Draft Angle Top α51015 51015

Mold Draft Angle Bottom β51015 51015

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

JEDEC Equivalent: MS-001

Drawing No. C04-018

.010” (0.254mm) per side.

§ Significant Characteristic

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

DS21794B-page 16  2003 Microchip Technology Inc.

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

Foot A ngle φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008

Lead Thickness

0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Pa ckag e Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004

Standoff § 1.551.421.32.061.056.052A2Molded Packag e Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050

Pitch 88

Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-057

§ Significant Characteristic

 2003 Microchip Technology Inc. DS21794B-page 17

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

10501050

Mold Draft Angle Bottom 10501050

Mold Draft Angle Top 0.300.250.19.012.010.007BLead Width 0.200.150.09.008.006.004

Lead Thickness

0.700.600.50.028.024.020LFoot Length 3.103.002.90.122.118.114DMolded Package Length 4.504.404.30.177.173.169E1Molded Pa ckag e Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002

Standoff § 0.950.900.85.037.035.033A2Molded Package Thickness 1.10.043AOverall Height 0.65.026

Pitch 88

Number of Pins MAXNOMMINMAXNOMMINDimensi on Li mits MILLIMETERS*INCHESUnits

Foot A ngle φ048048

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per side.

JEDEC Equivalent: MO-153

Drawing No. C04-086

§ Significant Characteristic

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

DS21794B-page 18  2003 Microchip Technology Inc.

APPENDIX A: REVISION HISTORY

Revision B

Corrections to Section 1.0, Electrical Characteristics.

Section 4.1, 6-Lead SOT-23 package to OT.

 2003 Microchip Technology Inc. DS21794B-page 19

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip

World Wide Web site.

The web site is used b y Micr ochip as a me ans to mak e

files and information easily available to customers. To

view t he site, the user must have acce ss to the In ternet

and a web browser, such as Netscape® or Microsoft®

Internet Explorer. Files are also available for FTP

download from our FTP site.

Connecting to the Microchip Internet

Web S ite

The Microchip web site is available at the following

URL:

www.microchip.com

The file transfer site is available by using an FTP

service to connect to:

ftp://ftp.microchip.com

The web site and file transfer site provide a variety of

services. Users may download files for the latest

Development Tools, Data Sheets, Application Notes,

User's Guides, Articles and Sample Programs. A vari-

ety of Microchip specific business information is also

available, including listings of Microchip sales offices,

distributors and factory representatives. Other data

available for consideration is:

• Latest Microchip Press Releases

• Technical Support Section with Frequently Asked

Questions

• Design Tips

• Device Errat a

• Job Postin gs

• Mic rochip Consultant Program Member Listing

• Links to other useful web sites related to

Microchip Products

• Confere nces for prod ucts, Dev elopment Systems,

technical information and more

• Listing of seminars and events

SYSTEMS INFORMATION AND

UPGRADE HOT LINE

The Systems Information and Upgrade Line provides

system users a listing of the latest versions of all of

Microchip's development systems software products.

Plus, this line provides information on how customers

can receive the mo st current upgrade kits. The Hot Line

Numbe rs are:

1-800-755-2345 for U.S. and most of Canada, and

1-480-792-7302 for the rest of the world.

042003

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

DS21794B-page 20  2003 Microchip Technology Inc.

READER RESPONSE

It is ou r intentio n to provide you with the b es t do cument a t ion po ss ib le to e ns ure suc c es sfu l u se of y ou r M icr oc hip pro d-

uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, subj ect matte r , and ways i n which o ur docum entatio n

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager

RE: Reader Response Total Pages Sent ________

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS21794B93AA56A/B/C, 93L C56A /B/C, 93C56A/B/C

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

 2003 Microchip Technology Inc. DS21794B-page 21

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Sales and Support

Device 93AA 56A : 2K 1.8V M icro wire Serial EEPROM

93AA56B: 2K 1.8V Microwire Serial EEPROM

93AA56C: 2K 1.8V Microwire Serial EEPRO M w/ORG

93LC56A: 2K 2.5V Microwire Serial EEPROM

93LC56B: 2K 2.5V Microwire Serial EEPROM

93LC56C: 2K 2.5V Microwire Serial EEPROM w/ORG

93C56A: 2K 5.0V Microwire Serial EEPROM

93C56B: 2K 5.0V Microwire Serial EEPROM

93C56C: 2K 5.0V Microwire Serial EEPROM w/ORG

Pinout: Blank = Standard pinout

X = Rotated pino ut

Tape & Reel: Blank = Standard packaging

T=Tape & Reel

Temperature Range I = -40°C to +85°C

E = -40°C to +125°C

Package MS = Plastic MSOP (Micro Small outline, 8-lead)

OT = SOT-23, 6-lead (Tape & Reel only)

P = Plastic DIP (300 mil body), 8-lead

SN = Plastic SOIC (150 mil body), 8-lead

ST = TSSOP, 8-lead

Lead Finish: Blank = Standard 63% / 37% SnPb

G = Pure Matte Sn

Examples:

a) 93AA56C-I/MS: 2K, 256x8 or 128x16 Serial

EEPROM, MSOP package, 1.8V

b) 93AA56B-I/MS: 2K, 128x16 Serial EEPROM,

MSOP package, 1.8V

c) 93AA56AT-I/OT: 2K, 256x8 Serial EEPROM,

SOT-23 package, tape and reel, 1.8V

d) 93AA56CT-I/MS: 2K, 256x8 or 128x16 Serial

EEPROM, MSOP package, tape and reel, 1.8V

a) 93LC56A-I/MS: 2K, 256x8 Serial EEPROM,

MSOP package, 2.5V

b) 93LC56BT-I/OT: 2K, 128x16 Serial EEPROM,

SOT-23 package, tape and reel, 2.5V

c) 93LC56B-I/MS: 2K, 128x16 Serial EEPROM,

MSOP package, 2.5V

d) 93LC56BXT-I/SNG: 2K, 128x16 Serial

EEPROM, SOIC package, rotated pinout,

Industrial temperature, Pb-free finish, 2.5V

a) 93C56B-I/MS: 2K, 128x16 Serial EEPROM,

MSOP package, 5.0V

b) 93C56C-I/MS: 2K, 256x8 or 128x16 Serial

EEPROM, MSOP package, 5.0V

c) 93C56AT-I/OT: 2K, 256x8 Serial EEPROM,

SOT-23 package, tape and reel, 5.0V

PART NO. X/XX

Package

Temperature

Range

Device

Lea d Fi nish

Tape & Reel

Pinout

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences

and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of

the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

DS21794B-page 22  2003 Microchip Technology Inc.

NOTES:

 2003 Microchip Technology Inc. DS21794B-page 23

Information contained in this publication regarding device

applications and the like is intended through sug gestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microc hip Technology Incorporat ed with respect

to the accuracy or use of such inf orm ation, or inf ringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical com-

ponents in life support systems is not authorized except with

express written approval by Microchip. No licenses are con-

veyed, implicitly or otherwise, under any intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, MPLAB, PIC, PIC m ic ro, PI C START,

PRO MATE and PowerSmart are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

AmpLab, FilterLab, microID, MXDEV, MXLAB, PI CMASTER,

SEEVAL and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, microPort,

Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,

PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,

PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,

SmartSensor , SmartShunt, SmartTel and Total Endurance are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorpora ted in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the co de protection features of our

products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such ac t s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999

and M ountain View, California i n March 20 02.

The Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro® 8-bit MCUs, KEELOQ® code hopping

devices, Serial EEPROMs, micr operipherals,

non-volatile memory and analog products. In

addition, Microchip’s quality system for the

design and manufacture of developmen t

systems is ISO 9001 certified.

DS21794B-page 24  2003 Microchip Technology Inc.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792- 72 00

Fax: 480-792-7277

Technical Support: 480-792-7627

Web Address: http://ww w.microchip .com

Atlanta

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Tel: 770-6 40- 003 4

Fax: 770-640-0307

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Tel: 978-6 92- 384 8

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Chicago

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Tel: 630-2 85- 007 1

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Dallas

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Addison, TX 7500 1

Tel: 972-8 18- 742 3

Fax: 972-818-2924

Detroit

Tri-Atria Office Building

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Tel: 408-4 36- 795 0

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China - Chengdu

Rm. 2401-2402, 24th Floor,

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China - Fuzhou

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China - Hong Kong SAR

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China - Sh a ngha i

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Tel: 86-21 -62 75- 57 00

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China - Shenzhen

Rm. 1812, 18/F, Building A, United Plaza

No. 5022 Binhe Road, Futian District

Shenzhen 518033, China

Tel: 86-75 5-8 290 13 80

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China - Sh unde

Room 401, Hongjian Building

No. 2 Fengxiangnan Road, Ronggui Town

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Tel: 86-765-8395507 Fax: 86-765-8395571

China - Qingda o

Rm. B505A, Fullhope Plaza,

No. 12 Hong Kong Central Rd.

Qingdao 266071, China

Tel: 86-532-5027355 Fax: 86-532-5027205

India

Divyasree Chambers

1 Floor, Wing A (A3/A4)

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Japan

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Korea

168-1, Youngbo Bldg. 3 Floor

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82-2-558-5934

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Tel: 65-6334-8870 Fax: 65-6334-8850

Taiwan

Kaohsiung Branch

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Tel: 886-7-536-4818

Fax: 886-7-536-4803

Taiwan

Taiwan Branch

11F-3, No. 207

Tung Hua North Road

Taipei, 105, Taiwan

Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

EUROPE

Austria

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Austria

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Denmark

Regus Business Centre

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Italy

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Milan, Italy

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United Kingdom

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07/28/03

WORLDWIDE SALES AND SERVICE