EVAL-AD7986EBZ - Analog Devices

18-Bit, 2 MSPS, PulSAR

15 mW ADC in LFCSP

Data Sheet AD7986

Rev. D Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

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Technical Support www.analog.com

FEATURES

18-bit resolution with no missing codes

Throughput: 2 MSPS (TURBO = high), 1.5 MSPS (TURBO = low)

Low power dissipation

15 mW at 2 MSPS, with external reference

26 mW at 2 MSPS with internal reference

INL: ±1 LSB typical, ±2.5 LSB maximum

SNR

95.5 dB, with on-chip reference

97.0 dB, with external reference

4.096 V internal reference: typical drift of 10 ppm/°C

True differential analog input voltage range: ±VREF

0 V to VREF with VREF up to 5.0 V

Allows use of any input range

No pipeline delay

Logic interface: 1.8 V/2.5 V/2.7 V

Proprietary serial interface: SPI-/QSPI™-/MICROWIRE™-/DSP-

compatible

Ability to daisy-chain multiple ADCs with busy indicator

20-lead 4 mm × 4 mm LFCSP

APPLICATIONS

Battery-powered equipment

Data acquisition systems

Medical instruments

Seismic data acquisition systems

TYPICAL APPLICATION CIRCUIT

1.5nF

10Ω

V–

REF

NOTES

1. GND REFERS TO REFGND, AGND, AND DGND.

V+

1.5nF

10Ω

V–

V+

IN–

AD7986

IN+

REF

AVDD,

DVDD

VIO

BVDD

5V 2.5V

1.8

2.7V

VIO

SDI

SCK

SDO

CNV

3- OR 4-WIRE

INTERFACE:

SPI, CS

DAISY CHAIN

(TURBO = LOW)

TURBO

10µF

REF

GND

07956-001

Figure 1.

GENERAL DESCRIPTION

The AD79861 is an 18-bit, 2 MSPS successive approximation,

analog-to-digital converter (ADC). It contains a low power,

high speed, 18-bit sampling ADC, an internal conversion clock,

an internal reference (and buffer), error correction circuits, and

a versatile serial interface port. On the rising edge of CNV, the

AD7986 samples the voltage difference between the IN+ and

IN− pins. e voltages on these pins usually swing in opposite

phases between 0 V and VREF. It features a very high sampling

rate turbo mode (TURBO = high) and a reduced power normal

mode (TURBO = low) for low power applications where the

power is scaled with the throughput.

In normal mode (TURBO = low), the SPI-compatible serial

interface also features the ability, using the SDI input, to daisy-

chain several ADCs on a single 3-wire bus and provide an optional

busy indicator. It is compatible with 1.8 V, 2.5 V, and 2.7 V using the

separate VIO supply.

The AD7986 is available in a 20-lead LFCSP with operation

specified from −40°C to +85°C.

1 Protected by U.S. Patent 6,703,961.

Table 1. MSOP, LFCSP 14-/16-/18-Bit PulSAR® ADCs

Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver

14-Bit AD7940 AD79421 AD79461

16-Bit AD7680 AD76851 AD76861 AD79801 ADA4941-1

AD7683 AD76871 AD76881 AD79831 ADA4841-1

AD7684 AD7694 AD76931

18-Bit AD76911 AD76901 AD79821 ADA4941-1

AD79841 ADA4841-1

AD7986 AD8021

1 Pin for pin compatible.

AD7986 Data Sheet

Rev. D | Page 2 of 28

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Typical Application Circuit ............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3 

Timing Specifications .................................................................. 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 12

Theory of Operation ...................................................................... 13

Circuit Information .................................................................... 13

Converter Operation .................................................................. 13

Conversion Modes of Operation .............................................. 13

Typical Connection Diagram ................................................... 14

Analog Inputs ............................................................................. 15

Driver Amplifier Choice ........................................................... 15

Voltage Reference Input ............................................................ 16

Power Supply ............................................................................... 16

Digital Interface .............................................................................. 17

Data Reading Options ............................................................... 18

CS Mode, 3-Wire Without Busy Indicator ............................. 19

CS Mode, 3-Wire with Busy Indicator .................................... 20

CS Mode, 4-Wire Without Busy Indicator ............................. 21

CS Mode, 4-Wire with Busy Indicator .................................... 22

Chain Mode Without Busy Indicator ...................................... 23

Chain Mode with Busy Indicator ............................................. 24

Application Hints ........................................................................... 25

Layout .......................................................................................... 25

Evaluating the Performance of the AD7986 ............................... 25

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 27

REVISION HISTORY

3/16—Rev. C to Rev. D

Changes to Figure 1 and Table 1 ..................................................... 1

Change to Transition Noise Parameter, Table 2 ........................... 3

Deleted Endnote 4, Table 2 .............................................................. 3

Changes to Figure 4 .......................................................................... 8

Changes to Figure 23 ...................................................................... 14

Changes to Driver Amplifier Choice Section ............................. 15

Changes to Reference Decoupling Section ................................. 16

Changes to Reading During Conversion, Fast Host (Turbo or

Normal Mode) Section and Split-Reading, Any Speed Host

(Turbo or Normal Mode) Section ................................................ 18

Changes to Figure 30 ...................................................................... 21

Changes to Figure 34 ...................................................................... 23

Changes to Evaluating the Performance of the AD7986 Section .. 25

Updated Outline Dimensions ....................................................... 27

Changes to Ordering Guide .......................................................... 27

8/14—Rev. B to Rev. C

Replaced QFN with LFCSP .......................................... Throughout

Changed Application Diagram Section to Typical Application

Circuit Section ................................................................................... 1

Change to Features Section .............................................................. 1

Added Patent Note, Note 2 ............................................................... 1

Changed 5 V to 4.096 V, Analog Input Heading, Table 7 ......... 14

Changes to Evaluating the Performance of the AD7986

Sec tion .............................................................................................. 25

Updated Outline Dimensions ....................................................... 27

Changes to Ordering Guide .......................................................... 27

3/11—Rev. A to Rev. B

Added Common-Mode Input Range Parameter, Table 2 ............ 3

8/10—Rev. 0 to Rev. A

Changes to Conversion Time: CNV Rising Edge to Data

Available (Turbo Mode/Normal Mode) Parameter, Table 4 ........ 5

Changes to Figure 32 ...................................................................... 22

4/09—Revision 0: Initial Version

Data Sheet AD7986

Rev. D | Page 3 of 28

SPECIFICATIONS

AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted.

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

RESOLUTION 18 Bits

ANALOG INPUT

Voltage Range (IN+) − (IN−) −VREF +VREF V

Absolute Input Voltage

IN+, IN−

−0.1

REF

+ 0.1

Common-Mode Input Range IN+, IN− VREF × 0.475 VREF × 0.5 VREF × 0.525 V

Analog Input CMRR fIN = 500 kHz 100 dB1

Leakage Current at 25°C Acquisition phase 250 nA

Input Impedance See the Analog Inputs section

ACCURACY

No Missing Codes 18 Bits

Differential Linearity Error −0.95 ±0.60 +1.50 LSB2

Integral Linearity Error −2.50 ±1.00 +2.50 LSB2

Transition Noise

1.4

LSB

Gain Error, TMIN to TMAX3 −20 ±2.4 +20 LSB2

Gain Error Temperature Drift ±0.5 ppm/°C

Zero Error, TMIN to TMAX3 −0.8 +0.8 mV

Zero Temperature Drift ±0.3 ppm/°C

Power Supply Sensitivity

AVDD = 2.5 V ± 5%

±4

LSB

THROUGHPUT

Conversion Rate 0 2.00 MSPS

Transient Response Full-scale step 100 ns

AC ACCURACY

Dynamic Range VREF = 4.096 V, internal reference 95.5 96.5 dB1

REF

= 5.0 V, external reference

Signal-to-Noise Ratio, SNR fIN = 20 kHz, VREF = 4.096 V, internal

reference

94.5 95.5 dB1

fIN = 20 kHz, VREF = 5.0 V, external

reference

96.5 97.0 dB1

Spurious-Free Dynamic Range, SFDR fIN = 20 kHz −115 dB1

Total Harmonic Distortion, THD fIN = 20 kHz, VREF = 4.096 V, internal

reference

−113 dB1

fIN = 20 kHz, VREF = 5.0 V, external

reference

−114 dB1

Signal-to-(Noise + Distortion), SINAD fIN = 20 kHz, VREF = 4.096 V 94.5 95.5 dB1

SAMPLING DYNAMICS

−3 dB Input Bandwidth 19 MHz

Aperture Delay

0.7

1 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

2 LSB means least significant bit. With the 4.096 V input range, one LSB is 31.25 µV.

3 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.

AD7986 Data Sheet

Rev. D | Page 4 of 28

AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted.

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

INTERNAL REFERENCE PDREF = low

Output Voltage TA = 25°C 4.081 4.096 4.111 V

Temperature Drift −40°C to +85°C ±10 ppm/°C

Line Regulation

AVDD = 2.5 V ± 5%

±50

ppm/V

Turn-On Settling Time CREF = 10 μF, CREFBUFIN = 0.1 μF 220 ms

REFIN Output Voltage REFIN at 25°C 1.2 V

REFIN Output Resistance 7.5 kΩ

EXTERNAL REFERENCE PDREF = high, REFIN = low

Voltage Range 2.4 5.1 V

Current Drain 2 MSPS, VREF = 5.0 V 500 µA

REFERENCE BUFFER

REFIN Input Voltage Range 1.2 V

REFIN Input Current 160 µA

DIGITAL INPUTS

Logic Levels

VIL −0.3 +0.1 × VIO V

VIH +0.9 × VIO VIO + 0.3 V

IIL −1 +1 µA

IIH −1 +1 µA

DIGITAL OUTPUTS

Data Format Serial, 18 bits, twos complement

Pipeline Delay Conversion results available immediately

after completed conversion

VOL ISINK = +500 µA 0.4 V

VOH ISOURCE = −500 µA VIO − 0.3 V

POWER SUPPLIES

AVDD, DVDD 2.375 2.5 2.625 V

BVDD 4.75 5.0 5.25

VIO Specified performance 1.8 2.5 2.7 V

VIO Range V

Standby Current1, 2 AVDD = DVDD = VIO = 2.5 V, BVDD = 5.0 V 2.25 µA

Power Dissipation

With Internal Reference 2 MSPS throughput 29 34 mW

Without Internal Reference 2 MSPS throughput 15 16.5 mW

With Internal Reference 1.5 MSPS throughput 26 30 mW

Without Internal Reference 1.5 MSPS throughput 11.5 13 mW

TEMPERATURE RANGE

Specified Performance TMIN to TMAX −40 +85 °C

1 With all digital inputs forced to VIO or GND as required.

2 During acquisition phase.

3 Contact an Analog Devices, Inc., sales representative for the extended temperature range.

Data Sheet AD7986

Rev. D | Page 5 of 28

TIMING SPECIFICATIONS

AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted.1

Table 4.

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available (Turbo Mode/Normal Mode) tCONV 400/500 ns

Acquisition Time tACQ 100 ns

Time Between Conversions (Turbo Mode/Normal Mode) tCYC 500/660 ns

CNV Pulse Width (CS Mode) tCNVH 10 ns

Data Read During Conversion (Turbo Mode/Normal Mode) tDATA 200/300 ns

Quiet Time During Acquisition from Last SCK Falling Edge to CNV Rising Edge

QUIET

SCK Period (CS Mode) tSCK 9 ns

SCK Period (Chain Mode) tSCK 11 ns

SCK Low Time tSCKL 3.5 ns

SCK High Time tSCKH 3.5 ns

SCK Falling Edge to Data Remains Valid tHSDO 2 ns

SCK Falling Edge to Data Valid Delay tDSDO 6 ns

CNV or SDI Low to SDO D17 MSB Valid (CS Mode) tEN 10 ns

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 8 ns

SDI Valid Setup Time from CNV Rising Edge tSSDICNV 4 ns

SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns

SDI Valid Hold Time from CNV Rising Edge (Chain Mode)

HSDICNV

SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns

SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns

SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 2 ns

SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 3 ns

SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 5 ns

1 See Figure 2 and Figure 3 for load conditions.

500µA I

1.4V

TO SDO C

20pF

07956-002

Figure 2. Load Circuit for Digital Interface Timing

90% VIO 10% V I O

IH1

IL1

IH1

tDELAY tDELAY

MINIMUM V

AND MAXI M UM V

USED. SEE DIGITAL INPUTS

SPECIFICATIONS IN TABLE 3.

07956-003

Figure 3. Voltage Levels for Timing

AD7986 Data Sheet

Rev. D | Page 6 of 28

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs

IN+, IN− to GND1 −0.3 V to VREF + 0.3 V

or ±130 mA

Supply Voltage

REF, BVDD to GND, REFGND −0.3 V to +6.0 V

AVDD, DVDD, VIO to GND −0.3 V to +2.7 V

AVDD and DVDD to VIO

+3 V to −6 V

Digital Inputs to GND

−0.3 V to VIO + 0.3 V

Digital Outputs to GND −0.3 V to VIO + 0.3 V

Storage Temperature Range −65°C to +150°C

Junction Temperature 150°C

θJA Thermal Impedance

20-Lead LFCSP 30.4°C/W

Lead Temperatures

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

1 See the Analog Inputs section for an explanation of IN+ and IN−.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

ESD CAUTION

Data Sheet AD7986

Rev. D | Page 7 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

07956-004

NOTES

1. THE EX P OSED P AD IS NOT CO NNE CTED INT E RNALLY .

FOR INCREASED RELIABILITY OF THE SOLDER JOINTS,

IT IS RE COMM E NDE D THAT THE P AD BE S OLDE RE D TO

THE SYSTEM GROUND PLANE.

SDI

15 TURBO

CNV

SCK

11 DVDD

REF

REFGND 2

REF

REFGND 5

IN–

PDREF 6

IN+

VIO 9

SDO 10

DGND

19 BVDD

20 REFIN

18 AGND

17 AGND

16 AVDD

AD7986

TOP VIEW

(No t t o Scal e)

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1, 2 REF AI Reference Output/Input Voltage.

When PDREF = low, the internal reference and buffer are enabled, producing 4.096 V on this pin.

When PDREF = high, the internal reference and buffer are disabled, allowing an externally supplied

voltage reference up to 5.0 V.

Decoupling is required with or without the internal reference and buffer. This pin is referred to the

REFGND pins and must be decoupled closely to the REFGND pins with a 10 µF capacitor.

3, 4

REFGND

Reference Input Analog Ground.

5 IN− AI Differential Negative Analog Input.

6 IN+ AI Differential Positive Analog Input.

7 PDREF DI Internal Reference Power-Down Input.

When low, the internal reference is enabled.

When high, the internal reference is powered down and an external reference must be used.

8 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface

(1.8 V, 2.5 V, or 2.7 V).

9 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.

10 DGND P Digital Power Ground.

11 DVDD P Digital Power. Nominally at 2.5 V.

SCK

Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock.

13 CNV DI Convert Input. This input has multiple functions. On the leading edge, it initiates the conversions

and selects the interface mode of the device: chain mode or CS mode. In CS mode, the SDO pin is

enabled when CNV is low. In chain mode, the data must be read when CNV is high.

14 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:

Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data

input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital

data level on SDI is output on SDO with a delay of 18 SCK cycles.

CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can

enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the

busy indicator feature is enabled.

TURBO

Conversion Mode Selection.

When TURBO = high, the maximum throughput (2 MSPS) is achieved. The ADC does not power down

between conversions.

When TURBO = low, the maximum throughput is lower (1.5 MSPS). The ADC powers down between

conversions.

AVDD

Input Analog Power. Nominally at 2.5 V.

17,18 AGND P Analog Power Ground.

AD7986 Data Sheet

Rev. D | Page 8 of 28

Pin No. Mnemonic Type1 Description

19 BVDD P Reference buffer power. Nominally 5.0 V.

If an external reference buffer is used to achieve the maximum SNR performance with 5 V reference,

the reference buffer must be powered down by connecting the REFIN pin to ground. The external

reference buffer must be connected to the BVDD pin.

REFIN

AI/O

Internal Reference Output/Reference Buffer Input.

When PDREF = low, the internal band gap reference produces a 1.2 V (typical) voltage on this pin,

which needs external decoupling (0.1 µF typical).

When PDREF = high, use an external reference to provide a 1.2 V (typical) to this pin.

When PDREF = high, and REFIN = low, the on-chip reference buffer and band gap are powered down.

An external reference must be connected to REF and BVDD.

21 (EPAD)

Exposed Pad

The exposed pad is not connected internally. For increased reliability of the solder joints, it is

recommended that the pad be soldered to the system ground plane.

1 AI = analog input, AI/O = bidirectional analog; DI = digital input, DO = digital output, and P = power.

Data Sheet AD7986

Rev. D | Page 9 of 28

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = DVDD = VIO = 2.5 V, BVDD = 5.0 V, VREF = 5.0 V, external reference (PDREF = high, REFIN = low), unless otherwise noted.

065,536 131,072 196,608 262,144

–2.5

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

2.5

CODE

INL (LSB)

POSITIVE INL = +1. 57LSB

NEGATIVE INL = –1. 25LSB

07956-005

Figure 5. Integral Nonlinearity vs. Code

0101 1661

8250

35,204

41,811

34,894

7662

1418 68 30

5000

10,000

15,000

20,000

25,000

30,000

35,000

40,000

45,000

3FF6 3FF8 3FFA 3FFC 3FFE 0

COUNTS

CODE IN HEX

07956-006

Figure 6. Histogram of DC Input at Code Center (External Reference)

0 1 55 547 407 35 0

5000

10,000

15,000

20,000

25,000

30,000

35,000

40,000

45,000

3FFEC 3FFEE 3FF0 3FF2 3FF4 3FF6 3FF8

COUNTS

CODE IN HEX

3662

12,773

31,020

39,395

29,138

2932

11,107

07956-007

Figure 7. Histogram of DC Input at Code Center (Internal Reference)

065,536 131,072 196,608 262,144

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

CODE

DNL (LSB)

POSITI VE DNL = +0.54L S B

NEGATI VE DNL = –0.60L S B

07956-008

Figure 8. Differential Nonlinearity vs. Code

0 4 142 34 1 0

5000

10,000

15,000

20,000

25,000

30,000

35,000

40,000

45,000

3FF5 3FF7 3FF9 3FFB 3FFD 3FFF 1

COUNTS

CODE IN HEX

10,211

38,665

41,434

30,897

2283

6399

1002

07956-009

Figure 9. Histogram of DC Input at Code Transition (External Reference)

0 1 31501282

6513 6879

1438165 16 0

5000

10,000

15,000

20,000

25,000

30,000

35,000

40,000

3FFEB 3FFED 3FFEF 3FF1 3FF3 3FF5 3FF7 3FF9

COUNTS

CODE IN HE X

18,953

22,077

37,385

36,210

07956-010

Figure 10. Histogram of DC Input at Code Transition (Internal Reference)

AD7986 Data Sheet

Rev. D | Page 10 of 28

0200k 400k 600k 800k 1M

–180

–200

–160

–140

–120

–100

–80

–60

–40

–20

FREQUENCY (Hz)

AMPLITUDE ( dB)

07956-111

= 2MSPS

= 20kHz

SNR = 97. 0dB

THD = – 114.0dB

SINAD = 97.0d B

Figure 11. FFT Plot (External Reference)

100

2.53.0 3.54.0 4.55.0

ENOB (Bits)

SNR, S INAD (dB)

REFERENCEVOLTAGE(V)

SNR

SINAD

ENOB

07956-212

Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage

100

1k 10k 100k 1M

SINAD (dB)

FREQUENCY (Hz)

07956-013

Figure 13. SINAD vs. Frequency

0200k 400k 600k 800k 1M

–180

–160

–140

–120

–100

–80

–60

–40

–20

FREQUENCY (Hz)

AMPLITUDE ( dB)

07956-114

S = 2MSPS

IN = 20kHz

SNR = 95. 5dB

THD = – 113.0dB

SINAD = 95.5d B

Figure 14. FFT Plot (Internal Reference)

105

110

100

115

120

125

–120

–125

–115

–110

–105

–100

–95

2.53.0 3.54.0 4.55.0

SFDR (dB)

THD (dB)

REFERENCE VOLTAGE (V)

THD

SFDR

07956-015

Figure 15. THD and SFDR vs. Reference Voltage

–125

–120

–115

–110

–105

–100

–95

–90

–85

–80

1k 10k 100k 1M

THD ( dB)

FREQUENCY ( Hz )

07956-216

Figure 16. THD vs. Frequency

Data Sheet AD7986

Rev. D | Page 11 of 28

100

–10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0

SNR (dB REF E RRE D TO FULL SCALE)

INPUT LEVEL (d B)

07956-032

Figure 17. SNR vs. Input Level

0.5

1.0

1.5

2.0

2.5

3.0

2.375 2.425 2.475 2.525 2.575 2.625

SUPPLY CURRE NT (mA)

AVDD AND DVDD VOL TAG E (V)

REF

AVDD

DVDD

BVDD

VIO

07956-033

Figure 18. Operating Currents vs. Supply Voltage

0.5

1.0

1.5

2.0

2.5

3.0

–55 –35 –15 525 45 65 85 105 125

SUPPLYCURRENT(mA)

TEMPERATURE (C)

REF

AVDD

BVDD

07956-034

Figure 19. Operating Currents vs. Temperature

–55 –35 –15 525 45 65 85 105 125

SUPPLY CURRE NT (µ A)

IAVDD + IDVDD + IVIO

TEMPERATURE (°C)

07956-035

Figure 20. Power-Down Currents vs. Temperature

AD7986 Data Sheet

Rev. D | Page 12 of 28

TERMINOLOGY

Integral Nonlinearity Error (INL)

INL refers to the deviation of each individual code from a line

drawn from negative full scale through positive full scale. The

point used as negative full scale occurs ½ LSB before the first

code transition. Positive full scale is defined as a level 1½ LSB

beyond the last code transition. The deviation is measured from

the middle of each code to the true straight line (see Figure 22).

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the

maximum deviation from this ideal value. It is often specified in

terms of resolution for which no missing codes are guaranteed.

Zero Error

Zero error is the difference between the ideal midscale voltage,

that is, 0 V, from the actual voltage producing the midscale

output code, that is, 0 LSB.

Gain Error

The first transition (from 100 ... 00 to 100 ... 01) must occur at a

level ½ LSB above nominal negative full scale (−4.095984 V for

the ±4.096 V range). The last transition (from 011 … 10 to

011 … 11) must occur for an analog voltage 1½ LSB below

the nominal full scale (+4.095953 V for the ±5 V range). The

gain error is the deviation of the difference between the actual

level of the last transition and the actual level of the first transition

from the difference between the ideal levels.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels (dB), between the rms

amplitude of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave

input. It is related to SINAD as follows:

ENOB = (SINADdB − 1.76)/6.02

and is expressed in bits.

Noise-Free Code Resolution

Noise-free code resolution is the number of bits beyond which it is

impossible to distinctly resolve individual codes. It is calculated as

Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise)

and is expressed in bits.

Effective Resolution

Effective resolution is calculated as

Effective Resolution = log2(2N/RMS Input Noise)

and is expressed in bits.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic

components to the rms value of a full-scale input signal and is

expressed in decibels.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to

the total rms noise measured with the inputs shorted together.

The value for dynamic range is expressed in decibels. It is measured

with a signal at −60 dBF so that it includes all noise sources and

DNL artifacts.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to

the rms sum of all other spectral components below the Nyquist

frequency, excluding harmonics and dc. The value for SNR is

expressed in decibels.

Signal-to-(Noise + Distortion) (SINAD)

SINAD is the ratio of the rms value of the actual input signal to

the rms sum of all other spectral components that are less than

the Nyquist frequency, including harmonics but excluding dc.

The value of SINAD is expressed in decibels.

Aperture Delay

Aperture delay is the measure of the acquisition performance

and is the time between the rising edge of the CNV input and

when the input signal is held for a conversion.

Transient Response

Transient response is the time required for the ADC to accurately

acquire the input after a full-scale step function is applied.

Data Sheet AD7986

Rev. D | Page 13 of 28

THEORY OF OPERATION

COMP CONTROL

LOGIC

SWITCHES CONTROL

BUSY

OUTPUT CODE

CNV

CC2C

65,536C 4C

131,072C

LSB SW+

MSB

LSB SW–

MSB

CC2C

65,536C 4C131,072C

IN+

REF

REFGND

IN–

07956-011

Figure 21. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7986 is a fast, low power, single-supply, precise, 18-bit

ADC using a successive approximation architecture. The AD7986

features different modes to optimize performance according to

the application. In turbo mode, the AD7986 is capable of convert-

ing 2,000,000 samples per second (2 MSPS).

The AD7986 provides the user with an on-chip track-and-hold

and does not exhibit any pipeline delay or latency, making it ideal

for multiple multiplexed channel applications.

The AD7986 can be interfaced to any 1.8 V to 2.7 V digital logic

family. It is available in a 20-lead LFCSP that allows space savings

and flexible configurations.

CONVERTER OPERATION

The AD7986 is a successive approximation ADC based on a

charge redistribution DAC. Figure 21 shows the simplified

schematic of the ADC. The capacitive DAC consists of two

identical arrays of 18 binary-weighted capacitors that are

connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the

input of the comparator are connected to AGND via SW+ and

SW−. All independent switches are connected to the analog inputs.

Therefore, the capacitor arrays are used as sampling capacitors

and acquire the analog signal on the IN+ and IN− inputs.

When the acquisition phase is complete and the CNV input goes

high, a conversion phase is initiated. When the conversion phase

begins, SW+ and SW− are opened first. The two capacitor arrays

are then disconnected from the analog inputs and connected to

the REFGND input. Therefore, the differential voltage between

Input IN+ and Input IN− captured at the end of the acquisition

phase is applied to the comparator inputs, causing the comparator

to become unbalanced. By switching each element of the capacitor

array between REFGND and REF, the comparator input varies

by binary-weighted voltage steps (VREF/2, VREF/4 … VREF/262,144).

The control logic toggles these switches, starting with the MSB,

to bring the comparator back into a balanced condition. After

the completion of this process, the device returns to the acquisition

phase, and the control logic generates the ADC output code

and a busy signal indicator.

Because the AD7986 has an on-board conversion clock, the

serial clock, SCK, is not required for the conversion process.

CONVERSION MODES OF OPERATION

The AD7986 features two conversion modes of operation: turbo

and normal. Turbo conversion mode (TURBO = high) allows the

fastest conversion rate of up to 2 MSPS, and does not power down

between conversions. The first conversion in turbo mode must

be ignored because it contains meaningless data. For applications

that require lower power and slightly slower sampling rates, the

normal mode (TURBO = low) allows a maximum conversion rate

of 1.5 MSPS, and powers down between conversion. The first

conversion in normal mode does contain meaningful data.

AD7986 Data Sheet

Rev. D | Page 14 of 28

Transfer Functions

The ideal transfer function for the AD7986 is shown in Figure 22

and Table 7.

100 ... 000

100 ... 001

100 ... 010

011 ... 101

011 ... 110

011 ... 111

ADC CODE (TWOS COMPLEMENT)

ANALOG INPUT

+FSR – 1.5 LSB

+FSR – 1 LSB

–FSR + 1 LSB

–FSR

–FSR + 0.5 LSB

07956-012

Figure 22. ADC Ideal Transfer Function

Table 7. Output Codes and Ideal Input Voltages

Description

Analog Input

VREF = 4.096 V

Digital Output

Code (Hex)

FSR − 1 LSB +4.095969 V 0x1FFFF1

Midscale + 1 LSB +31.25 μV 0x00001

Midscale 0 V 0x00000

Midscale − 1 LSB −31.25 μV 0x3FFFF

−FSR + 1 LSB −4.095969 V 0x20001

−FSR −4.096 V 0x200002

1 This is also the code for an overranged analog input (VIN+ − VIN− above

VREF − REFGND).

2 This is also the code for an underranged analog input (VIN+ − VIN− below REFGND).

TYPICAL CONNECTION DIAGRAM

Figure 23 shows an example of the recommended connection

diagram for the AD7986 when multiple supplies are available.

7956-016

1.5nF

10Ω

V–

0V TO V

REF

V+

1.5nF

10Ω

V–

V+

IN–

AD7986

IN+

REF

AVDD,

DVDD

DD VIO

BVDD

2.5

1.8V TO 2.7

VIO

SDI

SCLK

SDO

CNV

TURBO

10µF

REF

TO 0V GND

NOTES

1. GND REFERS TO REFGND, AGND, AND DGND.

3- OR 4-WIRE

INTERFACE:

SPI, CS

DAISY CHAIN (TURBO = LOW)

Figure 23. Typical Application Diagram with Multiple Supplies

Data Sheet AD7986

Rev. D | Page 15 of 28

ANALOG INPUTS

Figure 24 shows an equivalent circuit of the input structure of

the AD7986.

The two diodes, D1 and D2, provide ESD protection for the analog

inputs, IN+ and IN−. Take care to ensure the analog input signal

does not exceed the reference input voltage (REF) by more than

0.3 V. If the analog input signal exceeds this level, the diodes

become forward-biased and start conducting current. These

diodes can handle a forward-biased current of 130 mA maximum.

However, if the supplies of the input buffer (for example, the V+

and V− supplies of the buffer amplifier in Figure 23) are different

from those of REF, the analog input signal may eventually exceed

the supply rails by more than 0.3 V. In such a case (for example,

an input buffer with a short circuit), the current limitation can

protect the device.

REF

IN+ OR I N–

GND

07956-014

Figure 24. Equivalent Analog Input Circuit

The analog input structure allows the sampling of the true

differential signal between IN+ and IN−. By using these differential

inputs, signals common to both inputs are rejected.

During the acquisition phase, the impedance of the analog

inputs (IN+ or IN−) can be modeled as a parallel combination

of Capacitor CPIN and the network formed by the series connection

of Resistor RIN and Capacitor CIN. Capacitor CPIN is primarily the

pin capacitance. Resistor RIN is typically 400 Ω and is a lumped

component composed of serial resistors and the on resistance of

the switches. Capacitor CIN is typically 30 pF and is mainly the

ADC sampling capacitor.

During the sampling phase, where the switches are closed, the

input impedance is limited to Capacitor CPIN. Resistor RIN and

Capacitor CIN make a one-pole, low-pass filter that reduces

undesirable aliasing effects and limits noise.

When the source impedance of the driving circuit is low, the

AD7986 can be driven directly. Large source impedances

significantly affect the ac performance, especially THD. The

dc performances are less sensitive to the input impedance. The

maximum source impedance depends on the amount of THD

that can be tolerated. The THD degrades as a function of the

source impedance and the maximum input frequency.

DRIVER AMPLIFIER CHOICE

Although the AD7986 is easy to drive, the driver amplifier must

meet the following requirements:

• The noise generated by the driver amplifier must be kept as

low as possible to preserve the SNR and transition noise

performance of the AD7986. The noise from the driver is

filtered by the AD7986 analog input circuit one-pole, low-

pass filter, made by RIN and CIN or by the external filter if

one is used. Because the typical noise of the AD7986 is

44 µV rms, the SNR degradation due to the amplifier is













−2

2)(

log20

LOSS

Nef

SNR

where:

f–3dB is the input bandwidth, in megahertz, of the AD7986

(19 MHz) or the cutoff frequency of the input filter, if

one is used.

N is the noise gain of the amplifier (for example, 1 in buffer

configuration).

eN is the equivalent input noise voltage of the operational

amplifier, in nV/√Hz.

• For ac applications, the driver must have a THD perfor-

mance commensurate with the AD7986.

• For multichannel multiplexed applications, the driver

amplifier and the AD7986 analog input circuit must settle

for a full-scale step onto the capacitor array at an 18-bit level

(0.0004%, 4 ppm). In the data sheet of the driver amplifier,

settling at 0.1% to 0.01% is more commonly specified. This

may differ significantly from the settling time at an 18-bit

level and must be verified prior to driver selection.

Table 8. Recommended Driver Amplifiers

Amplifier Typical Application

AD8021 Very low noise and high frequency

AD8022 Low noise and high frequency

ADA4899-1 Ultralow noise and high frequency

AD8014 Low power and high frequency

AD7986 Data Sheet

Rev. D | Page 16 of 28

VOLTAGE REFERENCE INPUT

The AD7986 allows the choice of a very low temperature drift

internal voltage reference, an external reference, or an external

buffered reference.

The internal reference of the AD7986 provides excellent

performance and can be used in almost all applications.

Internal Reference, REF = 4.096V (PDREF = Low)

To use the internal reference, the PDREF input must be low. This

enables the on-chip band gap reference and buffer, resulting in

a 4.096 V reference on the REF pin (1.2 V on REFIN).

The internal reference is temperature compensated to 4.096 V ±

15 mV. The reference is trimmed to provide a typical drift of

10 ppm/°C.

The output resistance of REFIN is 6 kΩ when the internal

reference is enabled. It is necessary to decouple this pin with a

ceramic capacitor of at least 100 nF. The output resistance of REFIN

and the decoupling capacitor form an RC filter, which helps to

reduce noise.

Because the output impedance of REFIN is typically 6 kΩ, relative

humidity (among other industrial contaminants) can directly affect

the drift characteristics of the reference. A guard ring typically

reduces the effects of drift under such circumstances. However,

the fine pitch of the AD7986 makes this difficult to implement.

One solution, in these industrial and other types of applications,

is to use a conformal coating, such as Dow Corning® 1-2577 or

HumiSeal® 1B73.

External 1.2 V Reference and Internal Buffer (PDREF = High)

To use an external reference along with the internal buffer, PDREF

must be high. This powers down the internal reference and

allows the 1.2 V reference to be applied to REFIN, producing

4.096 V (typically) on the REF pin.

External Reference (PDREF = High, REFIN = Low)

To apply an external reference voltage directly to the REF pin,

PDREF must be tied high, and REFIN must be tied low. BVDD

must also be driven to the same potential as REF. For example,

if REF = 2.5 V, BVDD must be tied to 2.5 V.

The advantages of directly using the external voltage reference are:

 The SNR and dynamic range improvement (about 1.7 dB)

resulting from the use of a larger reference voltage (5 V)

instead of a typical 4.096 V reference when the internal

reference is used. This is calculated by













0.5

096.4

log20SNR

 The power savings when the internal reference is powered

down (PDREF high).

Reference Decoupling

The AD7986 voltage reference input, REF, has a dynamic input

impedance that requires careful decoupling between the REF

and REFGND pins. The Layout section describes how this can

be done.

When using an external reference, a very low impedance source

(for example, a reference buffer using the AD8031 or the AD8605),

and a 10 μF (X5R, 0805 size) ceramic chip capacitor are appropriate

for optimum performance.

If an unbuffered reference voltage is used, the decoupling value

depends on the reference used. For instance, a 22 μF (X5R,

1206 size) ceramic chip capacitor is appropriate for optimum

performance using a low temperature drift ADR434 reference.

If desired, a reference decoupling capacitor with values as small

as 2.2 μF can be used with minimal impact on performance,

especially DNL.

Regardless, there is no need for an additional lower value ceramic

decoupling capacitor (for example, 100 nF) between the REF

and REFGND pins.

POWER SUPPLY

The AD7986 uses four power supply pins: an analog supply

(AVDD), a buffer supply (BVDD), a digital supply (DVDD),

and a digital input/output interface supply (VIO). VIO allows

direct interface with any logic between 1.8 V and 2.7 V. To reduce

the number of supplies needed, VIO, DVDD, and AVDD can

be tied together. The AD7986 is independent of power supply

sequencing among all of the supplies. Additionally, it is very

insensitive to power supply variations over a wide frequency range.

Data Sheet AD7986

Rev. D | Page 17 of 28

DIGITAL INTERFACE

Although the AD7986 has a reduced number of pins, it offers

flexibility in the serial interface modes.

When in CS mode, the AD7986 is compatible with SPI,

MICROWIRE™, QSPI™, and digital hosts. In this mode, the

AD7986 can use either a 3-wire or a 4-wire interface. A 3-wire

interface using the CNV, SCK, and SDO signals minimizes wiring

connections, which is useful, for instance, in isolated applications.

A 4-wire interface using the SDI, CNV, SCK, and SDO signals

allows CNV, which initiates conversions, to be independent of

the readback timing (SDI). This is useful in low jitter sampling

or simultaneous sampling applications.

When in chain mode, the AD7986 provides a daisy-chain feature

using the SDI input for cascading multiple ADCs on a single data

line similar to a shift register. Chain mode is only available in

normal mode (TURBO = low).

The mode in which the device operates depends on the SDI

level when the CNV rising edge occurs. The CS mode is

selected if SDI is high, and the chain mode is selected if SDI is

low. The SDI hold time is such that when SDI and CNV are

connected together, the chain mode is always selected.

In normal mode operation, the AD7986 offers the option of

forcing a start bit in front of the data bits. This start bit can be

used as a busy signal indicator to interrupt the digital host and

trigger the data reading. Otherwise, without a busy indicator,

the user must time out the maximum conversion time prior to

readback.

The busy indicator feature is enabled in CS mode if CNV or

SDI is low when the ADC conversion ends (see Figure 28 and

Figure 32), and TURBO must be kept low for both digital

interfaces.

When CNV is low, reading can occur during conversion and

acquisition, and when split across acquisition and conversion,

as detailed in the following sections.

A discontinuous SCK is recommended because the device is

selected with CNV low, and SCK activity begins to clock

out data.

Note that in the following sections, the timing diagrams

indicate digital activity (SCK, CNV, SDI, and SDO) during

the conversion. However, due to the possibility of performance

degradation, digital activity must occur only prior to the safe

data reading time, tDATA, because the AD7986 provides error

correction circuitry that can correct for an incorrect bit decision

during this time. From tDATA to tCONV, there is no error correction,

and conversion results may be corrupted. Similarly, tQUIET, the

time from the last falling edge of SCK to the rising edge of CNV,

must remain free of digital activity. The user must configure the

AD7986 and initiate the busy indicator (if desired in normal

mode) prior to tDATA. It is also possible to corrupt the sample by

having SCK near the sampling instant. Therefore, it is recom-

mended to keep the digital pins quiet for approximately 20 ns

before and 10 ns after the rising edge of CNV, using a

discontinuous SCK whenever possible to avoid any potential

performance degradation.

AD7986 Data Sheet

Rev. D | Page 18 of 28

DATA READING OPTIONS

There are three different data reading options for the AD7986.

There is the option to read during conversion, to split the read

across acquisition and conversion (see Figure 25 and Figure 26),

and in normal mode, to read during acquisition. The desired

SCK frequency largely determines which reading option to

pursue.

Reading During Conversion, Fast Hosts (Turbo or

Normal Mode)

When reading during conversion (n), conversion results are for

the previous (n − 1) conversion. Reading must only occur up to

tDATA and, because this time is limited, the host must use a

fast SCK.

The required SCK frequency is calculated by

CNVH

DATA

SCK

Edges

SCKNumber

f−

−

≥_

To determine the SCK frequency, follow these examples to read

data from conversion (n − 1).

Turbo mode (2 MSPS),

Number_SCK_Edges = 18; tDATA = 200 ns; tCNVH = 10 ns; tEN = 10 ns

fSCK = 18/(200 ns − 10 ns − 10 ns) = 100 MHz

Normal mode (1.5 MSPS),

Number_SCK_Edges = 18; tDATA = 300 ns; tCNVH = 10 ns; tEN = 10 ns

fSCK = 18/(300 ns − 10 ns − 10 ns) = 64.3 MHz

The time between tDATA and tCONV is an input/output quiet time

where digital activity must not occur, or sensitive bit decisions

may be corrupt.

Split-Reading, Any Speed Host (Turbo or Normal Mode)

To allow for slower SCK, there is the option of a split read where

data access starts at the current acquisition (n) and spans into the

conversion (n). Conversion results are for the previous (n − 1)

conversion.

Similar to reading during conversion, split-reading must only

occur up to tDATA. For the maximum throughput, the only time

restriction is that split-reading take place during the tACQ

(minimum) + tDATA − tQUIET time. The time between the falling

edge of SCK and CNV rising is an acquisition quiet time, tQUIET.

To determine how to split the read for a particular SCK frequency,

follow these examples to read data from conversion (n − 1).

For turbo mode (2 MSPS),

fSCK = 75 MHz; tDATA = 200 ns; tCNVH = 10 ns; tEN = 10 ns

Number_SCK_Edges = 75 MHz × (200 ns − 10 ns − 10 ns) = 13.5

Thirteen bits are read during conversion (n), and five bits are

read during acquisition (n).

For normal mode (1.5 MSPS),

fSCK = 50 MHz; tDATA = 300 ns; tCNVH = 10 ns; tEN = 10 ns

Number_SCK_Edges = 50 MHz × (300 ns − 10 ns − 10 ns) = 14

Fourteen bits are read during conversion (n), and four bits are

read during acquisition (n).

For slow throughputs, the time restriction is dictated by the

required throughput by the user, and the host is free to run at

any speed. Similar to the reading during acquisition, for slow

hosts, the data access must take place during the acquisition

phase with additional time into the conversion.

Note that data access spanning conversion requires the CNV to

be driven high to initiate a new conversion, and data access is

not allowed when CNV is high. Thus, the host must perform

two bursts of data access when using this method.

Reading During Acquisition, Any Speed Hosts (Turbo or

Normal Mode)

When reading during acquisition (n), conversion results are

for the previous (n − 1) conversion. Maximum throughput is

achievable in normal mode (1.5 MSPS); however, in turbo

mode, 2 MSPS throughput is not achievable.

For the maximum throughput, the only time restriction is that the

reading takes place during the tACQ (minimum) time. For slow

throughputs, the time restriction is dictated by throughput required

by the user, and the host is free to run at any speed. Thus for slow

hosts, data access must take place during the acquisition phase.

Data Sheet AD7986

Rev. D | Page 19 of 28

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when a single AD7986 is connected

to an SPI-compatible digital host. The connection diagram is

shown in Figure 25, and the corresponding timing is given in

Figure 26.

With SDI tied to VIO, a rising edge on CNV initiates a conversion,

selects the CS mode, and forces SDO to high impedance. Once

a conversion is initiated, it continues until completion irrespective

of the state of CNV.

This can be useful, for instance, to bring CNV low to select other

SPI devices, such as analog multiplexers; however, CNV must be

returned high before the minimum conversion time elapses and

then held high for the maximum possible conversion time to avoid

the generation of the busy signal indicator. When the conversion is

complete, the AD7986 enters the acquisition phase and powers

down. When CNV goes low, the MSB is output onto SDO. The

remaining data bits are clocked by subsequent SCK falling edges.

The data is valid on both SCK edges. Although the rising edge

can capture the data, a digital host using the SCK falling edge

allows a faster reading rate, provided that it has an acceptable hold

time. After the 18th SCK falling edge or when CNV goes high

(whichever occurs first), SDO returns to high impedance.

AD7986

SDI SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

VIO

07956-018

Figure 25. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)

ACQUISITION (n)

ACQUISITION

(n + 1)

ACQUISITION

(n - 1)

BEGIN DATA (n – 1)

CONVERSION (n)

END DATA (n – 1)

SCK

CNV

SDO

16 17

CONVERSION (n – 1)

END DATA (n – 2)

CONV

DATA

(I/O QUIET

TIME)

(I/O QUIET

TIME)

18 16 17 18

11716152 012

SDI = 1

CONV

(QUIET

TIME)

CYC

ACQ

CNVH

QUIET

SCK

DIS

DSDO

HSDO

DATA

CONV

07956-116

Figure 26. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)

AD7986 Data Sheet

Rev. D | Page 20 of 28

CS MODE, 3-WIRE WITH BUSY INDICATOR

This mode is usually used when a single AD7986 is connected

to an SPI-compatible digital host having an interrupt input.

It is only available in normal conversion mode (TURBO = low).

The connection diagram is shown in Figure 27, and the

corresponding timing is given in Figure 28.

With SDI tied to VIO, a rising edge on CNV initiates a conversion,

selects the CS mode, and forces SDO to high impedance. SDO

is maintained in high impedance until the completion of the

conversion irrespective of the state of CNV. Prior to the minimum

conversion time, CNV can select other SPI devices, such as analog

multiplexers, but CNV must be returned low before the minimum

conversion time elapses and then held low for the maximum

possible conversion time to guarantee the generation of the

busy signal indicator.

When the conversion is complete, SDO goes from high imped-

ance to low impedance. With a pull-up on the SDO line, this

transition can be used as an interrupt signal to initiate the data

reading controlled by the digital host. The AD7986 then enters

the acquisition phase and powers down. The data bits are then

clocked out, MSB first, by subsequent SCK falling edges. The

data is valid on both SCK edges. Although the rising edge can

capture the data, a digital host using the SCK falling edge allows

a faster reading rate, provided that it has an acceptable hold time.

After the optional 19th SCK falling edge, SDO returns to high

impedance.

If multiple AD7986 devices are selected at the same time, the

SDO output pin handles this contention without damage or

induced latch-up. Meanwhile, it is recommended to keep this

contention as short as possible to limit extra power dissipation.

AD7986

SDI SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

VIO

IRQ

VIO

47kΩ

TURBO

07956-020

Figure 27. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)

SDO D17 D16 D1 D0

tDIS

SCK 123 171819

tSCK

tSCKL

tSCKH

tHSDO

tDSDO

CNV

CONVERSIONACQUISITION

tCONV

tCYC

ACQUISITION

URBO = 0

SDI = 1

tCNVH

tACQ

tQUIET

(QUIET

TIME)

07956-021

Figure 28. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)

Data Sheet AD7986

Rev. D | Page 21 of 28

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when multiple AD7986 devices are

connected to an SPI-compatible digital host.

A connection diagram example using two AD7986 devices is

shown in Figure 29 and the corresponding timing is given in

Figure 30.

With SDI high, a rising edge on CNV initiates a conversion, selects

the CS mode, and forces SDO to high impedance. In this mode,

CNV must be held high during the conversion phase and the

subsequent data readback. (If SDI and CNV are low, SDO is

driven low.)

Prior to the minimum conversion time, SDI can select other SPI

devices, such as analog multiplexers, but SDI must be returned

high before the minimum conversion time elapses and then held

high for the maximum possible conversion time to avoid the

generation of the busy signal indicator. When the conversion is

complete, the AD7986 enters the acquisition phase and powers

down. Each ADC result can be read by bringing the SDI input

low, which consequently outputs the MSB onto SDO. The

remaining data bits are then clocked by subsequent SCK falling

edges. The data is valid on both SCK edges. Although the rising

edge can capture the data, a digital host using the SCK falling

edge allows a faster reading rate, provided that it has an acceptable

hold time. After the 18th SCK falling edge, SDO returns to high

impedance and another AD7986 can be read.

AD7986

SDI SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

CS1

CS2

AD7986

SDI SDO

CNV

SCK

07956-022

Figure 29. CS Mode, 4-Wire Without Busy Indicator Connection Diagram

SDO D17 D16 D15 D1 D0

DIS

SCK 123 343536

HSDO

DSDO

CONVERSIONACQUISITION ACQUISITION

SDI (CS1)

CNV

SSDICNV

HSDICNV

16 17

SCK

SCKL

SCKH

D0 D17 D16

19 2018

SDI (CS2)

07956-023

QUIET

CYC

CONV

ACQ

Figure 30. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing

AD7986 Data Sheet

Rev. D | Page 22 of 28

CS MODE, 4-WIRE WITH BUSY INDICATOR

This mode is usually used when a single AD7986 is connected

to an SPI-compatible digital host with an interrupt input and

when it is desired to keep CNV, which samples the analog input,

independent of the signal that selects the data reading. This

independence is particularly important in applications where

low jitter on CNV is desired. This mode is only available in

normal conversion mode (TURBO = low).

The connection diagram is shown in Figure 31, and the

corresponding timing is given in Figure 32.

With SDI high, a rising edge on CNV initiates a conversion,

selects the CS mode, and forces SDO to high impedance. In this

mode, CNV must be held high during the conversion phase and

the subsequent data readback. (If SDI and CNV are low, SDO is

driven low.)

Prior to the minimum conversion time, SDI can select other SPI

devices, such as analog multiplexers, but SDI must be returned

low before the minimum conversion time elapses and then held

low for the maximum possible conversion time to guarantee the

generation of the busy signal indicator. When the conversion is

complete, SDO goes from high impedance to low impedance.

With a pull-up on the SDO line, this transition can be used as

an interrupt signal to initiate the data readback controlled by

the digital host. The AD7986 then enters the acquisition phase

and powers down. The data bits are then clocked out, MSB first,

by subsequent SCK falling edges. The data is valid on both SCK

edges. Although the rising edge can capture the data, a digital host

using the SCK falling edge allows a faster reading rate, provided

that it has an acceptable hold time. After the optional 19th SCK

falling edge or SDI going high (whichever occurs first), SDO

returns to high impedance.

AD7986

SDI SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

IRQ

VIO

47kΩ

CS1

TURBO

07956-024

Figure 31. CS Mode, 4-Wire with Busy Indicator Connection Diagram

(I/O QUIET

TIME)

SDO D17 D16 D1 D0

DIS

QUIET

SCK 1 2 3 17 18 19

SCK

SCKL

SCKH

HSDO

DSDO

CONVERSIONACQUISITION

CONV

CYC

ACQ

ACQUISITION

SDI

CNV

SSDICNV

HSDICNV

URBO = 0

07956-025

Figure 32. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing

Data Sheet AD7986

Rev. D | Page 23 of 28

CHAIN MODE WITHOUT BUSY INDICATOR

This mode can daisy-chain multiple AD7986 devices on a

3-wire serial interface. It is only available in normal conversion

mode (TURBO = low). This feature is useful for reducing

component count and wiring connections, for example, in

isolated multiconverter applications or for systems with a

limited interfacing capacity. Data readback is analogous to

clocking a shift register.

A connection diagram example using two AD7986 devices is

shown in Figure 33 and the corresponding timing is given in

Figure 34.

When SDI and CNV are low, SDO is driven low. With SCK low,

a rising edge on CNV initiates a conversion, selects the chain

mode, and disables the busy indicator.

In this mode, CNV is held high during the conversion phase and

the subsequent data readback. When the conversion is complete,

the MSB is output onto SDO, and the AD7986 enters the

acquisition phase and powers down. The remaining data bits

stored in the internal shift register are clocked by subsequent

SCK falling edges. For each ADC, SDI feeds the input of the

internal shift register and is clocked by the SCK falling edge.

Each ADC in the chain outputs the data MSB first, and 18 × N

clocks are required to read back the N ADCs. The data is valid

on both SCK edges. Although the rising edge can capture the

data, a digital host using the SCK falling edge allows a faster

reading rate and consequently more AD7986 devices in the chain,

provided that the digital host has an acceptable hold time. The

maximum conversion rate may be reduced due to the total

readback time.

CONVERT

DATA I N

CLK

DIGITAL HOST

AD7986

SDI SDO

CNV

SCK

AD7986

SDI SDO

CNV

SCK TURBO TURBO

07956-026

Figure 33. Chain Mode Without Busy Indicator Connection Diagram

SDOA = SDIBDA17 DA16 DA15

SCK 1 2 3 34 35 36

CONVERSIONACQUISITION

CONV

ACQUISITION

CNV

DA1

16 17

DA0

19 2018

SDIA = 0

SDOBDB17 DB16 DB15 DA1DB1 DB0 DA17 DA16

HSDO

DSDO

QUIET

DA0

07956-027

CYC

SCK

SCKH

HSDISCK

SSDISCK

HSCKCNV

SCKL

ACQ

Figure 34. Chain Mode Without Busy Indicator Serial Interface Timing

AD7986 Data Sheet

Rev. D | Page 24 of 28

CHAIN MODE WITH BUSY INDICATOR

This mode can also daisy-chain multiple AD7986 devices on a

3-wire serial interface while providing a busy indicator. This

feature is useful for reducing component count and wiring

connections, for example, in isolated multiconverter applica-

tions or for systems with a limited interfacing capacity. Data

readback is analogous to clocking a shift register. A connection

diagram example using three AD7986 devices is shown in

Figure 35, and the corresponding timing is given in Figure 36.

When SDI and CNV are low, SDO is driven low. With SCK

high, a rising edge on CNV initiates a conversion, selects the

chain mode, and enables the busy indicator feature. In this

mode, CNV is held high during the conversion phase and the

subsequent data readback.

When all ADCs in the chain have completed their conversions,

the SDO pin of the ADC closest to the digital host (see the

AD7986 ADC labeled C in Figure 35) is driven high. This

transition on SDO can be used as a busy indicator to trigger the

data readback controlled by the digital host. The AD7986 then

enters the acquisition phase and powers down. The data bits

stored in the internal shift register are clocked out, MSB first, by

subsequent SCK falling edges. For each ADC, SDI feeds the

input of the internal shift register and is clocked by the SCK

falling edge. Each ADC in the chain outputs the data MSB first,

and 18 × N + 1 clocks are required to read back the N ADCs.

Although the rising edge can capture the data, a digital host using

the SCK falling edge allows a faster reading rate and consequently

more AD7986 devices in the chain, provided that the digital

host has an acceptable hold time.

CONVERT

DATA I N

CLK

DIGITAL HOST

AD7986

SDI SDO

CNV

SCK

AD7986

SDI SDO

CNV

SCK IRQ

AD7986

SDI SDO

CNV

SCK TURBOTURBO

TURBO

07956-028

Figure 35. Chain Mode with Busy Indicator Connection Diagram

SDOA = SDIBDA17 DA16 DA15

SCK 1 2 3 39 53 54

tEN

CONVERSION

ACQUISITION

tCONV

tCYC

tACQ

ACQUISITION

CNV = SDIA

DA1

417

tSCK

tSCKH

tSCKL

DA0

19 3818

SDOB = SDICDB17 DB16 DB15 DA1DB1 DB0 DA17 DA16

tSSDISCK tHSDISCK

tHSDO

tDSDO

SDOCDC17 DC16 DC15 DA1 DA0DC1 DC0 DA16

21 35 3620 37

DB1 DB0 DA17DB17 DB16

tDSDOSDI

tHSCKCNV

DA0

tDSDOSDI

TURBO = 0

tQUIET

07956-029

Figure 36. Chain Mode with Busy Indicator Serial Interface Timing

Data Sheet AD7986

Rev. D | Page 25 of 28

APPLICATION HINTS

LAYOUT

Design the printed circuit board (PCB) that houses the AD7986 so

the analog and digital sections are separated and confined to

certain areas of the board. The pinout of the AD7986, with the

analog signals on the left side and the digital signals on the right

side, eases this task.

Avoid running digital lines under the device because these couple

noise onto the die, unless a ground plane under the AD7986 is

used as a shield. Fast switching signals, such as CNV or clocks,

must not run near analog signal paths. Crossover of digital and

analog signals must be avoided.

At least one ground plane must be used. It can be common or

split between the digital and analog sections. In the latter case,

the planes must be joined underneath the AD7986 devices.

The AD7986 voltage reference input (REF) has a dynamic input

impedance and must be decoupled with minimal parasitic induc-

tances. This is done by placing the reference decoupling ceramic

capacitor close to, ideally right against, the REF and REFGND pins

and connecting them with wide, low impedance traces.

Finally, the power supplies, VDD and VIO of the AD7986, must

be decoupled with ceramic capacitors, typically 100 nF, placed

close to the AD7986 and connected using short, wide traces to

provide low impedance paths and to reduce the effect of glitches

on the power supply lines.

EVALUATING THE PERFORMANCE OF THE AD7986

The evaluation board package for the AD7986, EVAL-

AD7986FMCZ, includes a fully assembled and tested evaluation

board and software for controlling the board from a PC, via the

controller board, EVAL-SDP-CH1Z.

AD7986 Data Sheet

Rev. D | Page 26 of 28

PADDLE

BVDD AVDD

DVDD

VIO

GND

GNDGND

REF REF REF

07956-030

Figure 37. Example Layout of the AD7986 (Top Layer)

EXTERNAL

REFERENCE

( ADR4 3 5 OR ADR4 4 5)

GND

VIO

CREF

BVDD AVDD

DVDD

VIO

GND

GNDGND

REF REF REF

CBVDD CAVDD

CVIO

CDVDD

07956-031

Figure 38. Example Layout of the AD7986 (Bottom Layer)

Data Sheet AD7986

Rev. D | Page 27 of 28

OUTLINE DIMENSIONS

0.50

BSC

0.50

0.40

0.30

0.25

0.20

COMPLIANT

JEDEC STANDARDS MO-220-WGGD.

061609-B

BOTTOMVIEWTOP VIEW

EXPOSED

PAD

PIN 1

INDICATOR

4.10

4.00 SQ

3.90

SEATING

PLANE

0.80

0.75

0.70 0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

COPLANARITY

0.08

PIN 1

INDICATOR

2.65

2.50 SQ

2.35

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

1516

Figure 39. 20-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.75 mm Package Height

(CP-20-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model1, 2, 3

Temperature

Range Package Description

Package

Option

Ordering

Quantity

AD7986BCPZ −40°C to +85°C 20-Lead Lead Frame Chip Scale Package LFCSP, Tray CP-20-10 490

AD7986BCPZ-RL7

−40°C to +85°C

20-Lead Lead Frame Chip Scale Package LFCSP, 7” Tape and Reel

CP-20-10

1,500

EVAL-AD7986FMCZ Evaluation Board

EVAL-SDP-CH1Z Controller Board

1 Z = RoHS Compliant Part.

2 The EVAL-AD7986FMCZ can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CH1Z for evaluation and/or demonstration purposes.

3 The EVAL-SDP-CH1Z allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the FMC designator.

AD7986 Data Sheet

Rev. D | Page 28 of 28

NOTES

registered trademarks are the property of their respective owners.

D07956-0-3/16(D)

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Analog Devices Inc.:

EVAL-AD7986EBZ