TOSHIBA TLCS-90 Series TMP90PH48 CMOS 8-Bit Microcontrollers TMP90PH48F 1. Outline and Characteristics The TMP90PM48 is a system evalution LSI having a built in One-Time PROM for TMP90C848. A programming and verification for the internal PROM is achieved by using a general EPROM programmer with an adapter socket. The function of this device is exactly same as the TMP90C848 by programming to the internal PROM. The differences between TMP90PH48 and TMP90C848 are the memory size (ROM). The following are the memory map of TMP90PH48 and TMP90C848. Parts No. ROM RAM Package Adapter Socket No. TMP90PH48N OTP 16384 x 8bit 512 x 8bit 80-FP BM1153 The information contained here is subject to change without notice. The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA. TOSHIBA CORPORATION 1/14 TMP90PH48 Figure 1. TMP90PH48F Block Diagram 2/14 TOSHIBA CORPORATION TMP90PH48 2. Pin Assignment and Functions The assignment of input/output pins, their names and functions are described below. 2.1 Pin Assignment Figure 2.1 shows pin assignment of the TMP90PH48. Figure 2.1 Pin Assignment (80-FP) TOSHIBA CORPORATION 3/14 TMP90PH48 2.2 Pin Names and Functions The TMP90PH48 has MCU mode and PROM mode. (1) MCU mode (The TMP90C848 and TMP90PH48 are pin compatible) Table 2.2 (1/2) Pin Name No. of pins I/O or tristates P00 ~ P07 8 I/O Port 0: 8-bit I/O port. Each bit can be set for input or output. P10 ~ P17 8 I/O Port 1: An 8-bit I/O port.Each bit can be set for input or output Pull-up resistance included. P20 ~ P27 8 I/O Port 2: 8-bit output port. P30 1 Output Port 30: 1-bit output port. P31 1 P32 /TxD P32 /RxD 1 P40 ~ P47 8 P50 ~ P57 /AN0 ~ AN7 8 P60 ~ 67 /AN8 ~ AN15 8 P70 ~ P73 4 P80 /T01 1 P81 /T03 P82 /INT0 P83 /INT1 /TI4 4/14 1 1 1 Output Port 31: 1-bit output port. Output Port 32: 1-bit output port. Output Used to transmit serial data. Input Port 33: 1-bit output port. Input Used to receive serial data. I/O Input Port 4: 8-bit I/O port. Each bit can be set for input or output (P40 - P43 O.D. 4mA sink, P44 - 47 10mA source). Port 5: 8-bit input port. Input Analog input: 8-bit analog input to the A/D converter. Input Port 6: 8-bit input port. Input Analog input: 8-bit analog input the A/D converter I/O Port 7: 4-bit I/O port. Each bit can be set for input or output. Programmable pull-up resistance included. I/O Port 80: 1-bit I/O port. Output I/O Output I/O Input I/O 1 Function Timer output 1: Used for timer 0 or timer 1 output. Port 81: 1-bit I/O port. Timer output 3: Used for timer 2 or timer 3 output. Port 82: 1-bit I/O port. Interrupt request pin 0: Level/rising edge programmable interrupt request pin. Port 83: 1-bit I/O port. Input Interrupt request pin 1: Rising/falling edge programmable interrupt request pin. Input Timer input 4: Count input/capture trigger signal for timer 4. TOSHIBA CORPORATION TMP90PH48 Table 2.2 (2/2) Pin name No. of pins I/O or tristate P84 /INT2 /TI5 1 Input Interrupt request pin 2: Rising edge programmable interrupt request pin. Input Timer input 5: Count input/capture trigger signal for timer 5. I/O P85 /T04 1 ALE I/O Function Port 84: 1-bit I/O port. Port 85: 1-bit I/O port. Output Timer output 4: used as the timer 4 output. 1 Output Address latch enable signal: The falling edge of this signal used as the timing to latch AD0 ~ AD7 addresses when accessing external memory. CLK 1 Output Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. Pulled up during resetting. EA 1 Input External access: Connected to the VCC pin when using the TMP90C848F with built-in ROM. RESET 1 Input Reset: Initializes the TMP90C848F. X1/X2 2 I/O High-speed crystal oscillator connection pin. Low-speed crystal oscillator connection pin. X1'/X2' 2 I/O TEST1/TEST2 2 I/O Testing pins Connects directly TEST1 and TEST2 at a normal state operation. AVCC 1 - Comparator power supply for the A/D converter. VREF 1 - A/D converter reference voltage input. AVSS 1 - Analog GND pin (0V) VCC 2 - Power supply (+5V10%) VSS 3 - GND pin TOSHIBA CORPORATION 5/14 TMP90PH48 (2) 6/14 PROM Mode Pin Function Name No. of pins I/O A7 ~ A0 8 Input A15 ~ A8 8 Input D7 ~ D0 8 I/0 OE 1 Input Output Enable Input P30 CE 1 Input Chip Enable Signal Input P31 VPP 1 Power Supply 12.5V/5V(Programming Power Supply) EA VCC 1 Power Supply 5V VCC VSS 1 Power Supply 0V VSS Pin Names No. of pins I/O P16, P17 2 Output Address inputs P15 ~ P10 Be fixed to "L" level (Note). 2 Output, Input Be fixed to "H" level. 8 I/O Be fixed to "H" level. P50 ~ P57 P60 ~ P67 8 8 Input Be fixed to "L" level. P70 ~ P73 4 I/O Be fixed to "H" level. P80 ~ P85 6 I/O RESET 1 Input CLK 1 Output P07 ~ P00 Pin Setting P32, P33 3 P27 ~ P20 Data Input/Output P40 ~ P47 VREF/ AVss/AVcc Pin Name (MCU mode) Function Be fixed to "L" level. Be fixed to "L" level. X1 1 Input X2 1 Output X1' 1 Input X2' 1 Output Refer to Figure 3.2 Resonator connection pin TOSHIBA CORPORATION TMP90PH48 3. Operation 3.1 MCU Mode The TMP90PH48 is the OTP version of the TMP90CC848 that is replaced an internal ROM from Mask ROM to EPROM. The function of TMP90PH48 is exactly same as that of TMP90CC848 except the internal ROM size. Refer to the TMP90C848 except the functions which are not described this section. The following is an explanation of the hardware configuration and operation in relation to the TMP90CH48. The TMP90PH48 has an MCU mode and a PROM mode. (1) Mode Setting and Function The MCU mode is set by opening the CLK pin (Output status). In the MCU mode, the operation is same as that of TMP90C848. (2) Memory Map Figure 3.1 shows the memory map TMP90PH48, and the accessing area by the respective addressing mode. Figure 3.1. TMP90PH48F Memory Map TOSHIBA CORPORATION 7/14 TMP90PH48 3.2 PROM Mode (1) PROM is achieved by using a general EPROM programmer with the adapter socket. The device slection (ROM type) should be "27256" with following conditions. Mode Setting and Function PROM mode is set by setting the RESET and CLK pins to the "L" level. The programming and verification for the internal Size = 256Kbit (32Kx 8bit) TPW = 1ms, VPP = 12.5V) Figure 3.2 shows the setting of pins in PROM mode Figure 3.2. PROM Mode Pin Setting (2) Programming Flow Chart The programming mode is set by applying 12.5V (programming voltage) to the VPP pin when the following pins are set as follows, (Vcc : 6.0V) *These conditions can be : "L" level) obtained by using adaptor (RESET (CLK : "L" level) socket. After the address and data have been fixed, a data on the Data Bus is programmed when the CE pin is set to "Low" (1ms plus is required). General programming procedure of an EPROM programmer is as follows, 8/14 * Write a data to a specified address for 1ms. * Verify the data. If the read-out data does not match the expected data, another writing is performed until the correct data is written (Max. 25 times). After the correct data is written, an additional writing is performed by using three times longer programming pulse width (1ms x programming times), or using three times more programming pulse number. Then, verify the data and increment the address. The verification for all data is done under the condition of Vpp = Vcc = 5V after all data were written. Figure 3.3 shows the programming flow chart. TOSHIBA CORPORATION TMP90PH48 Figure 3.3. Flow Chart TOSHIBA CORPORATION 9/14 TMP90PH48 (3) The Security Bit How to program the Security Bit. The TMP90PH48 has the Security Bit in PROM cell. If the Security Bit is programmed to "0", the content of the PROM is disable to read in PROM mode. 1) Connect A15 pins to Vcc. [Otherwise connect them GND to program PROM, (address 0000H ~ 3FFFH) 2) Set programming address to 0000H. 3) To program the Security Bit, Do to "0" 4) Set D2 ~ D7 to "1", respectively. Table 3.1 Data to Program Bit to PROGRAM The Security Bit PROM (0000H ~ 1FFFH) 10/14 D0 ~ D7 A0 ~ A12 A15 FEH all "0" all "1" - - all "0" TOSHIBA CORPORATION TMP90PH48 4. Electrical Characteristics TMP90PH48 4.1 Absolute Maximum Ratings Symbol Item Rating Unit -0.5 ~ + 7 V VCC Power supply voltage VIN Input voltage -0.5 ~ VCC + 0.5 V PD Power dissipation (Ta = 70C) 500 mW Soldering temperature (10s) 260 C TSOLDER TSTG Storage temperature -65 ~ 150 C TOPR Operating temperature -20 ~ 70 C 4.2 DC Characteristics VCC = 5V10% TA = -20 ~ 70C High-speed clock: 16 ~ 20MHz, Low-speed clock: 0.5 ~ 1MHz Typical values are for TA = 25C and Vcc = 5V Symbol Parameter Min Max Unit Condition VIL Input Low Voltage (P0) -0.3 0.8 V - VIL1 P1, P3, P4, P5, P6, P7, P8 -0.3 0.3VCC V - VIL2 RESET, P82 (INTO) -0.3 0.25VCC V - VIL3 EA -0.3 0.3 V - VIL4 X1, X1' -0.3 0.2VCC V - VIH Input High Voltage (P0) 2.2 VCC + 0.3 V - VIH1 P1, P3, P4, P5, P6, P7, P8 0.7VCC VCC + 0.3 V - VIH2 RESET, P82 (INTO) 0.75VCC VCC + 0.3 V - VIH3 EA VCC-0.3 VCC + 0.3 V - VIH4 X1, X1' 0.8VCC VCC + 0.3 V - VOL VOL1 Output Low Voltage (OPEN DRAIN Sink) - - 0.45 0.45 V 0.45 IOL = 1.6mA IOL = 4mA VOH VOH1 VOH2 VOH3 Output High Voltage 2.4 0.75VCC 0.9VCC 2.4 - - - - V V V 0.45 IOH = -400A IOH = -100A IOH = -20A IOH = 10A A 0.0 Vin VCC P44 ~ 47 (OPEN DRAIN Source) ILI Input Leakage Current 0.02 (Typ) 5 ILO Output Leakage Current 0.05 (Typ) 10 A 0.2 Vin VCC - 0.2 Operating Current (RUN) Idle 1 15 (Typ) 1.5 (Typ) 30 5 mA mA High-speed clock: 20MHz Low-speed clock: 1MHz 0.2 (Typ) 40 10 A A 0.2VinVCC-0.2 7 (Typ) 15 mA fosc = 10MHz AVcc = 5V 10% ICC (Vcc - Vss) Alcc AVcc - AVss) STOP (TA = -20 ~ 7C) STOP (TA = 0 ~ 50C) Operating Current VSTOP Power Down Voltage (@STOP) RAM BACK UP 2.0 6.0 V RRST RESET, P1, P7, Pull Up Register 30 130 K - 10 pF 0.4 1.0 (Typ) V CIO Pin Capacitance VTH Schmitt width (RESET, P82) TOSHIBA CORPORATION VIL2 = 0.2VCC, VIH2 = 0.8VCC - testfreq = 1MHz - 11/14 TMP90PH48 4.3 A/D Converter Characteristics VCC = 5V10% TA = -20 ~ 70C High-speed clock: 16 ~ 20MHz, Low-speed clock: 0.5 ~ 1MHz Symbol VREF Parameter Analog reference voltage Min Typ Max Unit V - 3.5 Vcc Vcc VREF - Vss 3.5 Vcc Vcc Analog power supply voltage - Vss Vss Vss Analog input voltage range - Vss - Vcc Supply current for analog reference voltage - - 0.8 2 VREF Analog reference voltage range AVss VAIN IREFAD Condition This A/D Converter is guaranteed only monotonicity because it has an offset value (when VAIN = 0V), but the 8-bit resolution is gotten except an offset value. mA The A/D converted data is recommended to be processed relatively. Figure 4.3 (1). A/D Converter Typical Conversion Characterics (VREF = 5V, Vss = 0V) 4.4 Zero-Cross Characteristics VCC = 5V10% TA = -20 ~ 70C High-speed clock: 16 ~ 20MHz, Low-speed clock: 0.5 ~ 1MHz Symbol Item Condition Min Max Unit 1 1.8 VAC P- P VZX Zero-cross detection input For AC, C = 0.1F AZX Zero-cross accuracy 50/60Hz sine wave - 135 mV FZX Zero-cross detection input frequency - 0.04 1 kHz 4.5 Timer/Counter Input Clock (TI0, TI2, and TI4) VCC = 5V10%TA = -20 ~ 70C High-speed clock: 16 ~ 20MHz, Low-speed clock: 0.5 ~ 1MHz Variable Symbol 12/14 10MHz Clock Parameter Unit Min Max Min Max tVCK Clock cycle 8x + 100 - 900 - ns tVCKL Low clock pulse width 4x + 40 - 440 - ns tVCKH High clock pulse width 4x + 40 - 440 - ns TOSHIBA CORPORATION TMP90PH48 4.6 Interrupt Operation VCC = 5V10%TA = -20 ~ 70C High-speed clock: 16 ~ 20MHz, Low-speed clock: 0.5 ~ 1MHz Variable Symbol 10MHz Clock Item tINTAL NMI, INT0 Low level pulse width tINTAH NMI, INT0 High level pulse width tINTBL INT1, INT2 Low level pulse width tINTBH INT1, INT2 High level pulse width Unit Min Max Min Max 4x - 400 - ns 4x - 400 - ns 8x + 100 - 900 - ns 8x + 100 - 900 - ns 4.7 Read Operation (PROM Mode) DC Characteristic, AC Characteristic TA = -40 ~ 85C Vcc = 5V10% Symbol Parameter VPP VIH1 VIL1 VPP read voltage Input high voltage (A0 ~ A15, CE, OE) Input low voltage (A ~ A15, CE, OE) tACC Address to output delay Condition Min Max Unit - - - 4.5 0.7 x VCC -0.3 5.5 Vcc + 0.3 0.3 x VCC V V V CL = 50PF - 2.25TCYC + ns TCYC = 400ns (10MHz Clock) = 200ns 4.8 Programming Operation (PROM Mode) DC Characteristic, AC Characteristic TA = 255C Vcc = 6V0.25V Symbol Parameter VPP VIH VIL VIH1 VIL1 ICC IPP Programming voltage Input high voltage (D0 ~ D7) Input low voltage (D0 ~ D7) Input high voltage (A0 ~ A15, CE, OE) Input low voltage (A0 ~ A15, CE, OE) VCC supply current VPP supply current tPW CE Program pulse width TOSHIBA CORPORATION Condition Min Typ Max Unit tOSC = 10MHz VPP = 13.00V 12.25 0.2VCC + 1.1 -0.3 0.7VCC -0.3 - 12.50 12.75 VCC + 0.3 0.2VCC - 0.1 VCC + 0.3 0.3VCC 50 50 V V V V V mA mA CL = 50PF 0.95 1.00 1.05 ms 13/14 TMP90PH48 4.9 Read Operation Timing Chart (PROM Mode) 4.10 Programming Operation Timing Chart (PROM Mode) 14/14 TOSHIBA CORPORATION