High Performance 64Kx16 CMOS SRAM AS7C1026 AS7C31026 (R) 64Kx16 CMOS SRAM Preliminary information Features * Organization: 65,536 words x 16 bits * High speed - 12/15/20/25 ns address access time - 6/8/10/12 ns output enable access time * Low power consumption - Active: 1100 mW max (25 ns cycle, 5V) - Standby: 28 mW max, CMOS I/O - Very low DC component in active power * 2.0V data retention * Equal access and cycle times * Easy memory expansion with CE, OE inputs * TTL-compatible, three-state I/O * 44-pin JEDEC standard package - 400 mil SOJ - 400 mil TSOP II * Center power and ground pins for low noise * ESD protection 2000 volts * Latch-up current 200 mA * Industrial temperature range available (-40 to +85 C) * 3.3V version available (AS7C31026) Logic block diagram Pin arrangement A0 A2 A3 A4 A5 A6 SOJ, TSOP Vcc Row decoder A1 64K x 16 Array GND A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC A7 I/O buffer A15 A14 A13 A12 A11 A9 Column decoder A8 WE Control circuit A10 I/O0-I/O7 I/O8-I/O15 UB OE LB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC CE Selection guide Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current AS7C1026 AS7C31026 7C1026-12 - 12 6 230 - 5 7C1026-15 7C31026-15 15 8 210 180 5 7C1026-20 7C31026-20 20 10 190 160 5 7C1026-25 7C31026-25 25 12 170 140 5 Unit ns ns mA mA mA Shaded areas contain advance information. ALLIANCE SEMICONDUCTOR 1 AS7C1026 AS7C31026 Preliminary information (R) Functional description The AS7C1026 and AS7C31026 are high performance CMOS 1,048,576-bit Static Random Access Memories (SRAM) organized as 65,536 words x 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20/25 ns with output enable access times (tOE) of 6/8/10/12 ns are ideal for high performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is High the device enters standby mode. The AS7C1026 is guaranteed not to exceed 28 mW power consumption in CMOS standby mode. This device also offers 2.0V data retention. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0-I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) High. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0-I/O7, and UB controls the higher bits, I/O8-I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1026) or 3.3V supply (AS7C31026). Both devices are packaged in common industry standard packages. Absolute maximum ratings Parameter Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Temperature under bias DC output current Symbol Vt PD Tstg Tbias Iout Min -1 - -55 -10 - Max +7.0 1.0 +150 +85 50 Unit V W oC o C mA NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE H L L L L L L L L WE X H H H L L L H X OE X L L L X X X H X Key: X = don't care, L = Low, H = High 2 LB X L H L L L H X H UB X H L L L H L X H I/O0-I/O7 High Z DOUT High Z DOUT DIN DIN High Z I/O8-I/O15 High Z High Z DOUT DOUT DIN High Z DIN Mode Standby Read I/O0-I/O7 Read I/O8-I/O15 Read I/O0-I/O15 Write I/O0-I/O15 Write I/O0-I/O7 Write I/O8-I/O15 High Z High Z Output disable AS7C1026 AS7C31026 Preliminary information (R) Recommended operating conditions Parameter Supply voltage AS7C1026 AS7C31026 Input voltage AS7C1026 AS7C31026 Ambient operating temperature Commercial Industrial Symbol VCC VCC GND VIH VIH VIL TA TA Min 4.5 3.0 0.0 2.2 2.0 -0.5 0 -40 Typ 5.0 3.3 0.0 - - - - - Max 5.5 3.6 0.0 VCC + 0.5 VCC + 0.5 0.8 70 85 Unit V V V V V V C C VIL min = -3.0V for pulse width less than tRC/2. DC operating characteristics Parameter Input leakage current Output leakage current Operating power supply current Standby power supply current Output voltage Symbol -12 -15 -20 -25 Min Max Min Max Min Max Min Max Test conditions Unit | ILI | 0V Vin VCC - 5 - 5 - 5 - 5 A | ILO | Outputs disabled 0V Vout VCC - 5 - 5 - 5 - 5 A ICC CE VIL, VCC = Max, outputs AS7C1026 open, f = fMax = 1/tRC AS7C31026 - - 230 - - - 210 180 - - 190 160 - - 170 mA 140 mA ISB CE VIL, VCC = Max, outputs open, f = fMax = 1/tRC - 70 - 60 - 50 - 40 mA - 5 - 5 - 5 - 5 mA ISB1 VOL VOH CE VCC-0.2V, VCC = Max, Vin GND + 0.2V or Vin VCC - 0.2V, f = 0 IOL = 8 mA, VCC = Min IOH = -4 mA, VCC = Min - 0.4 - 0.4 - 0.4 - 0.4 2.4 - 2.4 - 2.4 - 2.4 - V V Shaded areas contain advance information Capacitance Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE, WE, OE, LB, UB I/O Test conditions Vin = 0V Vin = Vout = 0V Max Unit 5 pF 7 pF 3 AS7C1026 AS7C31026 Preliminary information (R) Read cycle 3,9 -12 Parameter Read cycle time Address access time Symbol tRC tAA Chip enable (CE) access time -15 -20 -25 Min 12 - Max - 12 Min 15 - Max - 15 Min 20 - Max - 20 Min 25 - Max - 25 Unit ns ns Notes tACE - 12 - 15 - 20 - 25 ns 3 Output enable (OE) access time Output hold from address change tOE - 6 - 8 - 10 - 12 ns tOH 4 - 4 - 4 - 4 - ns 5 CE Low to output in low Z tCLZ 0 - 0 - 0 - 0 - ns 4, 5 CE High to output in high Z tCHZ - 6 - 6 - 8 - 8 ns 4, 5 OE Low to output in low Z Byte select access time Byte select Low to Low-Z Byte select High to HI-Z tOLZ 0 - 0 - 0 - 0 - ns 4, 5 tBA tBLZ tBHZ - 0 - 6 - 6 - 0 - 8 - 6 - 0 - 10 - 8 - 0 - 12 - 8 ns ns ns 4,5 4,5 OE High to output in high Z Power up time Power down time tOHZ - 6 - 6 - 8 - 8 ns 4, 5 tPU tPD 0 - - 12 0 - - 15 0 - - 20 0 - - 25 ns ns 4, 5 4, 5 3 Shaded areas contain advance information. Key to switching waveforms AAAAAAA AAAA AAAAAAA AAA Rising input AAAAAAA AAAA AAAAAAA AAA AAAAAAA AAAA AAAAAAA AAA Falling input Undefined output/don't care Read waveform 1 3,6,7,9 tRC Address Data out tAA tOH Previous data valid tOH AAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA Data valid Read waveform 2 3,6,8,9 tRC Address OE AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA tAA tOE tOLZ CE AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A tOHZ tHZ tACE tLZ LB, UB AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA tBLZ Data out 4 tOH AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA tBA AAAA AAAA AAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA tBHZ Data valid AAAA AAAA AAAA AAAAAAAA AAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAA AS7C1026 AS7C31026 Preliminary information (R) Write cycle 11 Parameter Write cycle time Chip enable (CE) to write end Address setup to write end Address setup time Write pulse width Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Byte select Low to end of write Symbol tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW tBW -12 Min Max 12 - 10 - 9 - 0 - 9 - 0 - 6 - 0 - - 6 1 - 9 - -15 Min Max 15 - 12 - 10 - 0 - 10 - 0 - 8 - 0 - - 6 1 - 9 - -20 Min Max 20 - 13 - 12 - 0 - 12 - 0 - 10 - 0 - - 8 2 - 12 - -25 Min Max 25 - 15 - 14 - 0 - 14 - 0 - 10 - 0 - - 8 2 - 14 - Unit ns ns ns ns ns ns ns ns ns ns ns Notes 5 4, 5 4, 5 Shaded areas contain advance information. Write waveform 1 10,11 Address CE LB, UB tWC AAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A tCW tBW AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A tAS WE AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA tWR AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA tAW AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAAAA AAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA tWP tDW Data in tDH Data valid tWZ Data out tOW Data undefined HI-Z AAAA AAAA AAAA A AAAA AAAA AAAA A AAAA AAAA AAAA A AAAA AAAA AAAA A AAAA AAAA AAAA AAAAAAAAAAAAA A Write waveform 210,11 tWC Address tAS CE LB, UB WE tAW tBW AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA tWP AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA tDW AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA tDH Data valid Data in tCLZ Data out tWR tCW HI-Z tWZ Data undefined tOW HI-Z AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAA AAAA 5 AS7C1026 AS7C31026 Preliminary information (R) Data retention characteristics 13 Parameter VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time Input leakage current Symbol VDR ICCDR tCDR tR | ILI | Test conditions VCC = 2.0V CE VCC-0.2V Vin VCC-0.2V or Vin 0.2V Min 2.0 - 0 tRC - Max - 500 - - 1 Unit V A ns ns A Data retention waveform Data retention mode VCC VDR 2.0V 4.5V 4.5V tCDR tR AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA CE AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA VIH AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA VDR AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AC test conditions - Output load: see Figure B, except as noted. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. Thevenin Equivalent: 168 Dout +1.728V +5V +5V 480 +3.0V GND Dout 90% 10% 90% 2ns 10% Figure A: Input pulse 255 480 Dout 30 pF* GND Figure B: Output load 255 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled and not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, C. These parameters are specified with CL = 5pF as in Figure C. Transition is measured 500mV from steady-state voltage. This parameter is guaranteed but not tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be High during address transitions. All write cycle timings are referenced from the last valid address to the first transitioning address. This data applicable to AS7C1026 only. The AS7C31026 functions similarly. 2V data retention applies to commercial temperature range operation only. 6 *including scope and jig capacitance GND Figure C: Output load for tCLZ, tCHZ, tOLZ, tOHZ, tOW Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 5 pF* AS7C1026 AS7C31026 Preliminary information (R) Typical DC and AC characteristics 12 1.4 0.6 0.4 ISB 0.2 0.0 4.0 1.5 4.5 5.0 5.5 Supply voltage (V) Normalized access time tAA vs. supply voltage VCC Output source current (mA) 4.5 5.0 5.5 Supply voltage (V) Normalized access time Output source current IOH vs. output voltage VOH 120 VCC = 5.0V Ta = 25C 80 60 40 20 0 0.0 1.25 2.5 3.75 Output voltage (V) 5.0 0.2 -10 35 80 125 Ambient temperature (C) Normalized supply current ICC vs. cycle frequency 1/tRC, 1/tWC 1.2 VCC = 5.0V 0.9 VCC = 5.0V Ta = 25C 1.0 0.8 0.6 0.4 0.2 0.0 -10 35 80 125 Ambient temperature (C) 0 25 50 75 Cycle frequency (MHz) 100 Typical access time change tAA vs. output capacitive loading Output sink current IOL vs. output voltage VOL 35 120 30 VCC = 5.0V Ta = 25C 80 60 40 20 0 0.0 1 1.4 1.0 100 5 -55 Normalized access time tAA vs. ambient temperature Ta 1.1 140 VCC = 5.0V 25 -10 35 80 125 Ambient temperature (C) 1.2 0.8 -55 6.0 Output sink current (mA) Normalized access time 0.9 1.3 625 0.04 1.4 Ta = 25C 1.0 100 ISB 0.4 1.5 1.1 140 0.6 0.0 -55 6.0 1.2 0.8 4.0 0.8 0.2 1.4 1.3 Normalized ISB1 (log scale) 0.8 ICC 1.0 Normalized supply current ISB1 vs. ambient temperature Ta Normalized ICC 1.0 1.2 ICC Normalized ICC, ISB Normalized ICC, ISB 1.2 Normalized supply current ICC, ISB vs. ambient temperature Ta Change in tAA (ns) 1.4 Normalized supply current ICC, ISB vs. supply voltage VCC VCC = 4.5V 25 20 15 10 5 0 1.25 2.5 3.75 Output voltage (V) 5.0 0 250 500 750 Capacitance (pF) 1000 7 AS7C1026 AS7C31026 Preliminary information (R) AS7C1026 ordering codes Package \ Access time Plastic SOJ, 400 mil TSOP II, 18.4x10.2 mm 5V commercial 5V industrial 3.3V commercial 5V commercial 3.3V commercial 12 ns AS7C1026-12JC - - - - 15 ns AS7C1026-15JC AS7C1026-15JI AS7C31026-15JC AS7C1026-15TC AS7C31026-15TC 20 ns AS7C1026-20JC AS7C1026-20JI AS7C31026-20JC AS7C1026-20TC AS7C31026-20TC 25 ns AS7C1026-25JC AS7C1026-25JI AS7C31026-25JC AS7C1026-25TC AS7C31026-25TC Shaded areas contain advance information. AS7C1026 part numbering system AS7C X SRAM prefix Blank 3 8 1026 = 5V CMOS = 3.3V CMOS -XX X C Temperature range, Device Access Package: J = SOJ 400 mil C = Commercial: 0C to 70C number time T = TSOP type 2, 18.4x10.2 mm I = Industrial: -40C to 85C AS7C1026 AS7C31026 (R) Representatives and sales offices DOMESTIC REPS ILLINOIS NEBRASKA RHODE ISLAND ALABAMA El-Mech 3511 N. Cicero Avenue Chicago, IL 60641 (312) 794-9100 CenTech 3751 Pennridge Dr., Suite #107 Bridgeton, MO 63044 (314) 291-4230 CenTech 10312 East 63rd Terrace Raytown, MO 64133 (816) 358-8100 Kitchen & Kutchin Associates 87 Cambridge Street Burlington, MA 01803 (617) 229-2660 NEVADA SOUTH CAROLINA Brooks Technical Group 883 N. Shoreline Blvd. Mountain View, CA 94043 (415) 960-3880 Concord Component Reps 10608 Dunhill Terrace Raleigh, NC 27615 (919) 846-3441 NEW HAMPSHIRE SOUTH DAKOTA Kitchen & Kutchin Associates 87 Cambridge Street Burlington, MA 01803 (617) 229-2660 D.A. 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