DAC1005D650HW-C1 - Integrated Device Technology

1. General description

The DAC1005D650 is a high-speed 10-bit dual-channel Digital-to-Analog Converter

(DAC) with selectable 2, 4 or 8 interpolating filters optimized for multi-carrier wireless

transmitters.

Thanks to its digital on-chip modulation, the DAC1005D650 allows the complex I and Q

inputs to be converted up from BaseBand (BB) to IF. The mixing frequency is adjusted

using a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator

(NCO). The phase is controlled by a 16-bit register.

Two modes of operation are available: separate data ports or a single interleaved

high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into

its original I and Q data and then latched.

The DAC1005D650 also includes a 2, 4 and 8 clock multiplier which provides the

appropriate internal clocks and an internal regulator to adjust the output full-scale current.

2. Features and benefits

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

Rev. 04 — 2 July 2012 Product data sheet

Dual 10-bit resolution IMD3: 79 dBc; fs = 640 Msps; fo=96MHz

650 Msps maximum update rate SFDR: 75 dBc; fdata =80MHz;

fs= 640 Msps; fo= 19 MHz; PLL on

Selectable 2, 4 or 8 interpolation

filters

Typical 0.95 W power dissipation at 4

interpolation

Input data rate up to 160 Msps Power-down and Sleep modes

Very low noise cap-free integrated PLL Differential scalable output current from

1.6 mA to 20 mA

32-bit programmable NCO frequency On-chip 1.29 V reference

Dual-port or Interleaved data modes External analog offset control

(10-bit auxiliary DACs)

1.8 V and 3.3 V power supplies Internal digital offset control

LVDS compatible clock Inverse (sin x) / x function

Two’s complement or binary offset

data format

Fully compatible SPI port

3.3 V CMOS input buffers Industrial temperature range from

40 C to +85 C

Product data sheet Rev. 04 — 2 July 2012 2 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

3. Applications

Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA

Communication: LMDS/MMDS, point-to-point

Direct Digital Synthesis (DDS)

Broadband wireless systems

Digital radio links

Instrumentation

Automated Test Equipment (ATE)

4. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

DAC1005D650HW-C1 HTQFP100 plastic thermal enhanced thin quad flat package; 100 leads;

body 14  14  1 mm; exposed die pad

SOT638-1

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 04 — 2 July 2012 3 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

5. Block diagram

Fig 1. Block diagram

001aak158

DAC1005D650

FIR1

2 ×

FIR1

FIR2

2 ×

FIR2

FIR3

2 ×

FIR3

NCO

cos sin

CLOCK GENERATOR/

PLL

COMPLEX MODULATOR

LATCH

CLKP

RESET_N

DAC

AUXILIARY

DAC

AUXILIARY

DAC

REFERENCE

BANDGAP

OFFSET

CONTROL

10-BIT

GAIN

CONTROL

10-BIT

OFFSET

CONTROL

10-BIT

GAIN

CONTROL

10-BIT

OFFSET

CONTROL

SCLK

SCS_N

SDIO

SDO

41, 42

45 to 48,

51 to 54

18 to 25,

28, 29

63 65 64

CLKN

Q0 to Q9

dual port/

interleaved

data modes

I0 to I9

SPI

AUXAN

GAPOUT

AUXAP

IOUTAN

VIRES

IOUTAP

IOUTBN

IOUTBP

AUXBN

AUXBP

mixer

−

mixer

sin x

Product data sheet Rev. 04 — 2 July 2012 4 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

6. Pinning information

6.1 Pinning

Fig 2. Pin configuration

DAC1005D650HW

VDDA(3V3) VDDA(3V3)

AUXAP AUXBP

AUXAN AUXBN

AGND AGND

VDDA(1V8) VDDA(1V8)

AGND GAPOUT

CLKP VIRES

CLKN d.n.c.

AGND RESET_N

VDDA(1V8) SCS_N

d.n.c. SCLK

d.n.c. SDIO

TM1 SDO

I7 n.c.

I6 n.c.

I5 Q0

I4 Q1

TM0

VDD(IO)(3V3)

GNDIO

TM3

VDD(IO)(3V3)

GNDIO

n.c.

I2 Q3

VDDD(1V8) AGND

DGND VDDA(1V8)

I1 AGND

I0 VDDA(1V8)

n.c. AGND

n.c. VDDA(1V8)

VDDD(1V8) AGND

DGND VDDA(1V8)

n.c. AGND

n.c. IOUTAN

VDDD(1V8) IOUTAP

DGND AGND

TM2 n.c.

DGND AGND

Q7 VDDA(1V8)

Q6 AGND

Q5 VDDA(1V8)

Q4 AGND

DGND

VDDD(1V8)

Q9/SELIQ

DGND

VDDD(1V8)

VDDA(1V8)

IOUTBP

IOUTBN

AGND

VDDA(1V8)

AGND

VDDD(1V8) AGND

001aak159

100

AGND

Product data sheet Rev. 04 — 2 July 2012 5 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

6.2 Pin description

Table 2. Pin description

Symbol Pin Type[1] Description

VDDA(3V3) 1 P analog supply voltage 3.3 V

AUXAP 2 O auxiliary DAC B output current

AUXAN 3 O complementary auxiliary DAC B output current

AGND 4 G analog ground

VDDA(1V8) 5 P analog supply voltage 1.8 V

VDDA(1V8) 6 P analog supply voltage 1.8 V

AGND 7 G analog ground

CLKP 8 I clock input

CLKN 9 I complementary clock input

AGND 10 G analog ground

VDDA(1V8) 11 P analog supply voltage 1.8 V

d.n.c. 12 - do not connect

d.n.c. 13 - do not connect

TM1 14 I/O test mode 1 (to connect to DGND)

TM0 15 I/O test mode 0 (to connect to DGND)

VDD(IO)(3V3) 16 P input/output buffers supply voltage 3.3 V

GNDIO 17 G input/output buffers ground

I9 18 I I data input bit 9 (MSB)

I8 19 I I data input bit 8

I7 20 I I data input bit 7

I6 21 I I data input bit 6

I5 22 I I data input bit 5

I4 23 I I data input bit 4

I3 24 I I data input bit 3

I2 25 I I data input bit 2

VDDD(1V8) 26 P digital supply voltage 1.8 V

DGND 27 G digital ground

I1 28 I I data input bit 1

I0 29 I I data input bit 0 (LSB)

n.c. 30 I not connected

n.c. 31 I not connected

VDDD(1V8) 32 P digital supply voltage 1.8 V

DGND 33 G digital ground

n.c. 34 I not connected

n.c. 35 I not connected

VDDD(1V8) 36 P digital supply voltage 1.8 V

DGND 37 G digital ground

TM2 38 - test mode 2 (to connect to DGND)

DGND 39 G digital ground

Product data sheet Rev. 04 — 2 July 2012 6 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

VDDD(1V8) 40 P digital supply voltage 1.8 V

Q9/SELIQ 41 I Q data input bit 9 (MSB)

select IQ

Q8 42 I Q data input bit 8

DGND 43 G digital ground

VDDD(1V8) 44 P digital supply voltage 1.8 V

Q7 45 I Q data input bit 7

Q6 46 I Q data input bit 6

Q5 47 I Q data input bit 5

Q4 48 I Q data input bit 4

DGND 49 G digital ground

VDDD(1V8) 50 P digital supply voltage 1.8 V

Q3 51 I Q data input bit 3

Q2 52 I Q data input bit 2

Q1 53 I Q data input bit 1

Q0 54 I Q data input bit 0 (LSB)

n.c. 55 I not connected

n.c. 56 I not connected

n.c. 57 I not connected

n.c. 58 I not connected

GNDIO 59 G input/output buffers ground

VDD(IO)(3V3) 60 P input/output buffers supply voltage 3.3 V

TM3 61 I/O test mode 3 (to connect to DGND)

SDO 62 O SPI data output

SDIO 63 I/O SPI data input/output

SCLK 64 I SPI clock

SCS_N 65 I SPI chip select (active LOW)

RESET_N 66 I general reset (active LOW)

d.n.c. 67 - do not connect

VIRES 68 I/O DAC biasing resistor

GAPOUT 69 I/O bandgap input/output voltage

VDDA(1V8) 70 P analog supply voltage 1.8 V

VDDA(1V8) 71 P analog supply voltage 1.8 V

AGND 72 G analog ground

AUXBN 73 O complementary auxiliary DAC B output current

AUXBP 74 O auxiliary DAC B output current

VDDA(3V3) 75 P analog supply voltage 3.3 V

AGND 76 G analog ground

VDDA(1V8) 77 P analog supply voltage 1.8 V

AGND 78 G analog ground

VDDA(1V8) 79 P analog supply voltage 1.8 V

Table 2. Pin description …continued

Symbol Pin Type[1] Description

Product data sheet Rev. 04 — 2 July 2012 7 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

[1] P = power supply

G = ground

I = input

O = output.

[2] H = heatsink (exposed die pad to be soldered).

AGND 80 G analog ground

VDDA(1V8) 81 P analog supply voltage 1.8 V

AGND 82 G analog ground

VDDA(1V8) 83 P analog supply voltage 1.8 V

AGND 84 G analog ground

IOUTBN 85 O complementary DAC B output current

IOUTBP 86 O DAC B output current

AGND 87 G analog ground

n.c. 88 - not connected

AGND 89 G analog ground

IOUTAP 90 O DAC A output current

IOUTAN 91 O complementary DAC A output current

AGND 92 G analog ground

VDDA(1V8) 93 P analog supply voltage 1.8 V

AGND 94 G analog ground

VDDA(1V8) 95 P analog supply voltage 1.8 V

AGND 96 G analog ground

VDDA(1V8) 97 P analog supply voltage 1.8 V

AGND 98 G analog ground

VDDA(1V8) 99 P analog supply voltage 1.8 V

AGND 100 G analog ground

AGND H[2] G analog ground

Table 2. Pin description …continued

Symbol Pin Type[1] Description

Product data sheet Rev. 04 — 2 July 2012 8 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

7. Limiting values

8. Thermal characteristics

[1] In compliance with JEDEC test board, in free air.

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD(IO)(3V3) input/output supply voltage (3.3 V) 0.5 +4.6 V

VDDA(3V3) analog supply voltage (3.3 V) 0.5 +4.6 V

VDDA(1V8) analog supply voltage (1.8 V) 0.5 +3.0 V

VDDD(1V8) digital supply voltage (1.8 V) 0.5 +3.0 V

VIinput voltage pins CLKP, CLKN, VIRES and GAPOUT

referenced to AGND

0.5 +3.0 V

pins I9 to I0, Q9 to Q0, SDO, SDIO, SCLK,

SCS_N and RESET_N referenced to GNDIO

0.5 +4.6 V

VOoutput voltage pins IOUTAP, IOUTAN, IOUTBP, IOUTBN,

AUXAP, AUXAN, AUXBP and AUXBN

referenced to AGND

0.5 +4.6 V

Tstg storage temperature 55 +150 C

Tamb ambient temperature 45 +85 C

Tjjunction temperature - 125 C

Table 4. Thermal characteristics

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from junction to ambient [1] 19.8 K/W

Rth(j-c) thermal resistance from junction to case [1] 7.7 K/W

Product data sheet Rev. 04 — 2 July 2012 9 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

9. Characteristics

Table 5. Characteristics

VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together;

Tamb =





Cto+85



C; typical values measured at Tamb = 25



C; RL= 50



; IO(fs) = 20 mA; maximum sample rate; PLL on;

unless otherwise specified.

Symbol Parameter Conditions Test[1] Min Typ Max Unit

VDD(IO)(3V3) input/output supply

voltage (3.3 V)

I3.03.33.6V

VDDA(3V3) analog supply voltage

(3.3 V)

I3.03.33.6V

VDDA(1V8) analog supply voltage

(1.8 V)

I1.71.81.9V

VDDD(1V8) digital supply voltage

(1.8 V)

I1.71.81.9V

IDD(IO)(3V3) input/output supply

current (3.3 V)

fo = 19 MHz; fs = 640 Msps;

8interpolation; NCO on

I-513mA

IDDA(3V3) analog supply current

(3.3 V)

fo = 19 MHz; fs = 640 Msps;

8interpolation; NCO on

I-4826mA

IDDD(1V8) digital supply current

(1.8 V)

fo = 19 MHz; fs = 640 Msps;

8interpolation; NCO on

I - 270 309 mA

IDDA(1V8) analog supply current

(1.8 V)

fo = 19 MHz; fs = 640 Msps;

8interpolation; NCO on

I - 330 358 mA

IDDD digital supply current for x / (sin x) function only I - 67 - mA

Ptot total power dissipation fo = 19 MHz; fs = 320 Msps;

4interpolation; NCO off;

DAC B off

C - 0.53 - W

fo = 19 MHz; fs = 320 Msps;

4interpolation; NCO off

C - 0.82 - W

fo = 19 MHz; fs = 320 Msps;

4interpolation; NCO on

C - 0.94 - W

fo = 19 MHz; fs = 640 Msps;

8interpolation; NCO off

C - 0.95 - W

fo = 19 MHz; fs = 640 Msps;

8interpolation; NCO on;

all VDD

I - 1.18 1.4 W

fo = 19 MHz; fs = 640 Msps;

8interpolation;

NCO low power on

C - 1.07 - W

Power-down mode

full power-down; all VDD I - 0.08 0.13 W

DAC A and DAC B Sleep

mode; 8 interpolation;

NCO on

I - 0.88 - W

Product data sheet Rev. 04 — 2 July 2012 10 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

Clock inputs (CLKP and CLKN)[2]

Viinput voltage CLKP; or CLKN Vgpd<50mV C [3] 825 - 1575 mV

Vidth input differential

threshold voltage

Vgpd < 50 mV C [3] 100 - +100 mV

Riinput resistance D - 10 - M

Ciinput capacitance D - 0.5 - pF

Digital inputs (I0 to I13, Q0 to Q13)

VIL LOW-level input

voltage

C GNDIO - 1.0 V

VIH HIGH-level input

voltage

C2.3-V

DD(IO)(3V3) V

IIL LOW-level input

current

VIL = 1.0 V I - 40 - A

IIH HIGH-level input

current

VIH = 2.3 V I - 80 - A

Digital inputs (SDO, SDIO, SCLK, SCS_N and RESET_N)

VIL LOW-level input

voltage

C GNDIO - 1.0 V

VIH HIGH-level input

voltage

C2.3-V

DD(IO)(3V3) V

IIL LOW-level input

current

VIL = 1.0 V I - 20 - nA

IIH HIGH-level input

current

VIH = 2.3 V I - 20 - nA

Analog outputs (IOUTAP, IOUTAN, IOUTBP and IOUTBN)

IO(fs) full-scale output

current

default register C - 20 - mA

VOoutput voltage compliance range C 1.8 - VDDA(3V3) V

Rooutput resistance D - 250 - k

Cooutput capacitance D - 3 - pF

NDAC(mono) DAC monotonicity guaranteed D - 8 - bit

EOoffset error variation C - 6 - ppm/C

EGgain error variation C - 18 - ppm/C

Reference voltage output (GAPOUT)

VO(ref) reference output

voltage

Tamb = 25 C I 1.24 1.29 1.34 V

VO(ref) reference output

voltage variation

C-117- ppm/C

IO(ref) reference output

current

external voltage 1.25 V D - 40 - A

Table 5. Characteristics …continued

VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together;

Tamb =





Cto+85



C; typical values measured at Tamb = 25



C; RL= 50



; IO(fs) = 20 mA; maximum sample rate; PLL on;

unless otherwise specified.

Symbol Parameter Conditions Test[1] Min Typ Max Unit

Product data sheet Rev. 04 — 2 July 2012 11 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN)

IO(aux) auxiliary output current differential outputs I - 2.2 - mA

VO(aux) auxiliary output voltage compliance range C 0 - 2 V

NDAC(aux)mono auxiliary DAC

monotonicity

guaranteed D - 10 - bit

Input timing (see Figure 10)

fdata data rate Dual-port mode input C - - 160 MHz

tw(CLK) CLK pulse width C 1.5 - Tdata  1.5 ns

th(i) input hold time C 1.1 - - ns

tsu(i) input set-up time C 1.1 - - ns

Output timing

fssampling frequency C - - 650 Msps

tssettling time to 0.5 LSB D - 20 - ns

NCO frequency range; fs = 640 Msps

fNCO NCO frequency register value = 00000000h D - 0 - MHz

fstep step frequency D - 0.149 - Hz

Low-power NCO frequency range; fDAC = 640 MHz

fNCO NCO frequency register value = 00000000h D - 0 - MHz

fstep step frequency D - 20 - MHz

Dynamic performance; PLL on

SFDR spurious-free dynamic

range

fdata = 80 MHz; fs= 320 Msps;

B=f

data / 2

fo = 35 MHz at 0 dBFS C - 82 - dBc

fdata = 80 MHz; fs= 640 Msps;

B=f

data / 2

fo = 4 MHz at 0 dBFS I - 76 - dBc

fo = 19 MHz at 0 dBFS I - 75 - dBc

fdata = 160 MHz; fs= 640 Msps;

B=f

data / 2

fo = 70 MHz at 0 dBFS C - 82 - dBc

Table 5. Characteristics …continued

VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together;

Tamb =





Cto+85



C; typical values measured at Tamb = 25



C; RL= 50



; IO(fs) = 20 mA; maximum sample rate; PLL on;

unless otherwise specified.

Symbol Parameter Conditions Test[1] Min Typ Max Unit

Product data sheet Rev. 04 — 2 July 2012 12 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.

[2] CLKP and CLKN inputs are at differential LVDS levels. An external differential resistor with a value of between 80  and 120  should

be connected across the pins (see Figure 8).

[3] Vgpd represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance

and the inductance between the receiver and the driver circuit ground.

[4] IMD3 rejection with 6 dBFS/tone.

SFDRRBW restricted bandwidth

spurious-free dynamic

range

fs = 640 Msps; fo = 96 MHz at

0dBFS

2.51 MHz  foffset  2.71 MHz;

B = 30 kHz

I-89 83 dBc

2.71 MHz  foffset  3.51 MHz;

B = 30 kHz

I-88 - dBc

3.51 MHz  foffset  4 MHz;

B = 30 kHz

I-89 81 dBc

4 MHz  foffset  40 MHz;

B=1MHz

I-83 67 dBc

IMD3 third-order

intermodulation

distortion

fs= 320 Msps; 4interpolation

fo1 =49MHz; f

o2 =51MHz C [4] -81- dBc

fo1 =95MHz; f

o2 =97MHz C [4] -80- dBc

fs=640Msps; 8interpolation

fo1 =95MHz; f

o2 =97MHz I [4] 67 79 - dBc

fo1 = 152 MHz; fo2 =154MHz C [4] -77- dBc

ACPR adjacent channel

power ratio

fdata =76.8MHz; f

s=614.4

Msps; fo=96MHz

1 carrier; B = 5 MHz I - 64 - dB

2 carriers; B = 10 MHz C - 61 - dB

4 carriers; B = 20 MHz C - 60 - dB

fdata = 153.6 MHz; fs= 614.4

Msps; fo= 115.2 MHz

1 carrier; B = 5 MHz C - 67 - dB

2 carriers; B = 10 MHz C - 63 - dB

4 carriers; B = 20 MHz C - 60 - dB

fdata = 153.6 MHz; fs= 614.4

Msps; fo= 153.6 MHz

1 carrier; B = 5 MHz C - 65 - dB

2 carriers; B = 10 MHz C - 63 - dB

4 carriers; B = 20 MHz C - 60 - dB

NSD noise spectral density fs = 640 Msps; 8 interpolation;

fo = 19 MHz at 0 dBFS

noise shaper disabled C - 138 - dBm/Hz

noise shaper enabled C - 139 - dBm/Hz

Table 5. Characteristics …continued

VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together;

Tamb =





Cto+85



C; typical values measured at Tamb = 25



C; RL= 50



; IO(fs) = 20 mA; maximum sample rate; PLL on;

unless otherwise specified.

Symbol Parameter Conditions Test[1] Min Typ Max Unit

Product data sheet Rev. 04 — 2 July 2012 13 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

10. Application information

10.1 General description

The DAC1005D650 is a dual 10-bit DAC operating at up to 650 Msps. Each DAC consists

of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 4-bit binary

weighted sub-DAC.

With an input data rate of up to 160 MHz, and a maximum output sampling rate of

650 Msps, the DAC1005D650 allows more flexibility for wide bandwidth and multi-carrier

systems. Combined with its quadrature modulator and its 32-bit NCO, the DAC1005D650

simplifies the frequency selection of the system. This is also possible because of the 2,

4 and 8 interpolation filters that remove undesired images.

Two modes are available for the digital input. In the Dual-port mode, each DAC uses its

own data input line. In Interleaved mode, both DACs use the same data input line.

Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and

IOUTBP/IOUTBN. This provides a full-scale output current (IO(fs)) up to 20 mA. An internal

reference is available for the reference current which is externally adjustable using pin

VIRES.

There are embedded features which provide analog offset correction (internal auxiliary

DACs), digital offset control and gain adjustment. All the functions can be set using a SPI.

The DAC1005D650 operates at both 3.3 V and 1.8 V using separate digital and analog

power supplies. The digital input is 3.3 V compliant and the clock input is LVDS compliant.

10.2 Serial interface (SPI)

10.2.1 Protocol description

The DAC1005D650 serial interface is a synchronous serial communication port allowing

easy interfacing with many industry microprocessors. It provides access to the registers

that define the operating modes of the chip in both write and read modes.

This interface can be configured as a 3-wire type (SDIO as bidirectional pin) or a 4-wire

type (SDIO and SDO as unidirectional pin, input and output port respectively). In both

configurations, SCLK acts as the serial clock, and SCS_N acts as the serial chip select

bar. If several DAC1005D650 devices are connected to an application on the same

SPI-bus, only a 3-wire type can be used.

Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW

assertion to drive the chip with between 2 to 5 bytes, depending on the content of the

instruction byte (see Table 7).

Product data sheet Rev. 04 — 2 July 2012 14 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

In Table 7 N1 and N0 indicate the number of bytes transferred after the instruction byte.

A0 to A4 indicates which register is being addressed. In the case of a multiple transfer,

this address concerns the first register after which the next registers follow directly in

decreasing order according to Table 9 “Register allocation map”.

10.2.2 SPI timing description

SPI can operate at a frequency of up to 15 MHz. The SPI timing is shown in Figure 4.

R/W indicates the mode access (see Table 6).

Fig 3. SPI protocol

001aaj812

RESET_N

SCS_N

SCLK

SDIO

SDO

(optional)

R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

Table 6. Read or Write mode access description

R/W Description

0 Write mode operation

1 Read mode operation

Table 7. Number of bytes to be transferred

N1 N0 Number of bytes

0 0 1 byte transferred

0 1 2 bytes transferred

1 0 3 bytes transferred

1 1 4 bytes transferred

Fig 4. SPI timing diagram

001aaj813

50 %

w(RESET_N)

su(SCS_N)

su(SDIO)

h(SDIO)

h(SCS_N)

w(SCLK)

50 %

RESET_N

SCS_N

SCLK

SDIO

50 %

Product data sheet Rev. 04 — 2 July 2012 15 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

The SPI timing characteristics are given in Table 8.

10.2.3 Detailed descriptions of registers

An overview of the details for all registers is provided in Table 9.

Table 8. SPI timing characteristics

Symbol Parameter Min Typ Max Unit

fSCLK SCLK frequency - - 15 MHz

tw(SCLK) SCLK pulse width 30 - - ns

tsu(SCS_N) SCS_N set-up time 20 - - ns

th(SCS_N) SCS_N hold time 20 - - ns

tsu(SDIO) SDIO set-up time 10 - - ns

th(SDIO) SDIO hold time 5 - - ns

tw(RESET_N) RESET_N pulse width 30 - - ns

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 04 — 2 July 2012 16 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

Table 9. Register allocation map

Address Register name R/W Bit definition Default

b7 b6 b5 b4 b3 b2 b1 b0 Bin Hex Dec

0 00h COMMon R/W 3W_SPI SPI_RST CLK_SEL - MODE_

SEL

CODING IC_PD GAP_PD 10000000 80 128

1 01h TXCFG R/W NCO_ON NCO_LP_

SEL

INV_SIN_

SEL

MODULATION[2:0] INTERPOLATION[1:0] 10000111 87 135

2 02h PLLCFG R/W PLL_PD - PLL_DIV_

PLL_DIV[1:0] PLL_PHASE[1:0] PLL_POL 00010000 10 16

3 03h FREQNCO_LSB R/W FREQ_NCO[7:0] 01100110 66 102

4 04h FREQNCO_LISB R/W FREQ_NCO[15:8] 01100110 66 102

5 05h FREQNCO_UISB R/W FREQ_NCO[23:16] 01100110 66 102

6 06h FREQNCO_MSB R/W FREQ_NCO[31:24] 00100110 26 38

7 07h PHINCO_LSB R/W PH_NCO[7:0] 00000000 00 0

8 08h PHINCO_MSB R/W PH_NCO[15:8] 00000000 00 0

9 09h DAC_A_Cfg_1 R/W DAC_A_PD DAC_A_

SLEEP

DAC_A_OFFSET[2:0] - - - 00000000 00 0

10 0Ah DAC_A_Cfg_2 R/W DAC_A_GAIN_

COARSE[1:0]

DAC_A_GAIN_FINE[5:0] 01000000 40 64

11 0Bh DAC_A_Cfg_3 R/W DAC_A_GAIN_

COARSE[3:2]

DAC_A_OFFSET[8:3] 11000000 C0 192

12 0Ch DAC_B_Cfg_1 R/W DAC_B_PD DAC_B_

SLEEP

DAC_B_OFFSET[2:0] - - - 00000000 00 0

13 0Dh DAC_B_Cfg_2 R/W DAC_B_GAIN_

COARSE[1:0]

DAC_B_GAIN_FINE[5:0] 01000000 40 64

14 0Eh DAC_B_Cfg_3 R/W DAC_B_GAIN_

COARSE[3:2]

DAC_B_OFFSET[8:3] 11000000 C0 192

15 0Fh DAC_Cfg R/W - - - - - - MINUS_

3DB

NOISE_

SHPER

00000000 00 0

... ... ... ... ... ... ... ... ... ... ... ... ... ... ...

26 1Ah DAC_A_Aux_MSB R/W AUX_A[9:2] 10000000 80 128

27 1Bh DAC_A_Aux_LSB R/W AUX_A_PD - - - - - AUX_A[1:0] 00000000 00 0

28 1Ch DAC_B_Aux_MSB R/W AUX_B[9:2] 10000000 80 128

29 1Dh DAC_B_Aux_LSB R/W AUX_B_PD - - - - - AUX_B[1:0] 00000000 00 0

Product data sheet Rev. 04 — 2 July 2012 17 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

10.2.4 Registers detailed description

Please refer to Table 9 for a register overview and their default values. In the following

tables, all default results are shown highlighted.

Table 10. COMMon register (address 00h) bit description

Default settings are shown highlighted.

Bit Symbol Access Value Description

7 3W_SPI R/W serial interface bus type

0 4 wire SPI

1 3 wire SPI

6 SPI_RST R/W serial interface reset

0no reset

1 performs a reset on all registers except 00h

5 CLK_SEL R/W data input latch

0 at CLK rising edge

1 at CLK falling edge

3 MODE_SEL R/W input data mode

0 dual-port

1 interleaved

2 CODING R/W coding

0binary

1 two’s compliment

1 IC_PD R/W power-down

0disabled

1 all circuits (digital and analog, except SPI)

are switched off

0 GAP_PD R/W internal bandgap power-down

0 power-down disabled

1 internal bandgap references are switched off

Table 11. TXCFG register (address 01h) bit description

Default settings are shown highlighted.

Bit Symbol Access Value Description

7 NCO_ON R/W NCO

0 disabled (the NCO phase is reset to 0)

1 enabled

6 NCO_LP_SEL R/W low-power NCO

0 disabled

1 NCO frequency and phase given by the five

MSBs of the registers 06h and 08h

respectively

Product data sheet Rev. 04 — 2 July 2012 18 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

4 to 2 MODULATION[2:0] R/W modulation

000 dual DAC: no modulation

001 positive upper single sideband

up-conversion

010 positive lower single sideband up-conversion

011 negative upper single sideband up-conversion

100 negative lower single sideband up-conversion

1 to 0 INTERPOLATION[1:0] R/W interpolation

01 fs = 2fclk

10 fs = 4fclk

11 fs = 8fclk

Table 12. PLLCFG register (address 02h) bit description

Default settings are shown highlighted.

Bit Symbol Access Value Description

7 PLL_PD R/W PLL

0 switched on

1 switched off

5 PLL_DIV_PD R/W PLL divider

0 switched on

1 switched off

4 to 3 PLL_DIV[1:0] R/W PLL divider factor

00 fs=2fclk

01 fs=4fclk

10 fs = 8 ¥ fclk

2 to 1 PLL_PHASE[1:0] R/W PLL phase shift of fs

00 0×

01 120

10 240

0 PLL_POL R/W DAC clock edge

0 normal

1 inverted

Table 13. FREQNCO_LSB register (address 03h) bit description

Bit Symbol Access Value Description

7 to 0 FREQ_NCO[7:0] R/W - lower 8 bits for the NCO frequency setting

Table 14. FREQNCO_LISB register (address 04h) bit description

Bit Symbol Access Value Description

7 to 0 FREQ_NCO[15:8] R/W - lower intermediate 8 bits for the NCO

frequency setting

Table 11. TXCFG register (address 01h) bit description …continued

Default settings are shown highlighted.

Bit Symbol Access Value Description

Product data sheet Rev. 04 — 2 July 2012 19 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

Table 15. FREQNCO_UISB register (address 05h) bit description

Bit Symbol Access Value Description

7 to 0 FREQ_NCO[23:16] R/W - upper intermediate 8 bits for the NCO

frequency setting

Table 16. FREQNCO_MSB register (address 06h) bit description

Bit Symbol Access Value Description

7 to 0 FREQ_NCO[31:24] R/W - most significant 8 bits for the NCO frequency

setting

Table 17. PHINCO_LSB register (address 07h) bit description

Bit Symbol Access Value Description

7 to 0 PH_NCO[7:0] R/W - lower 8 bits for the NCO phase setting

Table 18. PHINCO_MSB register (address 08h) bit description

Bit Symbol Access Value Description

7 to 0 PH_NCO[15:8] R/W - most significant 8 bits for the NCO phase setting

Table 19. DAC_A_Cfg_1 register (address 09h) bit description

Default settings are shown highlighted.

Bit Symbol Access Value Description

7 DAC_A_PD R/W DAC A power

0on

1off

6 DAC_A_SLEEP R/W DAC A Sleep mode

0disabled

1 enabled

5 to 3 DAC_A_OFFSET[2:0] R/W - lower 3 bits for the DAC A offset

Table 20. DAC_A_Cfg_2 register (address 0Ah) bit description

Bit Symbol Access Value Description

7 to 6 DAC_A_GAIN_COARSE[1:0] R/W - least significant 2 bits for the DAC A gain

setting for coarse adjustment

5 to 0 DAC_A_GAIN_FINE[5:0] R/W - the 6 bits for the DAC A fine adjustment

gain setting

Table 21. DAC_A_Cfg_3 register (address 0Bh) bit description

Bit Symbol Access Value Description

7 to 6 DAC_A_GAIN_COARSE[3:2] R/W - most significant 2 bits for the DAC A

gain setting for coarse adjustment

5 to 0 DAC_A_OFFSET[8:3] R/W - most significant 6 bits for the DAC A

offset

Product data sheet Rev. 04 — 2 July 2012 20 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

Table 22. DAC_B_Cfg_1 register (address 0Ch) bit description

Default settings are shown highlighted.

Bit Symbol Access Value Description

7 DAC_B_PD R/W DAC B power

0on

1off

6 DAC_B_SLEEP R/W DAC B Sleep mode

0disabled

1 enabled

5 to 3 DAC_B_OFFSET[2:0] R/W lower 3 bits for the DAC B offset

Table 23. DAC_B_Cfg_2 register (address 0Dh) bit description

Bit Symbol Access Value Description

7 to 6 DAC_B_GAIN_COARSE[1:0] R/W - less significant 2 bits for the DAC B gain

setting for coarse adjustment

5 to 0 DAC_B_GAIN_FINE[5:0] R/W - the 6 bits for the DAC B gain setting for

fine adjustment

Table 24. DAC_B_Cfg_3 register (address 0Eh) bit description

Bit Symbol Access Value Description

7 to 6 DAC_B_GAIN_COARSE[3:2] R/W - most significant 2 bits for the DAC B

gain setting for coarse adjustment

5 to 0 DAC_B_OFFSET[8:3] R/W - most significant 6 bits for the DAC B

offset

Table 25. DAC_Cfg register (address 0Fh) bit description

Default settings are shown highlighted.

Bit Symbol Access Value Description

1 MINUS_3DB R/W NCO gain

0unity

13 dB

0 NOISE_SHPER R/W noise shaper

0 disabled

1 enabled

Table 26. DAC_A_Aux_MSB register (address 1Ah) bit description

Bit Symbol Access Value Description

7 to 0 AUX_A[9:2] R/W - most significant 8 bits for the auxiliary DAC A

Table 27. DAC_A_Aux_LSB register (address 1Bh) bit description

Default settings are shown highlighted.

Bit Symbol Access Value Description

7 AUX_A_PD R/W auxiliary DAC A power

0on

1off

1 to 0 AUX_A[1:0] R/W lower 2 bits for the auxiliary DAC A

Product data sheet Rev. 04 — 2 July 2012 21 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

10.3 Input data

The setting applied to MODE_SEL (register 00h[3]; see Table 10 on page 17) defines

whether the DAC1005D650 operates in the Dual-port mode or in the Interleaved mode

(see Table 30).

10.3.1 Dual-port mode

The data input for Dual-port mode operation is shown in Figure 5 “Dual-port mode”. Each

DAC has its own independent data input. The data enters the input latch on the rising

edge of the internal clock signal and is transferred to the DAC latch.

10.3.2 Interleaved mode

The data input for Interleaved mode operation is shown in Figure 6 “Interleaved mode

operation”.

Table 28. DAC_B_Aux_MSB register (address 1Ch) bit description

Bit Symbol Access Value Description

7 to 0 AUX_B[9:2] R/W - most significant 8 bits for the auxiliary DAC B

Table 29. DAC_B_Aux_LSB register (address 1Dh) bit description

Default settings are shown highlighted.

Bit Symbol Access Value Description

7 AUX_B_PD R/W auxiliary DAC B power

0on

1off

1 to 0 AUX_B[1:0] R/W lower 2 bits for the auxiliary DAC B

Table 30. Mode selection

Bit 3 setting Function I9 to I0 Q9 to Q0

0 Dual-port mode (pin Q9) active active

1 Interleaved mode (pin SELIQ) active off

n in Qn = 0 to 9 and for In is 0 to 9.

Fig 5. Dual-port mode

001aaj585

LATCH

I2 ×2 ×2 ×

FIR 1

FIR 2

FIR 3

LATCH

Q2 ×2 ×2 ×

Product data sheet Rev. 04 — 2 July 2012 22 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

In the Interleaved mode, both DACs use the same data input at twice the Dual-port mode

frequency. Data enters the latch on the rising edge of the internal clock signal. The data is

sent to either latch I or latch Q, see Figure 6 “Interleaved mode operation” and Figure 7

“Interleaved mode timing (8x interpolation, latch on rising edge)”.

The SELIQ input (pin 41) allows the synchronization of the internally de-multiplexed I and

Q channels.

SELIQ can be either a synchronous or asynchronous (single rising edge, single pulse)

signal. The first data bits following the SELIQ rising edge are sent in channel I and the

following data bits are sent in channel Q. After this, the data is distributed alternately

between both channels.

10.4 Input clock

The DAC1005D650 can operate with a clock frequency of 160 MHz in the Dual-port mode

and up to 320 MHz in the Interleaved mode. The input clock is LVDS (see Figure 8) but it

can also be interfaced with CML (see Figure 9).

n in Qn = 9 and for In is 0 to 9.

Fig 6. Interleaved mode operation

Fig 7. Interleaved mode timing (8x interpolation, latch on rising edge)

001aaj586

LATCH

I2 ×2 ×2 ×

FIR 1

FIR 2

FIR 3

LATCH

Q2 ×2 ×2 ×

Qn/SELIQ

001aaj814

NIn

SELIQ

(synchronous alternative)

SELIQ

(asynchronous alternative 1)

SELIQ

(asynchronous alternative 2)

CLKdig

Latch I output

Latch Q output

XX N N + 2

N + 1 N + 2 N + 3 N + 4 N + 5

XX N + 1 N + 3

Product data sheet Rev. 04 — 2 July 2012 23 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

10.5 Timing

The DAC1005D650 can operate at an update rate (fs) of up to 650 Msps and with an input

data rate (fdata) of up to 160 MHz. The input timing is shown in Figure 10 “Input timing

diagram”.

The typical performances are measured at 50 % duty cycle but any timing within the limits

of the characteristics will not alter the performance.

In Table 31 “Frequencies”, the links between internal and external clocking are defined.

The setting applied to PLL_DIV[1:0] (register 02h[4:3]; see Table 12 “PLLCFG register

(address 02h) bit description”) allows the frequency between the digital part and the DAC

core to be adjusted.

Fig 8. LVDS clock configuration

Fig 9. Interfacing CML to LVDS

001aah021

100 Ω

LVDS

CLKINP

CLKINN

LVDS

diff

= 100 Ω

001aah020

55 Ω

1.1 kΩ

2.2 kΩ

100 nF

CML

100 nF

CLKINP

LVDS

CLKINN

AGND

VDDA(1V8)

1 kΩZdiff = 100 Ω

n in Qn = 0 to 9 and for In is 0 to 9.

Fig 10. Input timing diagram

001aaj815

tsu(i)

90 %

50 %

90 %

In/Qn

CLK

(CLKP-CLKN)

th(i)

tw(CLK)

N + 1 N + 2

Product data sheet Rev. 04 — 2 July 2012 24 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

The settings applied to PLL_PHASE[1:0] (register 02h[2:1]) and PLL_POL

(register 02h[0]), allows adjustment of the phase and polarity of the sampling clock. This

occurs at the input of the DAC core and depends mainly on the sampling frequency. Some

examples are given in Table 32 “Sample clock phase and polarity examples”.

10.6 FIR filters

The DAC1005D650 integrates three selectable Finite Impulse Response (FIR) filters

which enable the device to use interpolation rates of 2, 4 or 8.

All three interpolation filters have a stop-band attenuation of at least 80 dBc and a

pass-band ripple of less than 0.0005 dB.

The coefficients of the interpolation filters are given in Table 33 “Interpolation filter

coefficients”.

Table 31. Frequencies

Mode CLK input

(MHz)

Input data rate

(MHz)

Interpolation Update rate

(Msps)

PLL_DIV[1:0]

Dual-port 160 160 2320 01 (/4)

Dual-port 160 160 4640 01 (/4)

Dual-port 80 80 8640 10 (/8)

Interleaved 320 320 2320 00 (/2)

Interleaved 320 320 4640 00 (/2)

Interleaved 160 160 8640 01 (/4)

Table 32. Sample clock phase and polarity examples

Mode Input data rate

(MHz)

Interpolation Update rate

(Msps)

PLL_PHASE

[1:0]

PLL_POL

Dual-port 80 2160 01 1

Dual-port 80 4320 01 0

Dual-port 80 8640 01 1

Interleaved 160 2160 01 1

Interleaved 160 4320 01 0

Interleaved 160 8640 01 1

Product data sheet Rev. 04 — 2 July 2012 25 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

[1] H(n) is the digital filter coefficient.

Table 33. Interpolation filter coefficients

First interpolation filter[1] Second interpolation filter[1] Third interpolation filter[1]

Lower Upper Value Lower Upper Value Lower Upper Value

H(1) H(55) 4 H(1) H(23) 2 H(1) H(15) 39

H(2) H(54) 0 H(2) H(22) 0 H(2) H(14) 0

H(3) H(53) 13 H(3) H(21) 17 H(3) H(13) 273

H(4) H(52) 0 H(4) H(20) 0 H(4) H(12) 0

H(5) H(51) 34 H(5) H(19) 75 H(5) H(11) 1102

H(6) H(50) 0 H(6) H(18) 0 H(6) H(10) 0

H(7) H(49) 72 H(7) H(17) 238 H(7) H(9) 4964

H(8) H(48) 0 H(8) H(16) 0 H(8) - 8192

H(9) H(47) 138 H(9) H(15) 660 - - -

H(10) H(46) 0 H(10) H(14) 0 - - -

H(11) H(45) 245 H(11) H(13) 2530 - - -

H(12) H(44) 0 H(12) - 4096 - - -

H(13) H(43) 408------

H(14)H(42)0------

H(15) H(41) 650 - - - - - -

H(16)H(40)0------

H(17) H(39) 1003------

H(18)H(38)0------

H(19) H(37) 1521 - - - - - -

H(20)H(36)0------

H(21) H(35) 2315------

H(22)H(34)0------

H(23) H(33) 3671 - - - - - -

H(24)H(32)0------

H(25) H(31) 6642------

H(26)H(30)0------

H(27) H(29) 20756 - - - - - -

H(28) 32768------

Product data sheet Rev. 04 — 2 July 2012 26 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

10.7 Quadrature modulator and NCO

The quadrature modulator allows the 10-bit I and Q data to be mixed with the carrier

signal generated by the Numerically Controlled Oscillator (NCO).

The frequency of the NCO is programmed over 32-bit and allows the sign of the sine

component to be inverted in order to operate positive or negative, lower or upper single

sideband up-conversion.

10.7.1 NCO in 32-bit

When using the NCO, the frequency can be set by the four registers FREQNCO_LSB,

FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits.

The frequency for the NCO in 32-bit is calculated as follows:

(1)

where M is the decimal representation of FREQ_NCO[31:0].

The phase of the NCO can be set from 0 to 360 by both registers PHINCO_LSB and

PHINCO_MSB over 16 bits.

The default setting is fNCO = 96 MHz when fs = 640 Msps and the default phase is 0.

10.7.2 Low-power NCO

When using the low-power NCO, the frequency can be set by the 5 MSB of register

FREQNCO_MSB.

The frequency for the low-power NCO is calculated as follows:

(2)

where M is the decimal representation of FREQ_NCO[31:27].

The phase of the low-power NCO can be set by the 5 MSB of the register PHINCO_MSB.

10.7.3 Minus 3 dB

During normal use, a full-scale pattern will also be full scale at the output of the DAC.

Nevertheless, when the I and Q data are simultaneously close to full scale, some clipping

can occur and the Minus_3dB function can be used to reduce gain by 3 dB in the

modulator. This is to keep a full-scale range at the output of the DAC without added

interferers.

10.8 x / (sin x)

Due to the roll-off effect of the DAC, a selectable FIR filter is inserted to compensate for

the (sin x) / x effect. This filter introduces a DC loss of 3.4 dB. The coefficients are

represented in Table 34 “Inversion filter coefficients”.

fNCO



232

--------------

fNCO



--------------

Product data sheet Rev. 04 — 2 July 2012 27 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

[1] H(n) is the digital filter coefficient.

10.9 DAC transfer function

The full-scale output current for each DAC is the sum of the two complementary current

outputs:

(3)

The output current depends on the digital input data:

(4)

(5)

The setting applied to CODING (register 00h[2]; see Table 9 “Register allocation map”)

defines whether the DAC1005D650 operates with a binary input or a two’s complement

input.

Table 35 “DAC transfer function” shows the output current as a function of the input data,

when IO(fs) = 20 mA.

Table 34. Inversion filter coefficients

First interpolation filter[1]

Lower Upper Value

H(1) H(9) 2

H(2) H(8) 4

H(3) H(7) 10

H(4) H(6) 35

H(5) - 401

Table 35. DAC transfer function

Data

(Decimal)

I9/Q9 to I0/Q0 IOUTP IOUTN

Binary Two’s complement

0 00 0000 0000 10 0000 0000 0 mA 20 mA

... ... ... ... ...

512 10 0000 0000 00 0000 0000 10 mA 10 mA

... ... ... ... ...

1023 11 1111 1111 01 1111 1111 20 mA 0 mA

IOfs IIOUTP IIOUTN

IIOUTP IOfs DATA

1023

----------------





=

IIOUTN IOfs 1023 DATA–

1023

----------------------------------





=

Product data sheet Rev. 04 — 2 July 2012 28 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

10.10 Full-scale current

10.10.1 Regulation

The DAC1005D650 reference circuitry integrates an internal bandgap reference voltage

which delivers a 1.29 V reference to the GAPOUT pin. It is recommended to decouple pin

GAPOUT using a 100 nF capacitor.

The reference current is generated using an external resistor of 953  (1 %) connected to

pin VIRES. A control amplifier sets the appropriate full-scale current (IO(fs)) for both DACs

(see Figure 11 “Internal reference configuration”).

This configuration is optimum for temperature drift compensation because the bandgap

reference voltage can be matched to the voltage across the feedback resistor.

The DAC current can also be set by applying an external reference voltage to the

non-inverting input pin GAPOUT and disabling the internal bandgap reference voltage

with GAP_PD (register 00h[0]; see Table 10 “COMMon register (address 00h) bit

description”).

10.10.2 Full-scale current adjustment

The default full-scale current (IO(fs)) is 20 mA. It can be further adjusted for each DAC

using SPI. The adjustment range is between 1.6 mA to 22 mA 10 %.

The settings applied to DAC_A_GAIN_COARSE[3:0] (register 0Ah; see Table 20

“DAC_A_Cfg_2 register (address 0Ah) bit description” and register 0Bh; see Table 21

“DAC_A_Cfg_3 register (address 0Bh) bit description”) and to DAC_B_GAIN

COARSE[3:0] (register 0Dh; see Table 23 “DAC_B_Cfg_2 register (address 0Dh) bit

description” and register 0Eh; see Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit

description”) define the coarse variation of the full-scale current (see Table 36 “IO(fs)

coarse adjustment”).

Fig 11. Internal reference configuration

aaa-002266

REF.

BANDGAP

GAPOUT

VDDA(1V8)

VIRES

DAC

CURRENT

SOURCES

ARRAY

GND

100 nF

953 Ω

(1 %)

100

kΩ

Product data sheet Rev. 04 — 2 July 2012 29 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

The settings applied to DAC_A_GAIN_FINE[5:0] (register 0Ah; see Table 20

“DAC_A_Cfg_2 register (address 0Ah) bit description”) and to DAC_B_GAIN_FINE[5:0]

(register 0Dh; see Table 23 “DAC_B_Cfg_2 register (address 0Dh) bit description”) define

the fine variation of the full-scale current (see Table 37 “IO(fs) fine adjustment”).

The coding of the fine gain adjustment is two’s complement.

10.11 Digital offset adjustment

When the DAC1005D650 analog output is DC connected to the next stage, the digital

offset correction can be used to adjust the common mode level at the output of the DAC. It

adds an offset at the end of the digital part, just before the DAC.

The settings applied to DAC_A_OFFSET[8:0] (register 09h; see Table 19 “DAC_A_Cfg_1

Table 36. IO(fs) coarse adjustment

Default settings are shown highlighted.

DAC_GAIN_COARSE[3:0] IO(fs) (mA)

Decimal Binary

0 0000 1.6

1 0001 3.0

2 0010 4.4

3 0011 5.8

4 0100 7.2

5 0101 8.6

6011010.0

7 0111 11.4

8 1000 12.8

9 1001 14.2

10 1010 15.6

11 1011 17.0

12 1100 18.5

13 1101 20.0

14 1110 21.0

15 1111 22.0

Table 37. IO(fs) fine adjustment

Default settings are shown highlighted.

DAC_GAIN_FINE[5:0] Delta IO(fs)

Decimal Two’s complement

32 10 0000 10 %

... ... ...

0 00 0000 0

... ... ...

+31 01 1111 +10 %

Product data sheet Rev. 04 — 2 July 2012 30 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

Table 22 “DAC_B_Cfg_1 register (address 0Ch) bit description” and register 0Eh; see

Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit description”) define the range of

variation of the digital offset (see Table 38 “Digital offset adjustment”).

10.12 Analog output

The DAC1005D650 has two output channels each of which produces two complementary

current outputs. These allow the even-order harmonics and noise to be reduced. The pins

are IOUTAP/IOUTAN and IOUTBP/IOUTBN respectively and need to be connected using

a load resistor RL to the 3.3 V analog power supply (VDDA(3V3)).

Refer to Figure 12 for the equivalent analog output circuit of one DAC. This circuit consists

of a parallel combination of NMOS current sources, and their associated switches, for

each segment.

The cascode source configuration increases the output impedance of the source, thus

improving the dynamic performance of the DAC by introducing less distortion.

The device can provide an output level of up to 2 Vo(p-p) depending on the application, the

following stages and the targeted performances.

Table 38. Digital offset adjustment

Default settings are shown highlighted.

DAC_OFFSET[8:0] Offset applied

Decimal Two’s complement

256 1 0000 0000 256

255 1 0000 0001 255

... ... ...

1 1 1111 1111 1

0 0 0000 0000 0

+1 0 0000 0001 +1

... ... ...

+254 0 1111 1110 +254

+255 0 1111 1111 +255

Fig 12. Equivalent analog output circuit (one DAC)

001aah019

VDDA(3V3)

AGND

IOUTAP/IOUTBP

IOUTAN/IOUTBN

RLRL

AGND

Product data sheet Rev. 04 — 2 July 2012 31 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

10.13 Auxiliary DACs

The DAC1005D650 integrates two auxiliary DACs that can be used to compensate for

any offset between the DAC and the next stage in the transmission path.

Both auxiliary DACs have a resolution of 10-bit and are current sources (referenced to

ground). The settings applied to AUX_A[9:0] and AUX_B[9:0] define the offset data.

(6)

The output current depends on the auxiliary DAC data:

(7)

(8)

Table 39 “Auxiliary DAC transfer function” shows the output current as a function of the

auxiliary DAC data.

Table 39. Auxiliary DAC transfer function

Default settings are shown highlighted.

Data AUX_A[9:0] and AUX_B[9:0] (binary) IAUXP IAUXN

0 00 0000 0000 0 mA 2.2 mA

... ... ... ...

512 10 0000 0000 1.1 mA 1.1 mA

... ... ... ...

1023 11 1111 1111 2.2 mA 0 mA

IOAUX

IAUXP IAUXN

AUXP IOAUX

AUX 9:0

1023

-------------------------





=

AUXN IOAUX

(1023 A–UX 9:0

1023

---------------------------------------------





=

Product data sheet Rev. 04 — 2 July 2012 32 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

10.14 Output configuration

10.14.1 Basic output configuration

The use of a differentially-coupled transformer output provides optimum distortion

performance (see Figure 13 “Differential output with transformer; Vo(dif)(p-p) = 1 V”). In

addition, it helps to match the impedance and provides electrical isolation.

The DAC1005D650 can operate up to 2 Vo(p-p) differential outputs. In this configuration, it

is recommended to connect the center tap of the transformer to a 62  resistor connected

to the 3.3 V analog power supply, in order to adjust the DC common mode to

approximately 2.7 V (see Figure 14 “Differential output with transformer; Vo(dif)(p-p) = 2 V”).

10.14.2 DC interface to an AQM

When the system operation requires to keep the DC component of the spectrum, the

DAC1005D650 can use a DC interface to connect to an Analog Quadrature Modulator

(AQM). In this case, the offset compensation for LO cancellation can be made with the

use of the digital offset control in the DAC.

Figure 15 provides an example of a connection to an AQM with a 1.7 V common mode

input level.

Fig 13. Differential output with transformer; Vo(dif)(p-p) = 1 V

Fig 14. Differential output with transformer; Vo(dif)(p-p) = 2 V

001aaj817

50 Ω

IOUTnP/IOUTnN; V

o(cm)

= 2.8 V; V

o(dif)(p-p)

= 1 V

IOUTnP

IOUTnN

0 mA to 20 mA

2:1

0 mA to 20 mA

DDA(3V3)

001aaj818

50 Ω

100 Ω

IOUTnP/IOUTnN; Vo(cm) = 2.7 V; Vo(dif)(p-p) = 2 V

IOUTnP

IOUTnN

0 mA to 20 mA 4:1

0 mA to 20 mA

VDDA(3V3)

62 Ω

VDDA(3V3)

Product data sheet Rev. 04 — 2 July 2012 33 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

Figure 16 provides an example of a connection to an AQM with a 3.3 Vi(cm) common mode

input level.

Fig 15. An example of a DC interface to a 1.7 V AQM

Fig 16. An example of a DC interface to a 3.3 V AQM

001aaj541

51.1 Ω51.1 Ω

442 Ω

VDDA(3V3)

IOUTnP

IOUTnN 0 mA to 20 mA

BBP

(1) IOUTnP/IOUTnN; Vo(cm) = 2.67 V; Vo(dif)(p-p) = 1.98 V

(2) BBP/BBN; Vi(cm) = 1.7 V; Vi(dif)(p-p) = 1.26 V

BBN

AQM (Vi(cm) = 1.7 V)

768 Ω768 Ω

(1) (2)

001aaj542

54.9 Ω54.9 Ω

237 Ω

DDA(3V3)

IOUTnP

IOUTnN

BBP

BBN

AQM (V

i(cm)

= 3.3 V)

750 Ω750 Ω

5 V

1.27 kΩ1.27 kΩ

(1)

IOUTnP/IOUTnN; V

o(cm)

= 2.75 V; V

o(dif)(p-p)

= 1.97 V

(2)

BBP/BBN; V

i(cm)

= 3.3 V; V

i(dif)(p-p)

= 1.5 V

(1) (2)

Product data sheet Rev. 04 — 2 July 2012 34 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

The auxiliary DACs can be used to control the offset in a precise range or with precise

steps.

Figure 17 provides an example of a DC interface with the auxiliary DACs to an AQM with

a 1.7 V common mode input level.

Figure 18 provides an example of a DC interface with the auxiliary DACs to an AQM with

a 3.3 V common mode input level.

Fig 17. An example of a DC interface to a 1.7 Vi(cm) AQM using auxiliary DACs

Fig 18. An example of a DC interface to a 3.3 Vi(cm) AQM using auxiliary DACs

001aaj543

51.1 Ω51.1 Ω

442 Ω

VDDA(3V3)

IOUTnP

IOUTnN 0 mA to 20 mA

BBP

BBN

AQM (Vi(cm) = 1.7 V)

698 Ω698 Ω

51.1 Ω51.1 Ω

AUXnP

AUXnN 1.1 mA (typ.)

(1) IOUTnP/IOUTnN; Vo(cm) = 2.67 V; Vo(dif)(p-p) = 1.94 V

(2) BBP/BBN; Vi(cm) = 1.7 V; Vi(dif)(p-p) = 1.23 V; offset correction up to 36 mV

(1) (2)

001aaj544

54.9 Ω54.9 Ω

237 Ω

3.3 V

IOUTnP

IOUTnN

AUXnP

AUXnN

BBP

BBN

AQM (V

i(cm)

= 3.3 V)

750 Ω750 Ω

5 V

634 Ω634 Ω

442 Ω442 Ω

(1)

IOUTnP/IOUTnN; V

o(cm)

= 2.75 V; V

o(dif)(p-p)

= 1.96 V

(2)

BBP/BBN; V

i(cm)

= 3.3 V; V

i(dif)(p-p)

= 1.5 V; offset correction up to 36 mV

(1) (2)

Product data sheet Rev. 04 — 2 July 2012 35 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

The constraints to adjust the interface are the output compliance range of the DAC and

the auxiliary DACs, the input common mode level of the AQM, and the range of offset

correction required.

10.14.3 AC interface to an AQM

When the Analog Quadrature Modulator (AQM) common mode voltage is close to ground,

the DAC1005D650 must be AC-coupled and the auxiliary DACs are needed for offset

correction.

Figure 18 provides an example of a connection to an AQM with a 0.5 V common mode

input level when using auxiliary DACs.

10.15 Power and grounding

In order to obtain optimum performance, it is recommended that the 1.8 V analog power

supplies on pins 5, 11, 71, 77 and 99 should not be connected with those on pins 70, 79,

81, 83, 93, 95 and 97 on the top layer.

To optimize the decoupling, the power supplies should be decoupled with the following

pins:

•VDDD(1V8): pin 26 with 27; pin 32 with 33; pin 36 with 37; pin 40 with 39; pin 44 with 43

and pin 50 with 49.

•VDD(IO)(3V3): pin 16 with 17 and pin 60 with 59.

•VDDA(1V8): pin 5 with 4; pin 6 with 7; pin 11 with 10; pin 71 with 72; pin 77 with 78; pins

79, 81, 83 with 80, 82, 84; pins 93, 95, 97 with 92, 94, 96 and pin 99 with 98.

•VDDA(3V3): pin 1 with 100 and pin 75 with 76.

Fig 19. An example of an AC interface to a 0.5 Vi(cm) AQM using auxiliary DACs

001aaj589

66.5 Ω66.5 Ω

10 nF

VDDA(3V3)

IOUTnP

IOUTnN 0 mA to 20 mA

BBP

BBN

AQM (Vi(cm) = 0.5 V)

2 kΩ2 kΩ

5 V

174 Ω174 Ω

34 Ω34 Ω

AUXnP

AUXnN 1.1 mA (typ.)

10 nF

(1) IOUTnP/IOUTnN; Vo(cm) = 2.65 V; Vo(dif)(p-p) = 1.96 V

(2) BBP/BBN; Vi(cm) = 0.5 V; Vi(dif)(p-p) = 1.96 V; offset correction up to 70 mV

(1) (2)

Product data sheet Rev. 04 — 2 July 2012 36 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

10.16 Alternative parts

The following alternative parts are available.

Table 40. Alternative parts

Type number Description Sampling frequency

DAC1205D650 dual 12-bit DAC up to 650 Msps

DAC1405D650 dual 14-bit DAC up to 650 Msps

Product data sheet Rev. 04 — 2 July 2012 37 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

11. Package outline

Fig 20. Package outline SOT638-1 (HTQFP100)

UNIT A

max. A1A2A3bpHDHELpZD(1) ZE(1)

ceLywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.2 0.15

0.05 1.05

0.95 0.25 0.27

0.17 0.20

0.09 14.1

13.9 0.5 16.15

15.85 1.15

0.85 7°

0°

0.08 0.080.21

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT638-1 MS-026 03-04-07

05-02-02

D(1) E(1)

14.1

13.9 16.15

15.85

DhEh

7.1

6.1

7.1

6.1 1.15

0.85

EA1

detail X

(A3)

HEA2

vMB

vMA

100

7675 5150

pin 1 index

0 10 mm

scale

HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads;

body 14 x 14 x 1 mm; exposed die pad SOT638-1

exposed die pad side

Product data sheet Rev. 04 — 2 July 2012 38 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

12. Abbreviations

Table 41. Abbreviations

Acronym Description

BB BaseBand

CDMA Code Division Multiple Access

CML Current Mode Logic

CMOS Complementary Metal-Oxide Semiconductor

DAC Digital-to-Analog Converter

FIR Finite Impulse Response

GSM Global System for Mobile communications

IF Intermediate Frequency

IMD3 Third-order Inter Modulation Distortion

LISB Lower Intermediate Significant Byte

LMDS Local Multipoint Distribution Service

LSB Least Significant Bit

LTE Long Term Evolution

LVDS Low-Voltage Differential Signaling

MMDS Multichannel Multipoint Distribution Service

MSB Most Significant Bit

NCO Numerically Controlled Oscillator

NMOS Negative Metal-Oxide Semiconductor

PLL Phase-Locked Loop

SFDR Spurious-Free Dynamic Range

SPI Serial Peripheral Interface

TD-SCDMA Time Division-Synchronous Code Division Multiple Access

UISB Upper Intermediate Significant Byte

WCDMA Wideband Code Division Multiple Access

WiMAX Worldwide Interoperability for Microwave Access

Product data sheet Rev. 04 — 2 July 2012 39 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

13. Glossary

Spurious-Free Dynamic Range (SFDR): — The ratio between the RMS value of the

reconstructed output sine wave and the RMS value of the largest spurious observed

(harmonic and non-harmonic, excluding DC component) in the frequency domain.

Intermodulation Distortion (IMD): — From a dual-tone digital input sine wave (these

two frequencies being close together), the intermodulation distortion products IMD2 and

IMD3 (respectively, 2nd and 3rd order components) are defined below.

IMD2 — The ratio of the RMS value of either tone to the RMS value of the worst 2nd order

intermodulation product.

IMD3 — The ratio of the RMS value of either tone to the RMS value of the worst 3rd order

intermodulation product.

Restricted Bandwidth Spurious-Free Dynamic Range — The ratio of the RMS value of

the reconstructed output sine wave to the RMS value of the noise, including the

harmonics, in a given bandwidth centered around foffset.

Product data sheet Rev. 04 — 2 July 2012 40 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

14. Revision history

15. Contact information

For more information or sales office addresses, please visit: http://www.idt.com

Table 42. Revision history

Document ID Release date Data sheet status Change notice Supersedes

DAC1005D650 v.4 20120702 Product data sheet - DAC1005D650 v.3

DAC1005D650 v.3 20120131 Product data sheet - DAC1005D650 v.2

Modifications: •Section 2 “Features and benefits” has been updated.

•The values for VO(ref) in Table 5 “Characteristics” have been updated.

•Section 10.2.1 “Protocol description” has been updated.

•Section 10.10.1 “Regulation” has been updated.

DAC1005D650 v2 20100903 Product data sheet - DAC1005D650 v1

DAC1005D650 v1 20090728 Product data sheet - -

Product data sheet Rev. 04 — 2 July 2012 41 of 41

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating

16. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8

8 Thermal characteristics . . . . . . . . . . . . . . . . . . 8

9 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 9

10 Application information. . . . . . . . . . . . . . . . . . 13

10.1 General description . . . . . . . . . . . . . . . . . . . . 13

10.2 Serial interface (SPI) . . . . . . . . . . . . . . . . . . . 13

10.2.1 Protocol description . . . . . . . . . . . . . . . . . . . . 13

10.2.2 SPI timing description . . . . . . . . . . . . . . . . . . . 14

10.2.3 Detailed descriptions of registers . . . . . . . . . . 15

10.2.4 Registers detailed description. . . . . . . . . . . . . 17

10.3 Input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

10.3.1 Dual-port mode. . . . . . . . . . . . . . . . . . . . . . . . 21

10.3.2 Interleaved mode . . . . . . . . . . . . . . . . . . . . . . 21

10.4 Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

10.5 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10.6 FIR filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

10.7 Quadrature modulator and NCO . . . . . . . . . . 26

10.7.1 NCO in 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . 26

10.7.2 Low-power NCO . . . . . . . . . . . . . . . . . . . . . . 26

10.7.3 Minus 3 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10.8 x / (sin x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10.9 DAC transfer function. . . . . . . . . . . . . . . . . . . 27

10.10 Full-scale current . . . . . . . . . . . . . . . . . . . . . . 28

10.10.1 Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

10.10.2 Full-scale current adjustment. . . . . . . . . . . . . 28

10.11 Digital offset adjustment. . . . . . . . . . . . . . . . . 29

10.12 Analog output. . . . . . . . . . . . . . . . . . . . . . . . . 30

10.13 Auxiliary DACs . . . . . . . . . . . . . . . . . . . . . . . . 31

10.14 Output configuration. . . . . . . . . . . . . . . . . . . . 32

10.14.1 Basic output configuration . . . . . . . . . . . . . . . 32

10.14.2 DC interface to an AQM. . . . . . . . . . . . . . . . . 32

10.14.3 AC interface to an AQM . . . . . . . . . . . . . . . . . 35

10.15 Power and grounding. . . . . . . . . . . . . . . . . . . 35

10.16 Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 36

11 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 37

12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38

13 Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 40

15 Contact information . . . . . . . . . . . . . . . . . . . . 40

16 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41