Preliminary Technical Data ADP3418
a
REV. PrC 7/3/02
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Dual Boostrapped 12 V MOSFET
Driver with Output Disable
PRELIMINARY TECHNICAL DATA
FEATURES
All-In-One Synchronous Buck Driver
Bootstrapped High-Side Drive
One PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry
Output Disable Control Turns Off both MOSFETs to
Float Output per Intel VRM 10 Specification
APPLICATIONS
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
GENERAL DESCRIPTION
The ADP3418 is a dual high-voltage MOSFET driver
optimized for driving two N-channel MOSFETs which
are the two switches in a non-isolated synchronous buck
power converter. Each of the drivers is capable of driving
a 3000 pF load with a 20 ns propagation delay and a 30 ns
transition time. One of the drivers can be bootstrapped,
and is designed to handle the high-voltage slew rate asso-
ciated with floating high-side gate drivers. The ADP3418
includes overlapping drive protection (ODP) to prevent
shoot-through current in the external MOSFETs. The
OD pin shuts off both the high-side and the low-side
MOSFETs to prevent rapid output capacitor discharge
during system shutdown.
The ADP3418 is specified over the commercial tempera-
ture range of 0°C to 85°C and is available in a thermally-
enhanced 8-lead SOIC package.
FUNCTIONAL BLOCK DIAGRAM
Figure 1. General Application Circuit.
IN
OD
VCC
OVERLAP
PROTECTION
CIRCUIT
BST
DRVH
SW
DRVL
PGND
ADP3418
3
IN
VCC
ADP3418
BST
D1
DRVH
SW
DRVL
PGND
TO INDUCTOR
DELAY
OD
1V
+1V
12V
C
BST
Q1
Q2
3
–2– REV. PrC
ADP3418–SPECIFICATIONS1(VCC = 12 V, BST = 4 V to 26 V, TA = 0°C to +85°C, unless otherwise noted)
PRELIMINARY TECHNICAL DATA
Parameter Symbol Conditions Min Typ Max Units
SUPPLY
Supply Voltage Range V
CC
4.15 13.2 V
Supply Current I
SYS
BST = 12 V, IN = 0 V 5 7 mA
OD INPUT
Input Voltage High 2.0 V
Input Voltage Low 0.8 V
Input Current -1 +1 µA
Propagation Delay Time
2
tpdl
OD
See Figure 2 15 30 ns
tpdh
OD
See Figure 2 15 30 ns
PWM INPUT
Input Voltage High 2.0 V
Input Voltage Low 0.8 V
Input Current -1 +1 µA
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current V
BST
– V
SW
=12 V 1.75 3.0 Ω
Output Resistance, Sinking Current V
BST
– V
SW
=12 V 1.0 2.5 Ω
Transition Times
2
t
rDRVH
See Figure 3, V
BST
– V
SW
=12 V, 45 55 ns
C
LOAD
=3 nF
t
fDRVH
See Figure 3, V
BST
– V
SW
=12 V, 20 30 ns
C
LOAD
= 3 nF
Propagation Delay
2,3
t
pdhDRVH
See Figure 3, V
BST
– V
SW
=12 V 45 65 ns
t
pdlDRVH
V
BST
– V
SW
=12 V 15 35 ns
LOW-SIDE DRIVER
Output Resistance, Sourcing Current 1.75 3.0 Ω
Output Resistance, Sinking Current 1.0 2.5 Ω
Transition Times
2
t
rDRVL
See Figure 3, C
LOAD
= 3 nF 25 35 ns
t
fDRVL
See Figure 3, C
LOAD
= 3 nF 21 30 ns
Propagation Delay
2,3
t
pdhDRVL
See Figure 3 30 60 ns
t
pdlDRVL
See Figure 3 10 20 ns
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2
AC specifications are guaranteed by characterization, but not production tested.
3
For propagation delays, “tpdh” refers to the specified signal going high; “tpdl” refers to it going low.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
VCC ............................................................. –0.3 V to 15 V
BST ............................................................. –0.3 V to 30 V
BST to SW ................................................. –0.3 V to 15 V
S W ...................................................................–5 V to 25 V
All Other Inputs and Outputs ...... –0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range ..... 0°C to +85°C
Operating Junction Temperature Range ...0°C to +125°C
Storage Temperature Range................... –65°C to +150°C
θ
JA
.......................................................................... 123°C/W
Lead Temperature (Soldering, 10 sec) ................. +300°C
Vapor Phase (60 sec) .............................................. +215°C
Infrared (15 sec) ..................................................... +220°C
*This is a stress rating only; operation beyond these limits can cause the device to be
permanently damaged. Unless otherwise specified, all voltages are referenced to
PGND
ORDERING GUIDE
Temperature
Model Range Package
ADP3418JR 0°C to +85°C R-8 (SO-8)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3418 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
R-8
ADP3418
TOP VIEW
(Not to Scale)
BST
IN
OD
VCC
DRVH
SW
PGND
DRVL
1
2
3
8
7
6
45
–3–REV. PrC
ADP3418
PRELIMINARY TECHNICAL DATA
PIN FUNCTION DESCRIPTIONS
Pin Name Function
1 BST Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds
this bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be chosen
between 100 nF and 1 µF.
2 IN Logic-level Input. This pin has primary control of the drive outputs.
3OD Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
4 VCC Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.
5 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET.
7 S W This pin is connected to the buck-switching node, close to the upper MOSFET ’s source. It is the float-
ing return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent
turn-on of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions,
the high-low transition delay is determined at this pin.
8 DRVH Buck Drive. Output drive for the upper (buck) MOSFET.
IN
DRVH-SW
DRVL
SW
tpdlDRVL tfDRVL trDRVL
tpdlDRVH
tfDRVH
tpdhDRVH trDRVH
VTH VTH
1V
tpdhDRVL
Figure 3. Nonoverlap Timing Diagram (Timing Is Referenced to the 90% and 10% Points Unless Otherwise Noted)
Figure 2. Output Disable Timing Diagram
DRVH
OR
DRVL
tpdlOD
tpdhOD
90%
10%
OD
–4– REV. PrC
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
ADP3418
PRELIMINARY TECHNICAL DATA
8-Lead SOIC
R-8
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8º
0º
0.0196 (0.50)
0.0099 (0.25)
3
45
8
85
41
0.1968 (5.00)
0.1890 (4.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0500 (1.27)
BSC 0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10) 0.0192 (0.49)
0.0138 (0.35)
