PRELIMINARY TECHNICAL DATA Dual Boostrapped 12 V MOSFET Driver with Output Disable ADP3418 a Preliminary Technical Data FEATURES All-In-One Synchronous Buck Driver Bootstrapped High-Side Drive One PWM Signal Generates Both Drives Anticross-Conduction Protection Circuitry Output Disable Control Turns Off both MOSFETs to Float Output per Intel VRM 10 Specification FUNCTIONAL BLOCK DIAGRAM VCC BST DRVH IN APPLICATIONS Multiphase Desktop CPU Supplies Single-Supply Synchronous Buck Converters SW OVERLAP PROTECTION CIRCUIT OD GENERAL DESCRIPTION DRVL 3 ADP3418 The ADP3418 is a dual high-voltage MOSFET driver optimized for driving two N-channel MOSFETs which are the two switches in a non-isolated synchronous buck power converter. Each of the drivers is capable of driving a 3000 pF load with a 20 ns propagation delay and a 30 ns transition time. One of the drivers can be bootstrapped, and is designed to handle the high-voltage slew rate associated with floating high-side gate drivers. The ADP3418 includes overlapping drive protection (ODP) to prevent shoot-through current in the external MOSFETs. The OD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdown. PGND 12V VCC D1 ADP3418 The ADP3418 is specified over the commercial temperature range of 0C to 85C and is available in a thermallyenhanced 8-lead SOIC package. BST CBST IN DRVH Q1 SW TO INDUCTOR DELAY +1V DRVL Q2 1V OD PGND 3 Figure 1. General Application Circuit. REV. PrC 7/3/02 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c)Analog Devices, Inc., 2002 PRELIMINARY TECHNICAL DATA ADP3418-SPECIFICATIONS1 (VCC = 12 V, BST = 4 V to 26 V, T = 0C to +85C, unless otherwise noted) A Parameter Symbol Conditions SUPPLY Supply Voltage Range Supply Current VCC I SYS BST = 12 V, IN = 0 V OD INPUT Input Voltage High Input Voltage Low Input Current Propagation Delay Time2 Min Max Units 5 13.2 7 V mA 15 15 0.8 +1 30 30 V V A ns ns 0.8 +1 V V A 1.75 1.0 45 3.0 2.5 55 ns 20 30 ns 4.15 2.0 -1 tpdl OD tpdh OD See Figure 2 See Figure 2 PWM INPUT Input Voltage High Input Voltage Low Input Current 2.0 -1 HIGH-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current t rDRVH Transition Times 2 t fDRVH Propagation Delay 2,3 Typ t pdhDRVH tpdlDRVH LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current t rDRVL Transition Times 2 t fDRVL t pdhDRVL Propagation Delay 2,3 t pdlDRVL VBST - VSW =12 V VBST - VSW =12 V See Figure 3, VBST - VSW =12 V, CLOAD =3 nF See Figure 3, VBST - VSW =12 V, CLOAD = 3 nF See Figure 3, VBST - VSW =12 V VBST - VSW =12 V 45 15 65 35 ns ns See See See See 1.75 1.0 25 21 30 10 3.0 2.5 35 30 60 20 ns ns ns ns Figure Figure Figure Figure 3, CLOAD = 3 nF 3, CLOAD = 3 nF 3 3 NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2 AC specifications are guaranteed by characterization, but not production tested. 3 For propagation delays, "tpdh" refers to the specified signal going high; "tpdl" refers to it going low. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION R-8 VCC ............................................................. -0.3 V to 15 V B S T ............................................................. -0.3 V to 30 V BST to SW ................................................. -0.3 V to 15 V S W ................................................................... -5 V to 25 V All Other Inputs and Outputs ...... -0.3 V to VCC + 0.3 V Operating Ambient Temperature Range ..... 0C to +85C Operating Junction Temperature Range ... 0C to +125C Storage Temperature Range ................... -65C to +150C JA .......................................................................... 123C/W Lead Temperature (Soldering, 10 sec) ................. +300C Vapor Phase (60 sec) .............................................. +215C Infrared (15 sec) ..................................................... +220C *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. Unless otherwise specified, all voltages are referenced to PGND BST 1 ADP3418 IN 2 OD 3 VCC TOP VIEW (Not to Scale) 4 8 DRVH 7 SW 6 PGND 5 DRVL ORDERING GUIDE Model Temperature Range Package ADP3418JR 0C to +85C R-8 (SO-8) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3418 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -2- REV. PrC PRELIMINARY TECHNICAL DATA ADP3418 PIN FUNCTION DESCRIPTIONS Pin Name Function 1 BST Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds this bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be chosen between 100 nF and 1 F. 2 IN Logic-level Input. This pin has primary control of the drive outputs. 3 OD Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low. 4 VCC Input Supply. This pin should be bypassed to PGND with ~1 F ceramic capacitor. 5 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. 6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET. 7 SW This pin is connected to the buck-switching node, close to the upper MOSFET 's source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-on of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the high-low transition delay is determined at this pin. 8 DRVH Buck Drive. Output drive for the upper (buck) MOSFET. OD tpdlOD tpdhOD 90% DRVH OR DRVL 10% Figure 2. Output Disable Timing Diagram IN tpdlDRVL tfDRVL tpdlDRVH trDRVL DRVL tfDRVH tpdhDRVH DRVH-SW trDRVH VTH VTH tpdhDRVL SW 1V Figure 3. Nonoverlap Timing Diagram (Timing Is Referenced to the 90% and 10% Points Unless Otherwise Noted) REV. PrC -3- PRELIMINARY TECHNICAL DATA ADP3418 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead SOIC R-8 0.1968 (5.00) 0.1890 (4.80) 0.1574 (4.00) 0.1497 (3.80) PIN 1 8 5 1 4 0.2440 (6.20) 0.2284 (5.80) 0.0196 (0.50) 3 458 0.0099 (0.25) 0.0500 (1.27) BSC 0.0688 (1.75) 0.0098 (0.25) 0.0532 (1.35) 0.0040 (0.10) 8 0.0192 (0.49) 0.0098 (0.25) 0 0.0500 (1.27) SEATING 0.0160 (0.41) 0.0138 (0.35) PLANE 0.0075 (0.19) -4- REV. PrC