K4D28163HD-TC40 - Samsung Electronics

128M DDR SDRAM

K4D28163HD

- 1 - Rev. 1.0(Dec. 2001)

128Mbit DDR SDRAM

Revision 1.0

December 2001

2M x 16Bit x 4 Banks

Double Data Rate Synchronous RAM

Samsung Electronics reserves the right to change products or specification without notice.

128M DDR SDRAM

K4D28163HD

- 2 - Rev. 1.0(Dec. 2001)

Revision History

Revision 1.0 (December 22, 2001)

• Defined DC spec.

Revision 0.4 (December 10, 2001) - Target Spec

• Removed Full page Burst Length from the spec.

Revision 0.3 (November 6, 2001) - Target Spec

• Removed K4D28163HD-TC45/55 from the spec.

Revision 0.2 (October 25, 2001) - Target Spec

• Removed K4D28163HD-TC33/36 from the spec.

Revision 0.1 (October 12, 2001) - Target Spec

• Changed VDD from 3.3V + 10% to 3.3V + 5%

Revision 0.0 (October 10, 2001) - Target Spec

• Defined Target Specification

128M DDR SDRAM

K4D28163HD

- 3 - Rev. 1.0(Dec. 2001)

The K4D28163H is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 8 x1,048,976 words by

16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow

extremely high performance up to 1.0GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of

operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety

of high performance memory system applications.

• 3.3V + 5% power supply for device operation

• 2.5V + 5% power supply for I/O interface

• SSTL_2 compatible inputs/outputs

• 4 banks operation

• MRS cycle with address key programs

-. Read latency 3 (clock)

-. Burst length (2, 4 and 8)

-. Burst type (sequential & interleave)

• All inputs except data & DM are sampled at the positive

going edge of the system clock

• Differential clock input

• No Wrtie-Interrupted by Read Function

GENERAL DESCRIPTION

FEATURES

• 2 DQS’s ( 1DQS / Byte )

• Data I/O transactions on both edges of Data strobe

• DLL aligns DQ and DQS transitions with Clock transition

• Edge aligned data & data strobe output

• Center aligned data & data strobe input

• DM for write masking only

• Auto & Self refresh

• 64ms refresh period (4K cycle)

• 66pin TSOP-II

• Maximum clock frequency up to 250MHz

• Maximum data rate up to 500Mbps/pin

FOR 2M x 16Bit x 4 Bank DDR SDRAM

2M x 16Bit x 4 Banks Double Data Rate Synchronous RAM

with Bi-directional Data Strobe and DLL

ORDERING INFORMATION

Part NO. Max Freq. Max Data Rate Interface Package

K4D28163HD-TC40 250MHz 500Mbps/pin

SSTL_2 66pin TSOP-IIK4D28163HD-TC50 200MHz 400Mbps/pin

K4D28163HD-TC60 166MHz 333Mbps/pin

128M DDR SDRAM

K4D28163HD

- 4 - Rev. 1.0(Dec. 2001)

PIN CONFIGURATION (Top View)

PIN DESCRIPTION

CK,CK Differential Clock Input BA0, BA1 Bank Select Address

CKE Clock Enable A0 ~A11 Address Input

CS Chip Select DQ0 ~ DQ15 Data Input/Output

RAS Row Address Strobe VDD Power

CAS Column Address Strobe VSS Ground

WE Write Enable VDDQ Power for DQ’s

LDQS,UDQS Data Strobe VSSQ Ground for DQ’s

LDM,UDM Data Mask NC No Connection

RFU Reserved for Future Use

66 PIN TSOP(II)

(400mil x 875mil)

(0.65 mm Pin Pitch)

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

BA0

RAS

CAS

LDM

VDDQ

DQ7

VDD

AP/A10

BA1

LDQS

VDD

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

A11

CKE

UDM

VREF

VSSQ

DQ8

VSS

UDQS

VSS

128M DDR SDRAM

K4D28163HD

- 5 - Rev. 1.0(Dec. 2001)

INPUT/OUTPUT FUNCTIONAL DESCRIPTION

*1 : The timing reference point for the differential clocking is the cross point of CK and CK.

For any applications using the single ended clocking, apply VREF to CK pin.

Symbol Type Function

CK, CK*1 Input The differential system clock Input.

All of the inputs are sampled on the rising edge of the clock except

DQ’s and DM’s that are sampled on both edges of the DQS.

CKE Input Activates the CK signal when high and deactivates the CK signal

when low. By deactivating the clock, CKE low indicates the Power

down mode or Self refresh mode.

CS Input CS enables the command decoder when low and disabled the com-

mand decoder when high. When the command decoder is disabled,

new commands are ignored but previous operations continue.

RAS Input Latches row addresses on the positive going edge of the CK with

RAS low. Enables row access & precharge.

CAS Input Latches column addresses on the positive going edge of the CK with

CAS low. Enables column access.

WE Input Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

LDQS,(U)DQS Input/Output Data input and output are synchronized with both edge of DQS.

For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS

corresponds to the data on DQ8-DQ15.

LDM,UDM Input Data in Mask. Data In is masked by DM Latency=0 when DM is

high in burst write. For the x16, LDM corresponds to the data on

DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15.

DQ0 ~ DQ15 Input/Output Data inputs/Outputs are multiplexed on the same pins.

BA0, BA1Input Selects which bank is to be active.

A0 ~ A11 Input Row/Column addresses are multiplexed on the same pins.

Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA8.

VDD/VSS Power Supply Power and ground for the input buffers and core logic.

VDDQ/VSSQ Power Supply Isolated power supply and ground for the output buffers to provide

improved noise immunity.

VREF Power Supply Reference voltage for inputs, used for SSTL interface.

NC/RFU No connection/

Reserved for future use This pin is recommended to be left "No connection" on the device

128M DDR SDRAM

K4D28163HD

- 6 - Rev. 1.0(Dec. 2001)

BLOCK DIAGRAM (2Mbit x 16I/O x 4 Bank)

Bank Select

Timing Register

Address Register

Refresh Counter

Row Buffer

Row Decoder Col. Buffer

Data Input Register

Serial to parallel

2Mx16

Sense AMP

2-bit prefetch

Output BufferI/O Control

Column Decoder

Latency & Burst Length

Programming Register

Strobe

Gen.

CK,CK

ADDR

LCKE

CK,CK CKE CS RAS CAS WE LDM

LDMi

CK,CK

LCAS

LRAS LCBR LWE LWCBR

LRAS

LCBR

CK, CK

32 16

LWE

LDMi

x16

DQi

Data Strobe

Intput Buffer

DLL

UDM

128M DDR SDRAM

K4D28163HD

- 7 - Rev. 1.0(Dec. 2001)

• Power-Up Sequence

DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and keep CKE at low state (All other inputs may be undefined)

- Apply VDD before VDDQ .

- Apply VDDQ before VREF & VTT

2. Start clock and maintain stable condition for minimum 200us.

3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .

4. Issue precharge command for all banks of the device.

5. Issue a EMRS command to enable DLL

*1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.

*1,2 7. Issue precharge command for all banks of the device.

8. Issue at least 2 or more auto-refresh commands.

9. Issue a mode register set command with A8 to low to initialize the mode register.

*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.

*2 Sequence of 6&7 is regardless of the order.

FUNCTIONAL DESCRIPTION

Power up & Initialization Sequence

Command

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

tRP 2 Clock min.

precharge

ALL Banks 2nd Auto

Refresh Mode

Command

tRFC

1st Auto

Refresh

tRFC

EMRS MRS

2 Clock min.

DLL Reset

precharge

ALL Banks

tRP

Inputs must be

stable for 200us

200 Clock min.

2 Clock min.

CK,CK

128M DDR SDRAM

K4D28163HD

- 8 - Rev. 1.0(Dec. 2001)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,

addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for

variety of different applications. The default value of the mode register is not defined, therefore the mode register must be

written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and

WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of

address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.

Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents

can be changed using the same command and clock cycle requirements during operation as long as all banks are in the

idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2,

addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is

used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes

for various burst length, addressing modes and CAS latencies.

MODE REGISTER SET(MRS)

Address Bus

Mode Register

CAS Latency

A6A5A4Latency

0 0 0 Reserved

0 0 1 Reserved

0 1 0 Reserved

0 1 1 3

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Reserved

Burst Length

A2A1A0Burst Type

Sequential Interleave

0 0 0 Reserve Reserve

0 0 1 2 2

0 1 0 4 4

0 1 1 8 8

1 0 0 Reserve Reserve

1 0 1 Reserve Reserve

1 1 0 Reserve Reserve

1 1 1 Reserve Reserve

Burst Type

A3Type

0Sequential

1Interleave

* RFU(Reserved for future use)

should stay "0" during MRS

cycle.

MRS Cycle

Command

*1 : MRS can be issued only at all banks precharge state.

*2 : Minimum tRP is required to issue MRS command.

CK, CK

Precharge NOP NOPMRS NOPNOP

20 1 53 4 86 7

Any

NOP All Banks Command

tRP tMRD=2 tCK

BA1BA0A11 A10 A9A8A7A6A5A4A3A2A1A0

RFU 0RFU DLL TM CAS Latency BT Burst Length

BA0An ~ A0

0MRS

1EMRS

DLL

A8DLL Reset

0No

1Yes

Test Mode

A7mode

0Normal

1Test

NOP

128M DDR SDRAM

K4D28163HD

- 9 - Rev. 1.0(Dec. 2001)

The extended mode register stores the data for enabling or disabling DLL and selecting output driver

strength. The default value of the extended mode register is not defined, therefore the extened mode register

must be written after power up for enabling or disabling DLL. The extended mode register is written by assert-

ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE

already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11

and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1

and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are

required to complete the write operation in the extended mode register. The mode register contents can be

changed using the same command and clock cycle requirements during operation as long as all banks are in

the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address

pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific

codes.

A0DLL Enable

0Enable

1Disable

BA0An ~ A0

0MRS

1EMRS

EXTENDED MODE REGISTER SET(EMRS)

Address Bus

Extended

*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.

A6A1Output Driver Impedence Control

0 0 N/A Do not use

0 1 Weak 60%

1 0 N/A Do not Use

1 1 Matched Impedance 30%

RFU 1RFU D.I.C RFU D.I.C DLL

BA1BA0A11 A10 A9A8A7A6A5A4A3A2A1A0

Mode Register

128M DDR SDRAM

K4D28163HD

- 10 - Rev. 1.0(Dec. 2001)

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)

Parameter Symbol Min Typ Max Unit Note

Device Supply voltage VDD 3.135 3.3 3.465 V1

Output Supply voltage VDDQ 2.375 2.50 2.625 V1

Reference voltage VREF 0.49*VDDQ -0.51*VDDQ V2

Termination voltage Vtt VREF-0.04 VREF VREF+0.04 V3

Input logic high voltage VIH(DC) VREF+0.15 -VDDQ+0.30 V4

Input logic low voltage VIL(DC) -0.30 -VREF-0.15 V5

Output logic high voltage VOH Vtt+0.76 - - VIOH=-15.2mA

Output logic low voltage VOL - - Vtt-0.76 VIOL=+15.2mA

Input leakage current IIL -5 -5uA 6

Output leakage current IOL -5 -5uA 6

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 V

Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V

Voltage on VDD supply relative to Vss VDDQ -0.5 ~ 3.6 V

Storage temperature TSTG -55 ~ +150 °C

Power dissipation PD1.0 W

Short circuit current IOS 50 mA

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to

peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error

and an additional + 25mV for AC noise.

3. Vtt of the transmitting device must track VREF of the receiving device.

4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V.

Note :

128M DDR SDRAM

K4D28163HD

- 11 - Rev. 1.0(Dec. 2001)

DC CHARACTERISTICS

Note : 1. Measured with outputs open.

2. Refresh period is 64ms.

Parameter Symbol Test Condition Version Unit Note

-40 -50 -60

Operating Current

(One Bank Active) ICC1 Burst Lenth=2 tRC ≥ tRC(min)

IOL=0mA, tCC= tCC(min) 190 170 165 mA 1

Precharge Standby Current

in Power-down mode ICC2PCKE ≤ VIL(max), tCC= tCC(min) 5mA

Precharge Standby Current

in Non Power-down mode ICC2NCKE ≥ VIH(min), CS ≥ VIH(min),

tCC= tCC(min) 45 40 40 mA

Active Standby Current

power-down mode ICC3PCKE ≤ VIL(max), tCC= tCC(min) 15 mA

Active Standby Current in

in Non Power-down mode ICC3NCKE ≥ VIH(min), CS ≥ VIH(min),

tCC= tCC(min) 120 110 90 mA

Operating Current

( Burst Mode) ICC4 tRC ≥ tRFC(min)tRC ≥ tRFC(min)

Page Burst, All Banks activated. 350 310 280 mA

Refresh Current ICC5 tRC ≥ tRFC(min) 220 210 200 mA 2

Self Refresh Current ICC6 CKE ≤ 0.2V 2mA

Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C)

1. VID is the magnitude of the difference between the input level on CK and the input level on CK

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same

Note :

AC INPUT OPERATING CONDITIONS

Recommended operating conditions(Voltage referenced to VSS=0V, VDD=3.3V+ 5%, VDDQ=2.5V+ 5%,TA=0 to 65°C)

Parameter Symbol Min Typ Max Unit Note

Input High (Logic 1) Voltage; DQ VIH VREF+0.35 - - V

Input Low (Logic 0) Voltage; DQ VIL - - VREF-0.35 V

Clock Input Differential Voltage; CK and CK VID 0.7 -VDDQ+0.6 V1

Clock Input Crossing Point Voltage; CK and CK VIX 0.5*VDDQ-0.2 -0.5*VDDQ+0.2 V2

128M DDR SDRAM

K4D28163HD

- 12 - Rev. 1.0(Dec. 2001)

RT=50Ω

Output

CLOAD=30pF

(Fig. 1) Output Load Circuit

Z0=50ΩVREF

=0.5*VDDQ

Vtt=0.5*VDDQ

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter Symbol Value Unit

Decoupling Capacitance between VDD and VSS CDC1 0.1 + 0.01 uF

Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01 uF

1. VDD and VDDQ pins are separated each other.

All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2. VSS and VSSQ pins are separated each other

All VSS pins are connected in chip. All VSSQ pins are connected in chip.

Note :

AC OPERATING TEST CONDITIONS (VDD=3.3V±5%, TA= 0 to 65°C)

Parameter Value Unit Note

Input reference voltage for CK(for single ended) 0.50*VDDQ V

CK and CK signal maximum peak swing 1.5 V

CK signal minimum slew rate 1.0 V/ns

Input Levels(VIH/VIL)VREF+0.35/VREF-0.35 V

Input timing measurement reference level VREF V

Output timing measurement reference level Vtt V

Output load condition See Fig.1

CAPACITANCE (VDD=3.3V, TA= 25°C, f=1MHz)

Parameter Symbol Min Max Unit

Input capacitance( CK, CK )CIN1 1.0 5.0 pF

Input capacitance(A0~A11, BA0~BA1)CIN2 1.0 4.0 pF

Input capacitance

( CKE, CS, RAS,CAS, WE ) CIN3 1.0 4.0 pF

Data & DQS input/output capacitance(DQ0~DQ31)COUT 1.0 6.5 pF

Input capacitance(DM0 ~ DM3) CIN4 1.0 6.5 pF

128M DDR SDRAM

K4D28163HD

- 13 - Rev. 1.0(Dec. 2001)

AC CHARACTERISTICS

Parameter Sym-

bol -40 -50 -60 Unit Note

Min Max Min Max Min Max

CK cycle time CL=3 tCK 4.0 75.0 10 6.0 10 ns

CK high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

CK low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK

DQS out access time from CK tDQSCK -0.6 0.6 -0.7 0.7 -0.75 0.75 ns

Output access time from CK tAC -0.6 0.6 -0.7 0.7 -0.75 0.75 ns

Data strobe edge to Dout edge tDQSQ -0.4 -0.45 -0.5 ns 1

Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

CK to valid DQS-in tDQSS 0.85 1.15 0.8 1.2 0.75 1.25 tCK

DQS-In setup time tWPRES 0-0-0-ns

DQS-in hold time tWPREH 0.35 -0.3 -0.25 -tCK

DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

DQS-In high level width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 tCK

DQS-In low level width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 tCK

Address and Control input setup tIS 0.9 -1.0 -1.1 -ns

Address and Control input hold tIH 0.9 -1.0 -1.1 -ns

DQ and DM setup time to DQS tDS 0.4 -0.45 -0.5 -ns

DQ and DM hold time to DQS tDH 0.4 -0.45 -0.5 -ns

Clock half period tHP tCLmin

tCHmin -tCLmin

tCHmin -ns 1

Data output hold time from DQS tQH tHP-0.4 -tHP-0.45 -tHP-0.5 -ns 1

Note 1 :

- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data

strobe and all data associated with that data strobe are coincidentally valid.

- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst

case

output vaild window even then the clock duty cycle applied to the device is better than 45/55%

- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle

variation and replaces tDV

- tQHmin = tHP-X where

. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)

. X=A frequency dependent timing allowance account for tDQSQmax

128M DDR SDRAM

K4D28163HD

- 14 - Rev. 1.0(Dec. 2001)

AC CHARACTERISTICS (II)

K4D28163HD-TC40

Frequency Cas Latency tRC tRFC tRAS tRCD tRP tRRD tDAL Unit

250MHz ( 4.0ns ) 314 16 95528tCK

200MHz ( 5.0ns ) 312 14 84427tCK

166MHz ( 6.0ns ) 310 12 73326tCK

(Unit : Number of Clock)

AC CHARACTERISTICS (I)

Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM

Parameter Symbol -40 -50 -60 Unit Note

Min Max Min Max Min Max

Row cycle time tRC 14 -12 -10 -tCK

Refresh row cycle time tRFC 16 -14 -12 -tCK

Row active time tRAS 9100K 8100K 7100K tCK

RAS to CAS delay tRCD 5-4-3-tCK

Row precharge time tRP 5-4-3-tCK

Row active to Row active tRRD 2-2-2-tCK

Last data in to Row precharge

@Normal Precharge tWR 3-2-2-tCK 1

Last data in to Row precharge

@Auto Precharge tWR_A 3-3-3-tCK 1

Last data in to Read command tCDLR 2-2-2-tCK 1

Col. address to Col. address tCCD 1-1-1-tCK

Mode register set cycle time tMRD 2-2-2-tCK

Auto precharge write recovery

+ Precharge tDAL 8-7-6-tCK

Exit self refresh to read com- tXSR 200 -200 -200 -tCK

Power down exit time tPDEX 1tCK+tIS -1tCK+tIS -1tCK+tIS -ns

Refresh interval time tREF 15.6 -15.6 -15.6 -us

K4D28163HD-TC50

Frequency Cas Latency tRC tRFC tRAS tRCD tRP tRRD tDAL Unit

200MHz ( 5.0ns ) 312 14 8 4 4 2 7 tCK

166MHz ( 6.0ns ) 310 12 7 3 3 2 6 tCK

K4D28163HD-TC60

Frequency Cas Latency tRC tRFC tRAS tRCD tRP tRRD tDAL Unit

166MHz ( 6.0ns ) 310 12 7 3 3 2 6 tCK

128M DDR SDRAM

K4D28163HD

- 15 - Rev. 1.0(Dec. 2001)

0 1 2 3 4 5 6 7 8

BAa

tRCD

ACTIVEA ACTIVEB WRITEA WRITEB

13 14 15 16 17 18 19 20 21

BAa BAb

Ca Cb

BAa

9 10 11 12

PRECH

BAa

Normal Write Burst

(@ BL=4) Multi Bank Interleaving Write Burst

(@ BL=4)

BAa

BAb

tRAS

tRC

tRP

tRRD

COMMAND

DQS

CK, CK

A8/AP

ADDR

(A0~A7,

BA[1:0]

A9,A10)

ACTIVEA WRITEA

Da0 Da1 Da2 Da3

Simplified Timing @ BL=4

Db0 Db1 Db3

Da0 Da1 Da2 Da3 Db2

128M DDR SDRAM

K4D28163HD

- 16 - Rev. 1.0(Dec. 2001)

PACKAGE DIMENSIONS (66pin TSOP-II)

Units : Millimeters

0.30±0.080.65TYP(0.71)

22.22±0.10

0.125

(0.80)

10.16±0.10

0×~8×

#1 #33

#66 #34

(1.50)

0.65±0.08

1.00±0.10

1.20MAX

(0.50) (0.50)(10.76)

11.76±0.20

(10×)(10×)

+0.075

-0.035

(0.80)

0.10 MAX

0.075 MAX

[ ]

0.05 MIN

(10×)

(R0.15)

0.210±0.05

0.665±0.05

(R0.15)

(4×)

(R0.25)

0.45~0.75

0.25TYP

NOTE

1. ( ) IS REFERENCE

2. [ ] IS ASS’Y OUT QUALITY