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LCD Module Technical Specification
T-51431L016J-FW-P-AA
Table of Contents
1. Applications............................................................................................................................................... 2
2. Features...................................................................................................................................................... 2
3. Mechanical Specifications................................................................................................................. 2
4. Mechanical Drawing of panel........................................................................................................... 3
5. Input / Output Term inals..................................................................................................................... 4
6. Pixel arrangement and input connector pin No..............................................................6
7. Absolute Maximum Ratings...............................................................................................................7
8. Electrical Char acteristics.....................................................................................................................7
9. Power Sequence.................................................................................................................................. 18
10. Optical Char act er ist ics.................................................................................................................... 18
11. Handing Caut ions.............................................................................................................................. 21
12. Reliability................................................................................................................................................ 22
13. Indication of Lot Number Label................................................................................................... 22
14. Block Diag ram..................................................................................................................................... 23
Checked by (Des ign Engineering Div.)
Checked by (Qual i ty Assurance Div. )
Prepared by (Production Div.)
Revision History
Rev. Date Page Comment
Jan 1, 2001
OPTREX
First Edition
Final Revisi on
******
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1. Application
This technical specification applies to 1.6” color TFT-LCD panel. The 1.6” color TFT LCD
panel is designed for camcorder, digital camera application and other electronic products
which require hig h quality f lat panel displays.
2. Features
. Compatible with NTSC or PAL system
. High Resolut ion56,160 Dots
. Opt imu m Viewing Dir ection: 6 o’clock
. Up/Down and Left / Right I m age Reversion
3. Mechanical Specifications
Parameter Specifications Unit
Screen Size 1.6 (diag onal) inch
Surf ace Treatm ent Anti-Glar e
Display Format 240×234 dot
Active Area 32.4 (H)×24.336 (V) mm
Dot Pitch 0.135 (H)×0.104 (V) mm
Pixel Config uration Delta
Outline Dim ension 45.9 (W)×38. 6 ( H)×5.9 (D) mm
Weight 18±3g
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4. Mechanical Drawing of panel:
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5.Input / Output Terminals
Pin No Symbol I/O Description Remark
1 STH1 I/O Start pulse for sour ce driver Note 5-1
2AV
SS I Analog GND for sour ce dr iver
3AV
DD I Analog power input f o r sour ce dr iver Note 5-2
4V
BI Video Input B
5V
GI Video Input G
6V
RI Video Input R Note 5-4
7V
SS I Digit al G ND
8V
DD I Digital power input Note 5-3
9 CPH1 I Sampling and shift clock f or source driver
10 CPH2 I Sampling and shift clock f o r sour ce dr iver
11 CPH3 I Sampling and shift clock f o r sour ce dr iver
12 STH2 I/O Start pulse for sour ce dr iver Not e 5-1
13 Q2H I Video input rotat ion cont rol
14 INH I Output enable for sour ce dr iver
15 R/L I Left /Right Cont rol f or source driver Note 5-1
16 VCOM I Common electr ode voltage
17 VCOM I Common electr ode voltage Note 5-4
18 XOE I Output enable for gate dr iver
19 CPV I Clock input for gate dr iver
20 U/D I Up/Down Control f o r gate dr iver
21 DIO2 I/O Vertical start pulse
22 DIO1 I/O Vertical start pulse Note 5-5
23 VGL I Gate off voltage(alt er native every 1-H) Note 5-4
24 VEE I Gate driver negative voltage Note 5-6
25 VSS IGND
26 VCC I Logic power for g ate driver Note 5-3
27 VGH I Gate on voltag e Note 5-7
28 NC - No connection -
Note 5-1STH1, ST H2 and R/ L mode
R/L STH1 STH2 Remark
High(VDD) Input Output Left to rig ht
Low(0 Volt.) Output Input Right t o left
Note 5-2 : AVDD = +5V (Typ.)
Note 5-3 : VDD, VCC = +5Vor+3.3V (Typ.)
Note 5-4 : VCOM = 6VPP.
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i) Phase of t he video signal input and VCOM
The relat ion bet ween these values could ref er to 8-1 O per at ing condition.
Fig.1
ii) Liquid cr ystal transmission of the video signal input , V COM and timing
VCOM
H Level L Level
Video Signal Input Maximum Black White
Video Signal Input Minimum White Black
White : maximum t ransmission / Black : minimum transmission
Note 5-5 : DI O1, DIO2 and U/D mode
U/D DIO1 DIO2 Remarks
Hi (VDA) Input Output Down to up
Low (0 V.) Output Input Up to down
Note 5-6 : VEE = -15V (Typ.).
Note 5-7 : VGH = 15V (Typ.).
100% white
pedestal
Composite Video
Signal
R,G,B Video
Signal
(
V
R
,
V
G
,
V
B
)
V
COM
1H1H
V
GL
V
GL AC
V
GL DC
V
COM DC
V
COM AC
V
i AC
V
i DC
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6. Pixel arrang em ent and input connector pin NO .
B RBGRBGR G
R GRBGRBG B
B RBGRBGR G
R GRBGRBG B
B RBGRBGR G
R GRBGRBG B
124023923865432
1
234
233
4
3
2
128
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7. Absolute Maximum Ratings:
The followings are maximum values , which if exceeded, may cause f aulty operation or
damage t o t he unit. GND = 0 V, Ta = 25
Parameter Symbol MIN. MAX. Unit Remark
Supply Voltage for Source Driver Analog AVDD -0.3 +7 V
Digital VDD -0.3 +7
Supply Voltage Positive V GH -0.3 +45 V
for Gate Driver Negative VGL -23 +0.3 V
VGH VGL +15 +40 V
Analog input voltage VVideo -0.3 +7.3 V Notes:7-1
Storag e Temperat ur e -20 +70
Operation Temperature 0 +60 Notes:7-2
Notes 7-1 : Analog Input Voltage means VR,VG,VB.
Notes 7-2 : O per ating T em per ature define that cont r ast , response time, other display
optical character ar e Ta=+25.
8. Electrical Characteristics
8-1) Oper at ing conditions
Item Symbol Min. Typ. Max. Unit Remark
+3.0 +3.3 +3.6 V 3.3V operating
Vcc VDD +4.5 +5.0 +5.5 V 5.0V operating
AVDD +4.5 +5.0 +5.5 V
VGH +14.5 +15.0 +15.5 V
VEE -14.5 -15.0 -15.5 V
VGLAC -+6-V
P-P AC component
of VGL
Power supply
VGLDC -11.5 -12.0 -12.5 V DC component
of VGL
ViAC - +4.0 +4.6 V AC component
Video signal
( VR , VG , VB ) ViDC - +2.5 - V DC com ponent
VCAC -+6.0-V
P-P AC component
of Vcom
Vcom VCDC +0.9 +1.0 +1.1 V AC component
H level VIH 0.7VDD --V
L level VIL - - 0.3VDD VNote 8-1
Note 8-1 : STH1,STH2,CPH1,CPH2,CPH3,Q2H,INH,CPV,XOE,DIO1,DIO2.
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8-2) Curr ent consum ption ( GND=AVSS=0V )
Ta= 25
Parameter Symbol Condition Min. Typ. Max. Unit Remark
IGH VGH=15V - 0.015 0.02 mA
IGL VGL=-12V - 0.09 0.15 mA VGL center voltage
ICC VCC,VAA=5V - 0.09 0.15 mA
IADD VADD=5V - 0.73 0.9 mA
IEE VEE=-15V - 0.09 0.15 mA
Current for
driver
IDD VDD=5V - 0.2 0.25 mA
8-3) Back light dr iving & Power Consumption
Pin No Symbol Description Remark
1 VL1 Input te r m inal ( Hi voltage side)
2 VL2 Input terminal (Low voltage side) Note 8-2
Note 8-2Low voltage side of back light inverter connect s with Gr ound of inverter cir cuits.
Ta= 25
Parameter Symbol Min. Typ. Max. Unit Remark
Lamp voltage VL145 170 195 Vrms IL=3mA
Lamp current IL3mA
Lamp f r equency PL- 35 95 KHz Note 8- 3
Kick-off voltage( 25)Vs - - 500 Vrms
Kick-off voltage( 0)Vs - - 750 Vrms
Note 8-3 : The wave form of lamp driving voltage should be as closed to a perf ect SIN wave
as possible.
Power Consumption
Ta= 25
Parameter Symbol Conditions TYP. MAX Unit Remark
LCD Panel Power Consumption 8 8.5 mW Note 8- 4
Backlig ht Lamp Power Consumption 0.51 0.55 W Note 8-5
Total Power Consumpt ion 0.518 0.56 W
Note 8-4 : The power consumption for back light is not included.
Note 8-5 : Backlight lamp power consumption is calculated by IL×VL.
8-4) Input / Output Connect or
A) LCD Module Connector
FFC Down Connector
28 Pins
Pitch0.5 mm
B) Backlight Connecto r
JST BHR-03VS-1
Pin No.3
Pitch4 mm
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8-5) Tim ing Character istics Of Input Signals
Characteristics Symbol Min. Typ. Max. Unit Remark
1Field Scanning Period t1V - 262. 5 - H
1Line Scanning Period t 1H - 63. 5 - µs
Source Driver Oper at ing Freq uency fhc 0.5 1.57 2.5 MHz
Signal Sampling Pulse Width tchw 400 637 2000 ns
Signal Sampling Pulse Delay tchd 190.6 212.3 233 ns tchd 12,23
Signal Sampling Pulse Width(H) tchwh - 316.5 - ns
Signal Sampling Pulse Delay(L) tchwl - 316.5 - ns
Source Start Signal Pulse Width tshw - 637 - ns
Source Start Signal Setup T im e tshset 10 - - ns
Source Start Signal Hold Time tshhld 20 - - ns
Source Output Enable Pulse Widt h t ohw 2 4 - µs
Source Start Signal Rising Time tss - 9.8 - µs
Video Input Sig nal Start Point tvs - 10.0 - µs
Phase Difference Bet ween OEH&CPV toc 1.5 2. 3 - µs
Gate Clock Period tcvw 10 63.5 - µs
Gate Clock Pulse Width(H) tcvwh 1 0 31.7 48 µs
Gate Clock Pulse Widt h( L) tcvwl 10 31.7 48 µ s
Gate Star t Signal Pulse Width t svw 5 63. 5 126** µs
Gate Start Sig nal Set up Time tsvset 5 53. 2 - µs
Gate Start Signal Hold Time tsvhld 5 10.3 - µs
Phase Difference Bet ween OEH&ST H tosp - 4 - µs
Phase Difference Bet ween SYNC&OEH tohs - 1.4 - µs
Gate Output Enable Pulse Width toev - 2.5 - µs
Vcom Delay Time tdcom - - 3 µs
RGB Delay Time tdRGB - - 2 µs
Vertical Display Start tsv - 3 - tH
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8-6)Sig nal Timing Waveforms
234567 19202122 23 265 266 267 268 269 286285284283282
(22H~256H) (285H~519H)
t1V=262.5H
1st display period 2nd display period
tsvw
HD
VD
Xout
DIO
Fig. 8-1 Vertical Start Line for NTSC
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624 625 12 3 4 25 26 27 28 29 312313314315316340339338337336
(28H~299H) (339H~611H)
t1V=312.5H
1st display period 2nd display period
tsvw
HD
VD
Xout
DIO
Fig. 8-1 Vertical Start Line for PAL
*
*
o
d
d
f
i
e
l
d
:
S
c
a
n
l
i
n
e
s
1
4
n
+
6
1
4
n
+
1
2
(
n
=
2
,
3
,
4
.
.
)
a
r
e
n
o
t
d
i
s
p
l
a
y
e
d
.
e
v
e
n
f
i
e
l
d
:
S
c
a
n
l
i
n
e
s
1
4
n
+
1
2
1
4
n
+
2
0
(
n
=
2
,
3
,
4
.
.
)
a
r
e
n
o
t
d
i
s
p
l
a
y
e
d
.
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t1H=100 CPHclk=63.5u sec
Tshw
12310099 80
Invalidity data Validity data Invalidity data
128198
STH1,2
CPH1
R,G,B
Fig. 8-2 Horizontal Start Pixel
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HD
STH1,2
INH
CPV
XOE
Q2H
VCOM
VR,G,B
tss tshw
tosp
tohwtohs
tcvw
tcvwh
toc
toev
t
DCOM
t
DRGB
tvs
tcvwl
Fig. 8-3 Detail Horizontal Timing
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tcvw
tcvwh tcvwl
tsvset tsvhld
tsvw
CPV
DIO 1,2
Fig. 8-5 Vertical Shift Clock Timing
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tchw
tchwh tchwl
tchd12
tchd23
tshset tshhld
tshw
R1 (B1)
G1 (R1)
R2 (B2)
G2 (R2)
B1 (G1) B2 (G2)
CPH 1
CPH 2
CPH 3
STH 1,2
R3 (B3)
Fig. 8-4 Sampling Clock Timing
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Vertical tim ing (From up to down)
Display on panel first line
tsv
HD
VD
DIO2
Q2H
VCOM
(Odd field)
VCOM
(Even field)
Fig. 8-6(a) Vertical Timing (From Up to Down)
BRG
RGB
V(R,G,B)
ODD FIELD
V(R,G,B)
EVEN FIELD
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Vertical tim ing (From down to up)
Display on panel first line
VCOM
(Odd field)
VCOM
(Even field)
HD
VD
DIO1
Q2H
tsv
Fig. 8-6(b) Vertical Timing (From Down to Up)
BRG
RGB
V(R,G,B)
EVEN FIELD
V(R,G,B)
ODD FIELD
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9. Power Sequence(Volt age source)
The Power Sequence only effect by VCC,VSS,VDD,VEE and VGH, the others do not care.
10msT1<T2
1) 0ms<T3T4≦10ms
10.Optical Characteristics
10-1)Specification Ta = 25
Parameter Symbol Condition MIN. TYP. MAX. Unit Remarks
Viewing Horizontal θ±45 ±50 deg
Angle Vertical θ(to 12
o’clock) CR10 10 15 deg Note 10-3
θ(to 6
o’clock) 30 35 deg
Contrast Rat io CR 110 150 Note 10-1
Response time Rise Tr θ=0°30 ms
Fall Tf θ=0°50 ms Note 10-4
Transmission Ratio R 7.4 8 8.5 %
Brightness 200 250 cd/m2Note 10-2
White
Chromaticity X
yθ=0°0.250
0.260 0.300
0.310 0.350
0.360 Note 10-2
Lamp Life Time +2510,000 hr
Luminance when LCD is Whit e
Note 10-1 : CR Lum inance when LCD is Black
Contrast Rat io is m easur ed in optimum com m on elect r ode voltage.
The test configur ations of contrast ratio see section 10-2.
V
SS
(0V)
V
GH
ON
OFF OFF
V
DD
,V
CC
V
EE
T1
T2
T3
T4
Logic signal
V
COM
,V
GL
RGB-Video signal
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Note 10-2 : 1. Topcon BM-7(fast) luminance met er 1 field of view is used in the testing ( after
20~30 minutes operation) .
2.Lamp current : 3 mA
3.Inverter model : TDK- 347.
Note 10-3The definition of viewing angle diag rams :
ABC
observer
θ
3
6
9
12
LCD panel
φ
φ
: Viewing direction
θ
: Viewing angle
normal
(
θ = 0)
Note 10-4 : The def init ions of response time:
100%
90%
10%
0%
White White
Brightness
Black
Tr Tf
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10-2) T est Config ur ation
y LCD Display
y R, G, B Waveform of Pattern A at Te sting P oint
y R, G, B Waveform of Pattern B at Te sting P oint
500mm
BM-7(fast)
LCD
Backlight
R,G,B signal
Pattern
generator
input
Pattern A Pattern B
Testing Point Testing Point
16ms 16ms
16ms 16ms
Cau t ion: 1 . E n viro nm ent al ill u minat ion1 lux
2. Before test CR, Vco m voltage must
be adjusted ca refully to get the best
CR.
Vcom
RGB
waveform
RGB
waveform
Vcom
Vb=TBDV +/- 0.2V
Vw=TBDV +/- 0.2V
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11. Handling Cautions
11-1) Mounting of module
a) Please power off the module when you connect the input/output connector.
b) Please connect the ground pattern of the inverter circuit surely. If the
connection is not perfect, some following problems may happen possibly.
1.Th e noise from the backlight un it will increase.
2.The output from in verter circuit will be un stable.
3.In some cases a part of m odule will heat.
c) Polarizer which is made of soft material and susceptible to flaw must be
    handled carefully.
d) Protective film (Laminator) is applied on surface to protect it against
scratches and dirt. It is recommended to peel off the laminator before use
and taking care of static electricity.
11-2) Precautions in mounting
a) When metal part of the TFT-LCD module (shielding lid and rear case) is
soiled, wipe it with soft dry cloth.
b) Wipe off water drops or finger grease immediately. Long contact with water
may cause discoloration or spots.
c) TFT-LCD module uses glass which breaks or cracks easily if dropped or
bumped on hard surface. Please handle with care.
d) Since CMOS LSI is used in the module. So take care of static electricity
and earth yourself when handling.
11-3) Others
a) Do not expose the module to direct sunlight or intensive ultraviolet rays for
many Hours.
b) Store the module at a room temperature place.
a) The voltage of beginning electric discharge may over the normal voltage
because of leakage current from approach conductor by to draw lump read
lead line around.
b) If LCD panel breaks, it is possibly that the liquid crystal escapes from the
panel.
Avoid putting it into eyes or mouth. When liquid crystal sticks on hands,
clothes or feet. Wash it out immediately with soap.
c) Observe all other precautionary requirements in handling general electronic
components.
d) Please adjust the voltage of common electrode as material of attachment
by 1 module.
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12. Reliability
No. Test Item Test Condit ion
1 High Tem per ature Stor age Test Ta = +70 , 240 hrs
2 Low Temperature Storage Test Ta = -20, 240 hrs
3 Low Temperature Operation Test Ta = 0 , 240 hrs
4High T em perature & High Humidity
Operation Test Ta = +60, 95%RH, 240 hrs
5Therm al Cycling Test
(non-operating) -25 +25℃→ +70, 200 Cycles
30 min 5min 30 min
6Vibration T est
(non-operating)
Frequency10 ~ 55 HZ
Amplitude1. 0 m m
Sweep time: 11 mins
Test Per iod: 6 Cycles for each direct ion of X, Y, Z
7Shock Test
(non-operating)
100G, 6ms
Direction: ±X, ±Y, ±Z
Cycle: 3 times
8Electrostat ic Discharge Test
(non-operating)
150pF, 330Ω
Air:±15KV; Cont act: ±8KV
10 times/point, 4 points/panel face
Ta: am bient temperature
[Criteria]
Under the display quality test conditions with normal operat ion st ate, ther e should be no
change which may affect pract ical display f unct ion.
13. Indication of Lot Num ber Label
a) Indicated cont ent s of the label
Lot number
Internal number
Contents of lot number : SB9—STC O EM product
5th—Production year : 19999, 2000A, 20011……..
6th—Production month : 1, 2, 3, ….9, A, B, C
7th~10th—Serial numbers : 0001~9999
OOO-OOOOOO
xxxxxxxxxxxx
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14. Block Diagram
LCD Panel
H Driver
(Source)
Back-light
28 PIN Input
Inverter
V Driver
(Gate)