Features
•Configurations:
– Can be configured as a combination of keys and input/output lines
•Number of Keys:
–2 to 6
•Number of I/O Lines:
– 7, configurable for input or output, with PWM control for LED driving
•Technology:
– Patented spread-spectrum charge-transfer (direct mode)
•Key Outline Sizes:
– 6 mm x 6 mm or larger (panel thickness dependent); widely different sizes and
shapes possible
•Layers Required:
–One
•Electrode Materials:
– Etched copper
–Silver
–Carbon
– Indium Tin Oxide (ITO)
•Panel Materials:
– Plastic
–Glass
– Composites
– Painted surfaces (low particle density metallic paints possible)
•Panel Thickness:
– Up to 10 mm glass (electrode size dependent)
– Up to 5 mm plastic (electrode size dependent)
•Key Sensitivity:
– Individually settable via simple commands over serial interface
•Interface:
–I
2C-compatible slave mode (100 kHz). Discrete detection outputs
•Power:
– 1.8V to 5.5V
•Package:
– 28-pin 4 x 4 mm MLF RoHS compliant IC
•Signal Processing:
– Self-calibration
– auto drift compensation
– noise filtering
– Adjacent Key Suppression™
•Applications:
– Mobile appliances
QTouch™
6-channel
Sensor IC
AT42QT1060
9505E–AT42–02/09
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AT42QT1060
1. Pinout and Schematic
1.1 Pinout Configuration
1.2 Pin Descriptions
Table 1-1. Pin Listing
Pin Name Type Description If Unused, Connect To...
1 SNS1K IO To Cs capacitor and to key Leave open
2 SNS2K IO To Cs capacitor and to key Leave open
3 VDD P Positive power pin
4 VSS P Ground power pin
5 IO5 IO IO Port Pin 5 Leave open and set as output
6 IO6 IO IO Port Pin 6 Leave open and set as output
7 SNS3K IO To Cs capacitor and to key Leave open
8 SNS4K IO To Cs capacitor and to key Leave open
9 SNS5K IO To Cs capacitor and to key Leave open
10 SNS0 IO To Cs Capacitor Leave open
11 SNS1 IO To Cs Capacitor Leave open
12 SNS2 IO To Cs Capacitor Leave open
13 SNS3 IO To Cs Capacitor Leave open
14 SNS4 IO To Cs Capacitor Leave open
15 SNS5 IO To Cs Capacitor Leave open
16 VDD P Positive power pin
17 VDD P Positive power pin
SNS0K
IO4
IO3
RST
SNS4K
SNS0
SNS2
SNS1K
SNS2K
VSS
VDD
IO5
VSS
IO0
IO1
1
2
3
4
5
6
715
16
17
18
19
20
21
28 27 26 25 24 23 22
8914
13
12
11
10
QT1060
IO6
SNS3K
SNS3
SNS4
VDD
IO2
SNS5K
SNS1
SNS5
VDD
CHG
SDA
SCL
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AT42QT1060
18 VSS P Ground power pin
19 IO0 IO IO Port Pin 0 Leave open and set as output
20 IO1 IO IO Port Pin 1 Leave open and set as output
21 IO2 IO IO Port Pin 2 Leave open and set as output
22 CHG OD Change line Leave open
23 SDA OD I2C-compatible Data line Resistor to Vdd or
Vss only in standalone mode
24 SCL OD I2C-compatible Clock Line Resistor to Vdd or
Vdd only in standalone mode
25 RST I Reset, active low Vdd
26 IO3 IO IO Port Pin 3 Leave open and set as output
27 IO4 IO IO Port Pin 4 Leave open and set as output
28 SNS0K IO To Cs capacitor and to key Leave open
I Input only IO Input and output
OOutput only, push-pull PGround or power
OD Open drain output
Table 1-1. Pin Listing (Continued)
Pin Name Type Description If Unused, Connect To...
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AT42QT1060
1.3 Schematic
Figure 1-1. Typical Circuit
Note: In some systems it may be desirable to connect RST to the master reset signal.
Suggested regulator manufacturers:
• Torex (XC6215 series)
• Seiko (S817 series)
• BCDSemi (AP2121 series)
Re Figure 1-1 check the following sections for component values:
•Section 3.1 on page 9: Cs capacitors (Cs0 – Cs5)
•Section 3.2 on page 9: Series resistors (Rs0 – Rs5)
•Section 3.5 on page 10: Voltage levels
•Section 5.4 on page 16: SDA, SCL pull-up resistors (not shown)
•Section 3.3 on page 10: LED traces
SNS4
KEY 4
VDD
14
13
12
3
KEY 3
KEY 2
CHG
SDA
SCL
23
24 I C Clock in
2-compatible
Cs4
Rs4
Rs3
Rs2
Cs3
Cs2
QT1060
I C-compatible Data
2
8
7
2
22
11
KEY 1
Rs1
Cs1
1
VDD
VDD
VDD
6
5
27
26
IO6
IO3
IO4
IO5
1617
SNS4K
SNS3K
SNS3
SNS2K
SNS2
SNS1K
SNS1
Keep these parts
close to the IC
Note: Bypass capacitor to be tightly wired
between Vdd and Vss. Follow
regulator manufacturer for input and output
capacitors.
recommendations
from
Vunreg Voltage Reg
Note: The central pad on the underside of the chip
is a Vss pin and should be connected to ground.
18
VSS
Change
100k
VDD
Rchg
25 RST
100nF
CB1
4
VSS
IO Port
pins
SNS5
KEY 5
15 Cs5
Rs5
9
SNS5K
10
KEY 0
Rs0
Cs0
28
SNS0K
SNS0
21
20
19 IO0
IO1
IO2
SDA
SCL
23
24
VDD
Standalone Mode
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AT42QT1060
2. Overview
2.1 Introduction
The AT42QT1060 (QT1060) is a digital burst mode charge-transfer (QT™) capacitive sensor
driver designed specifically for mobile phone applications. The device can sense from two to six
keys; up to four keys can be disabled by not installing their respective sense capacitors (Cs). It
also has up to seven configurable input/output lines, with Pulse Width Modulation (PWM) for
LED driving.
This device includes all signal processing functions necessary to provide stable sensing under a
wide variety of changing conditions, and the outputs are fully debounced. Only a few external
parts are required for operation.
The QT1060 modulates its bursts in a spread-spectrum fashion in order to heavily suppress the
effects of external noise, and to suppress RF emissions.
2.2 Keys
The QT1060 can have a minimum of two keys and a maximum of six keys. These can be
constructed in different shapes and sizes. See “Features” on page 1 for the recommended
dimensions.
Unused keys should be disabled by removing the corresponding Cs and Rs components and
connecting the SNS pins as shown in the “If Unused” column of Table 1-1 on page 2. The
unused keys are always pared from the burst sequence in order to optimize speed. See
Section 7. on page 25 about setting up the keys.
2.3 Standalone Mode
The QT1060 can operate in a standalone mode where an I2C-compatible interface is not
required. To enter standalone mode, connect SDA to Vss and SCL to Vdd before powering up
the QT1060.
In standalone mode the default start-up values are used except for the I/O mask (Address 23).
The I/O mask is configured so that all the IOs are outputs (IO mask = 0x7F). This means that
key detection is reported via their respective IOs.
2.4 I/O Lines
2.4.1 Overview
There is an input/output (I/O) port consisting of seven lines that can be individually programmed
as inputs or outputs. They can be either a digital type or PWM. The PWM level can be set to 256
possible values and is common to all lines.
The I/O lines are normally initialized as inputs. However, if an I2C-compatible interface is not
used and the SDA and SCL pins are connected to Vss and Vdd respectively, then the I/O lines
are initialized as outputs (see Section 2.3).
The outputs can also be linked to either the detection channels or the output register to allow the
outputs to be either user controlled or to indicate detection. These options can be set in the pin
control masks (see Table 6-1 on page 17).
Unused I/O lines should be disabled by connecting as shown in the “If Unused” column of
Table 1-1 on page 2. See Section 7. on page 25 about setting up the I/O lines.
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AT42QT1060
2.4.2 I/O Mask
A 1 in any bit position of this mask sets the corresponding pin to an output. If a bit is 0, the pin is
an input and the function of the PWM, detect and active state masks will not matter for this pin.
The level of the input pins is reflected in the input Status register. Changes to the logic levels on
the inputs cause the CHG line to be asserted.
2.4.3 PWM Mask
A 1 in any bit position in this mask sets the corresponding pin to operate in PWM mode when its
user output buffer is active and configured as an output. A zero sets the pin in digital mode. The
PWM value is set in the PWM register that is writable via I2C-compatible communication.
2.4.4 Detection Mask
A 1 in any bit position in this mask sets the corresponding pin to be controlled by the status
register. If the pin is configured as an output, it is asserted automatically if there is a detection on
the corresponding sensor channel. A zero in any bit sets the pin to be controlled by the user
output buffer, allowing the user to control the pins directly.
2.4.5 Active Level Mask
A 1 in any bit position in this mask sets the corresponding pin to be active high if configured as
an output. A zero sets the pin to be active low.
2.5 Acquisition/Low Power Modes (LP)
There are several different acquisition modes. These are controlled via the Low Power (LP)
mode byte (see Section 6.12 on page 20) which can be written to via I2C-compatible
communication.
LP mode controls the intervals between acquisition measurements. Longer intervals consume
lower power but have increased response time. During calibration and during the detect
integrator (DI) period, the LP mode is temporarily set to LP mode 1 for a faster response.
The QT1060 operation is based on a fixed cycle time of approximately 16 ms. The LP mode
setting indicates how many of these periods exist per measurement cycle. For example, If LP
mode = 1, there is an acquisition every cycle (16 ms). If LP mode = 3, there is an acquisition
every 3 cycles (48 ms) etc.
SLEEP mode (LP mode = 0) is available for minimum current drain. In this mode, the device is
inactive, with the device status being held as it was before going to sleep, and no measurements
are carried out.
LP settings above mode 32 (512 ms) result in slower thermal drift compensation and should be
avoided in applications where fast thermal transients occur.
If LP mode = 255 the device operates in Free-run mode. In this mode the device will not enter LP
mode between measurements. The device continuously performs measurements one after
another, resulting in the fastest response time but the highest power consumption.
2.6 Adjacent Key Suppression (AKS) Technology
The device includes Atmel’s patented Adjacent Key Suppression (AKS) technology, to allow the
use of tightly spaced keys on a keypad with no loss of selectability by the user.
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AT42QT1060
There can be one AKS group, implemented so that only one key in the group may be reported
as being touched at any one time. A key with a higher delta signal dominates and pushes a key
with a smaller delta out of detect. This allows a user to slide a finger across multiple keys with
only the dominant key reporting touch.
The keys which are members of the AKS group can be set via the AKS mask (see Section 6.15
on page 22). Keys outside the group may be in detect simultaneously.
For maximum flexibility there is no automatic key recalibration timeout on key detection. The
user should issue a recalibration command if the key has been in detect for too long, for
example for more than 30 seconds (see Figure 2.9).
2.7 Change Line
The Change line (see CHG in Figure 1-1 on page 4) signals when there is a change in state in
the Detection or Input status bytes and is active low. It is cleared (allowed to float high) when the
host reads the status bytes.
If the status bytes change back to their original state before the host has read the status bytes
(for example, a touch followed by a release), the CHG line will be held low. In this case, a read to
any memory location will clear the CHG line.
The CHG line is open-drain and should be connected via a 100k resistor to Vdd. It is
necessary for minimum power operation as it ensures that the QT1060 can sleep for as long as
possible. Communications wake up the QT1060 from sleep causing a higher power
consumption if the part is randomly polled.
The keys enabled by the key bit mask or a change in the Input port status cause a key change
interrupt (see Table 6-1 on page 17). Create a guard channel by removing that key from the key
mask and including it in the AKS mask. Touching the guard channel does not cause an interrupt.
The key and AKS masks are set by using the mask commands (see Table 6-1 on page 17).
2.8 Types of Reset
2.8.1 External Reset
An external reset logic line can be used if desired, fed into the RST pin. However, under most
conditions it is acceptable to tie RST to Vdd.
2.8.2 Soft Reset
The host can cause a device reset by writing a nonzero value to the reset byte. This soft reset
triggers the internal watchdog timer on a ~16 ms interval.
• After ~16 ms the device resets and wakes again.
• After a further 30 ms initialization period the device begins responding to its I2C-compatible
slave address.
• After another ~80 ms the device asserts the CHG line to indicate it is ready for touch sensing.
The device NACKs any attempts to communicate with it during the first 30 ms of its initialization
period.
After CHG goes low, the device calibrates the sensing channels. When complete, the CHG pin is
set low once again.
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AT42QT1060
2.9 Calibration
The command byte can force a recalibration at any time by writing a nonzero value to the
calibration byte. This can be useful to clear out a stuck key condition after a prolonged period of
uninterrupted detection.
When the device recalibrates, it also autosenses which keys are enabled by examining the burst
length of each electrode. If the burst length is either too short (if there is a missing or open Cs
capacitor) or too long (a Cs capacitor is shorted), the key is ignored until the next calibration.
The count of the number of currently enabled keys is found in the status response byte. This
number can change after a CAL command; for example, if a Cs capacitor is intermittent.
2.10 Guard Channel
The device has a guard channel option, which allows any key, or combination of keys, to be
configured as a guard channel to help prevent false detection. Guard channel keys should be
more sensitive than the other keys (physically bigger or larger Cs), subject to burst length
limitations (see Section 2.11.3).
With guard channel enabled, the designated key(s) is connected to a sensor pad which detects
the presence of touch and overrides any output from the other keys using the chip’s AKS
feature. The guard channel option is enabled by an I2C-compatible command.
To enable a guard channel the relevant key should be removed from the key mask (see Table 6-
1 on page 17). In addition, the guard channel needs to be included within the AKS mask with the
other keys for the guard function to operate. Note that a detection on the guard channel does not
cause a change request.
With the guard channel not enabled, all the keys work normally.
Figure 2-1. Guard Channel Example
2.11 Signal Processing
2.11.1 Detect Threshold
The device detects a touch when the signal has crossed a threshold level and remained there
for a specified number of counts (see Section 6.11 on page 20). This can be altered on a
key-by-key basis using the key threshold I2C-compatible commands.
Guard channel
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AT42QT1060
2.11.2 Detect Integrator
The device features a fast detection integrator counter (DI filter), which acts to filter out noise at
the small expense of slower response time. The DI filter requires a programmable number of
consecutive samples confirmed in detection before the key is declared to be touched. There is
also a fast DI on the end of the detection (see Section 6.20 on page 23). The fast DI will not be
applied at the start of a detection if a detection on any other channel has already been declared.
2.11.3 Burst Length Limitations
In a balanced system common signals are regarded as thermal shifts and are removed by the
relative referencing drifting, if enabled. This means that the burst lengths must be similar. This
can be checked by reading the reference values (Address 52 – 63) and making sure that they
are similar. The absolute maximum difference is that the maximum value of reference is less
than three times the minimum value amongst all the channels. It is recommended having the
burst lengths (references) as close together as possible, through better routing and layout.
For example, if the keys have references of 250, 230, 220, 240, 200 and 210, this is acceptable.
If the keys have references of 250, 230, 220, 240, 200 and 710, the efficiency of the relative
referencing drifting will be affected. The last key’s (710) layout should be changed or relative
referencing be disabled. The closer the references are in value, the better the relative
referencing drifting performs.
If only normal drifting is enabled, the burst lengths can have bigger variations.
The normal operating limit of burst lengths is between 16 and 1536 counts. A value out of these
limits causes the respective key to be disabled and not measured until a calibration. Signal value
for an out-of-limit key is zero.
3. Wiring and Parts
3.1 Cs Sample Capacitors
Cs0 – Cs5 are the charge sensing sample capacitors; normally they are identical in nominal
value. The optimal Cs values depend on the thickness of the panel and its dielectric constant.
Thicker panels require larger values of Cs. Typical values are 2.2 nF to 10 nF.
The value of Cs should be chosen so that a light touch on a key produces a reduction of ~10 –
20 in the key signal value (see Section 6.22 on page 23). The chosen Cs value should never be
so large that the key signals exceed ~1000, as reported by the chip in the debug data.
The Cs capacitors must be X7R or PPS film type, for stability. For consistent sensitivity, they
should have a 10 percent tolerance. Twenty percent tolerance may cause small differences in
sensitivity from key to key and unit to unit. If a channel is not used, the Cs capacitor may be
omitted.
3.2 Rs Resistors
Series resistors Rs (Rs0 – Rs5) are inline with the electrode connections and should be used to
limit electrostatic discharge (ESD) currents and to suppress radio frequency (RF) interference.
They should be approximately 4.7 kto 20 k each.
Although these resistors may be omitted, the device may become susceptible to external noise
or radio frequency interference (RFI). For details of how to select these resistors see the
Application Note QTAN0002, Secrets of a Successful QTouch™ Design, downloadable from the
Touch Technology area of Atmel’s website, www.atmel.com.
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AT42QT1060
3.3 LED Traces and Other Switching Signals
Digital switching signals near the sense lines induce transients into the acquired signals,
deteriorating the SNR performance of the device. Such signals should be routed away from the
sensing traces and electrodes, or the design should be such that these lines are not switched
during the course of signal acquisition (bursts).
LED terminals which are multiplexed or switched into a floating state, and which are within, or
physically very near, a key (even if on another nearby PCB) should be bypassed to either Vss or
Vdd with at least a 10 nF capacitor. This is to suppress capacitive coupling effects which can
induce false signal shifts. The bypass capacitor does not need to be next to the LED, in fact it
can be quite distant. The bypass capacitor is noncritical and can be of any type.
LED terminals which are constantly connected to Vss or Vdd do not need further bypassing.
3.4 PCB Cleanliness
All capacitive sensors should be treated as highly sensitive circuits which can be influenced by
stray conductive leakage paths. QT devices have a basic resolution in the femtofarad range; in
this region, there is no such thing as “no clean flux”. Flux absorbs moisture and becomes
conductive between solder joints, causing signal drift and resultant false detections or transient
losses of sensitivity or instability. Conformal coatings trap in existing amounts of moisture which
then become highly temperature sensitive.
The designer should specify ultrasonic cleaning as part of the manufacturing process, and in
cases where a high level of humidity is anticipated, the use of conformal coatings after cleaning
to keep out moisture.
3.5 Power Supply
See Section8.2 on page26 for the power supply range. If the power supply fluctuates slowly
with temperature, the device tracks and compensates for these changes automatically with only
minor changes in sensitivity. If the supply voltage drifts or shifts quickly, the drift compensation
mechanism is not able to keep up, causing sensitivity anomalies or false detections.
The usual power supply considerations with QT parts apply to the device. The power should be
clean and come from a separate regulator if possible. However, this device is designed to
minimize the effects of unstable power, and except in extreme conditions should not require a
separate Low Dropout (LDO) regulator.
See underneath Figure 1-1 on page 4 for suggested regulator manufacturers.
It is assumed that a larger bypass capacitor (like1 µF) is somewhere else in the power circuit; for
example, near the regulator.
To assist with transient regulator stability problems, the QT1060 waits 500 µs any time it wakes
up from a sleep state (i.e. in SLEEP and LP modes) before acquiring, to allow Vdd to fully
stabilize.
Caution: A regulator IC shared with other logic can result in erratic operation and is
not advised.
A single ceramic 0.1 µF bypass capacitor, with short traces, should be placed very
close to the power pins of the IC. Failure to do so can result in device oscillation,
high current consumption, erratic operation etc.
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AT42QT1060
4. I2C-compatible Bus Operation
4.1 Interface Bus
More detailed information about the I2C-compatible bus protocol is available from
www.i2C-bus.org. Devices are connected onto the I2C-compatible bus as shown in Figure 4-1.
Both bus lines are connected to Vdd via pull-up resistors. The bus drivers of all I2C-compatible
devices must be open-drain type. This implements a wired-AND function which allows any and
all devices to drive the bus, one at a time. A low level on the bus is generated when a device
outputs a zero.
Figure 4-1. I2C-compatible Interface Bus
4.2 Transferring Data Bits
Each data bit transferred on the bus is accompanied by a pulse on the clock line. The level of the
data line must be stable when the clock line is high; The only exception to this rule is for
generating START and STOP conditions.
Table 4-2. I2C-compatible Bus Specifications
Parameter Unit
Address space 7-bit
Maximum bus speed (SCL) 100 kHz
Hold time START condition 4 µs minimum
Setup time for STOP condition 4 µs minimum
Bus free time between a STOP and START condition 4.7 µs minimum
Rise times on SDA and SCL 1 µs maximum
Vdd
Device 1 Devic e 2 Device 3 Device n R1 R2
SDA
SCL
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AT42QT1060
Figure 4-3. Data Transfer
4.3 START and STOP Conditions
The host initiates and terminates a data transmission. The transmission is initiated when the
host issues a START condition on the bus, and is terminated when the host issues a STOP
condition. Between START and STOP conditions, the bus is considered busy. As shown below,
START and STOP conditions are signaled by changing the level of the SDA line when the SCL
line is high.
Figure 4-4. START and STOP Conditions
4.4 Address Packet Format
All address packets are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit
and an acknowledge bit. If the READ/WRITE bit is set, a read operation is performed, otherwise
a write operation is performed. When the device recognizes that it is being addressed, it will
acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. An address packet consisting of
a slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively.
The most significant bit of the address byte is transmitted first. The address sent by the host
must be consistent with that selected with the option jumpers.
Figure 4-5. Address Packet Format
SDA
SCL
Data Stable Data Stable
Data Change
SDA
SCL
START STOP
SDA
SCL
Addr MSB Addr LSB R/W ACK
START
12 789
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AT42QT1060
4.5 Data Packet Format
All data packets are 9 bits long, consisting of one data byte and an acknowledge bit. During a
data transfer, the host generates the clock and the START and STOP conditions, while the
Receiver is responsible for acknowledging the reception. An acknowledge (ACK) is signaled by
the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA
line high, a NACK is signaled.
4.6 Combining Address and Data Packets Into a Transmission
A transmission consists of a START condition, an SLA+R/W, one or more data packets and a
STOP condition. The wired-ANDing of the SCL line is used to implement handshaking between
the host and the device. The device extends the SCL low period by pulling the SCL line low
whenever it needs extra time for processing between the data transmissions.
Holding down either SCL or SDA for clock stretching or any other purpose will slow down the
operation of the QT2160. If SCL or SDA is continuously held low for more than ~12ms, this will
be deemed as a error condition and the I2C-compatible unit reset.
Note: Each write or read cycle must end with a STOP condition. The QT2160 may not respond
correctly if a cycle is terminated by a new START condition.
Figure 4-7 shows a typical data transmission. Note that several data bytes can be transmitted
between the SLA+R/W and the STOP.
Figure 4-6. Data Packet Format
Figure 4-7. Packet Transmission
Data Byte
Next Data Byt
e
12 789 12 789
Da
ta MSB Data LSB ACK
Data Byte
STOP
SDA
SCL
Addr MSB Addr LSB R/W ACK
START SLA+R/W
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AT42QT1060
5. I2C-compatible Communications
5.1 I2C-compatible Protocol
5.1.1 Protocol
The I2C-compatible protocol is based around access to an address table (see Figure 6-1 on
page 17) and supports multibyte reads and writes. The maximum clock rate is 100 kHz.
5.1.2 Signals
The I2C-compatible interface requires two signals to operate:
•SDA - Serial Data
•SCL - Serial Clock
A third line, CHG, is used to signal when the device has seen a change in the status byte:
•CHG: Open-drain, active low when any capacitive key in the key mask has changed state or
any input line has changed state since the last I2C-compatible read. After reading the two
status bytes, this pin floats (high) again if it is pulled up with an external resistor. If the status
bytes change back to their original state before the host has read the status bytes (for
example, a touch followed by a release), the CHG line will be held low. In this case, a read to
any memory location will clear the CHG line.
5.1.3 Clock Stretching
The device has an internal monitor that resets its I2C-compatible hardware if either
I2C-compatible line is held low, without the other line changing, for more than about 14 ms. It is
important that no other device on the bus clock stretches for 14 ms, otherwise the monitor will
reset the I2C-compatible hardware and transfers with the chip may be corrupted.
If the device is configured to run in stand-alone mode, the monitor will be turned off.
5.2 I2C-compatible Address
There is one preset I2C-compatible address of 0x12. This is not changeable.
5.3 Data Read/Write
5.3.1 Writing Data to the Device
The sequence of events required to write data to the device is shown next.
Table 5-1. Description of Write Data Bits
Key Description
S Start condition
SLA+W Slave address plus write bit
A Acknowledge bit
SLA+W MemAddress
AASData A P
Host to Device Device to Host
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AT42QT1060
1. The host initiates the transfer by sending the START condition
2. The host follows this by sending the slave address of the device together with the
WRITE bit.
3. The device sends an ACK.
4. The host then sends the memory address within the device it wishes to write to.
5. The device sends an ACK.
6. The host transmits one or more data bytes; each is acknowledged by the device.
7. If the host sends more than one data byte, they are written to consecutive memory
addresses.
8. The device automatically increments the target memory address after writing each data
byte.
9. After writing the last data byte, the host should send the STOP condition.
Note: the host should not try to write beyond address 255 because this is the limit of the device’s
internal memory address.
5.3.2 Reading Data From the Device
The sequence of events required to read data from the device is shown next.
1. The host initiates the transfer by sending the START condition
2. The host follows this by sending the slave address of the device together with the
WRITE bit.
3. The device sends an ACK.
4. The host then sends the memory address within the device it wishes to read from.
5. The device sends an ACK.
6. The host must then send a STOP and a START condition followed by the slave address
again but this time accompanied by the READ bit.
7. The device returns an ACK, followed by a data byte.
8. The host must return either an ACK or NACK.
a. If the host returns an ACK, the device subsequently transmits the data byte from
the next address. Each time a data byte is transmitted, the device automatically
increments the internal address. The device continues to return data bytes until the
host responds with a NACK.
b. If the host returns a NACK, it should then terminate the transfer by issuing the
STOP condition.
MemAddress Target memory address within device
Data Data to be written
P Stop condition
Table 5-1. Description of Write Data Bits
Key Description
SLA+W MemAddressAAS S SLA+R A
AP
Ho st to Device
Device to Host
P
A
/A
Data 1 Data 2
Data n
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9505E–AT42–02/09
AT42QT1060
9. The device resets the internal address to the location indicated by the memory address
sent to it previously. Therefore, there is no need to send the memory address again
when reading from the same location.
5.4 SDA, SCL
The I2C-compatible bus transmits data and clock with SDA and SCL respectively. They are
open-drain; that is I2C-compatible master and slave devices can only drive these lines low or
leave them open. The termination resistors (not shown) pull the line up to Vdd if no
I2C-compatible device is pulling it down.
The termination resistors commonly range from 1 k to 10 kand should be chosen so that the
rise times on SDA and SCL meet the I2C-compatible specifications (1 µs maximum).
Standalone mode: if I2C-compatible communications are not required, then standalone mode
can be enabled by connecting SDA to Vss and SCL to Vdd. See Section 2.3 on page 5 for more
information.
17
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AT42QT1060
6. Setups
6.1 Introduction
The device calibrates and processes signals using a number of algorithms specifically designed
to provide for high survivability in the face of adverse environmental challenges. User-defined
Setups are employed to alter these algorithms to suit each application. These Setups are loaded
into the device over the I2C-compatible serial interfaces.
Table 6-1. Internal Register Address Allocation
Address Use R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 Chip ID R Major ID (= 3) Minor ID (= 1)
1 Version R Version number
2 Minor version R Minor version number
3 Reserved Reserved
4 Detection status R Calibrating Res'd Key5 Key4 Key3 Key2 Key1 Key0
5 Input port status R Res'd Input 6 Input 5 Input 4 Input 3 Input 2 Input 1 Input 0
6 – 11 Reserved Reserved
12 Calibrate R/W Writing a nonzero value forces a calibration
13 Reset R/W Writing a nonzero value forces a reset
14 Drift Option R/W Res'd Res'd Res'd Res'd Res'd Res'd Res'd DRIFT
15 Positive Recalibration
Delay R/W MSB LSB
16 NTHR key 0 R/W MSB LSB
17 NTHR key 1 R/W MSB LSB
18 NTHR key 2 R/W MSB LSB
19 NTHR key 3 R/W MSB LSB
20 NTHR key 4 R/W MSB LSB
21 NTHR key 5 R/W MSB LSB
22 LP mode R/W MSB LSB
23 I/O mask R/W MSB IO6 IO5 IO4 IO3 IO2 IO1 IO0
24 Key mask R/W CAL Res'd Key 5 Key 4 Key 3 Key 2 Key 1 Key 0
25 AKS mask R/W Res'd Res'd Key 5 Key 4 Key 3 Key 2 Key 1 Key 0
26 PWM mask R/W Res'd IO6 IO5 IO4 IO3 IO2 IO1 IO0
27 Detection mask R/W Res'd IO6 IO5 IO4 IO3 IO2 IO1 IO0
28 Active level mask R/W Res'd IO6 IO5 IO4 IO3 IO2 IO1 IO0
29 User output buffer R/W Res'd IO6 IO5 IO4 IO3 IO2 IO1 IO0
30 DI R/W MSB LSB
31 PWM level R/W MSB LSB
32 – 39 Reserved Reserved
18
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AT42QT1060
6.2 Address 0: Chip ID
MAJOR ID: Reads back as 3
MINOR ID: Reads back as 1
6.3 Address 1: Device Version Number
DEVICE VERSION NUMBER: this is the 8-bit firmware version number (0x03).
6.4 Address 2: Minor Version Number
MINOR VERSION NUMBER: this is the 8-bit minor firmware revision number (0x00).
6.5 Address 4: Detection Status
CAL: a 1 indicates that the QT1060 is currently calibrating.
KEY0–5: bits 0 to 5 indicate which keys are in detection, if any; touched keys report as 1,
untouched or disabled keys report as 0.
40 – 51 Key 0 – 5 Signal R
52 – 63 Key 0 – 5 Reference R
Note: Res'd = Reserved; only write zero to these bits.
Table 6-2. Chip ID
Address b7 b6 b5 b4 b3 b2 b1 b0
0 MAJOR ID MINOR ID
Table 6-1. Internal Register Address Allocation (Continued)
Address Use R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Table 6-3. Device Version Number
Address b7 b6 b5 b4 b3 b2 b1 b0
1 DEVICE VERSION NUMBER
Table 6-4. Minor Version Number
Address b7 b6 b5 b4 b3 b2 b1 b0
2 MINOR VERSION NUMBER
Table 6-5. Detection Status
Address b7 b6 b5 b4 b3 b2 b1 b0
4 CAL Reserved KEY5 KEY4 KEY3 KEY2 KEY1 KEY0
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AT42QT1060
6.6 Address 5: Input Port Status
INPUT 0 – 6: these bits indicate the state of the IO lines that are configured as inputs;
1indicating logic 1 on the input, 0 indicating logic 0. The bits corresponding to any keys
configured as outputs read as 0.
6.7 Address 12: Calibrate
Writing any nonzero value into this address triggers the device to start a calibration cycle. The
CAL flag in the status register is set when begun and cleared when the calibration has finished.
6.8 Address 13: Reset
Writing any nonzero value to this address triggers the device to reset.
6.9 Address 14: Drift Option
DRIFT: there are two types of drift option: normal and relative referencing.
If DRIFT = 0, relative referencing and normal drift are enabled.
If DRIFT = 1, only normal drift is enabled.
Relative referencing compensates for fast signal drifts that are common to all keys. This mode is
suitable if the keys are placed close to each other and have closely matched burst lengths (see
Section 2.11.3 on page 9). Normal drifting is also carried out but at a slower rate compared to
the relative referencing drift rate.
Default: 1 (relative referencing Off)
Table 6-6. Input Port Status
Address b7 b6 b5 b4 b3 b2 b1 b0
5 Reserved INPUT 6 INPUT 5 INPUT 4 INPUT 3 INPUT 2 INPUT 1 INPUT 0
Table 6-7. Calibrate
Address b7 b6 b5 b4 b3 b2 b1 b0
12 Writing a nonzero value forces a calibration
Table 6-8. Reset
Address b7 b6 b5 b4 b3 b2 b1 b0
13 Writing a nonzero value forces a reset
Table 6-9. Drift Option
Address b7 b6 b5 b4 b3 b2 b1 b0
14 DRIFT
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AT42QT1060
6.10 Address 15: Positive Recalibration Delay
POSITIVE RECALIBRATION DELAY: If any key is found to have a significant drop in
capacitance, i.e. an “away from touch” signal, then this is deemed to be an error condition. If this
condition persists for more than the Positive Recalibration Delay (PRD) period, then an
automatic recalibration is carried out on all keys.
The condition that the error is triggered on depends on the drift compensation mode. If relative
referencing drifting is enabled (DRIFT = 0), then an “away from touch” delta of more than four
counts triggers the error. If only normal mode drifting is enabled (DRIFT = 1), then an “away from
touch” delta of more than 75 percent of the NTHR triggers the error.
The PRD is incremented according to the current LP mode setting (the duration is equal to the
cycle time multiplied by the PRD value).
Default: ~7 ms x 40 = 280 ms (in free-run mode)
6.11 Address 16 – 21: NTHR Keys 0 – 5
NTHR Keys 0 – 5: these 8-bit values set the threshold value for each key to register a detection.
Default: 10 counts
6.12 Address 22: LP Mode
LP Mode: this 8-bit value determines the number of 16 ms intervals between key
measurements. Longer intervals between measurements yield lower power consumption at the
expense of slower response to touch.
Table 6-10. Positive Recalibration Delay
Address b7 b6 b5 b4 b3 b2 b1 b0
15 POSITIVE RECALIBRATION DELAY
Table 6-11. NTHR Keys 0 – 5
Address b7 b6 b5 b4 b3 b2 b1 b0
16–21 MSB LSB
Table 6-12. LP Mode
Address b7 b6 b5 b4 b3 b2 b1 b0
22 MSB LSB
21
9505E–AT42–02/09
AT42QT1060
A value of zero causes the device to enter SLEEP mode where no measurements are
performed.
A value of 255 causes the device to enter Free-run mode where measurements are continuously
performed without entering a low power mode between measurements. This provides the fastest
response time but also the highest power consumption.
Default: 2 (32 ms between key acquisitions)
6.13 Address 23: I/O Mask
IO0 – 6: these bits control the direction of the IO pins. A 1 sets the pin as an output, a 0 as an
input. See Section 6.24 on page 24 for I/O register precedence and example usage.
Default: 0 (all IO's are set as inputs, when using the I2C-compatible mode)
(all IO's are set as outputs (0x7F), when using the standalone mode)
6.14 Address 24: Key Mask
CAL: this bit controls whether the CAL bit causes a CHG transition.
KEY0 – 5 (Key Mask): these bits control whether a change in the corresponding bit in the
detection status register generates a transition on the CHG line. A 1 allows the status bit to
cause a CHG request, a 0 stops the corresponding bit from causing a CHG request.
Default: 0xBF (all bits create a CHG request)
LP7 –0Mode
0SLEEP
116 ms
232 ms
348 ms
464 ms
...254 4.064s
255 Free-run
Table 6-13. I/O Mask
Address b7 b6 b5 b4 b3 b2 b1 b0
23 Reserved IO6 IO5 IO4 IO3 IO2 IO1 IO0
Table 6-14. Key Mask
Address b7 b6 b5 b4 b3 b2 b1 b0
24 CAL Reserved KEY5 KEY4 KEY3 KEY2 KEY1 KEY0
22
9505E–AT42–02/09
AT42QT1060
6.15 Address 25: AKS Mask
KEY0 – 5 (AKS Mask): these bits control which keys are included in the AKS group. A 1 means
the corresponding key is included in the AKS group and may only go into detect when it has the
largest signal change of any key in the group. A 0 means that it is excluded and can go into
detect whenever its threshold is passed.
Default: 0x00 (no keys are within the AKS group)
6.16 Address 26: PWM Mask
IO0 – 6 (PWM Mask): these bits control which IOs that are configured as outputs, and its user
output buffer activated, will output a PWM signal. A 1 means the output generates a PWM
signal, a 0 means the output generates a logic level. The active level of the output (both logical
and PWM) is determined by the Active level mask. See Section 6.24 on page 24 for I/O register
precedence and example usage.
Default: 0x00 (PWM is off on all IOs)
6.17 Address 27: Detection Mask
IO0 – 6 (Detection Mask): these bits control which IOs that are configured as outputs will be
controlled by their corresponding capacitive key. A 1 means the output “n” generates an active
output when key “n” is detecting a touch. A 0 means that the output is controlled by the output
buffer. See Section 6.24 on page 24 for I/O register precedence and example usage.
Default: 0x3F (all IOs are controlled by key status)
6.18 Address 28: Active Level Mask
IO0 – 6 (Active Level Mask): these bits control the active logic level for the IOs that are
configured as outputs. A 1 means the output generates an active high output, a 0 means that the
output is active low. See Section 6.24 for IO register precedence and example usage.
Default: 0 (all IOs are active low output)
Table 6-15. AKS Mask
Address b7 b6 b5 b4 b3 b2 b1 b0
25 Reserved Reserved KEY5 KEY4 KEY3 KEY2 KEY1 KEY0
Table 6-16. PWM Mask
Address b7 b6 b5 b4 b3 b2 b1 b0
26 Reserved IO6 IO5 IO4 IO3 IO2 IO1 IO0
Table 6-17. Detection Mask
Address b7 b6 b5 b4 b3 b2 b1 b0
27 Reserved IO6 IO5 IO4 IO3 IO2 IO1 IO0
Table 6-18. Active Level Mask
Address b7 b6 b5 b4 b3 b2 b1 b0
28 Reserved IO6 IO5 IO4 IO3 IO2 IO1 IO0
23
9505E–AT42–02/09
AT42QT1060
6.19 Address 29: User Output Buffer
IO0 – 6 (User Output Buffer): these bits control the output level for the IO's that are configured
as outputs. A 1 means the output generates an active output, a 0 means that the output is
inactive. See Section 6.24 on page 24 for I/O register precedence and example usage.
Default: 0 (all IO's inactive)
6.20 Address 30: Detection Integrator
DETECTION INTEGRATOR: this 8-bit value controls the number of consecutive measurements
that must be confirmed as having passed the key threshold before that key is registered as
being in detect. A value of zero should not be used.
Default: 3
6.21 Address 31: PWM Level
PWM LEVEL: this 8-bit value controls the duty cycle of the PWM output signal. A value of 255
means the output is permanently active.
Default: 128 (50:50 duty cycle)
6.22 Address 40 – 51: Key Signal
KEY SIGNAL: addresses 40 – 51 allow key signals to be read for each key, starting with key 0.
There are two bytes of data for each key. These are the key’s 16-bit key signals which are
accessed as two 8-bit bytes, stored LSB first. These addresses are read-only.
Table 6-19. User Output Buffer
Address b7 b6 b5 b4 b3 b2 b1 b0
29 Reserved IO6 IO5 IO4 IO3 IO2 IO1 IO0
Table 6-20. Detection Integrator
Address b7 b6 b5 b4 b3 b2 b1 b0
30 MSB DETECTION INTEGRATOR LSB
Table 6-21. PWM Level
Address b7 b6 b5 b4 b3 b2 b1 b0
31 MSB PWM LEVEL LSB
Table 6-22. Key Signal
Address b7 b6 b5 b4 b3 b2 b1 b0
40 LSB OF KEY SIGNAL FOR KEY 0
41 MSB OF KEY SIGNAL FOR KEY 0
42 – 51 LSB/MSB OF KEY SIGNAL FOR KEYS 1 – 5
24
9505E–AT42–02/09
AT42QT1060
6.23 Address 52 –63: Reference Data
REFERENCE DATA: addresses 52 – 63 allow reference data to be read for each key, starting
with key 0. There are two bytes of data for each key. These are the key’s 16-bit reference data
which is accessed as two 8-bit bytes, stored LSB first. These addresses are read-only.
6.24 Mask Precedence
Table 6-24 gives the order of priority for the settings in the mask inputs/outputs. The settings in
the left-most column have the highest priority, those in the second-left have the next priority etc.
If two or more settings are incompatible then the setting in the left-hand column overrides the
other. The right-most column, I/O Function, specifies the expected result.
Note: X = don’t care (can be a 1 or a 0)
Table 6-23. Reference Data
Address b7 b6 b5 b4 b3 b2 b1 b0
52 LSB OF REFERENCE DATA FOR KEY 0
53 MSB OF REFERENCE DATA FOR KEY 0
54 – 63 LSB/MSB OF REFERENCE DATA FOR KEYS 1 – 5
Table 6-24. Input/Output Mask Precedence
I/O Mask
(bit n)
Detection Mask
(bit n)
PWM Mask
(bit n)
Active Level Mask
(bit n)
User Reg
(bit n)
QTouch Key
(channel n)
I/O Function
(I/O n)
0 X X X X X Digital Input
1 0 0 0 0 X Output - Vdd
1 0 0 0 1 X Output - 0V
1 0 0 1 0 X Output - 0V
1 0 0 1 1 X Output - Vdd
1 0 1 0 0 X Output - Vdd
10101XPWM Output
1 0 1 1 0 X Output - 0V
10111XPWM Output
1 1 0 0 X Untouched Output - Vdd
1 1 0 0 X Touched Output - 0V
1 1 0 1 X Untouched Output - 0V
1 1 0 1 X Touched Output - Vdd
1 1 1 0 X Untouched Output - Vdd
1 1 1 0 X Touched PWM Output
1 1 1 1 X Untouched Output - 0V
1 1 1 1 X Touched PWM Output
25
9505E–AT42–02/09
AT42QT1060
7. Setting Up Procedures
S et the num ber of k ey s required by
leav ing t he S N S pins unc onnec t ed in
unus ed k ey s .
D et erm ine w het her a c hange in t he
c orres ponding bit in the det ec t ion
s t atus regis ter generates a trans ition
on the CHG line.
[Address 24: Key Mask]
D etermine w hich key s are in the AKS
group.
[Address 25: AKS Mask]
D et ermi ne the num ber of
m eas urement s t hat m us t be
c onfirm ed as hav ing pas s ed t he k ey
thres hold bef ore t hat key is regis t ered
as being in detec t.
[Addres s 30: D etection Integrator]
To Set Up Keys
Tune t he s ens it iv ity of the k ey s by
adjus t ing the v alue of the s am pling
c apac it or , Cs and t he negativ e
threshold (NTHR)
[A ddres s 16 – 21: N T H R]
D et erm ine the direc tion of the I /O
lines. I f any line s are unus ed, s et
them t o be out puts and leav e t hem
unconnected.
[Address 23: I/O M as k]
Det erm ine whic h I/O s t hat are
c onfi gured as out puts will be
c ontrolled by t heir corres ponding
capacitive key.
[A ddres s 27: D et ec t ion M as k]
To S et U p I/O Li nes
Det erm ine whic h I/O s t hat are
c onf igured as out put s w il l out put a
P WM s ignal.
[Address 26: PW M Mask]
D et ermi ne the ac t iv e logic lev el f or the
I /O s that are c onf igured as out puts .
[Addres s 28: A c t iv e Lev el M as k]
D eterm ine the output lev el for the I /Os
t hat are c onfigured as output s .
[Addres s 29 : U s er Output Buffer ]
D et erm ine the dut y c y c le of the P WM
output s ignal.
[ Addres s 31 : P WM Lev el ]
26
9505E–AT42–02/09
AT42QT1060
8. Specifications
8.1 Absolute Maximum Specifications
8.2 Recommended Operating Conditions
8.3 DC Specifications
Vdd -0.5 to +6V
Max continuous pin current, any control or drive pin ±10 mA
Short circuit duration to ground, any pin infinite
Short circuit duration to Vdd, any pin infinite
Voltage forced onto any pin -0.6V to (Vdd + 0.6) Volts
CAUTION: Stresses beyond those listed under Absolute Maximum Specifications may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or other conditions beyond those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum specification
conditions for extended periods may affect device reliability.
Operating temp -40oC to +85oC
Storage temp -55oC to +125oC
Vdd +1.8V to 5.5V
Supply ripple+noise ±25 mV
Cx load capacitance per key 2 to 20 pF
Vdd = 3.3V, Cs = 10nF, load = 5 pF, 32 ms default sleep, Ta = recommended range, unless otherwise noted
Parameter Description Minimum Typical Maximum Units Notes
Vil Low input logic level – – 0.2Vdd V
Vih High input logic level 0.6Vdd – – V
Vol Low output voltage – – 0.5 V 4 mA sink
Voh High output voltage Vdd - 0.7V – – V 1 mA source
Iil Input leakage current – – ±1 µA
Ar Acquisition resolution – 8 – bits
27
9505E–AT42–02/09
AT42QT1060
8.4 AC Specifications
Cs = 10nF, Cx = 5 pF, Rs = 10k
LP Mode Idd (µA) at Vdd =
5V 3.3V 1.8V
0 (SLEEP) 2.48 1.8 1.1
1 (16 ms) 1745 1135 403
2 (32 ms) 1615 1065 373
4 (64 ms) 1545 1030 360
8 (128 ms) 1510 1010 351
16 (256 ms) 1500 1000 348
32 (512 ms) 1485 995 346
64 (1024 ms) 1475 992 345
Parameter Description Minimum Typical Maximum Units Notes
TRResponse time DI setting
x 16 ms –LP mode + (DI setting x
16 ms) ms Under host control
FQT Sample frequency 162 180 198 kHz Modulated
spread-spectrum (chirp)
TD
Power-up delay to
operate/calibration time –<230 –ms Can be longer if burst is
very long.
FI2C I2C-compatible clock rate – – 100 kHz –
Reset pulse width 5 – – µs –
28
9505E–AT42–02/09
AT42QT1060
8.5 Mechanical Dimensions
Note: The central pad on the underside of the MLF chip should be connected to ground. Do
not run any tracks underneath the body of the chip, only ground.
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
A
28M1
9/7/06
28M1, 28-pad, 4 x 4 x 1.0 mm Body, Lead Pitch 0.45 mm,
2.4 mm Exposed Pad, Micro Lead Frame Package (MLF)
SIDE VIEW
Pin 1 ID
BOTTOM VIEW
TOP VIEW
Note: The terminal #1 ID is a Laser-marked Feature.
D
E
e
K
A1
C
A
D2
E2
y
L
1
2
3
b
1
2
3
0.45 COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.80 0.90 1.00
A1 0.00 0.02 0.05
b 0.17 0.22 0.27
C 0.20 REF
D 3.95 4.00 4.05
D2 2.35 2.40 2.45
E 3.95 4.00 4.05
E2 2.35 2.40 2.45
e 0.45
L 0.35 0.40 0.45
y 0.00 – 0.08
K 0.20 – –
R 0.20
29
9505E–AT42–02/09
AT42QT1060
8.6 Marking
There are two possible types of chip marking.
8.7 Part Number
8.8 Moisture Sensitivity Level (MSL)
1
28
Pin 1 I D
LTCODE Chip Traceabilit y
Code
1060
AT
Program week code number 1 -52 where:
A = 1, B = 2.. .Z = 26
then using the under s c ore
A = 27...Z = 5 2
Abbreviation of Par t
number;
AT
42QT
1060
-MMU
1
28
Pin 1 ID
Part num b er;
AT42QT1060-MMU
AT42
LTCODE
Chip
Traceability
Code
-MMU
QT1060
Part Number Description
AT42QT1060-MMU 28-pin 4 x 4 mm MLF RoHS compliant IC
MSL Rating Peak Body Temperature Specifications
MSL3 260oC IPC/JEDEC J-STD-020
30
9505E–AT42–02/09
AT42QT1060
Revision History
Revision Number History
Revision A – September 2008 Initial Release for code revision 3.0
Revision B – October 2008 Minor amendments to burst length limitations
Revision C – November 2008 Minor amendments to improve clarity
Revision D – December 2008 Chip ID updated
Revision E – February 2009 Additional information on I2C-compatible interface added
31
9505E–AT42–02/09
AT42QT1060
Notes
9505E–AT42–02/09
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