MB90097-PFV - Fujitsu Limited

DS04-28825-5Ea

FUJITSU MICROELECTRONICS

DATA SHEET

2001.6

ASSP For Screen Display Control

CMOS

ON-Screen Display Controller

MB90097

■DESCRIPTION

The MB90097 is the on-screen display controller for displaying text and graphics on the TV screen. Since it has

a three-channel output control function, small package, and low voltage requirement for operation, it is suitable

for on-screen display on video equipment such as camera-integrated VTRs.

The MB90097 provides a display screen made up of 28 characters by 12 lines, capable of displaying 512 different

characters each consisting of 12 × 18 dots. The display functions of the MB90097 includes a wealth of character

qualifying functions such as character background shading (shadow casting) and individual character size setting,

supporting 16-color display for each character. They also include the line background, screen background, and

sprite character display functions, enabling the screen to be displayed in a variety of configurations. The integrated

font ROM contains 512 different character patterns all of which can be set by the user.

■FEATURES

• Character screen configuration: 28 characters × 12 lines (maximum)

• Character types: 512 different characters (integrated in ROM, user-definable through the entire area)

(Continued)

■PACKAGE

20-pin Plastic SSOP

(FPT-20P-M03)

MB90097

(Continued)

• Font configuration: 12 × 18 dots (font ROM configuration)

Capable of specifying the horizontal and vertical sizes of characters to be displayed.

• One of the following three horizontal sizes (S, M, L) can be set for each character:

S size : 6 dots

M size : 9 dots

L size : 12 dots

• Either of the following two vertical sizes (A, B) can be set for each line.

A : 18 dots

B : 12 dots

• Display modes: Character trimming Enabled/Disabled (Set for each line)

Character background None/Solid-fill/Shaded background (concaved)/Shaded

background (con vexed) (Set for each line)

Horizontal character merge/independent display with

shaded background (Set for each character)

Vertical line merge/independent display with shaded

background (Set for each line)

Character background extended display ON/OFF for line

spacings (Set for each line)

Line background None/Solid-fill/Shaded background (concaved)/Shaded

background (convexed) (Set for each line)

(Display extended to the left and right margins of the screen

and to the line spacing)

Character enlargement: Four types supported: Normal, Double width, Double height,

Double width × double height

(Set for each line)

Enlarged display dot interpolation function (Set for each line)

• Character screen display position control:

Horizontal display position Control in 2-dot units (movable through the entire screen)

Vertical display position Control in 2-dot units (movable through the entire screen)

Line spacing control Control in 1-dot units (Set between 0 to 7 dots for each

line; Displayed simultaneously at two areas above and

below the line.)

• Sprite character control:

Sprite character display OFF/ON

Sprite character types 256 types (character codes: 000H to 0FFH)

Sprite character trimming Enabled/Disabled

Sprite character configuration Two types: 1 character/Stack of 2 characters

Sprite character horizontal display position Control in 1-dot units (movable through the entire screen)

Sprite character vertical display position Control in 1-dot units (movable through the entire screen)

(Continued)

MB90097

(Continued)

• Screen background control: Screen background color OFF/ON

• Display colors Character color: 16 colors (Set for each character)

Character trimming color: 16 colors (Set for each line)

Character background color: 16 colors (Set for each character) *

Line background color: 16 colors (Set for each line)

Screen background color: 16 colors

Sprite character color: 16 colors

Sprite character trimming color: 16 colors

Shaded background frame highlight color: 16 colors

Shaded background frame shadow color: 16 colors

• Display signal output: Color signal output: 4 bits (Supporting 16 colors)

Display period signals: 3 channels (Output selector circuit provided)

• External interface: 16-bit serial inputs

• Chip select

• Serial clock

• Serial data

• Package : SSOP-20

• Supply voltage: 3.3 V

*: Transparent (Displaying the lower-layer color) when the character background color (color code) = “0”

MB90097

■PIN ASSIGNMENT

(Top view)

SCLK

SIN

RESET

VDD

SDR

EXD

TEST

GND

HSYNC

VSYNC

VC0

VC1

VC2

BLKA

VC3

BLKB

TESTO

BLKC

(FPT-20P-M03)

MB90097

■PIN DESCRIPTIONS

Pin no. Pin name I/O Function

1 SCLK I Shift clock input pin for serial transfer

This pin has an internal pull-up resistor.

2CS

I Chip select pin

This pin inputs a Low level signal for serial transfer.

The pin has an internal pull-up resistor.

3 SIN I Serial data input pin

This pin has an internal pull-up resistor.

4 RESET I Reset input pin

This pin inputs a Low level signal when turning the power on.

DD — + 3 V power supply pin

6 SDR I Data input direction select pin for serial transfer

This pin inputs the Low level signal in the LSB-first transfer mode for data

input; it inputs the High level signal in the MSB-first transfer mode.

8XD

EXD O

IExternal circuit pins for display dot clock generator

Connect these pins to external “L” and “C” to form an LC oscillator circuit.

For external input of a display dot clock, input the clock signal to the EXD

pin and leave the XD pin open.

9 TEST I LSI test input pin

Input the Low level signal during normal use.

10 GND — Ground pin

20 HSYNC I Hor izontal sync signal input pin

19 VSYNC I Vertical sync signal input pin

VC0

VC1

VC2

VC3

OColor code signal output pin

15 BLKA O Display period signal output pin for output channel A

13 BLKB O Display period signal output pin for output channel B

11 BLKC O Display period signal output pin for output channel C

12 TESTO O LSI test output pin

Leave this pin open (unconnected) during normal use.

MB90097

■ABSOLUTE MAXI MUM RATINGS

(VGND = 0 V)

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■RECOMMENDED OPERATING CONDITIONS (VGND = 0 V)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

representatives beforehand.

Parameter Symbol Rating Unit Remarks

Min. Max.

Power supply voltage VDD VGND – 0.3 VGND + 4.5 V

Input vo lta ge VIN VGND – 0.3 VDD + 0.3 V

Output voltage VOUT VGND – 0.3 VDD + 0.3 V

Power consumption Pd — 100 mW

Operati ng temperature Ta – 40 + 85 °C

Storage temperature Tstg – 55 + 150 °C

Parameter Symbol Value Unit Remarks

Min. Max.

Power supply voltage VDD 3.0 3.6 V

“H” leve l input voltage VIHS 0.8 × VDD VDD + 0.3 V

“L” level input voltage VILS VGND 0.2 × VDD V

Operating temperature Ta – 40 + 85 °C

MB90097

■ELECTRICAL CHARACTERISTICS

1. DC Characterist ics (VGND = 0 V, Ta = – 40°C to + 85°C)

Parameter Symbol Pin name Conditions Value Unit

Min. Typ. Max.

“H” level output voltage 1 VC3

VC2

VC1

VC0

BLKC

BLKB

BLKA

VDD = 3.0 V

IOH = – 4.0 mA VDD – 0.5 — — V

“L” level output voltage 1 VOL1 VDD = 3.0 V

IOL = 4.0 mA ——0.4V

“H” level output voltage 2 VOH2 XD

VDD = 3.0 V

IOH = – 0.5 mA VDD – 0.5 — — V

“L” level output voltage 2 VOL2 VDD = 3.0 V

IOL = 0.5 mA ——0.4V

“H” level input current SDR

HSYNC

VSYNC

EXD

TEST

RESET

VDD = 3.3 V

VIH = VDD — — – 10 µA

“L” level input current IIL VDD = 3.3 V

VIL = 0 V ——10µA

PULL-UP resistance RPULL SIN

SCLK

CS VDD = 3.3 V 20 — 110 kΩ

Power supply current ICC VDD

VDD = 3.0 V

fDC = 8 MHZ—4 6mA

VDD = 3.6 V

fDC = 8 MHZ—5 7mA

Input ca pacita n ce C except VDD,

GND ——10—pF

VOH1

IIH

MB90097

2. AC Characteristics

(1) Serial input timings (VDD = 3.0 V to 3.6 V, VGND = 0 V, Ta = – 40°C to + 85°C)

Parameter Symbol Pin name Value Unit

Min. Max.

Shift clock cycle time tCYC SCLK 250 — ns

Shift clock pulse width tWCH SCLK 100 — ns

tWCL 100 — ns

Shift clock signal rise/fall time tCR SCLK —200ns

tCF —200ns

Shift clock sta rt time tSS SCLK 100 — ns

Data setup time tSU SIN 100 — ns

Data hold time tHSIN 50 — ns

Chip select end time tEC CS 100 — ns

Chip select signal rise/fall time tCRC CS —200ns

tCFC —200ns

0.8 VDD

0.2 VDD

tCRC

0.8 VDD

0.2 VDD

tCFC

tCYC

tWCL

tWCH

tCR tCR

tCF

0.8 VDD

0.2 VDD

tEC

SCLK

0.8 VDD

0.2 VDD

tSU

SIN

tSS

MB90097

(2) Vertical and horizontal sync signal input timings (VDD = 3.0 V to 3.6 V, VGND = 0 V, Ta = – 40°C to + 85°C)

*1: During the horizontal sync signal pulse period, the MB90097 stops its internal operation, disabling writing to

the internal VRAM. Therefore, set the horizontal sync signal pulse width and VRAM write cycle (command 2 or

command 4 issuance cycle) to ensure that: horizontal sync signal pulse width < VRAM write cycle.

*2: Do not change the vertical sync signal (detection edge) in the vicinity of the horizontal sync signal edge of

vertical sync signal detection. Otherwise, it results in a deflection in the display when the sync signal fluctuates.

*3: VVE, VHE and HE are control bits of Command 13-0 (I/O pin control) .

Note: The above diagrams assume that sync signal input control (SIX bit) of I/O pin control (command 13-0) has

been set to negative logic (0). The H and L levels are inverted if it has been set to positive logic.

(Continued)

Parameter Symbol Pin name Value Unit

Min. Max.

Horizontal sync signal rise time tHR HSYNC —200ns

Horizontal sync signal fall time tHF —200ns

Vertical sync signal rise time tVR VSYNC —200ns

Vertical sync signal fall time tVF —200ns

Horizontal sync signal pulse width*1 tWH HSYNC 18 — Dot clock

—6µs

Vertical sync signal setup time1*2

(Except for WE = 1, VHE = 1, HE = 1)*3 tVS VSYNC 4 1H – 4 Dot clock

Vertical sync signal setup time2*2

(WE = 1, VHE = 1, HE = 1)*3 tVS VSYNC – 6 1H – 14 Dot clock

Vertical sync signal detection hold time tVH VSYNC 2— H

Vertical sync signal pulse width tWV VSYNC 220H

0.8 VDD

0.2 VDD

0.8 VDD

0.2 VDD

tVS

tWH

tVH

tVF

tHF tHR

tVR

0.8 VDD

0.2 VDD

0.8 VDD

0.2 VDD

VSYNC

HSYNC

(1) VSYNC : Leading-edge operation

HSYNC : VSYNC detection at the trailing edge (VVE = 0)

(VHE = 1)

tWV

MB90097

(Continued )

0.8 VDD

0.2 VDD

0.8 VDD

0.2 VDD

VSYNC

tVS

tWH

tVH

tVR

tHF tHR

tVF

0.8 VDD

0.2 VDD

0.8 VDD

0.2 VDD

HSYNC

(2) VSYNC : Trailing-edge operation

HSYNC : VSYNC detection at the trailing edge

0.8 VDD

0.2 VDD

0.8 VDD

0.2 VDD

VSYNC

tVS

tWH

tVH

tVF

tHF tHR

tVR

0.8 VDD

0.2 VDD

0.8 VDD

0.2 VDD

HSYNC

(3) VSYNC : Leading-edge operation

HSYNC : VSYNC detection at the leading edge

0.8 VDD

0.2 VDD

0.8 VDD

0.2 VDD

VSYNC

tVS

tWH

tVH

tVR

tHF tHR

tVF

0.8 V DD

0.2 VDD

0.8 VDD

0.2 VDD

HSYNC

(4) VSYNC : Trailing-edge operation

HSYNC : VSYNC detection at the leading edge

(VVE = 1)

(VHE = 1 and HE = 0)

tWV

(VVE = 0)

(VHE = 0)

tWV

(VVE = 1)

(VHE = 0) or (VHE = 1 and HE = 1)

MB90097

(4) Dot clock input timing (VDD = 3.0 V to 3.6 V, VGND = 0 V, Ta = – 40°C to + 85°C)

*1: Assumes a dot clock LC oscillator circuit or external dot clock input.

*2: Assumes frequency-doubled external dot clock input.

*3: Assume s dot cl oc k ext er nal input.

Parameter Symbol Pin name Value Unit Remarks

Min. Max.

Dot clock cycle time tDCYC1 EXD 112 166 ns *1

tDCYC2 EXD 56 83 ns *2

Dot clock pulse time

tDWH1 EXD 48 — ns *1

tDWL1 48 — ns

tDWH2 EXD 24 — ns *2

tDWL2 24 — ns

HSYNC, VSYNC setup tim e tDS HSYNC

VSYNC 13 — ns *3

HSYNC, VSYNC hold time tDH 0—ns*3

Data output delay time 1 VC3,

VC2,

VC1,

VC0,

BLKA,

BLKB,

BLKC

DD2 ns

Data output delay time 2 tDD2 tDD1 45 ns

tDD1

Data output

AC measurement conditions

C = 70 pF

tr = 5 ns

tf = 5 ns

VOH = 0.8 VDD

VOL = 0.2 VDD

VIH = 0.8 VDD

VIL = 0.2 VDD

data Undefined period Valid data

Note: Applicable only when the MB90097 is operating with external dot clock input (not applicable with the LC oscillator circuit).

HSYNC

VSYNC

Inputs

EXD input

0.2 VDD

0.8 VDD

0.2 VDD

tDCYC1, 2

tDWL1, 2

tDS

tDH

tDWH1, 2

0.8 VDD

0.2 VDD

tDD1

tDD2

MB90097

(4) Reset input timing (VDD = 3.0 V to 3.6 V, VGND = 0 V, Ta = – 40°C to + 85°C)

Note: To feed the EXD pin with the dot clock, it is necessary to input the clock during RESET. Configuring LC

oscillator circuit using the external L and C will eliminate this need because it will automatically oscillate.

Parameter Symbol P in name Value Unit Remarks

Min. Max.

Reset pulse width tWRST RESET 1—µs

Clock input time tWRSD EXD 5 — Dot clock Note

t WRST

t WRSD

0.2 V DD

RESET

EXD

MB90097

■COMMAND LIST

1. Display Control Commands

Command

no. Function Comma nd code/data

15 to 1211109876543210

0VRAM wri te

address setting 0000 AY3 AY2 AY1 AY0 FL 0 0 AX4 AX3 AX2 AX1 AX0

1Character data

setting 1 0001 MS1 MS0 MM1 MM0 MB3 MB2 MB1 MB0 MC3 MC2 MC1 MC0

2Character data

setting 2 0010 MR MO1 MO0 M8 M7 M6 M5 M4 M3 M2 M1 M0

3Line control dat a

setting 1 0011 LHS LW2 LW1 LW0 LFD LFC LFB LFA LF3 LF2 LF1 LF0

4Line control dat a

setting 2 0100 LDS LGS LG1 LG0 LD LE LM1 LM0 L3 L2 L1 L0

5-00 Screen output

control 1A 0101 0 0 0 0 SDS UDS 0 DSP 0 OA2 OA1 OA0

5-01 Screen output

control 1B 0101 0 0 0 1 SOB BGB BLB 0 0 OB2 OB1 OB0

5-02 Screen output

control 1C 0101 0 0 1 0 SOC BGC BLC 0 0 OC2 OC1 OC0

5-2 Vertical displa y

position control 0101 1 0 0 Y8Y7Y6Y5Y4Y3Y2Y1Y0

5-3 Horizontal display

position control 0101 1 1 0 X8X7X6X5X4X3X2X1X0

6-1 Shaded

background frame

color control 0110 0 1 0 0 BH3 BH2 BH1 BH0 BS3 BS2 BS1 BS0

7-3 Screen

background

control 011111000000U3U2U1U0

8-0 Sprite character

control 1 1000 0 0 SFB SFA SF3 SF2 SF1 SF0 SC3 SC2 SC1 SC0

8-1 Sprite character

control 2 1000 0 1 SD1 SD0 SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0

9-0 Sprite character

control 4 1001 0 0 SY9 SY8 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0

9-1 Sprite character

control 5 1001 1 0 SX9 SX8 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0

11-0 Screen extension

control 101100000EG0000000

11-2 Dot clock control 11011100000000DC2DC1DC0

13-0 I/O pin con tr ol 1101 0 0 VVE VHE HE 0 SIX 0 0 0 DBX DCX

13-1 Horizontal

blanking control 1 1101 0 1 0 0 0 0 BB5 BB4 BB3 BB2 BB1 BB0

13-2 Horizontal

blanking control 2 1101 1 0 0 BF8BF7BF6BF5BF4BF3BF2BF1BF0

MB90097

2. Command Description

• Command 0 (VRAM write address setting)

Command 0 sets the write address in VRAM and controls e xecution of “VRAM fill.”

The sets the write address by specifying the row and column addresses.

VRAM fill is activated by executing command 2 (character data setting 2).

• Command 1 (Character data setting 1)

Command 1 sets character data.

Executing command 2 (character data setting 2) sets VRAM to reflect it on the screen.

• Command 2 (Character data setting 2)

Command 2 writes additional character data to the location in VRAM specified by command 0 (VRAM write

address setting 1), along with the character data set b y command 1 (character data setting 1).

The VRAM write address is incremented automatically after execution of command 2.

00 0 0 AY3 AY2 AY1 AY0 FL 0 0 AX4 AX3 AX2 AX1 AX0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AY3 to AY0: Row address

(0 to BH)AX4 to AX0: Column address

(0 to 1BH)

FL: VRAM fill control

(0: OFF, 1: ON)

MC3 to MC0: Character color

(From among 16 colors)

MB3 to MB0: Character background color

(From among 16 colors)

MM1, MM0: Character background control

(0, 0: OFF)

(0, 1: Solid-fill display)

(1, 0: Concaved, shaded background)

(1, 1: Convexed, shaded background)

00 0 1 MS1 MS0 MM1 MM0 MB3 MB2 MB1 MB0 MC3 MC2 MC1 MC0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MS1, MS0: Character horizontal size control

(0, 0: S size, 6 dots)

(0, 1: M size, 9 dots)

(1, 0: L size, 12 dots)

(1, 1: Setting prohibited)

MR: Shaded background succeeding character merge control

(0: Disables succeeding character merge display.)

(1: Enables succeeding character merge display.)

M8 to M0: Character code

MO1, MO0: Character output control

00 1 0 MR MO1 MO0 M8 M7 M6 M5 M4 M3 M2 M1 M0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MB90097

• Command 3 (Line control data setting 1)

Command 3 sets line control data.

Executing command 4 (line control data setting 2) sets VRAM to reflect it on the screen.

• Command 4 (Line control data setting 2)

Command 4 writes additional line control data to the row address in line RAM specified by command 0

(VRAM write address setting), along with the line control data set by command 3 (line control data setting1).

Executing this command will not alter the VRAM write address.

• Command 5-00 (Screen output control 1A)

Command 5-00 controls screen display output.

00 1 1 LHS LW2 LW1 LW0 LFD LFC LFB LFA LF3 LF2 LF1 LF0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LHS: Line character vertical size type control

(0: Character vertical size A)

(1: Character vertical size B)

LW2 to LW0: Line spacing control

(0 to 7 dots in 1-dot units)

LF3 to LF0: Trimming color

(From among 16 colors)

LFD, LFC: Trimming output control

(0, 0: All OFF)

(0, 1: Trimming ON for character with no character background)

(1, 0: Trimming ON for solid-filled character with no character background

)

(1, 1: All ON)

LFB, LFA: Trimming control

(0, 0: Trimming OFF)

(0, 1: Reserved (Setting prohibited))

(1, 0: Reserved (Setting prohibited))

(1, 1: Eight-direction trimming)

01 0 0 LDS LGS LG1 LG0 LD LE LM1 LM0 L3 L2 L1 L0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LDS: Line character output control

(Control of character + trimming + character background)

(0: OFF, 1: ON)

LGS: Line enlargement interpolation control

(0: OFF, 1: ON)

LG1, LG0: Line enlargement control

(0, 0: Normal)

(0, 1: Double width)

(1, 0: Double height)

(1, 1: Double width × double height)

LE: Character background extension control

(0: Normal, 1: Extended)

LD: Shaded background succeeding line merge control

(0: Independent, 1: Merge with the next line)

LM1, LM0: Line background control

(0, 0: OFF)

(0, 1: Solid-fill display)

(1, 0: Concaved, shaded display)

(1, 1: Convexed, shaded display)

L3 to L0: Line background color

(From among 16 colors)

01 0 1 0 0 0 0 SDS UDS 0 DSP 0 OA2 OA1 OA0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SDS: Sprite character output control

(0: OFF, 1: ON)*

UDS: Screen background output control

(0: OFF, 1: ON)*

DSP: Display output control

(Control of character + trimming + character background +

line background)

(0: OFF, 1: ON)*

*: The low level input to the RESET pin initializes the SDS, UDS, and DSP bits to 0.

OA2 to OA0: Output-A character control

(From among eight types)

MB90097

• Command 5-01 (Screen output control 1B)

Command 5-01 controls output-B screen display output.

• Command 5-02 (Screen output control 1C)

Command 5-02 controls output-C screen display output.

• Command 5-2 (Vertical display position control)

This command controls the vertical display position of the screen.

• Command 5-3 (Horizontal display position control)

This command controls the horizontal display position of the screen.

01 0 1 0 0 0 1 SOB BGB BLB 0 0 OB2 OB1 OB0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SOB: Output-B sprite character output control

(0: OFF, 1: ON)

BGB: Output-B screen background output control

(0: OFF, 1: ON)

BLB : Output-B line background output control

(0: OFF, 1: ON)

OB2 to OB0: Output-B character control

(From among eight types)

01 0 1 0 0 1 0 SOC BGC BLC 0 0 OC2 OC1 OC0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SOC: Output-C sprite character output control

(0: OFF, 1: ON)

BGC: Output-C screen background output control

(0: OFF, 1: ON)

BLC : Output-C line background output control

(0: OFF, 1: ON)

OC2 to OC0: Output-C character control

(From among eight types)

01 0 1 1 0 0 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

15 14131211109876543210

Y8 to Y0: Vertical display position control

(0 to 1022 in 2-dot units)

01 0 1 1 1 0 X8 X7 X6 X5 X4 X3 X2 X1 X0

15 14131211109876543210

X8 to X0: Horizontal display position control

(0 to 1022 in 2-dot units)

MB90097

• Command 6-1 (Shaded background frame color control)

Command 6-1 controls the frame color of a shaded background.

• Command 7-3 (Screen background control)

Command 7-3 controls the screen background color.

• Command 8-0 (Sprite character control 1)

This command controls sprite characters.

• Command 8-1 (Sprite character control 2)

Command 8-1 controls sprite characters.

01 1 0 0 1 0 0 BH3 BH2 BH1 BH0 BS3 BS2 BS1 BS0

15 14131211109876543210

BH3 to BH0: Shaded background frame highlight color

(From among 16 colors)

BS3 to BS0: Shaded background frame shadow color

(From among 16 colors)

011111000000U3U2U1U0

15 14131211109876543210

U3 to U0: Screen background color

(From among 16 colors)

10 0 0 0 0 SFB SFA SF3 SF2 SF1 SF0 SC3 SC2 SC1 SC0

15 14131211109876543210

SFB, SFA: Sprite character trimming control

(0, 0: Trimming OFF)

(0, 1: Reserved)

(1, 0: Reserved)

(1, 1: Eight-direction trimming)

SF3 to SF0 : Sprite character trimming color

(From among 16 colors)

SC3 to SC0: Sprite character color

(From among 16 colors)

10 0 0 0 1 SD1 SD0 SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0

15 14131211109876543210

SD1, SD0: Sprite character configuration control

(0, 0: 1 character)

(0, 1: Reserved (Setting prohibited))

(1, 0: Stack of 2 characters)

(1, 1: Reserved (Setting prohibited))

SM7 to SM0: Sprite character code

(000H to 0FFH for 256 different characters)

MB90097

• Command 9-0 (Sprite character control 4)

Command 9-0 controls sprite characters.

• Command 9-1 (Sprite character control 5)

This command controls sprite characters.

• Command 11-0 (Screen extension control)

(Reserved)

• Command 11-2 (Dot clock control 1)

Command 11-2 controls the dot clock.

10 0 1 0 0 SY9 SY8 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0

15 14131211109876543210

SY9 to SY0: Sprite character vertical display position control

(0 to 1023 in 1-dot units)

10 0 1 1 0 SX9 SX8 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0

15 14131211109876543210

SX9 to SX0: Sprite character horizontal display position control

(0 to 1023 in 1-dot units)

101100 000EG0000000

15 14131211109876543210

EG0: (Reserved)

(0: Normal)

(1: Reserved (Setting prohibited))

: Set the EG0 bit to “0”.

10 1 1 1 0 0 0 0 0 0 0 0 DC2 DC1 DC0

15 14131211109876543210

DC2 to DC0: Dot clock selection control

(0, 0, 0: LC oscillation)

(0, 1, 0: External dot clock input)

(0, 1, 1: Frequency-doubled external dot clock input)

MB90097

• Command 13-0 (I/O pin control)

Command 13-0 controls input/output pins.

*1:When it i s set up VVE = 1, VHE = 1 and HE = 1, HSY NC edg e for verti c al s ync hr oni za tio n det ec tio n is the

standard of “Leading edge”.

*2:If there is the change of level for direction of VSYNC pin signal detection in the vicinity of position of vertical

sync detection, it may occur disorder in the display (deflection of vertical direction) . Input the meaningful

edge of VSYNC signal without this position of vertical sync detection.

*3:The low level input to the RESET pin initializes the DCX and DBX bits to 0.

• Command 13-1 (Horizontal blanking control 1)

Command 13-1 controls horizontal blanking (back porch).

• Command 13-2 (Horizontal blanking control 2)

Command 13-2 controls horizontal blanking (front porch).

VVE VHE HE Contents of vertical sync detection Position of vertical sync detection*3

0 0 0 Detection of VSYNC Leading edge HSYNC Leading edge

0 0 1 Detection of VSYNC Leading edge HSYNC Leading edge

0 1 0 Detection of VSYNC Leading edge HSYNC Trailing edge

0 1 1 Detection of VSYNC Leading edge HSYNC Trailing edge

1 0 0 Detection of VSYNC Trailing edge HSYNC Leading edge

1 0 1 Detection of VSYNC Trailing edge HSYNC Leading edge

1 1 0 Detection of VSYNC Trailing edge HSYNC Trailing edge

1 1 1 Detection of VSYNC Trailing edge HSYNC Leading edge + 10 cloc k

11 0 1 0 0 VVE VHE HE 0 SIX 0 0 0 DBX DCX

15 14131211109876543210

VVE: Edge selection for vertical synchronization detection*1

(0: Leading edge, 1: Trailing edge)

VHE: HSYNC edge selection for vertical synchronization detection*1

(0: Leading edge, 1: Trailing edge)

HE: Edge selection for horizontal synchronization operation*1

(0: Trailing edge, 1: Leading edge)

SIX : Logic control for sync signal input

(0: Negative logic, 1: Positive logic)

DCX: Logic control for display color signal output

(0: Positive logic, 1: Negative logic)*3

DBX: Logic control for display output period signal output

(0: Positive logic, 1: Negative logic)*3

11 0 1 0 1 0 0 0 0 BB5 BB4 BB3 BB2 BB1 BB0

15 14131211109876543210

BB5 to BB0: Back porch control

(0 to 126 in 2-dot units)

11 0 1 1 0 0 BF8 BF7 BF6 BF5 BF4 BF3 BF2 BF1 BF0

15 14131211109876543210

BF8 to BF0: Front porch control

(0 to 1022 in 2-dot units)

MB90097

4. Notes on Issuing Commands

This section summarizes notes on issuing commands.

(1) Initialization

The MB90097 enters the display-off state * upon reset input (input of a Low-level signal to the RESET pin). The

contents of VRAM (character RAM and line RAM) are not initialized then (undefined immediately after the power

supply is turned on).

When the MB90097 is released from the reset input, issue the following commands to initialize control

operation:

• Dot clock control 1 (Command 11-2)

• I/O pin control (Command 13-0)

After that, set all of other command data and the contents of VRAM.

(VRAM setting requires normal dot clock and sync signal inputs.)

* :The reset input initializes control bits to 0 as shown below

Screen output control 1A (command 5-00) SDS = 0 Sprite OFF

UDS = 0 Screen background OFF

DSP = 0 Character, character background, line

background OFF

I/O pin control (command 13-0) DCX = 0 Sets the VC0, VC1, VC2, and VC3 pins to

positive logic output.

DBX = 0 Sets the BLKA, BLKB, and BLKC pins to positive

logic output.

(2) Command refresh

Command data to the MB90097 and the contents of internal VRAM remain held as long as the MB90097 is

powered. If the serial control, sync, and dot clock signals are affected by external noise, however, they may

become abnormal signals, preventing the internal registers and VRAM from being set normally. You should

therefore refresh all of command data and VRAM data periodically to restore them from the abnormal state.

(3) Command issuance timing

When a VRAM write command, such as a character data setting or line control data setting command, or any

other control command is issued, the command is executed immediately, reflecting the result (command setting)

on the screen. When such a command is issued during a display period, the display in the relevant field may

involve transient distortion. To prevent this, you should issue the command during the vertical blanking interval.

Also, a restriction on the internal circuit configuration may cause deviation of the display position in the first

display field when the DSP, SDS, or UDS control bit of command 5-00 (screen output control 1A) is set from

OFF to ON. To prevent this, you should issue command 5-00 within the 2H period after the leading edge of the

V sync signal.

MB90097

■DISPLAY FUNCTIONS

1. Screen Configurati on

1. 1 Screen Elements

The display screen provided by the MB90097 consists of a pile of display screen elements.

• Screen configuration drawing

Display screen element name Display configuration Display position control

Sprite character (+ trimming) 1 (Stack of 2 characters) Horizontal/vertical: 1-dot units

Character (+ trimming) 28 characters × 12 lines Horizontal/vertical: 2-dot units

Character background 28 characters × 12 lines (Controlled simultaneously with

the character)

Line background 12 lines (Controlled simultaneously with

the character)

Screen background Full screen display in single

color (None)

Top layer

Bottom layer

Input image

Note: When a character is displayed on a line, the display of the shaded background shadow frame

for the line background overrides the character display.

The display of the shaded background shadow frame for the character background overrides

the character display and the shaded background shadow frame for the line background.

Screen background (Screen background color)

Line 0 Line background (Line background color)

Line 1

Line 2

Line 3

Line 4

Line 5

Line 6

Line 7

Line 8

Line 9

Line 10

Line 11

Character background

(Character background color)

Character + trimming

← Sprite character + trimming

MB90097

1. 2 Screen Display Modes

Display screen

elem en t name Display mode

Screen

background Undisplay

Display

Line

background

Undisplay

Line spacing (0 to 7

dots)

Solid-fill disp lay

Shaded

background

succeeding

line merge

Independent

Shaded background convexed display Merge

Character

background

Undisplay

Solid-fill disp lay

Character

background

extended

(enabled

with line

spacing)

Normal

Shaded

background

concaved

display Shaded

background

succeeding

character

merge

Independent Shaded

background

succeeding

line merge

Independent

Shaded

background

convexed

display Merge Merge Extended

Character

Undisplay (blank character (Arbitrarily set))

Display Trimming output

control

Undisplay

Dis pl ay f or ch ar ac te rs wit h no ch a r ac te r

background

Trimming

type

Display for all characters

Sprite

character

Undisplay

Display Trimming

type

Undisplay

Consisting of a stack of characters Eight-direction

trimming display

Shaded bac k ground conc aved dis pl ay

Eight-

direction

trimming

display

Undispla

Display for characters with no character

background or with solid-filled

character background

Consisting of a single character

MB90097

1. 3 Screen Output Control

The screen output control commands can control three channels of outputs A, B, and C independently.

Their output enable period signals are output to the BLKA, BLKB, and BLKC pins, respectively.

The output-A, -B, and -C control commands can set the character attribute display to OFF, line background

display, and screen background display arbitrarily based on the basic display screen, allowing three independent

screens to be configured and output.

The layer structure of the output screens exists only on the basic display screen. If the output-A, -B, or -C

control command sets the display of an arbitrary area to OFF, the lower layer cannot be displayed but appears

transparent.

The table below shows the relationships between screen output controls and control command bits.

*1: If character display is set to OFF with the character/trimming/character background overlapping the line

background or screen background, the corresponding area of the lower layer is not displayed but appears

transparent.

*2: If line background display is set to OFF with the line background overlapping the screen background, the

corresponding area of the screen background is not displayed but appears transparent.

*3: If sprite display is set to OFF with the sprite character/trimming overlapping a character, character background,

line background, or screen background, the corresponding area of the lower layer is not displayed but appears

transparent.

Note: Three-channel output control for each character serves as output control within the character area. When

trimming dots for a character are displayed in part of the area for an adjacent character, the output of the

trimming dots is controlled by the output control of that adjacent character. If there are trimming dots to the

left of the leftmost character on a line, they cannot be controlled by three-channel output control for each

character. In this case, set a blank character at the left end of the line.

When trimming dots are displayed to the right of the rightmost character on a line, they are controlled with

the three-channel output attribute of the rightmost character.

Basic display screen control Three-channel output controls

Elements to be controlled/Control bit name

(Unit of control) Output-A control Output-B control Output-C control

Character + trimming + character background +

line background

DSP (per screen) ←←←

Character + trimming + character

background LDS (per line) ←←←

Character M8-M0 (per character) OA2-OA0

(per screen)

MO1, MO0*1

(per character)

OB2-OB0

(per screen)

MO1, MO0*1

(per character)

OC2-OC0

(per screen)

MO1, MO0*1

(per character)

Character trimming

LFD-LFA (per line)

Character background

MM1, MM0 (per character)

Line background LM1, LM0 (per line) ←BLB*2

(per screen) BLC*2

(per screen)

Screen background color UDS (per screen) ←BGB

(per screen) BGC

(per screen)

Sprite character SDS (per screen) ←SOB*3

(per screen) SOC*3

(per screen)

Sprite character trimming

SFB, SFA (per screen) ←

MB90097

1. 4 Screen Display Position Control

(1) Display position control on the character screen

The MB90097 can simultaneously control the display start positions of a character (or a line of characters),

character trimming, character background, and line background.

• Vertical display position: Vertical display position control (command 5-2), Bits Y8 to Y0

Set the vertical display start position* relative to the VSYNC position.

The position can be set between 0 and 1022 dots in 2-dot units.

• Horizontal display position: Horizontal display position control (command 5-3), Bits X8 to X0

Set the vertical display start position* relative to the HSYNC position.

The position ca*n be set between 0 and 1022 dots in 2-dot units.

• Line spacing: Lin e co nt ro l da ta s ett ing 1 ( co mman d 3), Bit s LW2 to LW0

Set the number of dots to specify the height of the areas to be kept above and

below the characters on each line.

The spacing specified by the set value will be kept both above and below the

characters.

The line spacing can be set between 0 and 7 dots in 1-dot units for each line.

(Note: When line double-height displa y is on, the line spacing is doubled as well.

*: The actual display position is offset from the set value by several tens of dots in the positive direction.

• • •

HSYNC position*

Line 1

Line 2

Line 0

VSYNC position*

Line spacing

Vertical display position

Horizontal

display position

Character Character Character Character Character Character Character Character Character

* :For the VSYNC position, you can select the leading or trailing edge of the vertical sync signal pulse.

For the HSYNC position, you can select the leading or trailing edge of the horizontal sync signal pulse.

(For details, see Section 3 “Sync Signal Input” of “■ CONTROL FUNCTIONS.”)

MB90097

(2) Display position control of sprite characters

The MB90097 can control the display start positions of a sprite character and its trimming.

• Sprite character vertical display position: Sprite character control 4 (command 9-0), Bits SY9 to SY0

Set the vertical display start position* relative to the VSYNC

position.

The position can be set between 0 and 1023 dots in 1-dot units.

• Sprite character horizontal display position: Sprite character control 5 (command 9-1), Bits SX9 to SX0

Set the vertical display start position* relative to the HSYNC

position.

The position can be set between 0 and 1023 dots in 1-dot units.

*: The actual display position is offset from the set value b y several tens of dots in the positive direction.

HSYNC position*

Sprite character horizontal

display position

Sprite character

vertical display

position

Sprite character

VSYNC position*

* :For the VSYNC position, you can select the leading or trailing edge of the vertical sync signal pulse.

For the HSYNC position, you can select the leading or trailing edge of the horizontal sync signal pulse.

(For details, see Section 3 “Sync Signal Input” of “■ CONTROL FUNCTIONS.”)

MB90097

2. Font R OM Confi guration

The font ROM can incorporate 512 characters each made up of 12 × 18 dots.

• All of 512 characters can be set freely by the user.

(Note, however, that the blank cha racter must be set as an arbit rary character code bec ause even it is not

set by default.)

• The user areas available to sprite characters are from 000H to 0FFH.

000 H

001 H

002 H

101 H

102 H

0FF H

0FE H

100 H

1FE H

1FF H

Font ROM

↑

Character code

Areas available

to sprite characters

(User area)

12 dots

18 dots

(Character configuration example)

(User area)

MB90097

3. Display Memory (VRAM) Configuration

The display memory (VRAM) consists of the character RAM for setting individual characters and the line RAM

for setting individual lines.

• Character RAM: 28 characters × 12 lines (336 characters in total)

• Line RAM: 12 lines

3. 1 Display Memory and Display Screen

Areas of character RAM and those of line RAM correspond to displayed characters and lines on a one-to-one

basis, respectively.

• Display memory configuration

• Example of display screen configuration (with all characters in normal size)

0123456789012345678901234567

111111111122222222

Character RAM Line RAM

Column addresses

Row addresses

0123456789012345678901234567

111111111122222222

VRAM row address

VRAM column address

MB90097

3. 2 Writing to Display Memory

(1) Writing characters to character RAM

a) Writing a single character

Use the following commands to write data on an arbitrary character to an arbitrary address in character

RAM:

Note: Normal writing to VRAM requires input of a normal horizontal sync signal. Input of an invalid horizontal sync

signal may cause VRAM write to fail.

Also, you must set the horizontal sync signal pulse width and VRAM write cycle (command 2 or command

4 issuance cycle) such that: horizontal sync signal pulse width < VRAM write cycle.

b) Writing multiple characters collectively (VRAM fill)

Use the following commands to write data on an arbitrary character to an are a of character RAM from an

arbitrary address to the last address, filling the area with that data:

Note: Normal execution of VRAM fill requires input of a normal horizontal sync signal. Input of an invalid horizontal

sync signal may cause VRAM fill to fail.

VRAM write address setting

Character data setting 1

Character data setting 2

(Command 1)

(Command 2)

(Command 0) *1

Set the row and column addresses.

Write the character data to character RAM.

(The VRAM write address is incremented after writing to VRAM.)

*1: When writing to consecutive addresses continuously, you can omit this command for the latter character

RAM write.

*2: You can also omit this command if the current character data is the same as the one set by the preceding

“character data setting 1” command.

VRAM write address setting

Character data setting 1

Character data setting 2

(Command 1)

(Command 2)

(Command 0) Set the row and column addresses and specify “VRAM fill”.

The character RAM write executes VRAM fill.

* :The VRAM fill execution time is about 2 ms for the entire screen.

During e xecution of VRAM fill, do not issue command 0 to 4.

Issuing command 0 (FL = 0) during execution of VRAM fill will abort the VRAM fill.

(To write to VRAM after VRAM fill has aborted, issue command 0 again to set the VRAM write address.)

MB90097

(2) Writing to line RAM

Use the following commands to write data on an arbitrary line to an arbitrary address in line RAM:

Note: Normal writing to VRAM requires input of a normal horizontal sync signal. Input of an invalid horizontal sync

signal may cause VRAM write to fail.

Also, you must set the horizontal sync signal pulse width and VRAM write cycle (command 2 or command

4 issuance cycle) such that: horizontal sync signal pulse width < VRAM write cycle.

VRAM write address setting

Line control data setting 1

Line control data setting 2

(Command 3)

(Command 4)

(Command 0) Set the row address.

Write the line data to line RAM.

(The VRAM write address remains unchanged.)

*1: The line RAM fill function is not available. (It is prohibited to specify “Line RAM fill”.)

*2: You can omit this command if the current line control data is the same as the one set by the preceding

“line control dat a setting 1” command.

MB90097

4. Character Display

4. 1 Displayed Character Configuration

For each character to be displayed, you can set the vertical and horizontal sizes.

Each character is displayed by clipping the specified size of the specified character data from font ROM, starting

at the upper leftmost dot.

• Character horizontal size control (Setting for each character)

Character data setting 1 (Command 1): Bits MS1 and MS0

• Line character vertical size type control (Setting for each line)

Line control data setting 1 (Command 3): Bit LHS

MS1 MS0 Character hori zont al size

0 0 S size: 6 dots

0 1 M size: 9 dots

1 0 L size: 12 dots

1 1 (Setting prohibited)

LHS Line character vertical size type

0 Line character vertical size A: 18 dots

1 Line character vertical size B: 12 dots

MB90097

• Disp lay examples

(12 horizontal dots × 18 vertical dots)

L size M size S size M size

• A character stored in font ROM

• Display example 1 (character vertical size A: 18 dots)

• Display e xample 2 (character vertical size B: 12 dots)

MB90097

4. 2 Character Trimming

(1) Trimming output control

Trimming output control turns ON or OFF the trimming of characters depending on their character background

type. One of the four character background types can be set for each line.

• Trimming output control (Setting for each line)

Line control data setting 1 (Command 3): Bits LFD and LFC

Trimming output contr ol

(Setting for eac h line) Character background type

(Setting for each character) Trimming output

LFD LFC MM1 MM0 Background display

0000Undisplay ×

0 1 Solid-filled background ×

Concaved, shaded

background ×

Convexed, shaded

background ×

0100

Undisplay

0 1 Solid-filled background ×

Concaved, shaded

background ×

Convexed, shaded

background ×

1000

Undisplay

Solid-filled background

Concaved, shaded

background ×

Convexed, shaded

background ×

1100

Undisplay

Solid-filled background

Concaved, shaded

background

Convexed, shaded

background

× : Undisplay

: display

MB90097

(2) Trimming type control

As the type of trimming, you can select “eight-direction trimming” or “undisplay”.

• Trimming type control (Setting for each screen)

Line control data

setting 1 (Command 3): Bits LFB and LFA

(3) Trimming colors

The trimming color can be set to one of 16 different colors for each line.

• Trimming color (Setting for each line, selected from among 16 colors)

Line control data setting 1 (Command 1): Bits LF3 to LF0

(4) Trimming display rules

The following display rules apply to trimming display:

• Trimming dots for a character can be displayed in the right or left adjacent character area only when the

character background types of the two characters are the same.

• Trimming dots for the character at the left or right end of a line can be displayed beyond the character area

only when the character background type is “no character background”.

(When three-channel output control for each character is used, however, do not attempt to display trimming

dots outside the character area at the left end of a line. Trimming dots for that area cannot be controlled in

character units. Note also that trimming dot display outside the character area at the right end of a line

depends on the character output control setting for the rightmost character on the line.)

• Trimming displa y for a character does not apply to the areas abov e and below the character (the area for the

character on the line above, the area for the character on the line below, the upper line spacing, and the lower

line spacing).

• When a line is displayed enlarged, trimming dots on the line are not enlarged but those in the normal dot

size are displayed around the enlarged character dots.

Note: For output control of each character using three-channel output control, design the display and font taking

account of trimming dot display protruding to the area for the adjacent character to the right or left.

Three-channel output control for each character is display output control of the character area. Turning on

or off the display of trimming dots protruding to the right or left adjacent character area depends on the

character output control setting for that adjacent character.

Trimming

output control Trimming output

LFB LFA

00Undisplay

0 1 Reserved (Setting prohibited)

1 0 Reserved (Setting prohibited)

1 1 Eight-direction trimmin g

MB90097

4. 3 Line Enlarged Display

Line enlarged display control is used to control the display size of each line including the characters, character

backgrounds, and line background on that line (as well as the line spacing portions). This also controls

enlargement of the shadow frames of shaded backgrounds. It does not however control the enlargement of the

trimming dot width.

Note that the lines and characters following the line for which line enlarged display has been specified are shifted

down accordingly.

• Line enlargement control (Setting for each line)

Line control data setting 2 (Command 4): Bits LG1 and LG0

(1) Line enlarged display examples

LG1 LG0 Display size

00Normal size

0 1 Double-width size

1 0 Double-height size

1 1 Double-width/height size

Line spacing

Displayed line

•Normal size

• Double-width size

• Double-he ight size

MB90097

• Double-width/height size

(2) Dot interpolation for enlarged display

Dot interpolation display is enabled only when the line enlargement control is in the double-width size display.

You can designate the display in line units.

Dot interpolation is performed in character units; dots are not interpolated between the neighboring characters.

Outline display is generated and displayed in the character dots and interpolation dots. Outline dot width is not

displayed enlarged.

• Line enlargement interpolation control (Setting for each line)

Line control data setting 2 (Command 4): Bit LGS

• Interpolated display examples (Basic type)

LGS Interpolation control

0 Interpolation OFF

1 Interpolation ON

Line spacing

Normal size Double-width height size

Character dot

Arbitrary dot*

Arbitrary dot*Character dot

*: Blank dot or character dot

Interpolating dot Character dot

Character dot Interpolating dot

MB90097

5. Character Background Display

5. 1 Character Background Display

For each character, you can set the character background selected from among four types and the character

background color from among 16 colors.

• Character background control • Character background color

(Setting for each character) (Setting for each character, selected from among 16 colors)

Character data setting 1 (Command 1) : Character data setting 1 (Command 1) :

Bits MM1 and MM0 Bits MB3 to MB0

• Display examples

MM1 M M0 Ch ara ct er backgr o und

NO background

(undisplay)

0 1 Solid-filled background

Concaved, shaded

background

Convexed, shaded

background

Note:The character background color is transparent when all of

MB3 to MB0 have been set to 0.

(If character background display has been set for a

character with the above settings, the corresponding portion

of the lower layer will be displayed.)

• Shaded background highlight color

(Setting for each screen, selected from among 16 colors)

Shaded background frame color control (Command 6-1) :

Bits BH3 to BH0

• Shaded background shadow color

(Setting for each screen, selected from among 16 colors)

Shaded background frame color control (Command 6-1) :

Bits BS3 to BS0

(a) No background

Character

background color

(b) Solid-filled background

Shaded

background

shadow color

Shaded

background

highlight color

Shaded

background

highlight color

Character

background color

Shaded

background

shadow color

Lower-layer

output (Line

background

color, screen

background color,

or no output)

Character display

Character

background color

Note : The shaded background frame for a character is

displayed inside the circumference of the character area.

MB90097

5. 2 Shaded Background Succeeding Character Merge Display

Specifying “shaded background character display” and “shaded background succeeding character merge

display” for a character undisplays the right line of the shadow frame of the character and the left line of the

shadow frame of the next (right adjacent) character. This enables two or more characters with shaded

backgrounds to be joined horizontally.

• Shaded background succeeding character merge control (Setting for each character)

Character data setting 2 (Command 2) : Bit MR

MR Shaded background succeeding

character merge control

0OFF

1ON

(Succeeding character merge = OFF)

(Succeeding character merge = ON) (Succeeding character merge = ON) (Succeeding character merge = OFF)

(Succeeding character merge = OFF) (Succeeding character merge = OFF)

• Display examples of independent characters with shaded backgrounds

• Display examples of merged characters with shaded backgrounds

MB90097

5. 3 Shaded Background Succeeding Line Merge Display

Specifying “shaded background character display" for characters on a line and both of “character background

extended display” and “shaded background succeeding line merge display” for the line undisplays the lower

lines of the shadow frames of the characters on that line and the upper lines of the shadow frames of the

characters on the next line. (Specify both of “shaded background succeeding line merge display” and “character

background extended display” for the current line and “character background extended display” for the next line.)

• Shaded background succeeding line merge control • Character background extended display control

(Setting for each line) (Setting for each line)

Line control data setting 2 (Command 4) : Line control data setting 2 (Command 4) :

Bit L D Bit LE

• Display examples of merged lines of characters with shaded backgrounds

LD Shaded background

succeeding line merge control

0OFF

1ON

LE Character background

extended display control

0 OFF (Normal display)

1 ON (Extended display)

Succeeding line merge = OFF

and

Extended display = ON

(Succeeding character merge = ON) (Succeeding character merge = OFF) (Succeeding character merge = OFF)

Succeeding line merge = ON

and

Extended display = ON

Note: If character background extended display is not specified, shaded background succeeding line merge

display is disabled for character backgrounds. (The setting of shaded background succeeding line merge

display applies only to the line background shadow frame.)

MB90097

5. 4 Character Background Extended Display

Character background extended display extends character backgrounds to line spacing portions.

(Note that this setting is required to apply shaded background succeeding line merge display to character

backgrounds.)

• Character background extended display (Setting for each line)

Line control data setting 2 (Command 4): Bit LE

LE Character background extended display

0 OFF (Normal display)

1 ON (Extended display)

(No character background) (Solid-filled background) (Concaved, shaded background) Line spacing

(No character background) (Solid-filled background) (

Concaved

, shaded background) Line spacing

• Display example with character background extended displa y = ON

(Line spacing = 2)

• Display example with character background extended display = OFF

(Line spacing = 2)

MB90097

6. Line Background Display

6. 1 Line Background Display

Line background display for a line displays the line background in the line area of the characters on the line, the

areas to the right and left of that area, and the line spacing areas above and below it.

There are four types of line backgrounds are available (None, Solid fill, Concaved shaded background, and

Convexed shaded background), one of which can be set for each line.

Shaded line background display is used to display the shaded background frame highlight color and shaded

background frame shadow color above and below the line background area, respectively, along with the line

background color display.

• Line background control • Line background color

(Setting for each line) (Setting for each line, selected from among 16 colors)

Line control data setting 2 (Command 4) : Line control data setting 2 (Command 4) :

Bits LM1 and LM0 Bits L3 to L0

• Line background display examples

LM1 LM0 Line background

0 0 No background (undisplay)

0 1 Solid-filled background

Concaved, shaded

background

Convexed, shaded

background

• Shaded background highlight color

(Setting for each screen, selected from among 16 colors)

Shaded background frame color control (Command 6-1) :

Bits BH3 to BH0

• Shaded background shadow color

(Setting for each screen, selected from among 16 colors)

Shaded background frame color control (Command 6-1) :

Bits BS3 to BS0

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J No line background

Solid-filled background

(Shaded background frame highlight color)

Convexed, shaded background

(Shaded background frame shadow color)

Concaved, shaded background

(Shaded background frame highlight color)

Character display area

MB90097

6. 2 Shaded Background Succeeding Line Merge Display

Specifying “shaded background succeeding line merge display” for a line enables the line to be displayed with

the line background merged with that of the next line.

This undisplays the lower line of the line background shadow frame of the current line and the upper line of the

line background shadow frame of the next line, allowing two or more lines to be displayed with shaded line

backgrounds.

• Shaded background succeeding line merge control (Setting for each line)

Line control data setting 2 (Command 4): Bit LD

• Examples of shaded background succeeding line merge display

LD Shaded background succeeding line

merge contr ol

0OFF

1ON

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

(Shaded background frame highlight color)

Character display area

Convexed, shaded background with

succeeding line merge ON

Convexed, shaded background with

succeeding line merge OFF

(Shaded background frame shadow color)

Convexed, shaded background with

succeeding line merge OFF

(Shaded background frame shadow color)

Concaved, shaded background with

succeeding line merge ON

Note: Specifying shaded background succeeding line merge display applies merge control to the character and

line backgrounds at the same time. If character background extended display is off for a line, however,

merge control ignores the shaded background characters on that line.

MB90097

7. Screen Background Display

7. 1 Screen Background Color Display

The screen background color can be output to the bottom layer of display output.

• Screen background output control

Screen output control 1A (Command 5-00): Bit UDS

• Screen background color code

Screen background control 4 (Command 7-3): Bits U3 to U0

One of 16 colors can be set.

• Three-channel output control

When screen background color output is ON (UDS = 1), the screen background outputs to output B and output

C can be controlled independently. (Output A is controlled only with the UDS bit.)

• Output-B screen background color output control

Screen output control 1B (Command 5-01): Bit BGB

• Output-C screen background color output control

Screen output control 1C (Command 5-02): Bit BGC

* :Enabled only when screen background color output is ON (UDS = 1).

UDS Screen background color display

0OFF

1ON

BGB Output-B screen background color output

0OFF

1ON*

BGC Output-C screen background color output

0OFF

1ON*

MB90097

8. Sprite Character Display

Sprite characters are displayed on the top layer of the display screen.

(1) Sprite character configuration

• Sprite character display example

(2) Sprite character display control

• Sprite character output control

Screen output control 1A (Command 5-00): Bit SDS

• Sprite chara ct er code

Sprite character control 2 (Command 8-1): Bits SM7 to SM0

A sprite character code can be selected from among character codes 00H to FFH for 256 types of characters.

When the sprite character consists of two characters, only an even-numbered character code can be set.

• Sprite chara ct er color

Sprite character control 1 (Command 8-0): Bits SC3 to SC0

One of 16 colors can be set.

• Sprite character trimming color

Sprite character control 1 (Command 8-0): Bits SF3 to SF0

One of 16 colors can be set.

SDS Sprite character output

0OFF

1ON

AAAAAAAAAAAAAAAAAAAAA

AASAAAAAAAAAAAAAAAAAA

AAAAAAAAAAAAAAAAAAAAA

Sprite character

(displayed in the L size)

MB90097

• Sprite character trimming contr ol

Sprite character control 1 (Command 8-0): Bits SFB and SFA

• Sprite character vertical display position control

Sprite character control 4 (Command 9-0): Bits SY9 to SY0

Settabl e betwee n 0 and 1023 dots in 1- dot units.

• Sprite character horizontal display position control

Sprite character control 5 (Command 9-1): Bits SX9 to SX0

Settabl e betwee n 0 and 1023 dots in 1- dot units.

• Sprite character configuration control

Sprite character control 2 (Command 8-1): Bits SD1 and SD0

• Sprite character configuration example

SFB SFA Sprite character trimming output

00Undisplay

0 1 Reserved (Setting prohibited)

1 0 Reserved (Setting prohibited)

1 1 Eight-directio n trimming

SD1 SD2 Sprite character configuration

0 0 1 character

0 1 Reserved (Setting prohibited)

1 0 Stack of 2 characters

1 1 Reserved (Setting prohibited)

n+1

Character code

• Sprite character code = n

Example of a 1-character sprite character (SD1, SD0) = (0, 0)

Example of a 2-character sprite character (SD1, SD0) = (1, 0)

MB90097

(3) Three-channel output control for sprite characters

When sprite character output is ON (SDS = 1), the sprite character outputs to output B and output C can be

controlled independently. (Output A is controlled only with the SDS bit.)

• Output-B sprite character output control

Screen output control 1B (Command 5-01): Bit SOB

• Output-C sprite character output control

Screen output control 1C (Command 5-02): Bit SOC

*1: When the lower layer has display output, that portion appear transparent.

(The lower layer cannot be displayed.)

*2: Enabled only when screen background color output is ON (SDS = 1).

SOB Output-B sprite character output

0OFF*1

1ON*2

SOC Output-C sprite character output

0OFF*1

1ON*2

MB90097

■CONTROL FUNCTIONS

1. Serial Command Contr ol

The MB90097 executes serial command/data transfer using the chip select (CS), serial clock (SCLK), and serial

data input (SIN) pins. The data transfer direction (MSB-first or LSB-first transfer) is selected under control of the

serial data input direction select (SDR) pin. The data length is 16 bits. If the CS pin goes High during transfer

with data less than 16 bits, command transfer is not guaranteed. Keeping the CS pin Lo w allo ws mult iple ite ms

of command data to be transferred continuously. (It is however recommended to set the CS pin to the High level

at intervals of tens of words for word synchronization.)

The SCLK clock frequency is 4 MHz at maximum. Set it such that: VRAM write cycle (a minimum of 16 clock

pulses) > input horizontal sync pulse width. If this condition is not satisfied, VRAM write may fail.)

(1) MSB-first signal input timing

DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DF

SCLK

SIN

SDR (Fixed at High)

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF D0

SDR (Fixed at Low)

SCLK

SIN

(2) LSB-first signal input timing

MB90097

2. Dot Clock Control

For the dot clock, you can select internal generation by the LC oscillator circuit or external input.

For the external input, you can select dot clock frequency direct input or frequency-doubled input.

Set bits DC2 to DC0 of command 11-2 (dot clock control 1) to select dot clock control.

• Dot clock selection control

Dot clock control 1 (Command 11-2: Bits DC2 to DC0)

(1) Dot clock LC oscillation

Connect the relevant pins to external “L” and “C” to form an LC oscillator circuit.

External input of a horizontal sync signal is used to internally perform oscillation stop control, enabling horizontal

display synchronization.

Note: The horizontal synchronization operation edge must be the trailing edge.

Set the horizontal synchronization operation edge (bit HE) of I/O pin control (command 13-0) to 0.)

DC2 DC1 DC0 Dot clock control

0 0 0 LC osci llation

0 1 0 External input (dot clock)

0 1 1 External input (2 × dot clock)

Else Setting prohibited

MB90097

XD EXD

MB90097

(2) External dot clock input

The MB90097 inputs a dot clock signal to the EXD pin.

Note: The input horizontal cycle must be synchronized in integer multiples of the input clock cycle.

The input clock signal must be a continuous signal without being intermitted.

(3) External “2 ×” (frequency-doubled) dot clock input

Input the 2 × (frequency-doubled) dot clock signal to the EXD pin.

Note: The input horizontal cycle must be synchronized in integer multiples of the input clock cycle.

The horizontal synchronization operation edge must be the trailing edge.

(Set the horizontal synchronization operation edge (bit HE) of I/O pin control (command 13-0) to 0.)

The input clock signal must be a continuous signal without being intermitted.

MB90097

XD EXD

Open Dot clock

MB90097

XD EXD

Open 2 ×

Dot clock

MB90097

3. Sync Signal Input

3. 1 Vertical Synchronization Detection

Vertical synchronization is detected by sensing the level of the vertical sync signal at the leading or trailing edge

of the horizontal sync pulse to detect the transition. The vertical display position on the screen depends on the

vertical synchronization detection position.

Use I/O pin control (command 13-0) to select operation control.

• Selecting a vertical synchronization detection edge • Selecting a vertical synchronization detection

HSYNC edge

Note: When VVE = 1,VHE = 1 and HE =1, the trailing edge of VSYNC is detected at the leading edge of HSYNC .

“HE” is the horizontal sync operation edge selection bit.

• Sync signal input logic control

• Principle of operation of detecting vertical synchronization

(Example with sync signal input logic SIX = 0)

(1) Detecting the leading edge of the vertical sync pulse at the leading edge of the horizontal sync pulse

(VVE = 0, VHE = 0)

SIX Sync signal input logic

0 The HSY NC and VSYNC pins are active low inputs.

1 The HSY NC and VSYNC pins are active high inputs.

VVE Vertical synchronization

detection edge

0 Detect the leading edge of VSYNC.

1 Detect the trailing edge of VSYNC.

VHE Vertical synchronization detection

HSYNC edge

0Detect vertical synchronization at the

leading edge of HSYNC.

1Detect vertical synchronization at the

trailing edge of HSYNC.

HSYNC input

Internally detected VSYNC

VSYNC input

1H pulse generated

Synchronization detected position

MB90097

(2) Detecting the leading edge of the vertical sync pulse at the trailing edge of the horizontal sync pulse

(VVE = 0, VHE = 1)

VSYNC input

HSYNC input

Internally detected VSYNC

VSYNC input

HSYNC input

Internally detected VSYNC

VSYNC input

HSYNC input

Internally detected VSYNC

1H pulse generated

Synchronization detected position

(3) Detecting the trailing edge of the vertical sync pulse at the leading edge of the horizontal sync pulse

(VVE = 1, VHE = 0) or (VVE = 1, VHE = 1, HE = 1)

(4) Detecting the trailing edge of the vertical sync pulse at the trailing edge of the horizontal sync pulse

(VVE = 1, VHE = 1, HE = 0)

MB90097

3. 2 Operation in Horizontal Synchronization

(1) Operation with dot clock LC oscillation

The sync pulse of the input horizontal sync signal is used to control the oscillation and stop of the dot clock,

enabling display horizontal synchronization.

Bit HE (horizontal synchronization operation edge) of I/O pin control (command 13-0) must be set to “0”.

• Operation example of horizontal synchronization

HSYNC input

LC oscillation

dot clock input

(EXD pin)

Internal HSYNC

Internal dot clock

8 to 12 clock

Clock stop period

Horizontal synchronization position

(Reference display position)

MB90097

(2) Operation with external dot clock input

You can select horizontal sync leading-edge or trailing-edge operation.

• Horizontal synchronization operation edge selection

I/O pin control (Command 13-0): Bit HE

• Examples of horizontal synchronization operations

HE Horizont al synchr onization ope ration edge

0 Trailing-edge operation

1 Leading-edge operation

HSYNC input

Dot clock input

Internal HSYNC

Internal dot clock

8 to 12 clock

Clock stop period

Horizontal synchronization position

(Reference display position)

HSYNC input

Dot clock input

Internal HSYNC

Internal dot clock

8 to 12 clock Clock stop period

Horizontal synchronization position

(Reference display position)

About 16 clock

(a) Horizontal syznc trailing-edge operation (HE = 0)

(b) Horizontal sync leading-edge operation (HE = 1)

MB90097

3. 3 Vertical Blanking Control

Vertical blanking control is used to internally generate the vertical blanking interval for display signal output

control.

Displa y si ngn al outp ut is sto ppe d duri ng the ve rtic al bla nk ing inter va l.

Vertical blanking control results in either of the following two operations depending on the setting of bit VVE

(vertical synchronization detection edge selection control) of I/O pin control (command 13-0).

About 17H

VSYNC input

Vertical blanking interval

About 14H

VSYNC input

Vertical blanking interval

(2) Operation of vertical sync trailing-edge detect ion

(1) Operation of vertical sync leading-edge detection

MB90097

3. 4 Horizontal Blanking Control

Horizontal blanking control is used to generate the horizontal blanking interval for display signal output control.

Display signal output is stopped during the horizontal blanking interval.

Horizontal blanking control can be set for the back porch or front porch by command control.

Horizontal blanking control results in either of the following two operations depending on the setting of bit HE

(horizontal synchronization operation edge selection control) of I/O pin control (command 13-0).

• Horizontal blanking (back porch) control

Horizontal blanking control 1 (Command 13-1): Bits BB5 to BB0

Setting between 0 and 126 dots in 2-dot units.

• Horizontal blanking (front porch) control

Horizontal blanking control 2 (Command 13-2): Bits BF8 to BF0

Setting between 0 and 1022 dots in 2-dot units.

Notes: • The back porch must be shorter than the front porch. Do not make any other setting.

• The ac tual hori zontal blanking interval is o ffset f rom th e set value by several tens of d ots i n the p ositive

direction.

Front porch

HSYNC input

Horizontal blanking interval

Back porch

Front porch

HSYNC input

Horizontal blanking interval

Back porch

(2) When the horizontal synchronization operation edge is the leading edge (bit HE = 1)

(1) When the horizontal synchronization operation edge is the trailing edge (bit HE = 0)

MB90097

4. Display Signal Output

4. 1 Three-Channel Output Control

(1) Display control bits and control ranges

The following chart summarizes the relationships among display control and three-channel output control bits.

• If character display of a character is turned OFF by bits OA2-OA0, OB2-OB0, OC2-OC0, or MO1, MO0, the

character (including its trimming and character background) is displayed transparent, including the

corresponding portion of the lower layer (line and screen backgrounds).

• If line background display is turned OFF by bit BLB, the line background and the corresponding portion of the

screen background display layer are displayed transparent.

• If line background display is turned OFF by bit BLC, the line background and the corresponding portion of the

screen background display layer are displayed transparent.

• If screen background display is turned OFF by bit BGB, the screen background display layer is displayed

transparent.

• If screen background display is turned OFF by bit BGC, the screen background display layer is displayed

transparent.

• If sprite character display is turned OFF by bit SCB, the sprite character (including its trimming) and the

corresponding portions of all lower layers are displayed transparent.

• If sprite character display is turned OFF by bit SCC, the sprite character (including its trimming) and the

corresponding portions of all lower layers are displayed transparent.

Character

background

MM1, MM0

Line background

LM1, LM0 BLB BLC

Screen background

UDS BGCBGB

Sprite character

SDS SOB SOC

OA2 to OA0,

MO1, MO0 OB2 to OB0,

MO1, MO0 OC2 to OC0,

MO1, MO0

DSP

LDS

Display output control

Line character output control

Character background control

Line background control

Screen background output control

Sprite character output control

A-channel output B-channel output C-channel output

MB90097

(2) Output-A/B/C control

The character attributes (character, trimming, and character background) of each character can be displayed

by three-channel (A/B/C) output control.

Commands 5-00 to 5-02 are used for output control for each screen; command 2 is used for output control for

each character.

When trimming dots for a character are displayed protruding to the area for an adjacent character, the output

of the trimming dots is controlled by the character output control of that adjacent character. Three-channel output

control for each character serves as output control within the character area (12 × 18 dots for normal-sized

characters).

If there are trimming dots to the left of the leftmost character on a line, they cannot be controlled by three-channel

output control. In this case, place a blank character at the left end of the line and set characters to be displayed

to the right.

When trimming dots are displayed to the right of the rightmost character on a line, the three-channel output

control of the trimming dots depends on the character output control of the rightmost character.

• Output-A character control

Screen output control 1A (Command 5-00):Bits OA2 to OA0

Settable, selected from among eight types.

• Output-B character control

Screen output control 1B ( Command 5-01): Bits OB2 to OB0

Settable, selected from among eight types.

• Output-C character control

Screen output control 1C (Command 5-02): Bits OC2 to OC0

Settable, selected from among eight types.

• Character output control

Character data setting 2 (Command 2): Bits MO1 and MO0

Settable, selected from among four types for each character.

: Display ON

× : Display OFF

(Continued)

Output-A/B/C character control Character output control Output (Pin output)

OA2

OB2

OC2

OA1

OB1

OC1

OA0

OB0

OC0

MO1 MO0 Output-A (BLKA pin output)

Output-B (BLKB pin output)

Output-C (BLKC pin output)

000

×All display OFF

01×

11×

001

00 All display ON

MB90097

(Continued )

: Display ON

× : Display OFF

Output-A/B/C character control Character output control Output (Pin output)

OA2

OB2

OC2

OA1

OB1

OC1

OA0

OB0

OC0

MO1 MO0 Output-A (BLKA pin output)

Output-B (BLKB pin output)

Output-C (BLKC pin output)

010

×Display ON for only characters with

MO0 = 1

011

×Display ON for only characters with

MO1 = 1

01×

100

×Display ON for only characters with

MO0 = 1 or MO1 = 1

101

00 Display ON for only characters with

MO0 = 0

01×

110

00 Display ON for only characters with

MO1 = 0

11×

111

00 Display ON for only characters with

MO0 = 0 or MO1 = 0

01×

10×

11×

MB90097

4. 2 Display Signal Output Timings

Display signals are output as shown below.

• Output cha nnel-A displ ay peri od si gna l: BLK A pin

• Output cha nnel-B displ ay peri od si gna l: BLK B pin

• Output channel-C display period signal: BLKC pin

• Color code signals: VC3 t o VC0 pi n

• Display signal output example

Notes: The settings for the above display are as follows:

• Output A: All items are output (with screen background output).

• Output B: Only character attributes are output.

• Output C: Output OFF

• Color settings: Character color code: 1

Trimming color code: 2

Character background color code: 3

Screen bac kg ro und colo r code : 4

Trimming color Trimming color

Screen

background

color

Character

background

color

Character

color Character

background

color

Screen

background

color

(4) (4)(3) (3)(2) (2)(1)

Displayed character

Display color

VC3-0 output

(Color code)

BLKA output

BLKB output

BLKC output

HIGH level

LOW level

Display line

MB90097

■CONTENTS OF MB90097-001 (STANDARD PRODUCT) FONT ROM

(Continued)

MB90097

(Continued)

MB90097

■ORDERING INFORMATION

Part number Package Remarks

MB90097-PFV 20-pin plastic SSOP

(FPT-20P-M03)

MB90097

■PACKAGE DIMENSION

1999 FUJITSU LIMITED F20012S-3C-5

6.50±0.10(.256±.004)

4.40±0.10 6.40±0.20

(.252±.008)(.173±.004)

.049

–.004

+.008

–0.10

+0.20

1.25 (Mounting height)

0.10(.004)

0.65(.026) 0.24±0.08

(.009±.003)

1 10

20 11

"A"

0.10±0.10 (Stand off)

0.17±0.03

(.007±.001)

0.13(.005)

(.004±.004)

Details of "A" part

0~8°

(.018/.030)

0.45/0.75

(.020±.008)

0.50±0.20

0.25(.010)

LEAD No.

INDEX

20-pin plastic SSOP

(FPT-20P-M03)

Dimensions in mm (inches).

* : These dimensions do not include resin protrusion.

MB90097

MEMO

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen,

Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

206 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://www.fmk.fujitsu.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD.

151 Lorong Chuan, #05-08 New Tech Park,

Singapore 556741

Tel: +65-6281-0770 Fax: +65-6281-0220

http://www.fujitsu.com/sg/services/micro/semiconductor/

FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.

Rm.3102, Bund Center, No.222 Yan An Road(E),

Shanghai 200002, China

Tel: +86-21-6335-1560 Fax: +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road

Tsimshatsui, Kowloon

Hong Kong

Tel: +852-2377-0226 Fax: +852-2376-3269

http://cn.fujitsu.com/fmc/tw

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-

ing the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS

or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or

other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result from the use of information contained herein.

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limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect

to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in

nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in

weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising

in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

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The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited Strategic Business Development Dept.