AAT3244ITP-AA-T1 - AnalogicTech

AAT3244

300mA Adjustable Dual CMOS

Low Voltage LDO Linear Regulator

3244.2007.08.1.1 1

PowerLinear™

General Description

The AAT3244 is a dual, low input voltage, low

dropout (LDO) linear regulator with two Power OK

(POK) outputs. Two integrated regulators provide

high power outputs of 300mA from an input voltage

range of 1.8V to 5.5V.

Two POK pins provide open drain signals when

their respective regulator is within regulation. The

AAT3244 has independent voltage inputs and

enable pins for increased design flexibility. The

device features a very low quiescent current (typi-

cally 85µA) and low dropout voltages (200mV at

full load), making it ideal for portable applications

where battery life is critical.

The AAT3244 is available in a space-saving, Pb-free

12-pin TSOPJW package and is capable of opera-

tion over the -40°C to +85°C temperature range.

Features

• Low Input Voltage

— 1.8V to 5.5V

• Ultra-Low Adjustable Output Voltage

— 3.6V to 0.6V

• High Output Current

— 300mA per LDO

• Low Dropout Voltage

— Typ 200mV @ 300mA

• Low 85µA Quiescent Current (Both LDOs On)

• High Output Accuracy: ±1.5%

• Independent Input Supply and Enable Pins

• Over-Temperature Protection

• 12-Pin TSOPJW Package

• -40°C to +85°C Temperature Range

Applications

• Cellular Phones

• Digital Cameras

• Handheld Instruments

• Microprocessor/DSP Core/IO Power

• PDAs and Handheld Computers

Typical Application

INA

ENA

OUTA

Enable A

= 3.6V

GND

ENB

Enable B

INB OUTB

OUTA

= 1.8V

OUTB

= 3.3V

2.2μF

1μF

GND

FBB

FBA

POKA POKA

VCC

POKB

2.2μF

59kΩ

100kΩ

100kΩ267kΩ

118kΩ

59kΩ

Pin Descriptions

Pin Configuration

TSOPJW-12

(Top View)

Pin # Symbol Function

1 OUTA 300mA regulator output pin; should be closely decoupled with a low equivalent series

resistance (ESR) ceramic capacitor.

2 INA Input voltage pin for LDOA; should be closely decoupled.

3 FBA Feedback input pin for LDOA. This pin is connected to OUTA. It is used to see the output

of LDOA to regulate to the desired value via an external resistor divider.

4 FBB Feedback input pin for LDOB. This pin is connected to OUTB. It is used to see the output

of LDOB to regulate to the desired value via an external resistor divider.

5 INB Input voltage pin for LDOB; should be closely decoupled.

6 OUTB 300mA regulator output pin; should be closely decoupled with a low ESR ceramic

capacitor.

7 POKB Power OK pin with open drain output. It is pulled low when the OUTB pin is outside the

regulation window of ±10%. Place a pull-up resistor between POKB and OUTB.

8 ENB Enable pin for LDOB. Active high. VEN must be less than or equal to VCC.

9 VCC Input bias supply. Connect to an "always ON" supply voltage between 2.7V and 5.5V.

10 GND Ground connection pin.

11 ENA Enable pin for LDOA. Active high. VEN must be less than or equal to VCC.

12 POKA Power OK pin with open drain output. It is pulled low when the OUTA pin is outside the

regulation window of ±10%. Place a pull-up resistor between POKA and OUTA.

OUTA

INA

FBA

FBB

INB

OUTB

POK

ENA

GND

VCC

ENB

POKB

AAT3244

300mA Adjustable Dual CMOS

Low Voltage LDO Linear Regulator

23244.2007.08.1.1

Absolute Maximum Ratings1

Thermal Information

Symbol Description Value Units

PDMaximum Power Dissipation (TA= 25°C) 625 mW

θJA Thermal Resistance2160 °C/W

Symbol Description Value Units

VCC, VIN Input Voltage, LDO Input Voltage to GND 6.0 V

VFB FB to GND -0.3 to VIN + 0.3 V

VEN EN to GND -0.3 to 6.0 V

TJOperating Junction Temperature Range -40 to 150 °C

TLEAD

Maximum Soldering Temperature (at leads, 300 °C

10 sec)

AAT3244

300mA Adjustable Dual CMOS

Low Voltage LDO Linear Regulator

3244.2007.08.1.1 3

1. Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at condi-

tions other than the operating conditions specified is not implied. Only one Absolute Maximum Rating should be applied at any one time.

2. Mounted on an FR4 board.

Electrical Characteristics1

VCC = VINA = VINB = 3.6V; TA= -40°C to +85°C, unless otherwise noted. Typical values are TA= 25°C.

Symbol Description Conditions Min Typ Max Units

Bias Power Supply

VCC Bias Power Supply Input 2.7 5.5 V

IQQuiescent Current VENA = VENB = VIN; ILOAD = 0 85 160 µA

ISHDN Shutdown Current VENA = VENB = GND 1.0 µA

UVLO Under-Voltage Lockout Voltage VCC Rising 2.6 V

Hysteresis 200 mV

LDOA, LDOB; IOUT = 300mA

VIN Input Voltage 1.8 5.5 V

VOUT Output Voltage Tolerance IOUT = 1mA TA= 25°C -2.0 2.0 %

to 300mA TA= -40°C to +85°C -3.5 3.5

VFB Feedback Voltage 0.594 0.6 0.606 V

VDO Dropout Voltage2IOUT = 300mA 200 300 mV

ΔVOUT/

VOUT /ΔVIN

Line Regulation3VIN = VOUT + 1.0V to 5.0V 0.09 %/V

VEN(L) Enable Threshold Low 0.6 V

VEN(H) Enable Threshold High 1.5 VCC V

tEN Turn-On Enable Time 100 µs

VPOK Power OK Trip Threshold VOUT Rising, TA= 25°C 80 98 % of VOUT

VPOKHYS Power OK Hysteresis 1.0 % of VOUT

VPOK(LO) Power OK Output Voltage Low ISINK = 1mA 0.4 V

IPOK POK Output Leakage Current VPOK < 5.5V, VOUT in Regulation 1.0 µA

IOUT Output Current VIN(MIN) = 2.5V 300 mA

ISD Shutdown Current VIN = 5V 1.0 µA

TSD

Over-Temperature Shutdown 140 °C

Threshold

THYS

Over-Temperature Shutdown 15 °C

Hysteresis

AAT3244

300mA Adjustable Dual CMOS

Low Voltage LDO Linear Regulator

43244.2007.08.1.1

1. The AAT3244 is guaranteed to meet performance specifications over the -40°C to +85°C operating temperature range and is assured

by design, characterization, and correlation with statistical process controls.

2. VDO is defined as VIN - VOUT when VOUT is 98% of nominal.

3. CIN = 10µF.

4. To calculate minimum input voltage, use the following equation: VIN(MIN) = VOUT(MAX) + VDO(MAX) as long as VIN ≥ 1.8V.

Typical Characteristics

Output Voltage vs. Temperature

= 3.6V; V

OUT

= 2.5V)

Temperature (°C)

Output Voltage (V)

2.42

2.44

2.46

2.48

2.50

2.52

2.54

2.56

2.58

2.60

-40 -15 10 35 60 85

100mA

200mA

50mA

300mA

Quiescent Current vs. Temperature

OUT

= 2.5V)

Temperature (°C)

Quiescent Current (µA)

-40 -15 10 35 60 85

= 3.0V

= 3.6V

= 4.2V

Quiescent Current vs. Input Voltage

OUT

= 2.5V)

Input Voltage (V)

Quiescent Current (µA)

100

110

120

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.

-40°C

85°C 25°C

Dropout Voltage vs. Output Current

OUT

= 2.5V)

Output Current (mA)

Dropout Voltage (mV)

100

120

140

160

180

0 50 100 150 200 250 300

25°C

85°C

-40°C

Output Voltage vs. Input Voltage

OUT

= 2.5V)

Input Voltage (V)

Output Voltage (V)

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

2.60

2.5 2.6 2.7 2.8 2.9 3.0

300mA

250mA

200mA

150mA

50mA

100mA

Dropout Voltage vs. Temperature

OUT

= 2.5V; I

OUT

= 300mA)

Temperature (°C)

Dropout Voltage (mV)

100

120

140

160

180

200

220

-40 -15 10 35 60 85

AAT3244

300mA Adjustable Dual CMOS

Low Voltage LDO Linear Regulator

3244.2007.08.1.1 5

Typical Characteristics

Line Transient

(3.6V– 4.2V; VOUT = 1.8V)

Time (50µs/div)

Input Voltage (top) (V)

Output Voltage (AC coupled)

(bottom) (mV)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

-100

-50

100

Over-Current Protection

Time (50ms/div)

Current (A)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Load Transient

(1mA–200mA; V

OUT

= 1.8V)

Time (50µs/div)

Output Current (top) (A)

Output Voltage (AC coupled)

(bottom) (mV)

0.0

0.1

0.2

0.3

100

150

-100

-50

Load Transient

(200mA–300mA; V

OUT

= 1.8V)

Time (50µs/div)

Output Current (top) (A)

Output Voltage (AC coupled)

(bottom) (mV)

0.0

0.1

0.2

0.3

0.4

-50

-25

Load Regulation

OUT

= 2.5)

Output Current (mA)

Output Voltage Error (%)

0.00

0.50

1.00

1.50

2.00

-2.00

-1.50

-1.00

-0.50

0 1 10 100 100

= 2.7V V

= 3.0V

= 3.6V

= 4.2V

Turn-On Time

OUT

= 1.8V)

Time (50µs/div)

Enable (top) (V)

Output Voltage (bottom) (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

AAT3244

300mA Adjustable Dual CMOS

Low Voltage LDO Linear Regulator

63244.2007.08.1.1

AAT3244

300mA Adjustable Dual CMOS

Low Voltage LDO Linear Regulator

3244.2007.08.1.1 7

Typical Characteristics

Ground Current vs. Input Voltage

Input Voltage (V)

Ground Current (µA)

100

110

120

130

2.5 3 3.5 4 4.5 5 5.5

OUT

= 10mA

OUT

= 50mA

OUT

= 100mA

OUT

= 300mA

POK Output Response

Time (200µs/div)

OUT

(1V/div)

(2V/div)

POK

(2V/div)

Enable Threshold Voltage vs. Input Voltage

Input Voltage (V)

Enable Voltage (V)

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.

AAT3244

300mA Adjustable Dual CMOS

Low Voltage LDO Linear Regulator

83244.2007.08.1.1

Functional Block Diagram

INA

OUTB

GND

OUTA

INB

FBB

FBA

ENA

ENB

Over-Temperature

Protection

Voltage

Reference

94%

POKA

POKB

VCC

LDO

Bias

Functional Description

The AAT3244 is a high performance, low input volt-

age, dual LDO linear regulator. Both LDOA and

LDOB are capable of delivering 300mA of current,

within power dissipation limits. The LDOs are

designed to operate with low-cost ceramic capaci-

tors. For added flexibility, both regulators have

independent input voltages operating from 1.8V to

5.5V, but share a common bias voltage, VCC. The

VCC voltage should be tied to the highest system

voltage available and should be available at all

times. Each regulator has an independent enable

pin. An external feedback pin for each LDO allows

programming the output voltage from 3.6V to 0.6V.

The regulators have thermal protection in case of

adverse operating conditions.

A power OK comparator for each output is also

integrated, which indicates when the output is with-

in regulation. The POK is an open drain output and

is held low when the AAT3244 is in shutdown

mode.

Refer to the Thermal Considerations section of this

datasheet for details on device operation at maxi-

mum output current loads.

AAT3244

300mA Adjustable Dual CMOS

Low Voltage LDO Linear Regulator

3244.200708.0.66 (ADVANCED INFORMATION) 9

Applications Information

To assure the maximum possible performance is

obtained from the AAT3244, please refer to the fol-

lowing application recommendations.

Input Capacitor

A 1µF or larger capacitor is typically recommended

for CIN in most applications. A CIN capacitor is not

required for basic LDO regulator operation; howev-

er, if the AAT3244 is physically located more than

three centimeters from an input power source, a

CIN capacitor will be needed for stable operation.

CIN should be located as closely to the device sup-

ply pin as practically possible. CIN values greater

than 1µF will offer superior input line transient

response and will assist in maximizing the highest

possible power supply ripple rejection.

Ceramic, tantalum, or aluminum electrolytic capac-

itors may be selected for CIN. There is no specific

capacitor ESR requirement for CIN; however, for

300mA LDO regulator output operation, ceramic

capacitors are recommended for CIN due to their

inherent capability over tantalum capacitors to with-

stand input current surges from low impedance

sources, such as batteries in portable devices.

Output Capacitor

For proper load voltage regulation and operational

stability, a capacitor is required between pins OUT

and GND. The COUT capacitor connection to the

LDO regulator ground pin should be made as

direct as practically possible for maximum device

performance.

The AAT3244 has been specifically designed to func-

tion with very low ESR ceramic capacitors. For best

performance, ceramic capacitors are recommended.

Typical output capacitor values for maximum out-

put current conditions range from 1µF to 10µF.

Applications requiring low output noise and opti-

mum power supply ripple rejection should use

2.2µF or greater for COUT. If desired, COUT may be

increased without limit. In low output current appli-

cations where output load is less than 10mA, the

minimum value for COUT can be as low as 0.47µF.

Capacitor Characteristics

Ceramic composition capacitors are highly recom-

mended over all other types of capacitors for use

with the AAT3244. Ceramic capacitors offer many

advantages over their tantalum and aluminum elec-

trolytic counterparts. A ceramic capacitor typically

has very low ESR, is lower cost, has a smaller PCB

footprint, and is non-polarized. Line and load tran-

sient response of the LDO regulator is improved by

using low ESR ceramic capacitors. Since ceramic

capacitors are non-polarized, they are not prone to

incorrect connection damage.

Equivalent Series Resistance

ESR is a very important characteristic to consider

when selecting a capacitor. ESR is the internal

series resistance associated with a capacitor that

includes lead resistance, internal connections,

size and area, material composition, and ambient

temperature.

Typically, capacitor ESR is measured in milliohms

for ceramic capacitors and can range to more than

several ohms for tantalum or aluminum electrolytic

capacitors.

Ceramic Capacitor Materials

Ceramic capacitors less than 0.1µF are typically

made from NPO or C0G materials. NPO and C0G

materials generally have tight tolerance and are

very stable over temperature. Larger capacitor val-

ues are usually composed of X7R, X5R, Z5U, or

Y5V dielectric materials. These two material types

are not recommended for use with LDO regulators

since the capacitor tolerance can vary more than

±50% over the operating temperature range of the

device. A 2.2µF Y5V capacitor could be reduced to

1µF over temperature; this could cause problems

for circuit operation. X7R and X5R dielectrics are

much more desirable. The temperature tolerance

of X7R dielectric is better than ±15%. Capacitor

area is another contributor to ESR. Capacitors

AAT3244

300mA Adjustable Dual CMOS

Low Voltage LDO Linear Regulator

10 3244.2007.08.1.1

which are physically large in size will have a lower

ESR when compared to a smaller sized capacitor

of an equivalent material and capacitance value.

These larger devices can improve circuit transient

response when compared to an equal value capac-

itor in a smaller package size. Consult capacitor

vendor datasheets carefully when selecting capac-

itors for LDO regulators.

POK Output

The AAT3244 features integrated Power OK com-

parators which can be used as an error flag. The

POK open drain output goes low when output volt-

age is 6% (typical) below its nominal regulation

voltage. Additionally, any time one of the regulators

is in shutdown, the respective POK output is pulled

low. Connect a 100kΩpull up resistor from POKA

to either INA or OUTA, and POKB to either INB or

OUTB.

Enable Function

The AAT3244 features an LDO regulator enable/ dis-

able function. Each LDO has its own dedicated

enable pin. These pins (ENA, ENB) are active high

and are compatible with CMOS logic. To assure the

LDO regulators will switch on,

In shutdown, the AAT3244 will consume less than

1.0µA of current. If the enable function is not needed

in a specific application, it may be tied to VCC to

keep the LDO regulator in a continuously on state.

Thermal Protection

The AAT3244 has an internal thermal protection cir-

cuit which will activate when the device die temper-

ature exceeds 140°C. The LDO regulator output will

remain in a shutdown state until the internal die

temperature falls back approximately 15°C below

the trip point.

No-Load Stability

The AAT3244 is designed to maintain output volt-

age regulation and stability under operational no-

load conditions. This is an important characteristic

for applications where the output current may drop

to zero.

Reverse Output-to-Input Voltage

Conditions and Protection

Under normal operating conditions, a parasitic

diode exists between the output and input of the

LDO regulator. The input voltage should always

remain greater than the output load voltage, main-

taining a reverse bias on the internal parasitic

diode.

Conditions where VOUT might exceed VIN should be

avoided since this would forward bias the internal

parasitic diode and allow excessive current flow

into the OUTA/B pins, possibly damaging the LDO

regulator. In applications where there is a possibil-

ity of VOUT exceeding VIN for brief amounts of time

during normal operation, the use of a larger value

CIN capacitor is highly recommended. A larger

value of CIN with respect to COUT will result in a

slower CIN decay rate during shutdown, thus pre-

venting VOUT from exceeding VIN. In applications

where there is a greater danger of VOUT exceeding

VIN for extended periods of time, it is recommend-

ed to place a Schottky diode across INA/B to

OUTA/B (connecting the cathode to INA/B and

anode to OUTA/B). The Schottky diode forward

voltage should be less than 0.45V.

Low Voltage Input Bias Considerations

The input voltage of both LDOs is designed to

operate down to 1.8V input. However, to operate

the LDO to its full potential, the AAT3244 requires

a minimum bias voltage (VCC) of 2.7V for all LDO

input voltages between 1.8V and 2.7V. In portable

systems utilizing single-cell Lithium-ion batteries,

the VCC pin may be connected directly to the bat-

tery. In non-portable applications, the voltage can

be connected to any supply from 2.7V to 5.5V. In

the event that one of the input supplies is above

2.7V, this can also be connected to VCC, assuming

that the supply will always be available.

1.5V ≤ V

≤ V

AAT3244

300mA Adjustable Dual CMOS

Low Voltage LDO Linear Regulator

3244.2007.08.1.1 11

Adjustable Output Resistor Selection

Resistors R1, R2 and R3, R4 of Figure 1 program

the outputs to regulate at a voltage higher than

0.6V. To limit the bias current required for the exter-

nal feedback resistor string while maintaining good

noise immunity, the suggested value for R2 and R4

is 59kΩ. Decreased resistor values are necessary

to maintain noise immunity on the FB pin, resulting

in increased quiescent current. Table 1 summarizes

the resistor values for various output voltages.

With enhanced transient response for extreme

pulsed load application, an external feed-forward

capacitor, (C6 and C7 in Figure 1), can be added.

Table 1. Adjustable Resistor Values For LDO

Regulator.

R2 = 59kΩR2 = 221kΩ

VOUT (V) R1 (kΩ) R1 (kΩ)

0.8 19.6 75

0.9 29.4 113

1.0 39.2 150

1.1 49.9 187

1.2 59.0 221

1.3 68.1 261

1.4 78.7 301

1.5 88.7 332

1.8 118 442

1.85 124 464

2.0 137 523

2.5 187 715

3.3 267 1000

3.6 295 1105

⎛⎞

⎝⎠

R1 = - 1

OUT

REF

Figure 1: AAT3244 Schematic.

TSOPJW-12

POKA

POKB

OUT

OUT B

INA

POKA

ENA

POKB

INB

OUT A

OUT B

1uF

22pF

GND

AAT3244

INA

ENB

ENA

ENB

VCC

FBA

FBB

VCC

2.2uF

INB

ON/OFF

100K

Adj.

59K

Adj.

59K

(Optional)

AAT3244

300mA Adjustable Dual CMOS

Low Voltage LDO Linear Regulator

12 (ADVANCED INFORMATION) 3244.200708.0.66

Thermal Considerations and High

Output Current Applications

The AAT3244 is designed to deliver continuous out-

put load currents of 300mA under normal operating

conditions and can supply up to 600mA during circuit

start-up conditions. This is desirable for applications

where there might be a brief high inrush current dur-

ing a power-on event. The limiting characteristic for

the maximum output load current safe operating

area is essentially package power dissipation and

the internal preset thermal limit of the device. In

order to obtain high operating currents, careful

device layout and circuit operating conditions need

to be taken into account. The following discussions

will assume the LDO regulator is mounted on a print-

ed circuit board utilizing the minimum recommended

footprint as stated in the layout considerations sec-

tion of this document. At any given ambient temper-

ature (TA), the maximum package power dissipation

can be determined by the following equation:

Constants for the AAT3244 are TJ(MAX) (the maxi-

mum junction temperature for the device, which is

125°C) and θJA = 160°C/W (the package thermal

resistance). Typically, maximum conditions are cal-

culated at the maximum operating temperature of

TA= 85°C and under normal ambient conditions

where TA= 25°C. Given TA= 85°C, the maximum

package power dissipation is 250mW. At TA=

25°C, the maximum package power dissipation is

625mW. The maximum continuous output current

for the AAT3244 is a function of the package power

dissipation and the input-to-output voltage drop

across the LDO regulator. To determine the maxi-

mum output current for a given output voltage, refer

to the following equation. This calculation accounts

for the total power dissipation of the LDO regulator,

including that caused by ground current.

This formula can be solved for IOUTA to determine

the maximum output current for LDOA:

The following is an example for a 2.5V output:

VOUTA = 2.5V

VOUTB = 1.5V

IOUTB = 150mA

VIN = 4.2V

IGND = 125µA

IOUTA(MAX) = 129mA

From the discussion above, PD(MAX) was deter-

mined to equal 625mW at TA= 25°C.

Therefore, with Regulator B delivering 150mA at

1.5V, Regulator A can sustain a constant 2.5V out-

put at a 129mA load current at an ambient temper-

ature of 25°C. Higher input-to-output voltage differ-

entials can be obtained with the AAT3244, while

maintaining device functions within the thermal

safe operating area. To accomplish this, the device

thermal resistance must be reduced by increasing

the heat sink area or by operating the LDO regula-

tor in a duty-cycled mode.

For example, an application requires VIN = 4.2V

while VOUTA = 1.5V at a 300mA load, VOUTB = 1.5V

at a 200mA load, and TA= 25°C. To maintain this

high input voltage and output current level, the

LDO regulator must be operated in a duty-cycled

mode.

Refer to the following calculation for duty-cycle

operation:

IGND = 125μA

IOUTA = 300mA

IOUTB = 200mA

VIN = 4.2V

VOUT = 1.5V

PD(MAX) is assumed to be 625mW

%DC = 46.3%

%DC = 100(P

D(MAX)

)

[(V

- V

OUTA

+ (V

· I

GND

)] + [(V

- V

OUTB

+ (V

· I

GND

)]

%DC = 100 · 625mW

[(4.2V - 1.5V)300mA + (4.2V · 125µA)] + [(4.2V - 1.5V)200mA + (4.2V · 125µA)]

OUTA(MAX)

= 625mW - (2 · 4.2V · 125µA) - (4.2 - 1.5) · 150m

4.2 - 2.5

OUTA(MAX)

= P

D(MAX)

- (2 · V

· I

GND

) - (V

- V

OUTB

) · I

OUTB

- V

OUTA

D(MAX)

= [(V

- V

OUTA

+ (V

· I

GND

)] + [(V

- V

OUTB

+ (V

· I

GND

)]

D(MAX)

= T

J(MAX)

- T

AAT3244

300mA Adjustable Dual CMOS

Low Voltage LDO Linear Regulator

3244.2007.08.1.1 13

For a 300mA output current and a 2.7V drop across

the AAT3244 at an ambient temperature of 25°C,

the maximum on-time duty cycle for the device

would be 46.3%.

Under-Voltage Lockout

Under-voltage lockout (UVLO) guarantees suffi-

cient VCC bias and proper operation of all internal

circuits prior to activation.

Printed Circuit Board Layout

Recommendations

The suggested PCB layout for the AAT3244 in a

TSOPJW-12 package is shown in Figures 2 and 3.

The following guidelines should be used to help

ensure a proper layout.

1. The input capacitors (C1and C2) should con-

nect as closely as possible to input pins (Pin 2

and Pin 5) and GND (Pin 10).

2. The output traces of the feedback resistors (R1

and R3) should be separate from any power

trace and connect as closely as possible to the

load point. Sensing along a high-current load

trace will degrade DC load regulation. Feedback

resistors should be placed as closely as possible

to the FB pin (Pin 3 and Pin 4) to minimize the

length of the high impedance feedback trace.

4. The resistance of the trace from the load returns

to GND (Pin 10) should be kept to a minimum.

This will help to minimize any error in DC regu-

lation due to differences in the potential of the

internal signal ground and the power ground.

5. The feedback node is connected directly to the

non-inverting input of the error amplifier, thus

any noise or ripple from the divider resistors

will be subsequently amplified by the gain of

the error amplifier. This effect can increase

noise seen on the LDO regulator output, as

well as reduce the maximum possible power

supply ripple rejection. For low output noise

and highest possible power supply ripple rejec-

tion performance, it is critical to connect the

divider resistors (R2 and R4) and output

capacitors (C4 and C5) directly to the LDO reg-

ulator ground pin. This method will eliminate

any load noise or ripple current feedback

through the LDO regulator.

Evaluation Board Layout

The AAT3244 evaluation layout follows the recom-

mend printed circuit board layout procedures and

can be used as an example for good application

layouts (See Figures 2 and 3).

Note: Board layout shown is not to scale.

Figure 2: AAT3244 Evaluation Board Figure 3: AAT3244 Evaluation Board

Top Side Layout. Bottom Side Layout.

AAT3244

300mA Adjustable Dual CMOS

Low Voltage LDO Linear Regulator

14 3244.2007.08.1.1

Ordering Information

All AnalogicTech products are offered in Pb-free packaging. The term “Pb-free” means

semiconductor products that are in compliance with current RoHS standards, including

the requirement that lead not exceed 0.1% by weight in homogeneous materials. For more

information, please visit our website at http://www.analogictech.com/pbfree.

Voltage

Package LDO A LDO B Marking1Part Number (Tape and Reel)2

TSOPJW-12 0.6V 0.6V WTXYY AAT3244ITP-AA-T1

1. XYY = assembly and date code.

2. Sample stock is generally held on part numbers listed in BOLD.

Legend

Voltage Code

Adjustable A

(0.6V)

AAT3244

300mA Adjustable Dual CMOS

Low Voltage LDO Linear Regulator

3244.2007.08.1.1 15

Package Information

TSOPJW-12

All dimensions in millimeters.

0.20 + 0.10

- 0.05

0.055 ± 0.045 0.45 ± 0.15

7° NOM

4° ± 4°

3.00 ± 0.10

2.40 ± 0.10

2.85 ± 0.20

0.50 BSC 0.50 BSC 0.50 BSC 0.50 BSC 0.50 BSC

0.15 ± 0.05

0.9625

0.0375

1.00 + 0.10

- 0.065

0.04 REF

0.010

2.75 ± 0.25

Advanced Analogic Technologies, Inc.

830 E. Arques Avenue, Sunnyvale, CA 94085

Phone (408) 737-4600

Fax (408) 737-4611

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