SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347C – JANUARY 2001 – REVISED JANUAR Y 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus Family
D
UBT Transceiver Combines D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched,
Clocked, and Clock-Enabled Mode
D
TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
D
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
D
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
D
GTLP Buffered CLKAB Signal (CLKOUT)
D
LVTTL Interfaces Are 5-V Tolerant
D
Medium-Drive GTLP Outputs (50 mA)
D
LVTTL Outputs (–24 mA/24 mA)
D
GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
D
Ioff, Power-Up 3-State, and BIAS VCC
Support Live Insertion
D
Bus Hold on A-Port Data Inputs
D
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
The SN74GTLPH16916 is a medium-drive, 17-bit UBT transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, and clock-enabled modes
of data transfer . Additionally, it provides for a copy of CLKAB at GTLP signal levels (CLKOUT) and conversion
of a GTLP clock to LVTTL logic levels (CLKIN). The device provides a high-speed interface between cards
operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times
faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP’s reduced output swing
(<1 V), reduced input threshold levels, improved differential input, OECcircuitry, and TI-OPC circuitry.
Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using
several backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with
equivalent load impedance down to 19 Ω.
Copyright 2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI-OPC, UBT, and Widebus are trademarks of Texas Instruments.
DGG OR DGV PACKAGE
(TOP VIEW)
1
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OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
CLKIN
OEBA
LEBA
CEAB
CLKAB
B1
GND
B2
B3
BIAS VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VREF
B16
B17
GND
CLKOUT
CLKBA
CEBA
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347C – JANUARY 2001 – REVISED JANUARY 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLPH16916 is given only at the preferred higher noise-margin GTLP, but the
user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V
and VREF = 1 V) signal levels.
Normally , the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS V CC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly
terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This
improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However , to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
40°Cto85°C
TSSOP – DGG Tape and reel SN74GTLPH16916GR GTLPH16916
–
40°C
to
85°C
TVSOP – DGV Tape and reel SN74GTLPH16916VR GL916
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347C – JANUARY 2001 – REVISED JANUARY 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional description
The SN74GTLPH16916 is a medium-drive (50 mA), 17-bit UBT transceiver containing D-type latches and
D-type flip-flops for data-path operation in transparent, latched, clocked, or clock-enabled modes and can
replace any of the functions shown in Table 1. Data polarity is noninverting.
Table 1. SN74GTLPH16916 UBT Transceiver Replacement Functions
FUNCTION 8 BIT 9 BIT 10 BIT 16 BIT 18 BIT
Transceiver ’245, ’623, ’645 ’863 ’861 ’16245, ’16623 ’16863
Buffer/driver ’241, ’244, ’541 ’827 ’16241, ’16244, ’16541 ’16825
Latched transceiver ’543 ’16543 ’16472
Latch ’373, ’573 ’843 ’841 ’16373 ’16843
Registered transceiver ’646, ’652 ’16646, ’16652 ’16474
Flip-flop ’374, ’574 ’821 ’16374
Standard UBT ’16500, ’16501
Universal bus driver ’16835
Registered transceiver with clock enable ’2952 ’16470, ’16952
Flip-flop with clock enable ’377 ’823 ’16823
Standard UBT with clock enable ’16600, ’16601
SN74GTLPH16916 UBT transceiver replaces all above functions
Additionally, the SN74GTLPH16916 allows for transparent conversion of CLKAB-to-GTLP signal levels
(CLKOUT) and CLKOUT-to-LVTTL logic levels (CLKIN).
Data flow in each direction is controlled by clock enables (CEAB and CEBA), latch enables (LEAB and LEBA),
clock (CLKAB and CLKBA), and output enables (OEAB and OEBA). CEAB and CEBA enable all 17 bits, and
OEAB and OEBA control the 17 bits of data and the CLKOUT/CLKIN buffered clock path for the A-to-B and
B-to-A directions, respectively.
For A-to-B data flow when CEAB is low, the device operates on the low-to-high transition of CLKAB for the
flip-flop and on the high-to-low transition of LEAB for the latch path, i.e., if CEAB and LEAB are low , the A data
is latched regardless of the state of CLKAB (high or low) and, if LEAB is high, the device is in transparent mode.
When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.
The data flow for B to A is similar to A to B, except CEBA, OEBA, LEBA, and CLKBA are used.
SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347C – JANUARY 2001 – REVISED JANUARY 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
OUTPUT ENABLE†
INPUTS OUTPUT
MODE
CEAB OEAB LEAB CLKAB A B
MODE
X H X X X Z Isolation
L L L H X B0‡
Latched storage of A data
LLL LXB
0§
Latched
storage
of
A
data
X L H X L L
True trans
p
arent
XLH XH H
True
transparent
LLL ↑L L
Clocked storage of A data
LLL ↑HH
Clocked
storage
of
A
data
H L L X X B0§Clock inhibit
†A-to-B data flow is shown. B-to-A data flow is similar, but uses CEBA, OEBA, LEBA, and
CLKBA. The condition when OEAB and OEBA are both low at the same time is not
recommended.
‡Output level before the indicated steady-state input conditions were established, provided
that CLKAB was high before LEAB went low
§Output level before the indicated steady-state input conditions were established
BUFFERED CLOCK
INPUTS OPERATION OR
MODE
CE LE OEAB OEBA FUNCTION
MODE
X X H H Z Isolation
X X L H CLKAB to CLKOUT
True delayed clock signal
X X H L CLKOUT to CLKIN
True
delayed
clock
signal
X X L L CLKAB to CLKOUT,
CLKOUT to CLKIN T rue delayed clock signal
with feedback path
This condition is not recommended.
SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347C – JANUARY 2001 – REVISED JANUARY 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
CLK
1D
C1
CLK
B1
OEAB
CEAB
CLKAB
LEAB
LEBA
CLKBA
CEBA
OEBA
A1
1 of 17 Channels
CE
CE
CLKOU
T
CLKIN
1
56
55
2
28
30
29
27
354
31
26
VREF 35
SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347C – JANUARY 2001 – REVISED JANUARY 2002
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC and BIAS VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1): A port and control inputs –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
B port and VREF –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1): A port –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: A port 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any A port output in the high state, IO (see Note 2) 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DGG package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 48°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347C – JANUARY 2001 – REVISED JANUARY 2002
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Notes 4 through 7)
MIN NOM MAX UNIT
VCC,
BIAS VCC Supply voltage 3.15 3.3 3.45 V
VTT
Termination voltage
GTL 1.14 1.2 1.26
V
V
TT
Termination
voltage
GTLP 1.35 1.5 1.65
V
VREF
Reference voltage
GTL 0.74 0.8 0.87
V
V
REF
Reference
voltage
GTLP 0.87 1 1.1
V
VI
In
p
ut voltage
B port VTT
V
V
I
Input
voltage
Except B port VCC 5.5
V
VIH
High level in
p
ut voltage
B port VREF+0.05
V
V
IH
High
-
level
input
voltage
Except B port 2
V
VIL
Low level in
p
ut voltage
B port VREF–0.05
V
V
IL
Low
-
level
input
voltage
Except B port 0.8
V
IIK Input clamp current –18 mA
IOH High-level output current A port –24 mA
IOL
Low level out
p
ut current
A port 24
mA
I
OL
Low
-
level
output
current
B port 50
mA
∆t/∆vInput transition rise or fall rate Outputs enabled 10 ns/V
∆t/∆VCC Power-up ramp rate 20 µs/V
TAOperating free-air temperature –40 85 °C
NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and
VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs
can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection
sequence is acceptable, but generally, GND is connected first.
6. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
7. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction
and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to
minimize current drain.
SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347C – JANUARY 2001 – REVISED JANUARY 2002
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range for GTLP
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 3.15 V, II = –18 mA –1.2 V
VCC = 3.15 V to 3.45 V, IOH = –100 µA VCC–0.2
VOH A port
VCC = 3 15 V
IOH = –12 mA 2.4 V
V
CC =
3
.
15
V
IOH = –24 mA 2
VCC = 3.15 V to 3.45 V, IOL = 100 µA 0.2
A port
VCC = 3 15 V
IOL = 12 mA 0.4
V
CC =
3
.
15
V
IOL = 24 mA 0.5
VOL VCC = 3.15 V to 3.45 V, IOL = 100 µA 0.2 V
B
p
ort
IOL = 10 mA 0.2
B
port
VCC = 3.15 V IOL = 40 mA 0.4
IOL = 50 mA 0.55
A-port and VI = 0 or VCC ±10
II
control inputs VCC = 3.45 V VI = 5.5 V ±20 µA
B port
CC
VI = 0 to 1.5 V ±10
µ
IBHL§A port VCC = 3.15 V, VI = 0.8 V 75 µA
IBHHA port VCC = 3.15 V, VI = 2 V –75 µA
IBHLO#A port VCC = 3.45 V, VI = 0 to VCC 500 µA
IBHHO|| A port VCC = 3.45 V, VI = 0 to VCC –500 µA
VCC
=
3.45 V, IO
=
0,
Outputs high 50
ICC A or B port
VCC
=
3
.
45
V
,
IO
=
0
,
VI (A port or control input) = VCC or GND, Outputs low 50 mA
VI (B port) = VTT or GND Outputs disabled 50
∆ICC
k
VCC = 3.45 V, One A-port or control input at VCC – 0.6 V,
Other A-port or control inputs at VCC or GND 1.5 mA
CiControl inputs VI = 3.15 V or 0 4 5.5 pF
A port VO = 3.15 V or 0 7 8.5 p
F
io B port or CLKOUT VO = 1.5 V or 0 8.5 9.5
pF
CoCLKIN VO = 3.15 V or 0 6 6.5 pF
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡For I/O ports, the parameter II includes the off-state output leakage current.
§The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and
then raising it to VILmax.
The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and
then lowering it to VIHmin.
#An external driver must source at least IBHLO to switch this node from low to high.
|| An external driver must sink at least IBHHO to switch this node from high to low.
k
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
hot-insertion specifications for A port over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN MAX UNIT
Ioff VCC = 0, BIAS VCC = 0, VI or VO = 0 to 5.5 V 10 µA
IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = 0 ±30 µA
IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = 0 ±30 µA
SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347C – JANUARY 2001 – REVISED JANUARY 2002
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
live-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN MAX UNIT
Ioff VCC = 0, BIAS VCC = 0, VI or VO = 0 to 1.5 V 10 µA
IOZPU VCC = 0 to 1.5 V, BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA
IOZPD VCC = 1.5 V to 0, BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA
ICC (BIAS VCC)
VCC = 0 to 3.15 V
BIAS VCC =315Vto345V
VO(B
p
ort)=0to15V
5 mA
I
CC
(BIAS
V
CC
)
VCC = 3.15 V to 3.45 V
BIAS
V
CC =
3
.
15
V
to
3
.
45
V
,
V
O
(B
port)
=
0
to
1
.
5
V
10 µA
VOVCC = 0, BIAS VCC = 3.3 V, IO = 0 0.95 1.05 V
IOVCC = 0, BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0.6 V –1µA
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted)
MIN MAX UNIT
fclock Clock frequency CLKAB to B or CLKBA to A 175 MHz
t
Pulse duration
LEAB or LEBA high 2.8
ns
t
w
Pulse
duration
CLKAB to B or CLKBA to A High or low 2.8
ns
A before CLKAB↑1.8
B before CLKBA↑1.5
t
Setu
p
time
A before LEAB↓1
ns
t
su
Setup
time
B before LEBA↓2
ns
CEAB before CLKAB↑1.5
CEBA before CLKBA↑1.4
A after CLKAB↑0.3
B after CLKBA↑0.4
th
Hold time
A after LEAB↓1.1
ns
t
h
Hold
time
B after LEBA↓0.4
ns
CEAB after CLKAB↑1
CEBA after CLKBA↑1
SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347C – JANUARY 2001 – REVISED JANUARY 2002
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1)
PARAMETER FROM
(INPUT) TO
(OUTPUT) MIN TYP†MAX UNIT
fmax CLKAB or CLKBA B or A 175 MHz
tPLH
A
B
2.1 6
ns
tPHL
A
B
2.1 6
ns
tPLH
LEAB
B
2.2 6.3
ns
tPHL
LEAB
B
2.2 6.3
ns
tPLH
CLKAB
B
2.2 6.3
ns
tPHL
CLKAB
B
2.2 6.3
ns
tPLH
CLKAB
CLKOUT
3.2 8
ns
tPHL
CLKAB
CLKOUT
3.2 8
ns
ten
OEAB
B or CLKOUT
2.6 6.5
ns
tdis
OEAB
B
or
CLKOUT
2.6 6.1
ns
trRise time, B outputs (20% to 80%) 2.4 ns
tfFall time, B outputs (80% to 20%) 2 ns
tPLH
B
A
1.8 5.8
ns
tPHL
B
A
1.8 5.8
ns
tPLH
LEBA
A
1.7 5.3
ns
tPHL
LEBA
A
1.7 5.3
ns
tPLH
CLKBA
A
1.8 5.7
ns
tPHL
CLKBA
A
1.8 5.7
ns
tPLH
CLKOUT
CLKIN
2.5 6.5
ns
tPHL
CLKOUT
CLKIN
2.5 6.5
ns
ten
OEBA
A or CLKIN
1.5 6.2
ns
tdis
OEBA
A
or
CLKIN
1.5 5.9
ns
†All typical values are at VCC = 3.3 V, TA = 25°C.
SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347C – JANUARY 2001 – REVISED JANUARY 2002
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
S1 Open
GND
500 Ω
500 Ω TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
6 V
GND
tPLH tPHL
Output
Control
Output
W aveform 1
S1 at 6 V
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOH
VOL
0 V
VOL + 0.3 V
VOH – 0.3 V
≈0 V
3 V
0 V
tw
Input
3 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
(VM = 1.5 V for A port and 1 V for B port)
(VOH = 3 V for A port and 1.5 V for B port)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
Output
Input
1.5 V
Test
Point
CL = 30 pF
(see Note A)
From Output
Under Test
25 Ω
LOAD CIRCUIT FOR B OUTPUTS
0 V
VOH
VOL
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
Output
1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
6 V
tPLH tPHL
VOH
0 V
VMVM
Data
Input
3 V
0 V
tsu th
Timing
Input
1.5 V 1.5 V
1.5 V 1.5 V
1 V 1 V
1 V 1 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
Figure 1. Load Circuits and Voltage Waveforms
SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347C – JANUARY 2001 – REVISED JANUARY 2002
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation
is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance
capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC
circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC
load, to help the designer better understand the performance of the GTLP device in this typical backplane. See
www.ti.com/sc/gtlp for more information.
Drvr
1.5 V
.25”2”
1”1”
1.5 V
1”1”
2”.25”
Rcvr Rcvr Rcvr
Figure 2. Medium-Drive Test Backplane
Slot 1 Slot 2 Slot 9 Slot 10
Conn. Conn. Conn. Conn.
ZO = 70 Ω
38Ω
38Ω
From Output
Under Test Test
Point
1.5 V
CL = 9 pF
19 Ω
LL = 19 nH
Fi
g
ure 3. Medium-Drive RLC Network
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3)
PARAMETER FROM
(INPUT) TO
(OUTPUT) TYP†UNIT
tPLH
A
B
4.5
ns
tPHL
A
B
4.5
ns
tPLH
LEAB
B
4.7
ns
tPHL
LEAB
B
4.7
ns
tPLH
CLKAB
B
4.7
ns
tPHL
CLKAB
B
4.7
ns
tPLH
CLKAB
CLKOUT
6
ns
tPHL
CLKAB
CLKOUT
6
ns
ten
OEAB
B or CLKOUT
4.8
ns
tdis
OEAB
B
or
CLKOUT
4.4
ns
trRise time, B outputs (20% to 80%) 1.2 ns
tfFall time, B outputs (80% to 20%) 2.5 ns
†All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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