DATASHEET ISL8026, ISL8026A FN8736 Rev 2.00 October 28, 2016 Compact Synchronous Buck Regulators Features The ISL8026, ISL8026A are highly efficient, monolithic, synchronous step-down DC/DC converters that can deliver 6A of continuous output current from a 2.5V to 5.5V input supply. The devices use current mode control architecture to deliver a very low duty cycle operation at high frequency with fast transient response and excellent loop stability. * 2.5V to 5.5V input voltage range * Very low ON-resistance FETs - P-channel 36m and N-channel 13m typical values * High efficiency synchronous buck regulator with up to 95% efficiency The ISL8026, ISL8026A integrate a very low ON-resistance P-channel (36m) high-side FET and N-channel (13m) low-side FET to maximize efficiency and minimize external component count. The 100% duty-cycle operation allows less than 180mV dropout voltage at 6A output current. The operation frequency of the Pulse-width Modulator (PWM) is adjustable from 500kHz to 4MHz. The default switching frequency, which is set by connecting the FS pin high, is 1MHz for the ISL8026 and 2MHz for the ISL8026A. * 1.0% reference accuracy over load/line/temperature (-40C to +85C) * 1.5% reference accuracy over load/line/temperature (-40C to +125C) * Internal soft-start: 1ms or adjustable * Soft-stop output discharge during disable * Adjustable frequency from 500kHz to 4MHz - default at 1MHz (ISL8026) or 2MHz (ISL8026A) The ISL8026, ISL8026A can be configured for discontinuous or forced continuous operation at light load. Forced continuous operation reduces noise and RF interference, while discontinuous mode provides higher efficiency by reducing switching losses at light loads. * External synchronization up to 4MHz * Over-temperature, overcurrent, overvoltage and negative overcurrent protection Fault protection is provided by internal hiccup mode current limiting during short-circuit and overcurrent conditions. Other protection, such as overvoltage and over-temperature, are also integrated into the device. A power-good output voltage monitor indicates when the output is in regulation. Applications The ISL8026, ISL8026A offer a 1ms Power-Good (PG) timer at power-up. When in shutdown, the ISL8026, ISL8026A discharge the output capacitor through an internal soft-stop switch. Other features include internal fixed or adjustable soft-start and internal/external compensation. * Li-ion battery powered devices The ISL8026, ISL8026A are offered in a space saving 16 Ld 3x3 Pb-free TQFN package with an exposed pad for improved thermal performance and 0.8mm maximum height. The complete converter occupies less than 142mm2. * Industrial PCs 13 PHASE * Routers and switchers * Portable instruments * Test and measurement systems Related Literature * UG033, "ISL8026xEVAL3Z Evaluation Board User Guide" 100 VOUT PG PGND/ SGND SYNC R2 200k : C3* 22pF R3 100k : FB 17 5 EN *C3 IS OPTIONAL. IT IS RECOMMENDED TO PUT A PLACEHOLDER FOR IT AND CHECK LOOP ANALYSIS BEFORE USE. VO R 2 = R 3 ------------ - 1 VFB 80 3.3VOUT PWM 70 60 50 40 (EQ. 1) FIGURE 1. TYPICAL APPLICATION CIRCUIT CONFIGURATION (INTERNAL COMPENSATION OPTION) FN8736 Rev 2.00 October 28, 2016 3.3VOUT PFM 90 EFFICIENCY (%) 14 PHASE 15 PGND EN 4 * Video processor/SOC power PAD 3 * C/P, FPGA and DSP power GND VIN COMP 2 8 R1 100k: +1.8V/6A PGND ISL8026 SS C1 2 x 22F VIN 7 PG 1 FS GND +2.5V ...+5.5V 6 VIN PHASE VIN 16 L1 1.0H C2 2 x 22F * DC/DC POL modules 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 OUTPUT LOAD (A) FIGURE 2. EFFICIENCY vs LOAD 1MHz 5VIN Page 1 of 23 ISL8026, ISL8026A Table of Contents Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typical Operating Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SKIP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Negative Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Discharge Mode (Soft-Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100% Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Derating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 17 18 18 18 18 18 18 18 18 18 18 18 19 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Inductor and Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 19 19 19 PCB Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 FN8736 Rev 2.00 October 28, 2016 Page 2 of 23 ISL8026, ISL8026A Pin Configuration VIN PHASE PHASE PHASE ISL8026, ISL8026A (16 LD TQFN) TOP VIEW 16 15 14 13 VIN 1 12 PGND 11 PGND PG 3 10 PGND/SGND SYNC 4 9 FB VIN 2 6 7 FS SS 8 COMP 5 EN EPAD Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1, 2, 16 VIN Input supply voltage. Place a minimum of two 22F ceramic capacitors from VIN to PGND as close as possible to the IC for decoupling. 3 PG Power-good is an open-drain output. Use a 10k to 100k pull-up resistor connected between VIN and PG. At power-up or EN HI, PG rising edge is delayed by 1ms once the output voltage reaches regulation. 4 SYNC 5 EN Regulator enable pin. Enable the output when driven high. Shut down the chip and discharge output capacitor when driven low. 6 FS This pin sets the oscillator switching frequency using a resistor, RFS, from the FS pin to GND. The frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz (ISL8026), 2MHz (ISL8026A) if FS is connected to VIN. 7 SS SS is used to adjust the soft-start time. Connect to SGND for internal 1ms rise time. Connect a capacitor from SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC. 8, 9 COMP, FB 10 Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or ground for PFM mode. Connect to an external function generator for synchronization with the positive edge trigger. There is an internal 1M pull-down resistor to prevent an undefined logic state in case the SYNC pin is floating. The feedback network of the regulator, FB, is the negative input to the transconductance error amplifier. The output voltage is set by an external resistor divider connected to FB. With a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. COMP is the output of the amplifier if COMP is not tied to VIN. Otherwise, COMP is disconnected through a MOSFET for internal compensation. Must connect COMP to VIN in internal compensation mode to meet a typical application. Additional external networks across COMP and SGND might be required to improve the loop compensation of the amplifier operation. In addition, the regulator power-good and undervoltage protection circuitry use FB to monitor the regulator output voltage. PGND/SGND Power/signal ground 11, 12 PGND Power ground 13, 14, 15 PHASE Switching node connections. Connect to one terminal of the inductor. This pin is discharged by a 100 resistor when the device is disabled. See "Block Diagram" on page 5 for more detail. Exposed Pad - The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many vias as possible under the pad connecting to the SGND plane for optimal thermal performance. FN8736 Rev 2.00 October 28, 2016 Page 3 of 23 ISL8026, ISL8026A Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING OPERATION FREQUENCY (MHz) TEMP. RANGE (C) PACKAGE (RoHS COMPLIANT) PKG. DWG. # ISL8026IRTAJZ 026A 1 -40 to +85 16 Ld 3x3 TQFN L16.3x3D ISL8026AIRTAJZ 26AA 2 -40 to +85 16 Ld 3x3 TQFN L16.3x3D ISL8026FRTAJZ 026F 1 -40 to +125 16 Ld 3x3 TQFN L16.3x3D ISL8026AFRTAJZ 026AF 2 -40 to +125 16 Ld 3x3 TQFN L16.3x3D ISL8026EVAL3Z Evaluation board for ISL8026 ISL8026AEVAL3Z Evaluation board for ISL8026A NOTES: 1. Add "-T" suffix for 6k unit or "-T7A" suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8026, ISL8026A. For more information on MSL please see techbrief TB363. TABLE 1. SUMMARY OF KEY DIFFERENCES PART NUMBER IOUT (MAX) (A) ISL8026 6 ISL8026A fSW RANGE (MHz) VIN RANGE (V) VOUT RANGE (V) PART SIZE (mm) 2.5 to 5.5 0.6 to 5.5 3x3 Programmable 0.5MHz to 4MHz Programmable 1MHz to 4MHz TABLE 2. ISL8026 COMPONENT SELECTION VOUT 0.8V 1.2V 1.5V 1.8V 2.5V 3.3V 3.6V C1 2 x 22F 2 x 22F 2 x 22F 2 x 22F 2 x 22F 2 x 22F 2 x 22F C2 4 x 22F 2 x 22F 2 x 22F 2 x 22F 2 x 22F 2 x 22F 2 x 22F C3 22pF 22pF 22pF 22pF 22pF 22pF 22pF L1 0.47~1H 0.47~1H 0.47~1H 0.68~1.5H 0.68~1.5H 1~2.2H 1~2.2H R2 33k 100k 150k 200k 316k 450k 500k R3 100k 100k 100k 100k 100k 100k 100k TABLE 3. ISL8026A COMPONENT SELECTION VOUT 0.8V 1.2V 1.5V 1.8V 2.5V 3.3V 3.6V C1 22F 22F 22F 22F 22F 22F 22F C2 3 x 22F 2 x 22F 2 x 22F 2 x 22F 2 x 22F 2 x 22F 2 x 22F C3 22pF 22pF 22pF 22pF 22pF 22pF 22pF L1 0.22~0.47H 0.22~0.47H 0.22~0.47H 0.33~0.68H 0.33~0.68H 0.47~1H 0.47~1H R2 33k 100k 150k 200k 316k 450k 500k R3 100k 100k 100k 100k 100k 100k 100k FN8736 Rev 2.00 October 28, 2016 Page 4 of 23 ISL8026, ISL8026A Block Diagram COMP SS SHUTDOWN FS SYNC 55pF Soft SOFTSTART SHUTDOWN 100k + BANDGAP VREF + EN + COMP - EAMP - VIN OSCILLATOR PWM/PFM LOGIC CONTROLLER PROTECTION HS DRIVER 3pF + P PHASE LS DRIVER N PGND FB 6k SLOPE Slope COMP 0.8V + CSA - + OV 0.85*VREF PG + UV + OCP - + SKIP - ISET THRESHOLD 1ms DELAY NEG CURRENT SENSING SGND ZERO-CROSS SENSING 0.5V SCP + 100 SHUTDOWN FIGURE 3. FUNCTIONAL BLOCK DIAGRAM FN8736 Rev 2.00 October 28, 2016 Page 5 of 23 ISL8026, ISL8026A Absolute Maximum Ratings Thermal Information (Reference to GND) Thermal Resistance JA (C/W) JC (C/W) 16 LD TQFN Package (Notes 4, 5) . . . . . . . 47 6.5 Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55C to +125C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.8V (DC) or 7V (20ms) EN, FS, PG, SYNC, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V PHASE . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms) COMP, SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V ESD Ratings Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 3kV Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . . 2kV Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 200V Latch-Up (Tested per JESD-78A; Class 2, Level A) . . . . . 100mA at +85C Recommended Operating Conditions VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V to 5.5V Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 6A Ambient Temperature Range (Industrial) . . . . . . . . . . . . . . -40C to +85C Ambient Temperature Range (Full-Range Industrial) . . .-40C to +125C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. JC, "case temperature" location is at the center of the exposed metal pad on the package underside. Electrical Specifications Unless otherwise noted, all parameter limits are established across the recommended operating conditions and are measured at the following conditions: VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are at TA = +25C. Unless otherwise noted, Boldface limits apply across the operating temperature range, -40C to +125C PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT 2.3 2.5 V INPUT SUPPLY VIN Undervoltage Lockout Threshold VUVLO Rising, no load Falling, no load Quiescent Supply Current Shutdown Supply Current IVIN ISD 2.10 2.25 V SYNC = GND, no load at the output 50 A SYNC = GND, no load at the output and no switching 50 62 A SYNC = VIN, fSW = 1MHz, no load at the output (ISL8026) 9 16 mA SYNC = VIN, fSW = 2MHz, no load at the output (ISL8026A) 16 23 mA SYNC = GND, VIN = 5.5V, EN = low 5 8 A OUTPUT REGULATION Reference Voltage VFB Bias Current VREF IVFB -40C < TJ < +85C 0.594 0.600 0.606 V -40C < TJ < +125C 0.591 0.600 0.606 V VFB = 0.75V 0.1 A Line Regulation VIN = VO + 0.5V to 5.5V (minimal 2.5V) 0.2 %/V Soft-Start Ramp Time Cycle SS = SGND 1 ms Soft-Start Charging Current ISS VSS = 0.1V 1.45 1.85 2.25 A OVERCURRENT PROTECTION Current Limit Blanking Time tOCON 17 Clock pulses Overcurrent and Auto Restart Period tOCOFF 8 SS cycle Positive Peak Current Limit IPLIMIT Peak Skip Limit ISKIP Zero Cross Threshold Negative Current Limit FN8736 Rev 2.00 October 28, 2016 6A application 6A application (See "Application Information" on page 19 for more detail) 7.5 9 11 A 1 1.3 1.8 A 300 mA -1.5 A -300 INLIMIT -4.5 -3.0 Page 6 of 23 ISL8026, ISL8026A Electrical Specifications Unless otherwise noted, all parameter limits are established across the recommended operating conditions and are measured at the following conditions: VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are at TA = +25C. Unless otherwise noted, Boldface limits apply across the operating temperature range, -40C to +125C (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT COMPENSATION Error Amplifier Transconductance Transresistance Rt Internal compensation 60 A/V External compensation 120 A/V 6A application (test at 3.6V) -40C < TJ < +85C 0.119 0.140 0.166 0.110 0.140 0.170 VIN = 5V, IO = 200mA 36 63 m VIN = 2.7V, IO = 200mA 52 89 m VIN = 5V, IO = 200mA 13 30 m VIN = 2.7V, IO = 200mA 17 36 m 6A application (test at 3.6V) -40C < TJ < +125C PHASE P-Channel MOSFET ON-Resistance N-Channel MOSFET ON-Resistance PHASE Maximum Duty Cycle 100 PHASE Minimum On-Time SYNC = High % 140 ns OSCILLATOR Nominal Switching Frequency fSW fSW = VIN, ISL8026A. -40C < TJ < +85C 1600 2000 2400 kHz fSW = VIN, ISL8026A. -40C < TJ < +125C 1550 2000 2450 kHz 780 1000 1200 kHz fSW = VIN, ISL8026 fSW with RS = 402k 490 kHz fSW with RS = 42.2k 4200 kHz SYNC Logic LOW to HIGH Transition Range 0.70 SYNC Hysteresis SYNC Logic Input Leakage Current 0.75 0.80 V 0.15 VIN = 3.6V 3.6 V 5 A 0.3 V 1 2 ms 0.01 0.10 A PG Output Low Voltage Delay Time (Rising Edge) Time from VOUT reached regulation PG Pin Leakage Current PG = VIN 0.5 OVP PG Rising Threshold 0.80 UVP PG Rising Threshold 80 85 V 90 % UVP PG Hysteresis 30 mV PGOOD Delay Time (Falling Edge) 7.5 s EN Logic Input Low 0.4 Logic Input High V 0.9 V EN Logic Input Leakage Current Pulled up to 3.6V 0.1 1 A Thermal Shutdown Temperature Rising 150 C Thermal Shutdown Hysteresis Temperature Falling 25 C NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. FN8736 Rev 2.00 October 28, 2016 Page 7 of 23 ISL8026, ISL8026A Typical Operating Performance 100 100 90 90 0.8VOUT 0.9VOUT 80 1.2VOUT 70 1.5VOUT 60 1.8VOUT 2.5VOUT EFFICIENCY (%) EFFICIENCY (%) Unless otherwise noted, operating conditions are: TA = +25C, VIN = 5V, EN = VIN, SYNC = VIN, L = 1.0H, C1 = 22F, C2 = 2 x 22F, IOUT = 0A to 6A. Resistor load is used in the test. 0.8VOUT 1.2VOUT 70 1.5VOUT 60 0 40 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 OUTPUT LOAD (A) 0 FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3 VIN PWM) 100 90 90 3.3VOUT 80 2.5VOUT 1.8VOUT 70 1.2VOUT 1.5VOUT 60 EFFICIENCY (%) EFFICIENCY (%) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 OUTPUT LOAD (A) FIGURE 5. EFFICIENCY vs LOAD (1MHz 3.3 VIN PFM) 100 3.3VOUT 80 2.5VOUT 1.8VOUT 70 1.5VOUT 40 0 60 40 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 6. EFFICIENCY vs LOAD (1MHz 5VIN PWM) FIGURE 7. EFFICIENCY vs LOAD (1MHz 5VIN PFM) 100 100 90 90 0.8VOUT 80 0.9VOUT 1.2VOUT 70 1.5VOUT 60 1.8VOUT 2.5VOUT 50 EFFICIENCY (%) EFFICIENCY (%) 1.2VOUT 50 50 40 1.8VOUT 2.5V OUT 50 50 40 0.9VOUT 80 80 0.8VOUT 0.9VOUT 1.2VOUT 70 1.5VOUT 60 1.8VOUT 2.5VOUT 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 OUTPUT LOAD (A) FIGURE 8. EFFICIENCY vs LOAD (2MHz 3.3VIN PWM) FN8736 Rev 2.00 October 28, 2016 40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 OUTPUT LOAD (A) FIGURE 9. EFFICIENCY vs LOAD (2MHz 3.3VIN PFM) Page 8 of 23 ISL8026, ISL8026A Typical Operating Performance 100 100 90 90 80 3.3VOUT 70 2.5VOUT 1.8VOUT 60 1.2VOUT 0.9VOUT 1.5VOUT EFFICIENCY (%) EFFICIENCY (%) Unless otherwise noted, operating conditions are: TA = +25C, VIN = 5V, EN = VIN, SYNC = VIN, L = 1.0H, C1 = 22F, C2 = 2 x 22F, IOUT = 0A to 6A. Resistor load is used in the test. (Continued) 0 2.5VOUT 1.2VOUT 0.9VOUT 1.5VOUT 0.912 5VIN PFM 0.807 3.3VIN PFM 0.804 5VIN PWM 0.801 0.798 0.795 0.789 OUTPUT VOLTAGE (V) 0.915 0.813 0.810 3.3VIN PWM 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 OUTPUT LOAD (A) FIGURE 11. EFFICIENCY vs LOAD (2MHz 5VIN PFM) 0.816 0.792 5VIN PFM 0.909 0.906 3.3VIN PFM 0.903 5VIN PWM 0.900 0.897 0.894 3.3VIN PWM 0.891 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 0.8V) FIGURE 13. VOUT REGULATION vs LOAD (1MHz, VOUT = 0.9V) 1.219 1.525 1.214 1.209 5VIN PFM 1.204 1.199 1.194 1.189 3.3VIN PWM 5VIN PWM 3.3VIN PFM 1.515 5VIN PFM 1.510 5VIN PWM 1.505 1.500 1.495 3.3V PWM IN 1.490 1.184 1.179 1.520 3.3VIN PFM OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.8VOUT 60 40 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 OUTPUT LOAD (A) FIGURE 10. EFFICIENCY vs LOAD (2MHz 5VIN PWM) OUTPUT VOLTAGE (V) 3.3VOUT 70 50 50 40 80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 OUTPUT LOAD (A) FIGURE 14. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V) FN8736 Rev 2.00 October 28, 2016 1.485 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 OUTPUT LOAD (A) FIGURE 15. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V) Page 9 of 23 ISL8026, ISL8026A Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25C, VIN = 5V, EN = VIN, SYNC = VIN, L = 1.0H, C1 = 22F, C2 = 2 x 22F, IOUT = 0A to 6A. Resistor load is used in the test. (Continued) 1.825 2.510 2.505 3.3VIN PFM 1.815 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.820 5VIN PFM 1.810 5VIN PWM 1.805 1.800 1.795 1.790 1.785 3.3VIN PWM 0 3.3VIN PFM 2.500 5VIN PFM 2.495 5VIN PWM 2.490 2.485 2.480 2.475 3.3V PWM IN 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.470 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 16. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V) FIGURE 17. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V) 3.341 OUTPUT VOLTAGE (V) 3.333 3.325 5VIN PFM 3.317 3.309 3.301 5VIN PWM 3.293 3.285 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 OUTPUT LOAD (A) FIGURE 18. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V) FN8736 Rev 2.00 October 28, 2016 Page 10 of 23 ISL8026, ISL8026A Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25C, VIN = 5V, EN = VIN, SYNC = VIN, L = 1.0H, C1 = 22F, C2 = 2 x 22F, IOUT = 0A to 6A. Resistor load is used in the test. (Continued) PHASE 5V/DIV PHASE 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 5V/DIV VEN 5V/DIV PG 5V/DIV PG 5V/DIV 1ms/DIV 1ms/DIV FIGURE 19. START-UP AT NO LOAD (PFM) FIGURE 20. START-UP AT NO LOAD (PWM) PHASE 5V/DIV PHASE 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 5V/DIV VEN 5V/DIV PG 5V/DIV PG 5V/DIV 500s/DIV FIGURE 21. SHUTDOWN AT NO LOAD (PFM) 500s/DIV FIGURE 22. SHUTDOWN AT NO LOAD (PWM) PHASE 5V/DIV PHASE 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 5V/DIV VEN 5V/DIV PG 5V/DIV PG 5V/DIV 500s/DIV 500s/DIV FIGURE 23. START-UP AT 6A LOAD (PWM) FIGURE 24. SHUTDOWN AT 6A LOAD (PWM) FN8736 Rev 2.00 October 28, 2016 Page 11 of 23 ISL8026, ISL8026A Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25C, VIN = 5V, EN = VIN, SYNC = VIN, L = 1.0H, C1 = 22F, C2 = 2 x 22F, IOUT = 0A to 6A. Resistor load is used in the test. (Continued) IOUT 2A/DIV IOUT 2A/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 5V/DIV VEN 5V/DIV PG 5V/DIV PG 5V/DIV 1ms/DIV 200s/DIV FIGURE 25. START-UP AT 6A LOAD (PFM) FIGURE 26. SHUTDOWN AT 6A LOAD (PFM) VEN 5V/DIV VEN 5V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 2A/DIV IL 2A/DIV PG 5V/DIV PG 5V/DIV 1ms/DIV 50s/DIV FIGURE 28. SHUTDOWN AT 3A LOAD (PWM) FIGURE 27. START-UP AT 3A LOAD (PWM) VEN 5V/DIV VOUT 1V/DIV IL 2A/DIV PG 5V/DIV VEN 5V/DIV VOUT 1V/DIV IL 2A/DIV PG 5V/DIV 1ms/DIV 50s/DIV FIGURE 29. START-UP AT 3A LOAD (PFM) FIGURE 30. SHUTDOWN AT 3A LOAD (PFM) FN8736 Rev 2.00 October 28, 2016 Page 12 of 23 ISL8026, ISL8026A Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25C, VIN = 5V, EN = VIN, SYNC = VIN, L = 1.0H, C1 = 22F, C2 = 2 x 22F, IOUT = 0A to 6A. Resistor load is used in the test. (Continued) IOUT 2A/DIV IOUT 2A/DIV VOUT 1V/DIV VOUT 1V/DIV VIN 5V/DIV VIN 5V/DIV PG 5V/DIV PG 5V/DIV 1ms/DIV 1ms/DIV FIGURE 31. START-UP VIN AT 6A LOAD (PFM) FIGURE 32. START-UP VIN AT 6A LOAD (PWM) IOUT 2A/DIV IOUT 2A/DIV VOUT 1V/DIV VOUT 1V/DIV VIN 5V/DIV VIN 5V/DIV PG 5V/DIV PG 5V/DIV 1ms/DIV 1ms/DIV FIGURE 33. SHUTDOWN VIN AT 6A LOAD (PFM) FIGURE 34. SHUTDOWN VIN AT 6A LOAD (PWM) PHASE 5V/DIV PHASE 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VIN 5V/DIV VIN 5V/DIV PG 5V/DIV PG 5V/DIV 1ms/DIV FIGURE 35. START-UP VIN AT NO LOAD (PFM) FN8736 Rev 2.00 October 28, 2016 1ms/DIV FIGURE 36. START-UP VIN AT NO LOAD (PWM) Page 13 of 23 ISL8026, ISL8026A Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25C, VIN = 5V, EN = VIN, SYNC = VIN, L = 1.0H, C1 = 22F, C2 = 2 x 22F, IOUT = 0A to 6A. Resistor load is used in the test. (Continued) PHASE 5V/DIV PHASE 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VIN 5V/DIV VIN 5V/DIV PG 5V/DIV PG 5V/DIV 2ms/DIV 2ms/DIV FIGURE 37. SHUTDOWN VIN AT NO LOAD (PFM) FIGURE 38. SHUTDOWN VIN AT NO LOAD (PWM) PHASE 1V/DIV PHASE 1V/DIV 10ns/DIV 10ns/DIV FIGURE 39. JITTER AT NO LOAD PWM FIGURE 40. JITTER AT FULL LOAD PWM PHASE 5V/DIV PHASE 5V/DIV VOUT RIPPLE 20mV/DIV VOUT RIPPLE 20mV/DIV IL 1A/DIV IL 1A/DIV 500ns/DIV 20ms/DIV FIGURE 41. STEADY STATE AT NO LOAD PWM FIGURE 42. STEADY STATE AT NO LOAD PFM FN8736 Rev 2.00 October 28, 2016 Page 14 of 23 ISL8026, ISL8026A Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25C, VIN = 5V, EN = VIN, SYNC = VIN, L = 1.0H, C1 = 22F, C2 = 2 x 22F, IOUT = 0A to 6A. Resistor load is used in the test. (Continued) PHASE 5V/DIV PHASE 5V/DIV IL 2A/DIV IL 1A/DIV VOUT RIPPLE 20mV/DIV VOUT RIPPLE 20mV/DIV 500ns/DIV 500ns/DIV FIGURE 44. STEADY STATE AT 3A PFM FIGURE 43. STEADY STATE AT 6A PWM VOUT RIPPLE 100mV/DIV VOUT RIPPLE 50mV/DIV IL 2A/DIV IL 2A/DIV 200s/DIV 200s/DIV FIGURE 45. LOAD TRANSIENT (PWM) FIGURE 46. LOAD TRANSIENT (PFM) PHASE 5V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 5A/DIV IL 5A/DIV PG 5V/DIV PG 5V/DIV 5s/DIV FIGURE 47. OUTPUT SHORT-CIRCUIT FN8736 Rev 2.00 October 28, 2016 20s/DIV FIGURE 48. OVERCURRENT PROTECTION Page 15 of 23 ISL8026, ISL8026A Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25C, VIN = 5V, EN = VIN, SYNC = VIN, L = 1.0H, C1 = 22F, C2 = 2 x 22F, IOUT = 0A to 6A. Resistor load is used in the test. (Continued) PHASE 5V/DIV PHASE1 5V/DIV BACK TO PFM AT 360mA 600mA MODE TRANSITION, COMPLETELY ENTER TO PWM AT 640mA VOUT1 RIPPLE 20mV/DIV VOUT1 RIPPLE 20mV/DIV IL 500mA/DIV IL 500mA/DIV 1s/DIV 1s/DIV FIGURE 49. PFM TO PWM TRANSITION FIGURE 50. PWM TO PFM TRANSITION PHASE 5V/DIV VOUT 2V/DIV IL 2A/DIV VOUT 1V/DIV PG 2V/DIV PG 5V/DIV 20s/DIV 2ms/DIV FIGURE 51. OVERVOLTAGE PROTECTION FIGURE 52. OVER-TEMPERATURE PROTECTION FN8736 Rev 2.00 October 28, 2016 Page 16 of 23 ISL8026, ISL8026A Theory of Operation with the 55pF and 100k RC network. The maximum EAMP voltage output is precisely clamped to 1.6V. The ISL8026, ISL8026A are step-down switching regulators optimized for battery-powered applications. The regulators operate at a 1MHz or 2MHz fixed default switching frequency for high efficiency and allow smaller form factor when FS is connected to VIN. By connecting a resistor from FS to SGND, the operational frequency adjustable range is 500kHz to 4MHz. At light load, the regulator reduces the switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. The quiescent current when the output is not loaded is typically only 50A. The supply current is typically only 5A when the regulator is shut down. VEAMP VCSA DUTY CYCLE IL VOUT PWM Control Scheme Pulling the SYNC pin HI (>0.8V) forces the converter into PWM mode, regardless of output current. The ISL8026, ISL8026A employs the current-mode Pulse-width Modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. Figure 3 on page 5 shows the functional block diagram. The current loop consists of the oscillator, the PWM comparator, current sensing circuit and the slope compensation for the current loop stability. The slope compensation is 440mV/Ts, which changes with frequency. The gain for the current sensing circuit is typically 140mV/A. The control reference for the current loops comes from the Error Amplifier's (EAMP) output. FIGURE 53. PWM OPERATION WAVEFORMS SKIP Mode Pulling the SYNC pin LOW (<0.4V) forces the converter into PFM mode. The ISL8026, ISL8026A enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. Figure 54 illustrates the skip mode operation. A zero-cross sensing circuit shown in Figure 3 on page 5 monitors the N-FET current for zero crossing. When 16 consecutive cycles are detected, the regulator enters the Skip mode. During the sixteen detecting cycles, the current in the inductor is allowed to become negative. The counter is reset to zero when the current in any cycle does not cross zero. The PWM operation is initialized by the clock from the oscillator. The P-Channel MOSFET is turned on at the beginning of a PWM cycle and the current in the MOSFET starts to ramp up. When the sum of the current amplifier, CSA, and the slope compensation reaches the control reference of the current loop, the PWM comparator COMP sends a signal to the PWM logic to turn off the P-FET and turn on the N-channel MOSFET. The N-FET stays on until the end of the PWM cycle. Figure 53 shows the typical operating waveforms during the PWM operation. The dotted lines illustrate the sum of the slope compensation ramp and the Current-Sense Amplifier's (CSA) output. Once the skip mode is entered, the pulse modulation starts being controlled by the Skip comparator shown in Figure 3 on page 5. Each pulse cycle is still synchronized by the PWM clock. The P-FET is turned on at the clock's rising edge and turned off when the output is higher than 1.2% of the nominal regulation or when its current reaches the peak skip current limit value. Then, the inductor current is discharged to 0A and stays at zero (the internal clock is disabled) and the output voltage reduces gradually due to the load current discharging the output capacitor. When the output voltage drops to the nominal voltage, the P-FET will be turned on again at the rising edge of the internal clock as it repeats the previous operations. The output voltage is regulated by controlling the VEAMP voltage to the current loop. The bandgap circuit outputs a 0.6V reference voltage to the voltage loop. The feedback signal comes from the VFB pin. The soft-start block only affects the operation during the start-up and will be discussed separately. The error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. The voltage loop is internally compensated PWM The regulator resumes normal PWM mode operation when the output voltage drops 2.5% below the nominal voltage. PFM PWM CLOCK 16 CYCLES IL PFM CURRENT LIMIT LOAD CURRENT 0 NOMINAL +1.2% VOUT NOMINAL NOMINAL -2.5% FIGURE 54. SKIP MODE OPERATION WAVEFORMS FN8736 Rev 2.00 October 28, 2016 Page 17 of 23 ISL8026, ISL8026A Frequency Adjust Soft Start-Up The frequency of operation is fixed at 1MHz for ISL8026, 2MHz for ISL8026A when FS is tied to VIN. Adjustable frequency ranges from 500kHz to 4MHz via a simple resistor connecting FS to SGND, according to Equation 2: The soft start-up reduces the inrush current during the start-up. The soft-start block outputs a ramp reference to the input of the error amplifier. This voltage ramp limits the inductor current as well as the output voltage speed, so that the output voltage rises in a controlled fashion. When VFB is less than 0.1V at the beginning of the soft-start, the switching frequency is reduced to 200kHz, so that the output can start-up smoothly at light load condition. During soft-start, the IC operates in the Skip mode to support prebiased output condition. 220 10 3 R FS k = ------------------------------ - 14 f OSC kHz (EQ. 2) Overcurrent Protection The overcurrent protection is realized by monitoring the CSA output with the OCP comparator, as shown in Figure 3 on page 5. The current sensing circuit has a gain of 140mV/A, from the P-FET current to the CSA output. When the CSA output reaches the threshold, the OCP comparator is tripled to turn off the P-FET immediately. The overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper MOSFET. Upon detection of an overcurrent condition, the upper MOSFET will be immediately turned off and will not be turned on again until the next switching cycle. Upon detection of the initial overcurrent condition, the overcurrent fault counter is set to 1. If, on the subsequent cycle, another overcurrent condition is detected, the OC fault counter will be incremented. If there are 17 sequential OC fault detections, the regulator will be shut down under an overcurrent fault condition. An overcurrent fault condition will result in the regulator attempting to restart in a hiccup mode within the delay of eight soft-start periods. At the end of the 8th soft-start wait period, the fault counters are reset and soft-start is attempted again. If the overcurrent condition goes away during the delay of 8 soft-start periods, the output will resume back into regulation after hiccup mode expires. Negative Current Protection Similar to overcurrent, the negative current protection is realized by monitoring the current across the low-side N-FET, as shown in Figure 3 on page 5. When the valley point of the inductor current reaches -3A for 4 consecutive cycles, both P-FET and N-FET are turned off. The 100 in parallel to the N-FET will activate discharging the output into regulation. The control will begin to switch when output is within regulation. The regulator will be in PFM for 20s before switching to PWM, if necessary. PG PG is an open-drain output of a window comparator that continuously monitors the buck regulator output voltage. PG is actively held low when EN is low and during the buck regulator soft-start period. After 1ms delay of the soft-start period, PG becomes high impedance as long as the output voltage is within the nominal regulation voltage set by VFB. When VFB drops 15% below or raises 0.8V above the nominal regulation voltage, the ISL8026, ISL8026A pulls PG low. Any fault condition forces PG low until the fault condition is cleared by attempts to soft-start. For logic level output voltages, connect an external pull-up resistor, R1, between PG and VIN. A 100k resistor works well in most applications. Tie SS to SGND for internal soft-start, which is approximately 1ms. Connect a capacitor from SS to SGND to adjust the soft-start time. This capacitor, along with an internal 1.85A current source sets the soft-start interval of the converter, tSS, as shown by Equation 3. C SS F = 3.1 t SS s (EQ. 3) CSS must be less than 33nF to insure proper soft-start reset after fault condition. Enable The Enable (EN) input allows the user to control the turning on or off of the regulator for purposes such as power-up sequencing. When the regulator is enabled, there is typically a 600s delay for waking up the bandgap reference and then the soft start-up begins. Discharge Mode (Soft-Stop) When a transition to shutdown mode occurs or the VIN UVLO is set, the outputs discharge to GND through an internal 100 switch. Power MOSFETs The power MOSFETs are optimized for best efficiency. The ON-resistance for the P-FET is typically 36m and the ON-resistance for the N-FET is typically 13m. 100% Duty Cycle The ISL8026, ISL8026A features a 100% duty cycle operation to maximize the battery life. When the battery voltage drops to a level that the ISL8026, ISL8026A can no longer maintain the regulation at the output, the regulator completely turns on the P-FET. The maximum dropout voltage under the 100% duty cycle operation is the product of the load current and the ON-resistance of the P-FET. Thermal Shutdown The ISL8026, ISL8026A has built-in thermal protection. When the internal temperature reaches +150C, the regulator is completely shut down. As the temperature drops to +125C, the ISL8026, ISL8026A resumes operation by stepping through the soft-start. UVLO When the input voltage is below the Undervoltage Lockout (UVLO) threshold, the regulator is disabled. FN8736 Rev 2.00 October 28, 2016 Page 18 of 23 ISL8026, ISL8026A Power Derating Characteristics To prevent the regulator from exceeding the maximum junction temperature, some thermal analysis is required. The temperature rise is given by Equation 4: (EQ. 4) T RISE = PD JA Where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by Equation 5: (EQ. 5) T J = T A + T RISE Where TA is the ambient temperature. For the TQFN package, the JA is 47 (C/W). The actual junction temperature should not exceed the absolute maximum junction temperature of +125C when considering the thermal design. 6 OUTPUT CURRENT (V) 5 1.8V 0.8V 3 1 VIN = 5V, ZERO LFM 60 70 80 90 100 TEMPERATURE (C) Output Voltage Selection The output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage, relative to the internal reference voltage, and feed it back to the inverting input of the error amplifier (refer to Figure 1 on page 1). The output voltage programming resistor, R2, will depend on the value chosen for the feedback resistor and the desired output voltage of the regulator. The value for the feedback resistor, R3, is typically between 10k and 100k, as shown in Equation 7. (EQ. 7) If the output voltage desired is 0.6V, then R3 is left unpopulated and R2 is shorted. There is a leakage current from VIN to PHASE. It is recommended to preload the output with 10A minimum. For better performance, add 22pF in parallel with R2 (200k). Check loop analysis before use in application. 2 0 50 In Table 3, the minimum output capacitor value is given for the different output voltages to ensure that the whole converter system is stable. Additional output capacitance should be added for better performance in applications where high load transient or low output ripple is required. It is recommended to check the system level performance along with the simulation model. VO R 2 = R 3 ------------ - 1 VFB 3.3V 4 The ISL8026, ISL8026A uses an internal compensation network and the output capacitor value is dependent on the output voltage. The ceramic capacitor is recommended to be X5R or X7R. The recommended X5R or X7R minimum output capacitor values are shown in Table 3 on page 4. 110 120 130 Input Capacitor Selection Application Information The main functions for the input capacitor are to provide decoupling of the parasitic inductance and provide a filtering function to prevent the switching current flowing back to the battery rail. At least two 22F X5R or X7R ceramic capacitors are a good starting point for the input capacitor selection. Output Inductor and Capacitor Selection Loop Compensation Design To consider steady state and transient operations, the ISL8026 typically uses a 1.0H output inductor and the ISL8026A uses a 0.68H output inductor. The higher or lower inductor value can be used to optimize the total converter system performance. For example, for a higher output voltage 3.3V application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. It is recommended to set the ripple inductor current approximately 30% of the maximum output current for optimized performance. The inductor ripple current can be expressed, as shown in Equation 6: When COMP is not connected to VIN, the COMP pin is active for external loop compensation. The ISL8026, ISL8026A uses constant frequency peak current mode control architecture to achieve a fast loop transient response. An accurate current sensing pilot device in parallel with the upper MOSFET is used for peak current control signal and overcurrent protection. The inductor is not considered as a state variable since its peak current is constant and the system becomes a single order system. It is much easier to design a type II compensator to stabilize the loop than to implement voltage mode control. Peak current mode control has an inherent input voltage feed-forward function to achieve good line regulation. Figure 56 on page 20 shows the small signal model of the synchronous buck regulator. FIGURE 55. DERATING CURVE vs TEMPERATURE VO V O 1 - --------- V IN I = --------------------------------------L fS (EQ. 6) The inductor's saturation current rating needs to be at least larger than the peak current. The ISL8026, ISL8026A protects the typical peak current 9A. The saturation current needs to be over 10A for maximum output current application. FN8736 Rev 2.00 October 28, 2016 Page 19 of 23 ISL8026, ISL8026A + ^ iin ^ iL LP Vind^ ILd^ 1:D ^ Vin + The loop gain at crossover frequency of fc has a unity gain. Therefore, the compensator resistance R6 is determined by Equation 9. Rc Rt GAIN (VLOOP (S(fi)) The compensator design procedure is as follows: vo^ RLP Co 2f c V o C o R t 3 R 6 = ---------------------------------- = 12.2 10 f c V o C o GM V FB Ro Where GM is the sum of the transconductance, gm, of the voltage error amplifier in each phase. Compensator capacitor C6 is then given by Equation 10. Ti(S) d^ K Fm + Ro Co Vo Co Rc Co 1 C 6 = --------------- = --------------- ,C 7 = max (--------------,----------------) R6 Io R6 R 6 f s R 6 Tv(S) He(S) v^comp -Av(S) FIGURE 56. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK REGULATOR Vo R2 (EQ. 10) Put one compensator pole at zero frequency to achieve high DC gain, and put another compensator pole at either ESR zero frequency or half switching frequency, whichever is lower in Equation 10. An optional zero can boost the phase margin. CZ2 is a zero due to R2 and C3. Put compensator zero 2 to 5 times fc. 1 C 3 = ---------------f c R 2 C3 VFB R3 (EQ. 9) VREF VCOMP - (EQ. 11) Example: VIN = 5V, VO = 1.8V, IO = 6A, fsw = 1MHz, R2 = 200k, R3 = 100k, Co = 2x22F/3m, L = 1H, fc = 100kHz, then compensator resistance R6: GM + R6 3 C7 R 6 = 12.2 10 100kHz 1.8V 44F = 97.6k (EQ. 12) 1.8V 44 F C 6 = -------------------------------- = 135pF 6A 97.6k (EQ. 13) C6 44F-,------------------------------------------------1 C 7 = max (3m --------------------------------) = (1pF, 3.3pF) (EQ. 14) 97.6k 1MHz 97.6k FIGURE 57. TYPE II COMPENSATOR Figure 57 shows the type II compensator and its transfer function is expressed as shown in Equation 8: S S 1 + ------------ 1 + ------------- GM R 3 cz1 cz2 v comp - = -------------------------------------------------------- --------------------------------------------------------------A v S = --------------- C6 + C7 R2 + R3 S S v FB S 1 + ------------- 1 + ------------- cp1 cp2 (EQ. 8) Where, R2 + R3 C6 + C7 1 1 cz1 = --------------- , cz2 = --------------- cp1 = ----------------------- cp2 = ----------------------R6 C6 C7 C3 R2 R3 R6 C6 R2 C3 It is also acceptable to use the closest standard values for C6 and C7. There is approximately 3pF parasitic capacitance from VCOMP to GND. Therefore, C7 is optional. Use C6 = 150pF and C7 = OPEN. 1 C 3 = ------------------------------------------------ = 16pF 100kHz 200k (EQ. 15) Use C3 = 15pF. Note that C3 may increase the loop bandwidth from previous estimated value. Figure 58 on page 21 shows the simulated voltage loop gain. It is shown that it has a 150kHz loop bandwidth with a 42 phase margin and 10dB gain margin. It may be more desirable to achieve an increased phase margin. This can be accomplished by lowering R6 by 20% to 30%. Compensator design goal: High DC gain Choose loop bandwidth fc less than 100kHz Gain margin: >10dB Phase margin: >40 FN8736 Rev 2.00 October 28, 2016 Page 20 of 23 ISL8026, ISL8026A PCB Layout Recommendation 60 45 GAIN (dB) 30 15 0 -15 -30 100 1k 10k FREQUENCY (Hz) 100k 1M 180 150 The PCB layout is a very important converter design step to make sure the designed converter works well. For the ISL8026, ISL8026A, the power loop is composed of the output inductor L's, the output capacitor (COUT), the PHASE pins and the PGND pin. It is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide. The switching node of the converter, the PHASE pins and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. The input capacitor should be placed as close as possible to the VIN pin. The ground of input and output capacitors should be connected as close as possible. The heat of the IC is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal pad is preferable. In addition, a solid ground plane is helpful for better EMI performance. It is recommended to add at least 5 vias ground connection within the pad for the best thermal relief. PHASE () 120 90 60 30 0 100 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 58. SIMULATED LOOP GAIN FN8736 Rev 2.00 October 28, 2016 Page 21 of 23 ISL8026, ISL8026A Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE October 28, 2016 FN8736.2 On page 1, last paragraph - converted - 0.22in2 to 142mm2. Added "1.5% reference accuracy over load/line/temperature (-40C to +125C)" to Features section on page 1. Updated Ordering Information table on page 4: Added 2 parts - ISL8026FRTAJZ and ISL8026AFRTAJZ Removed "-T" from bulk parts and added Tape and Reel unit options to Note 1. Updated Recommended Operating Conditions: Added full-range industrial temperature range Electrical Spec table updates: Reference Voltage added temp -40C < TJ < +85C and added row for -40C < Tj < +125C Transresistance - Added temp -40C < TJ < +85C and added row for temperature -40C < TJ < +125C Nominal Switching Frequency - added temperature -40C < Tj < +85C and added row for temperature -40C < TJ < +125C June 26, 2015 FN8736.1 Updated the 4th Features bullet by changing from 1.2% to 1% and adding temperature range. Updated Applications bullets. on page 1. Added Related Literature section. Added evaluation boards to Ordering Information table on page 4. In "Electrical Specifications" on page 6, updated min/max specs for Reference Voltage parameter (min) from"0.593" to "0.594" and (max) from "0.607" to "0.606". Updated Equation 9 and Equations 12 through 14 on page 20. Updated example IO information from "5A" to "6A" on page 20. May 13, 2015 FN8736.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. (c) Copyright Intersil Americas LLC 2015-2016. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8736 Rev 2.00 October 28, 2016 Page 22 of 23 ISL8026, ISL8026A Package Outline Drawing For the most recent package outline drawing, see L16.3x3D. L16.3x3D 16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 3/10 4X 1.50 3.00 A 12X 0.50 B 13 6 PIN 1 INDEX AREA 16 6 PIN #1 INDEX AREA 12 3.00 1 1.60 SQ 4 9 (4X) 0.15 8 0.10 M C A B 5 16X 0.400.10 TOP VIEW 4 16X 0.23 0.05 BOTTOM VIEW SEE DETAIL "X" 0.10 C 0.75 0.05 C 0.08 C SIDE VIEW (12X 0.50) (2.80 TYP) ( 1.60) (16X 0.23) C 0 . 2 REF 5 0 . 02 NOM. 0 . 05 MAX. (16X 0.60) TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.25mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be 7. JEDEC reference drawing: MO-220 WEED. either a mold or mark feature. FN8736 Rev 2.00 October 28, 2016 Page 23 of 23