Description
The HCPL- 5120 contains a
GaAsP LED optically coupled to
an integrated circuit with a
power output stage. The device
is ideally suited for driving
power IGBTs and MOSFETs
used in motor control inverter
applications. The high
operating voltage range of the
output stage provides the drive
voltages required by gate
controlled devices. The voltage
and current supplied by this
optocoupler makes it ideally
suited for directly driving IGBTs
with ratings up to 1200 V/100
A. For IGBTs with higher
ratings, the HCPL- 5120 can be
used to drive a discrete power
stage, which drives the IGBT
gate.
The products are capable of
operation and storage over the
full military temperature range
and can be purchased as either
commercial products, with full
MIL- PRF- 38534 Class H testing,
or from Defense Supply Center
Columbus (DSCC) Standard
Microcircuit Drawing (SMD)
5962- 04204. All devices are
Agilent HCPL-5120 & HCPL-5121
DSCC SMD 5962-04204
2.0 Amp Output Current IGBT
Gate Drive Optocoupler
Data Sheet
manufactured and tested on a
MIL- PRF- 38534 certified line
and are included in the DSCC
Qualified Manufacturers List,
QML- 38534 for Hybrid
Microcircuits.
Schematic Diagram
Applications
• Industrial and Military
Environments
• High Reliability Systems
• Harsh Industrial Environments
• Transportation, Medical, and Life
Critical Systems
• Uninterruptible Power Supplies
(UPS)
• Isolated IGBT/MOSFET Gate Drive
• AC and Brushless DC Motor Drives
• Industrial Inverters
• Switch Mode Power Supplies
(SMPS)
1
3
SHIELD
2
4
8
6
7
5
N/C
CATHODE
ANODE
N/C
V
CC
V
O
V
O
V
EE
Features
•Performance Guaranteed over Full
Military Temperature Range:
-55°C to +125°C
• Manufactured and Tested on a MIL-
PRF-38534 Certified Line
• Hermetically Sealed Packages
• Dual Marked with Device Part
Number and DSCC Drawing
Number
• QML-38534
• HCPL-3120 Function Compatibility
• 2.0 A Minimum Peak Output Current
• 0.5V Maximum Low Level Output
Voltage (VOL) Eliminates Need for
Negative Gate Drive
•10 kV/µs Minimum Common Mode
Rejection (CMR) at VCM = 1000V
•I
CC = 5 mA Maximum Supply
Current
• Under Voltage Lock-Out Protection
(UVLO) with Hysteresis
• Wide Operating VCC Range: 15 to 30
Volts
• 500 ns Maximum Propagation Delay
•± 0.35µs Maximun Delay Between
Devices
CAUTION: It is advised that normal static precautions be taken in handling and assembly of
this component to prevent damage and/or degradation which may be induced by ESD.
2
Truth Table
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
Device Marking
Outline Drawing
LED VCC − VEE
“POSITIVE GOING”
(i.e., TURN-ON)
VCC − VEE
“NEGATIVE GOING”
(i.e., TURN-OFF)
VO
OFF 0 − 30 V 0 − 30 V LOW
ON 0 − 11 V 0 − 9.5 V LOW
ON 11 − 13.5 V 9.5 − 12 V TRANSITION
ON 13.5 − 30 V 12 − 30 V HIGH
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
A
HCPL-512x
5962-04204
01Hxx 50434 COUNTRY OF MFR.
Agilent CAGE CODE*
Agilent DESIGNATOR
DSCC SMD*
PIN ONE/
ESD IDENT
Agilent P/N
DSCC SMD*
* QUALIFIED PARTS ONLY
SGP
QYYWWZ
3.81 (0.150)
MIN.
4.32 (0.170)
MAX.
9.40 (0.370)
9.91 (0.390)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
0.76 (0.030)
1.27 (0.050)
8.13 (0.320)
MAX.
7.36 (0.290)
7.87 (0.310)
0.20 (0.008)
0.33 (0.013)
7.16 (0.282)
7.57 (0.298)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
Selection Guide − Package Styles and
Lead Configuration Options
Agilent Part Number and Options
Commercial HCPL-5120
MIL-PRF-38534, Class H HCPL-5121
Standard Lead Finish Gold Plate
Solder Dipped Option −200
Butt Cut/Gold Plate Option −100
Gull Wing/Soldered Option −300
SMD Part Number
Prescript for all below 5962-
Either Gold or Solder 0420401HPX
Gold Plate 0420401HPC
Solder Dipped 0420401HPA
Butt Cut/Gold Plate 0420401HYC
Butt Cut/Soldered 0420401HYA
Gull Wing/Soldered 0420401HXA
3
Hermetic Optocoupler Op tions
Option Description
100 Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available
on commercial and hi-rel product (see drawings below for details).
200 Lead finish is solder dipped rather than gol d plated. This option is available on commercial and hi-rel product.
DSCC Drawing part numbers contain provisions for lead finish.
300 Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is avail-
able on commercial and hi- re l pr oduct (see drawings belo w for de tails). This option has solder dipped leads.
1.14 (0.045)
1.40 (0.055)
4.32 (0.170)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
7.36 (0.290)
7.87 (0.310)
0.20 (0.008)
0.33 (0.013)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
0.51 (0.020)
MIN.
4.57 (0.180)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
1.40 (0.055)
1.65 (0.065) 9.65 (0.380)
9.91 (0.390)
5° MAX.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
4
Absolute Maximum Ratings
Notes:
1. No derating required for typical case-to - ambient thermal resistan ce (θCA=140°C/W). Refer to Figure 35.
2. Maximum pulse width = 10µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum =
2.0A. See Applications section for additional details on limiting IOH peak.
3. Derate linearly above 102°C free air temperature at a rate of 6mW/°C for typical case-to-ambient thermal resistance (θCA=140°C/W). Refer to Figure 36.
4. Derate linearly above 102°C free air temperature at a rate of 6mW/°C for typical case-to-ambient thermal resistance (θCA=140°C/W). Refer to Figure 35
and 36.
ESD Classification
Recommended Operating Conditions
Parameter Symbol Min. Max. Units Note
Storage Temperature TS-65 +150 °C
Operating Temper ature TA-55 +125 °C
Case Temperatur e TC+145 °C
Junction Temperature TJ+150 °C
Lead Solder Temperature 260 for 10s °C
Average Input Current IF AVG 25 mA 1
Peak Transient Input Current
(<1 µs pulse width, 300 pps) IF PK 1.0 A
Reverse Input Voltage VR5V
“High” Peak Output Current IOH (PEAK) 2.5 A 2
“Low” Peak Output Current IOL (PEAK) 2.5 A 2
Supply Voltage (VCC-VEE)0 35 V
Output Voltage VO (PEAK) 0V
CC V
Emitter Power Dissipation PE45 mW 1
Output Power Dissipation PO250 mW 3
Total Power Dissipation PT295 mW 4
MIL-STD-883, Method 3015 (▲), Class 1
Parameter Symbol Min. Max. Units
Power Supply Voltage (VCC – VEE)1530Volts
Input Current (ON) IF (ON) 10 18 mA
Input Voltage (OFF) VF (OFF) -3.0 0.8 Volts
Operating Temper ature TA-55 125 °C
5
Electrical Specifications (DC)
Over recommended op erating conditions (TA = -55 to +125 °C, IF(ON) = 10 to 18 mA, VF(OFF) = -3.0 to 0.8V, VCC = 15 to 30 V,
VEE = Ground), unless otherwise specified.
*All typical values at TA = 25°C and VCC − VEE = 30 V, unless otherwise noted.
Parameter Symbol Test Conditions Group A
Subgroups
(13)
Limits Units Fig Note
Min. Typ.* Max.
High Level
Output Current IOH VO = (VCC − 4 V) 1, 2, 3 0.5 1.5 A 2, 3, 17 2
VO = (VCC − 15 V) 2.0 A 1
Low Level
Output Current IOL VO = (VEE + 2.5 V) 1, 2, 3 0.5 2.0 A 5, 6, 18 2
VO = (VEE + 15 V) 2.0 A 1
High Level
Output Vo ltage VOH IO = -100 mA 1, 2, 3 (VCC - 4) (VCC − 3) V 1, 3, 19 3, 4
Low Level
Output Vo ltage VOL IO = 100 mA 1, 2, 3 0.1 0.5 V 4, 6, 20
High Level
Supply Current ICCH Output Open,
IF = 10 to 18 mA 1, 2, 3 2.5 5.0 mA 7, 8
Low Level
Supply Current ICCL Output Open,
VF = -3.0 to +0.8V 1, 2, 3 2.5 5.0 mA
Threshold Input Cur-
rent Low to High IFLH IO = 0 mA,
VO > 5 V 1, 2, 3 3.5 9.0 mA 9, 15,
21
Threshold Input
Voltage High to Low VFHL 1, 2, 3 0.8 V
Input Forward
Voltage VFIF = 10 mA 1, 2, 3 1.2 1.5 1.8 V 16
Temperature
Coefficient of
Forward Voltage
∆VF/∆TAIF = 10 mA -1.6 mV/°C
Input Reverse
Breakdown Voltage BVRIR = 10 µA1, 2, 3 5V
Input Capacitance CIN f = 1 MHz,
VF = 0 V 80 pF
UVLO Threshold VUVLO+ VO > 5 V,
IF = 10 mA 1, 2, 3 11.0 12.3 13.5 V 22, 37
VUVLO- 1, 2, 3 9.5 10.7 12.0
UVLO Hysteresis UVLOHYS 1.6
6
Switching Specifications (AC)
Over recommended operating conditions (TA = -55 to +125°C, IF(ON) = 10 to 18 mA, VF(OFF) = -3.0 to 0.8V, VCC = 15 to 30 V,
VEE = Ground), unless otherwise specified.
*All typical values at TA = 25°C and VCC − VEE = 30 V, unless otherwise noted.
Parameter Symbol Test Conditions Group A
Subgroups
(13)
Limits Units Fig Note
Min. Typ.* Max.
Propagation De lay
Time to Hi gh
Output Level
tPLH Rg = 10 Ω,
Cg = 10 nF,
f = 10 kHz,
Duty Cycle = 50%
9, 10, 11 0.10 0.30 0.50 µs10, 11,
12, 13,
14, 23
11
Propagation De lay
Time to Low Output
Level
tPHL 9, 10, 11 0.10 0.30 0.50 µs
Pulse Width
Distortion PWD 9, 10, 11 0.3 µs12
Propagation De lay
Difference Between
Any Two Parts
PDD
(tPHL − tPLH)9, 10, 11 -0.35 0.35 µs33, 34 7
Rise Time tr0.1 µs23
Fall Time tf0.1 µs
UVLO Turn On Delay tUVLO ON VO > 5 V, IF = 10 mA 0.8 µs22
UVLO Turn Off Delay tUVLO OFF VO < 5 V, IF = 10 mA 0.6
Output High Level
Common Mode Tran-
sient Immunity
|CMH|I
F = 10mA,
VCM = 1000 V,
VCC = 30 V
TA = 25°C
910 kV/µs24 8,
9,
14
Output Low Level
Common Mode Tran-
sient Immunity
|CML|V
CM = 1000 V,
VF = 0 V,
VCC = 30 V
TA = 25°C
910 kV/µs8,
10,
14
7
Package Characteristics
Over recommended op erating conditions (TA = -55 to +125 °C ) unless otherwise specified.
*All typicals at TA = 25°C.
Notes:
1. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum
= 2.0 A. See Applications section for additional details on limiting IOH peak.
2. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%.
3. In this test VOH is measured with a dc load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps.
4. Maximum pulse width = 1 ms, maximum duty cycle = 20%.
5. This is a momentary withstand test, not an operating condition.
6. Device considered a two-ter minal device: pins on input side shorted togeth er and pins on output side shorted together.
7. The difference between tPHL and tPLH between any two HC PL-5120 part s under the sam e test condition.
8. Pins 1 and 4 need to be connected to LED common.
9. Co m mon mo de tra n sient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will
remain in the high state (i.e., VO > 15.0 V).
10. Common mode tran sient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will
remain in a low state (i.e., VO < 1.0 V).
11. This load condition approximates the gate load of a 1200 V/75A IGBT.
12. Pulse Width Distortion (PWD) is defined as |tPHL-tPLH| for any given device.
13. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and Class H parts receive 100% testing at 25, 125, and -5 5°C (Subgrou ps 1 and 9,
2 and 10, 3 and 11, respectively).
14. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits specified for
all lots not specifically tested.
Parameter Symbol Test Conditions Group A
Subgroups
(13)
Limits Units Fig Note
Min. Typ.* Max.
Input-Output
Leakage Current II-O VI-O = 1500Vdc
RH = 45%,
t = 5 sec.,
TA = 25°C
1 1.0 µA5, 6
Resistance
(Input-Output) RI-O VI-O = 500 VDC 1010 Ω6
Capacitance
(Input-Output) CI-O f = 1 MHz 2.5 pF 6
8
Figure 1. V OH vs. Temperature Figure 2. IOH vs. Te mperature Figure 3. VOH vs. IOH
Figure 4. V OL vs. Temperature Figure 5. IOL vs. Temperature Figure 6. VOL vs. IOL
Figure 7. ICC vs. Temperature Figure 8. ICC vs. VCC Figure 9. IFLH vs. Temperature
IF = 10mA to 18mA
IOUT = -100mA
VCC = 15 to 30V
VEE = 0V
4
3
2
1
0
(V
OH
- V
CC
) - HIGH OUTPUT VOLTAGE DROP - V
-55 -35 -15 5 25 45 65 85 105 125
TA - TEMPERATURE - oC
I
OH
- OUTPUT HIGH CURRENT - A
IF = 10mA to 18mA
VOUT = (VCC - 4V)
VCC = 15 to 30V
VEE = 0V
T
A
- TEMPERATURE -
o
C
1.4
1.6
1.8
2.0
2.2
2.4
-55 -35 -15 5 25 45 65 85 105 125
-6
-5
-4
-3
-2
-1
0.0 0.5 1.0 1.5 2.0 2.5
IOH - OUTPUT HIGH CURRENT - A
(V
OH
- V
CC
) - OUTPUT HIGH VOLTAGE DROP - V
I
F
= 10 to 18mA
V
CC
= 15 t o 30V
V
EE
= 0V
125
o
C
25
o
C
-5
o
C
0.00
0.05
0.10
0.15
0.20
0.25
0.30
-55 -35 -15 5 25 45 65 85 105 125
T
A
- TEMPERATURE -
o
C
V
OL
- OUTPUT LOW VOLTAGE - V
V
F(OFF)
= -3.0 to 0.8V
I
OUT
= 100mA
V
CC
= 15 to 30V
V
EE
= 0V
0
1
2
3
4
-35 5 25 45 65 85 105 125
T
A
- TEMPERATURE -
o
C
I
LOW
- OUTPUT LOW CURRENT - A
-55 -15
V
F(OFF)
= -3.0 to 0.8V
V
OUT
= 2.5V
V
CC
= 15 to 30V
V
EE
= 0V
0
1
2
3
4
5
6
7
8
0.0 0.5 1.0 1.5 2.0 2.5
I
OL
- OUTPUT LOW CURRENT - A
V
OL
- OUTPUT LOW VO LTAG E - V
V
F(OFF)
= -3.0 to 0.8V
V
CC
= 15 t o 30V
V
EE
= 0V
125
o
C
25
o
C
-5
o
C
1.5
2.0
2.5
3.0
3.5
4.0
-55 -35 -15 5 25 45 65 85 105 125
T
A
- TEMPERATURE -
o
C
ICC - SUPP LY CURRE NT - mA
VCC = 30V
VEE = 0V
IF = 10mA for ICCH
IF = 0mA for ICCL
I
CCH
I
CCL
1.5
2.0
2.5
3.0
3.5
4.0
15 20 25 30
VCC - SUPPLY VOLTAG E - V
I
CC
- SUPP LY CURRE NT - mA
IF = 10mA for ICCH
IF = 0mA for ICCL
TA = 25 oC
VEE = 0V
I
CCH
I
CCL
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-55 -35 5 25 45 65 85 125
-15 105
TA - TEMPERATURE - oC
I
FLH
- LOW TO HIGH CURRENT THRESHOLD - mA
VCC = 15 to 30V
VEE = 0V
OUTPUT = OPEN
9
Figure 10. Propagation Delay vs. VCC Figure 11. Propagation Delay vs. IF Figure 12. Propagation Delay vs. Temperature
Figure 13. Propagation Delay vs. Rg Figure 14. Propagation Delay vs. Cg Figure 15. Transfer Characteristics
Figure 16. Input Current vs. Forward Voltage
100
200
300
400
500
15 20 25 30
VCC - SUPPLY VOLTAG E - V
T
P
- PROPAGATION DELAY - ns
IF = 10mA
VCC = 30V, VEE = 0V
Rg = 10 Ω, Cg = 10 nF
Duty Cycle = 50%
TA = 25 oC, f = 10khz
T
PLH
T
PHL
100
200
300
400
500
6 8 10 12 14 16 18 20 22 24 26
I
F
- FORWARD LED CURRENT - mA
T
P
- PROPAGATION DELAY - ns
VCC = 30V, VEE = 0V
Rg = 10 Ω, Cg = 10 nF
TA = 25 oC
Duty Cycle = 50%
f = 10khz
T
PLH
T
PHL
100
200
300
400
500
-55 -35 -15 5 25 45 65 85 105 125
T
A
- TEMPERATURE -
o
C
T
P
- PROPAGATION DELAY- ns
IF = 10mA
VCC = 30V, VEE = 0V
Rg = 10 Ω, Cg = 10 nF
Duty Cycle = 50%
f = 10khz
T
PLH
T
PHL
01020304050
100
200
300
400
500
TP - PROPAGATION DELAY -ns
Rg - SERIES LO AD RESISTANCE - Ω
VCC = 30V, VEE = 0V
TA = 25 oC, IF = 10mA
Cg = 10 nF
Duty Cycle = 50%
f = 10khz
T
PLH
T
PHL
Cg - LOAD CAPACITANCE - nF
T
P
- PROPAGATION DELAY -ns
100
200
300
400
500
0 20 40 60 80 100
T
PLH
T
PHL
VCC = 30V, VEE = 0V
TA = 25 oC, IF = 10mA
Rg = 10 Ω
Duty Cycle = 50%
f = 10khz
0
5
10
15
20
25
30
012345
IF - FORWARD LED CURRENT - mA
V
O
- OUTPUT VOLTAGE - V
TA = 25 oC
0.001
0.01
0.1
1
10
100
1000
1.20 1.30 1.40 1.50 1.60
VF - FORWARD VOLTAGE - V
1.10
I
F
- FORWARD CURRENT - mA
TA = 25oC
10
Figure 17. IOH Test Circuit
Figure 19. VOH Test Circuit
Figure 21. IFLH Test Circuit
Figure 22. UVLO Test Circuit
0.1 µF
V
CC
= 15
to 30 V
1
3
+
2
4
8
6
7
5
+4 V
I
OH
IF = 10 to
18 mA
_
_
0.1 µF
V
CC
= 15
to 30 V
1
3
I
F
= 10 to
18 mA +
2
4
8
6
7
5
100 mA
V
OH
_
0.1 µF
V
CC
= 15
to 30 V
1
3
I
F
+
2
4
8
6
7
5
V
O
> 5 V _
0.1 µF
V
CC
1
3
I
F
= 10 mA +
2
4
8
6
7
5
V
O
> 5 V _
Figure 18. IOL Test Circuit
Figure 20. VOL Test Circuit
0.1 µF
V
CC
= 15
to 30 V
1
3
+
2
4
8
6
7
5
2.5 V
I
OL
+
_
_
0.1 µF
V
CC
= 15
to 30 V
1
3
+
2
4
8
6
7
5
100 mA
V
OL
_
11
Figure 23. tPLH, tPHL, tr, and tf Tes t Circuit and Waveforms
Figure 24. CMR Test Circuit and Waveforms
0.1 µF VCC = 15
to 30 V
10 Ω
1
3
IF = 10 to 18 mA
VO
+
+
2
4
8
6
7
5
10 KHz
50% DUTY
CYCLE
500 Ω
10 nF
IF
VOUT
tPHL
tPLH
tf
tr
10%
50%
90%
Tr = Tf < 10 ns_
_
_
0.1 µF
V
CC
= 30 V
1
3
I
F
V
O
+
+
2
4
8
6
7
5
A
+
B
V
CM
= 1000 V
5 V
V
CM
∆t
0 V
V
O
SWITCH AT B: I
F
= 0 mA
V
O
SWITCH AT A: I
F
= 10 mA
V
OL
V
OH
∆t
V
CM
δV
δt=
_
_
_
12
Applications Information
Eliminating Negative IGBT Gate Drive
To keep the IGBT firmly off, the
HCPL- 5120 has a very low
maximum VOL specification of
0.5 V. The HCPL- 5120 realizes
this very low VOL by using a
DMOS transistor with 1 Ω
(typical) on resistance in its
pull down circuit. When the
HCPL- 5120 is in the low state,
the IGBT gate is shorted to the
emitter by Rg + 1 Ω. Minimizing
Rg and the lead inductance from
the HCPL- 5120 to the IGBT
gate and emitter (possibly by
mounting the HCPL- 5120 on a
small PC board directly above
the IGBT) can eliminate the
need for negative IGBT gate
drive in many applications as
shown in Figure 25. Care should
be taken with such a PC board
design to avoid routing the
IGBT collector or emitter traces
close to the HCPL- 5120 input
as this can result in unwanted
coupling of transient signals
into the HCPL- 5120 and
degrade performance. (If the
IGBT drain must be routed near
the HCPL- 5120 input, then the
LED should be reverse- biased
when in the off state, to prevent
the transient signals coupled
from the IGBT drain from
turning on the HCPL- 5120.)
Selecting the Gate Resistor (Rg) to
Minimize IGBT Switching Losses.
Step 1: Calculate Rg Minimum from
the IOL Peak Specification.
The IGBT and Rg in Figure 26
can be analyzed as a simple RC
circuit with a voltage supplied
by the HCPL- 5120.
(VCC - V
EE - V
OL)
Rg = –––––––––––––––––
IOLPEAK
(VCC – VEE – 2V)
= ––––––––––––––––––
IOLPEAK
(15 V + 5 V – 2V)
= –––––––––––––––––––
2.5 A
= 7.2
Ω
≈ 8 Ω
The VOL value of 2 V in the
previous equation is a
conservative value of VOL at the
peak current of 2.5A (see Figure
6). At lower Rg values the
voltage supplied by the HCPL-
5120 is not an ideal voltage
step. This results in lower peak
currents (more margin) than
predicted by this analysis. When
negative gate drive is not used
VEE in the previous equation is
equal to zero volts
Step 2: Check the HCPL-5120 Power
Dissipation and Increase Rg if
Necessary.
The HCPL- 5120 total power
dissipation (PT) is equal to the
sum of the emitter power (PE)
and the output power (PO):
PT = PE + PO
PE = IF
•
VF
•
Duty Cycle
PO = PO(BIAS) + PO (SWITCHING)
= ICC
•
(VCC - V
EE) + ESW(Rg,
Qg)
•
f
For the circuit in Figure 26
with IF (worst case) = 18 mA,
Rg = 8 Ω, Max Duty Cycle = 80%,
Qg = 500 nC, f = 20 kHz and TA
max = 125°C:
PE = 18 mA
•
1.8 V
•
0.8 = 26 mW
PO = 4.25 mA
•
20 V + 1.0 µJ
•
20
kHz
= 85 mW + 20 mW
= 105 mW
< 112 mW (PO(MAX) @ 125
°
C
= 250 mW - 23
°
C
•
6 mW/°C)
The value of 4.25 mA for ICC in
the previous equation was
obtained by derating the ICC
max of 5 mA (which occurs at -
55°C) to ICC max at 125°C.
Since PO for this case is less
than PO(MAX), Rg of 8 Ω is
appropriate.
Figure 25. Recommended LED Drive and Application Circuit
+ HVDC
3-PHASE
AC
- HVDC
0.1 µF VCC = 18 V
1
3
+
2
4
8
6
7
5
270 Ω
CONTROL
INPUT
Rg
Q1
Q2
74XXX
OPEN
COLLECTOR
_
+5 V
13
Figure 27. Energy Dissipated in the HCPL-5120
for Each IGBT Switching Cycle
LED Drive Circuit Considerations for
Ultra High CMR Performance.
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive
coupling from the input side of
the optocoupler, through the
package, to the detector IC as
shown in Figure 28. The HCPL-
5120 improves CMR
performance by using a detector
IC with an optically transparent
Faraday shield, which diverts
the capacitively coupled current
away from the sensitive IC
circuitry. However, this shield
does not eliminate the
capacitive coupling between the
LED and optocoupler pins 5- 8
as shown in Figure 29. This
capacitive coupling causes
perturbations in the LED
current during common mode
transients and becomes the
major source of CMR failures
for a shielded optocoupler. The
main design objective of a high
CMR LED drive circuit becomes
keeping the LED in the proper
state (on or off) during common
mode transients. For example,
the recommended application
circuit (Figure 25), can achieve
10 kV/µs CMR while minimizing
component complexity.
Techniques to keep the LED in
the proper state are discussed
in the next two sections.
Figure 28. Optocoupler Input to Output Capaci-
tance Model for Unshielded Optocouplers.
Figure 29. Optocoupler Input to Output Capaci-
tance Model for Shielded Optocoupl e rs.
Figure 26. Typical Application Circuit with Negative IGBT Gate Drive
+ HVDC
3-PHASE
AC
- HVDC
0.1 µF V
CC
= 15 V
1
3
+
2
4
8
6
7
5
Rg
Q1
Q2
V
EE
= -5 V
+
270 Ω
+5 V
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
_
_
PE Parameter Description
IFLED Current
VFLED On Voltage
Duty Cycle Maximum LED
Duty Cycle
PO Parameter Description
ICC Supply Current
VCC Positive Supply
Voltage
VEE Negative Supply
Voltage
ESW (Rg, Qg) Energy Dissipation in
the HCPL-5120 for
each IGBT Switchin g
Cycle (See Figure 27)
f S witching Frequency
Esw - ENERGY PER SWITCHING CYCLE - µJ
0
0
Rg - GATE RESISTANCE - Ω
100
3
20
7
40
2
60 80
6Qg = 100 nC
Qg = 250 nC
Qg = 500 nC
5
4
1
VCC = 19 V
VEE = -9 V
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
C
LEDO1
C
LEDO2
14
CMR with the LED On (CMRH).
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This
is achieved by overdriving the
LED current beyond the input
threshold so that it is not
pulled below the threshold
during a transient. A minimum
LED current of 10 mA provides
adequate margin over the
maximum IFLH of 7 mA to
achieve 10 kV/µs CMR.
CMR with the LED Off (CMRL).
A high CMR LED drive circuit
must keep the LED off (VF ≤
VF(OFF)) during common mode
transients. For example, during
a - dVcm/dt transient in Figure
30, the current flowing through
CLEDP also flows through the
RSAT and VSAT of the logic gate.
As long as the low state voltage
developed across the logic gate
is less than VF(OFF), the LED
will remain off and no common
mode failure will occur.
Figure 30. Equivalent Circuit for Figure 25 During Common Mode Transient.
Rg
1
3
V
SAT
2
4
8
6
7
5
+
VCM
I
LEDP
C
LEDP
C
LEDN
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING ∆dVCM/dt
+5 V
+VCC = 18 V
* * *
0.1
µF
+_
_
* * *
_
The open collector drive circuit,
shown in Figure 31, cannot keep
the LED off during a +dVcm/dt
transient, since all the current
flowing through CLEDN must be
supplied by the LED, and it is
not recommended for
applications requiring ultra high
CMRL performance. Figure 32 is
an alternative drive circuit
which, like the recommended
application circuit (Figure 25),
does achieve ultra high CMR
performance by shunting the
LED in the off state.
Figure 31. Not Recommended Open Collector
Drive Circuit
Figure 32. Recommended LED Drive Circuit for
Ultra-High CMR
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
Q1
I
LEDN
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
15
IPM Dead Time and Propagation
Delay Specifications.
The HCPL- 5120 includes a
Propagation Delay Difference
(PDD) specification intended to
help designers minimize “dead
time” in their power inverter
designs. Dead time is the time
period during which both the
high and low side power
transistors (Q1 and Q2 in
Figure 25) are off. Any overlap
in Q1 and Q2 conduction will
result in large currents flowing
through the power devices
between the high and low
voltage motor rail
To minimize dead time in a
given design, the turn on of
LED2 should be delayed
(relative to the turn off of
LED1) so that under worst- case
conditions, transistor Q1 has
just turned off when transistor
Q2 turns on, as shown in Figure
33. The amount of delay
necessary to achieve this
conditions is equal to the
maximum value of the
propagation delay difference
specification, PDDMAX, which is
specified to be 350 ns over the
operating temperature range of
-55
°C to 125°C.
Delaying the LED signal by the
maximum propagation delay
difference ensures that the
minimum dead time is zero, but
it does not tell a designer what
the maximum dead time will be.
The maximum dead time is
equivalent to the difference
between the maximum and
minimum propagation delay
difference specifications as
shown in Figure 34. The
maximum dead time for the
HCPL- 5120 is 700 ns (= 350 ns
- (- 350 ns)) over an operating
temperature range of - 55°C to
125°C.
Note that the propagation delays
used to calculate PDD and dead
time are taken at equal
temperatures and test
conditions since the
optocouplers under
consideration are typically
mounted in close proximity to
each other and are switching
identical IGBTs.
Figure 33. Minimum LED Skew for Zero Dead Time
Figure 34. Waveforms for Dead Time Calculations
PDD* MAX = (t
PHL
- t
PLH
)
MAX
= t
PHL MAX
- t
PLH MIN
*PDD = PROPAGATION
DELAY DIFFERENCE
NOTE:
FOR PDD CALCULATIONS
THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME
TEMPERATURE AND TEST
CONDITIONS.
V
OUT1
I
LED2
V
OUT2
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
t
PHL MAX
t
PLH MIN
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (t
PHL MAX
- t
PHL MIN
) + (t
PLH MAX
- t
PLH MIN
)
= (t
PHL MAX
- t
PLH MIN
) - (t
PHL MIN
- t
PLH MAX
)
= PDD* MAX - PDD* MIN
*PDD = PROPAGATION
DELAY DIFFERENCE
NOTE:
FOR DEAD TIME AND
PDD CALCULATIONS ALL
PROPAGATION DELAYS ARE
TAKEN AT THE SAME
TEMPERATURE AND TEST
CONDITIONS.
V
OUT1
I
LED2
V
OUT2
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
t
PHL MAX
t
PHL MIN
t
PLH MIN
t
PLH MAX
(t
PHL
- t
PLH
) MAX
= PDD* MAX
Figure 35. Input Thermal Derating Curve,
Dependence of case-to-ambient Thermal
Resistance
Figure 36. Output Thermal Derating Curve,
Dependence of case-to-ambient Thermal
Resistance
-55 -25 5 35 95 125
PE - INPUT POWER - mW
65
T
A
- AMBIENT TEMPERATURE -
o
C
50
30
20
10
0
40
= 70
o
C/W
= 140
o
C/W
= 210
o
C/W
case-to-ambient thermal resistance
0
50
100
150
200
250
300
-55 -25 5 35 65 95 125
P
O
- OUTPUT POWER - mW
T
A
- AMBIENT TEMPERATURE -
o
C
= 70
o
C/W
= 140
o
C/W
= 210
o
C/W
case-to-ambient thermal resistance
www.agilent.com/
semiconductors
For product information and a complete list
of distributors, please go to our web site.
For technical assistan ce call:
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or (916) 788-6763
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Data subject to change.
Copyright2004 Agilent Technologies, Inc.
June 28, 2004
5989-0942EN
Under Voltage Lockout Feature.
The HCPL-5120 contains an under
voltage lockout (UVLO) feature that
is designed to protect the IGBT under
fault conditions which cause the
HCPL-5120 supply voltage
(equivalent to the fully-charged IGBT
gate voltage) to drop below a level
necessary to keep the IGBT in a low
resistance state. When the HCPL-
5120 output is in the high state and the
supply voltage drops below the
HCPL-5120 VUVLO– threshold (9.5 <
VUVLO– < 12.0) the optocoupler
output will go into the low state with a
typical delay, UVLO Turn Off Delay,
of 0.6 µs.
When the HCPL-5120 output is in the
low state and the supply voltage rises
above the HCPL-5120 VUVLO+
threshold (11.0 < VUVLO+ < 13.5) the
optocoupler output will go into the
high state (assuming LED is “ON”)
with a typical delay, UVLO T u rn On
Delay of 0.8 µs.
7
Figure 37. Under Voltage Lock Out
MIL-PRF-38534 Class H and DSCC
SMD Test Program
Agilent Technologies’ Hi- Rel
Optocouplers are in compliance
with MIL- PRF- 38534 Class H.
Class H devices are also in
compliance with DSCC drawing
5962- 04204.
Testing consists of 100%
screening and quality
conformance inspection to MIL-
PRF- 38534.
V
O
- OUTPUT VOLTAGE - V
0
0
(V
CC
- V
EE
) - SUPPLY VOLTAGE - V
10
5
14
10 15
2
20
6
8
4
12
(12.3, 10.8)
(10.7, 9.2)
(10.7, 0.1) (12.3, 0.1)
