IDT707288S25PF8 - Integrated Device Technology, Inc.

MAY 2000

DSC 3592/7

HIGH-SPEED

64K x 16 BANK-SWITCHABLE

DUAL-PORTED SRAM WITH

EXTERNAL BANK SELECTS

Features

◆◆

◆64K x 16 Bank-Switchable Dual-Ported SRAM Architecture

– Four independent 16K x 16 banks

– 1 Megabit of memory on chip

◆◆

◆Fast asynchronous address-to-data access time: 15ns

◆◆

◆User-controlled input pins included for bank selects

◆◆

◆Independent port controls with asynchronous address &

data busses

◆◆

◆Four 16-bit mailboxes available to each port for inter-

IDT707288S/L

NOTES:

1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins

serve as mailbox address inputs.

2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for

more details.

Functional Block Diagram

processor communications; interrupt option

◆◆

◆Interrupt flags with programmable masking

◆◆

◆Dual Chip Enables allow for depth expansion without

external logic

◆◆

◆UB and LB are available for x8 or x16 bus matching

◆◆

◆TTL-compatible, single 5V (±10%) power supply

◆◆

◆Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)

16Kx16

MEMORY

ARRAY

(BANK 3)

MUX

R/WL

CE0L

CE1L

UBL

LBL

OEL

I/O8L-15L

I/O0L-7L

A13L

A0L(1)

A5L(1)

A0L(1)

LBL/UBL

OEL

R/WL

CEL

MAILBOX

INTERRUPT

LOGIC

16Kx16

MEMORY

ARRAY

(BANK 1)

MUX

16Kx16

MEMORY

ARRAY

(BANK 0)

MUX

CONTROL

LOGIC

I/O

CONTROL

BANK

DECODE

ADDRESS

DECODE

R/WR

CE0R

CE1R

UBR

LBR

OER

I/O8R-15R

I/O0R-7R

A13R

A0R(1)

CONTROL

LOGIC

I/O

CONTROL

BANK

DECODE

ADDRESS

DECODE

A5R(1)

A0R(1)

LBR/UBR

OER

R/WR

CER

3592 drw 01

MBSELR

INTR

MBSELL

INTL

BKSEL3(2)

BKSEL0(2) BANK

SELECT

BA1R

BA0R

BA1L

BA0L

6.42

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description

The IDT707288 is a high-speed 64K x 16 (1M bit) Bank-Switchable

Dual-Ported SRAM organized into four independent 16K x 16 banks. The

device has two independent ports with separate control, address, and

I/O pins for each port, allowing each port to asynchronously access

any 16K x 16 memory block not already accessed by the other port.

Accesses by the ports into specific banks are controlled via bank select pin

inputs under the user's control. Mailboxes are provided to allow inter-

processor communication. Interrupts are provided to indicate mailbox

writes have occurred. An automatic power down feature controlled by

the chip enables (CE0 and CE1) permits the on-chip circuitry of each port

to enter a very low standby power mode and allows fast depth expansion.

The IDT707288 offers a maximum address-to-data access time as fast

as 15ns, and is packaged in a 100-pin Thin Quad Flatpack (TQFP).

Functionality

The IDT707288 is a high-speed asynchronous 64K x 16 Bank-

Switchable Dual-Ported SRAM, organized in four 16K x 16 banks. The

two ports are permitted independent, simultaneous access into separate

banks within the shared array. There are four user-controlled Bank Select

input pins, and each of these pins is associated with a specific bank within

the memory array. Access to a specific bank is gained by placing the

associated Bank Select pin in the appropriate state: VIH assigns the bank

to the left port, and VIL assigns the bank to the right port (See Truth Table

IV). Once a bank is assigned to a particular port, the port has full access

to read and write within that bank. Each port can be assigned as many

banks within the array as needed, up to and including all four banks.

The IDT707288 provides mailboxes to allow inter-processor commu-

nication. Each port has four 16-bit mailbox registers available to which it

can write and read and which the opposite port can read only. These

mailboxes are external to the common SRAM array, and are accessed

by setting MBSEL = VIL while setting CE = VIH. Each mailbox has an

associated interrupt: a port can generate an interrupt to the opposite port

by writing to the upper byte of any one of its four 16-bit mailboxes. The

interrupted port can clear the interrupt by reading the upper byte. This read

will not alter the contents of the mailbox.

If desired, any source of interrupt can be independently masked via

software. Two registers are provided to permit interpretation of interrupts:

the Interrupt Cause Register and the Interrupt Status Register. The

Interrupt Cause Register gives the user a snapshot of what has caused

the interrupt to be generated - the specific mailbox written to. The

information in this register provides post-mask signals: interrupt sources

that have been masked will not be updated. The Interrupt Status Register

gives the user the status of all bits that could potentially cause an interrupt

regardless of whether they have been masked. Truth Table V gives a

detailed explanation of the use of these registers.

6.42

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

INDEX

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

IDT707288PF

PN100-1(4)

100-Pin TQFP

Top View(5)

GND

OER

R/WR

MBSELR

CE1R

CE0R

BKSEL3

GND

A9R

A10R

A8R

A7R

A6R

A11R

I/O10R

I/O11R

I/O12R

I/O13R

I/O14R

I/O15R

GND

UBR

LBR

3592 drw 02

I/O15L

GND

OEL

R/WL

MBSELL

CE1L

CE0L

Vcc

BKSEL0

A11L

A10L

A9L

A8L

A7L

A6L

I/O10L

I/O11L

I/O12L

I/O13L

I/O14L

UBL

LBL

GND

I/O5R

I/O4R

I/O3R

I/O2R

I/O0R

I/O0L

GND

I/O2L

I/O4L

I/O5L

I/O6L

I/O7L

I/O3L

I/O1R

I/O7R

I/O8R

I/O9R

I/O8L

I/O9L

I/O6R

A4R

A5L

A4L

A3R

A0R

A12R

INTR

INTL

BKSEL1

A3L

A5R

GND

Vcc

I/O1L

Vcc

GND

A13R

BA0R

BA1R

A1R

A2R

BKSEL2

GND

A0L

A12L

BA0L

BA1L

A1L

A2L

A13L

Pin Names

NOTES:

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

NOTES:

1. Duplicated per port.

2. Each bank has an input pin assigned that allows the user to toggle the assignment

of that bank between the two ports. Refer to Truth Table IV for more details. When

changing the bank assignments, accesses of the affected banks must be

suspended. Accesses may continue uninterrupted in banks that are not being

reallocted.

3. Generated upon mailbox access.

4. All Vcc pins must be connected to power supply.

5. All GND pins must be connected to ground supply.

6. The first six address pins (A0-A5) for each port serve dual functions. When MBSEL

= VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins

serve as mailbox address inputs (A6-A13 are ignored).

Pin Configurations(1,2,3)

A0 - A13(1,6) Address Inputs

BA0 - BA1(1) B ank Ad d re s s Inp uts

MBSEL(1) Mailb ox Ac ce ss Co ntrol Gate

BKSEL0-3(2) B ank Se le ct Inp uts

R/W(1) Re ad/Write Enab le

OE(1) Output Enab le

0, CE

1(1) Chip Enables

, LB(1) I/ O B yte E nab l e s

I/O0 - I/O15(1) B i di re c tio nal Data Inp ut/ Outp ut

INT(1) Interrup t F lag (Output)(3)

VCC(4) +5VPower

GND(5) Ground

3 592 t bl 01

6.42

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth Table III  Mailbox Read/Write Control(1)

NOTES:

1. Chip Enable references are shown above with the actual CE0 and CE1 levels; CE is a reference only.

2. Port "A" and "B" references are located where CE is used.

3 . "H" = VIH and "L" = VIL.

4. CE and MBSEL cannot both be active at the same time.

Truth Table I  Chip Enable(1,2,3,4)

Truth Table II  Non-Contention Read/Write Control

NOTES:

1. BA0L - BA1L ≠ BA0R - BA1R: cannot access same bank simultaneously from both ports.

2. Refer to Truth Table I.

3. CE and MBSEL cannot both be active at the same time.

NOTES:

1. There are four mailbox locations per port written to and read from all the I/O's (I/O0-I/O15). These four mailboxes are addressed by A0-A5. Refer to Truth Table V.

2. Refer to Truth Table I.

3. Each mailbox location contains a 16-bit word, controllable in bytes by setting input levels to UB and LB appropriately.

CE CE0CE1Mode

LVIL VIH Port Se le cted (TTL Active)

< 0.2V >VCC -0.2V Po rt Se lec te d (CMOS Activ e)

VIH X Port Deselected (TTL Inactive)

IL Port Deselected (TTL Inactive)

>VCC -0.2V X Po rt Des ele cte d (CMOS Inactiv e)

X<0.2V Port Deselected (CMOS Inactive)

3 592 t b l 02

Inputs(1) Outputs

Mode

CE(2) R/WOE UB LB MBSEL I/O8-15 I/O0-7

H X X X X H Hig h-Z Hig h-Z De se lcte d : P o wer-Do wn

X(3) XXHH X

(3) Hi g h-Z Hig h-Z B o th B yte s De s e le c te d

LLXLHHDATA

IN High-Z Write to Upper Byte Only

L L X H L H High-Z DATAIN Wri te to Lo we r B y te O nly

LLXLLHDATA

IN DATAIN Write to B o th By te s

LHLLHHDATA

OUT High-Z Read Upper Byte Only

LHLHLHHigh-ZDATA

OUT Re ad Lo we r By te Only

LHLLLHDATA

OUT DATAOUT Re ad B o th B yte s

X(3) XHXX X

(3) High-Z High-Z Outputs Disabled

3 5 92 tbl 03

Inputs Outputs

Mode

CE(2) R/WOE UB LB MBSEL I/O8-15 I/O0-7

HHL X

(3) X(3) LDATA

OUT DATAOUT Read Data from Mailbox, ↓ cle ars interrup t

HHLLLLDATA

OUT DATAOUT Read Data from Mailbox, ↓ cle ars interrup t

HLX L

(3) L(3) LDATA

IN DATAIN Write Data into Mailb ox

LXXXXL ____ ____ No t All owe d

3592 tbl 04

6.42

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Absolute Maximum Ratings(1)

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (V CC = 5.0V ± 10%)

Capacitance(1)

(TA = +25°C, f = 1.0mhz) TQFP Package

Recommended DC Operating

Conditions

Maximum Operating Temperature

and Supply Voltage(1)

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those

indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect

reliability.

2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.

NOTES:

1. VIL > -1.5V for pulse width less than 10ns.

2. VTERM must not exceed Vcc + 10%.

NOTES:

1. This parameter is determined by device characterization but is not production

tested.

2 . 3dV represents the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

3. COUT represents CI/O as well.

NOTE:

1. At Vcc < 2.0V, input leakages are undefined.

NOTES:

1. This is the parameter TA. This is the "instant on" case temperature.

Symbol Rating Commercial

& Industrial Unit

VTERM(2) Te rminal Voltage

wi th Re s p e ct

to GND

-0.5 to +7.0 V

TBIAS Temperature

Under Bias -55 to +125 oC

TSTG Storage

Temperature -65 to +150 oC

IOUT DC Outp ut

Current 50 mA

3592 tbl 05

Grade Ambient

Temperature GND Vcc

Commercial 0OC to + 70OC0V5.0V

+ 10%

Industrial -40OC to + 85OC0V 5.0V

+ 10%

3 592 t bl 06

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 4.5 5.0 5.5 V

GND Ground 0 0 0 V

VIH Inp ut Hig h Vo l tag e 2. 2 ____ 6.0(2) V

VIL Inp ut Lo w Vo l tag e -0. 5(1) ____ 0.8 V

3592 tbl 07

Symbol Parameter Conditions(2) Max. Unit

CIN Inp ut Cap ac itanc e V IN = 3dV 9 pF

COUT(3) Outp ut Capac i tanc e V OUT = 3dV 10 pF

3592 tbl 08

Symbol Parameter Test Conditions

707288S 707288L

UnitMin. Max. Min. Max.

|ILI| Input Leak age Curre nt(1) VCC = 5.5V, VIN = 0V to VCC ___ 10 ___ 5µA

|ILO| Output Leakage Current CE = VIH, MBSEL = VIH, VOUT = 0V to VCC ___ 10 ___ 5µA

VOL Output Lo w Vo ltage IOL = +4mA ___ 0.4 ___ 0.4 V

VOH Output Hig h Voltag e IOH = -4mA 2.4 ___ 2.4 ___ V

3592 t bl 0 9

6.42

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(1,6) (VCC = 5.0V ± 10%)

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)

3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input

levels of GND to 3V.

4. f = 0 means no address or control lines change.

5 . Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6. Refer to Truth Table I.

707288X15

Com'l Only 707288X20

Com'l & Ind 707288X25

Com'l & Ind

S ym bol P arameter Test Condi tion V ersi on Typ. (2) Max. Typ.(2) Max. Typ.(2) Max. Unit

ICC Dynamic Op erating Curre nt

(Bo th Po rts Activ e) CE = VIL, Outputs Disabled

MBSEL = VIH

f = fMAX(3)

COM'L S

L220

220 350

300 200

200 340

290 190

190 330

280 mA

IND S

L____

____

____ 250

250 370

320 240

240 360

310

ISB1 Stand by Current

(Bo th Po rts - TTL Le ve l

Inputs)

CEL = CER = VIH

MBSELR = MBSELL = VIH

f = fMAX(3)

COM'L S

L50

50 90

65 45

45 90

65 40

40 90

65 mA

IND S

L____

____

____ 45

45 100

75 40

40 100

ISB2 Stand by Current

(One Port - TTL Leve l Inputs ) CE"A" = VIL and CE"B" = VIH(5)

Active Po rt Outputs Disable d,

f=fMAX(3)

MBSELR = MBSELL = VIH

COM'L S

L130

130 230

200 120

120 215

185 110

110 200

170 mA

IND S

L____

____

____ 140

140 235

205 130

130 220

190

ISB3 Full Standby Current (Both

P orts - A ll CMOS Le ve l

Inputs)

Bo th Ports CEL and

CER > VCC - 0. 2V

VIN > VCC - 0.2V o r

VIN < 0. 2 V, f = 0(4)

MBSELR = MBSELL > VCC - 0. 2V

COM'L S

L1.5

1.5 15

51.5

1.5 15

51.5

1.5 15

5mA

IND S

L____

____

____ 1.5

1.5 30

10 1.5

1.5 30

ISB4 Full Stand by Current

(One Port - All CMOS Le ve l

Inputs)

CE"A" < 0. 2V and

CE"B" > VCC - 0. 2V(5)

MBSELR = MBSELL > VCC - 0. 2V

VIN > VCC - 0.2V or V IN < 0.2V

Active Port Outputs Disabled

f = fMAX(3)

COM'L S

L145

145 230

195 135

135 210

180 130

130 200

170 mA

IND S

L____

____

____ 135

135 230

200 130

130 220

190

3592 tbl 10

6.42

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Test Conditions

Figure 1. AC Output Test Load

Figure 3. Lumped Capacitance Load Typical Derating Curve

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(4)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = VIL and MBSEL = VIH. To access mailbox, CE = VIH and MBSEL = VIL.

4. 'X' in part numbers indicates power rating (S or L).

5. Refer to Truth Table I.

Inp ut P ul se Le v e ls

Input Ris e/Fall Time s

Inp ut Ti mi ng Re fere nc e Le v el s

Output Re ference Levels

Outp ut Lo ad

GND to 3.0V

3ns Max .

1.5V

Figures 1,2 and 3

3592 tbl 11 3592 drw 04

893Ω

30pF

347Ω

DATAOUT

INT

893Ω

5pF*

347Ω

DATAOUT

ÆtACE/tAA

(Typical, ns)

3592 drw 05

20 40 10060 80 120 140 160 180 200

Capacitance (pF)

-1

- 10pF is the I/O capacitance

of this device, and 30pF is the

AC Test Load Capacitance

707288X15

Com'l Only 707288X20

Com 'l & I nd 707288X25

Com 'l & I nd

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.

READ CYCLE

tRC Re ad Cyc le Time 15 ____ 20 ____ 25 ____ ns

tAA Address Access Time ____ 15 ____ 20 ____ 25 ns

tACE Chip Enable Acces s Time(3) ____ 15 ____ 20 ____ 25 ns

tABE Byte Enable Access Time(3) ____ 15 ____ 20 ____ 25 ns

tAOE Outp ut Enable Acce ss Time ____ 9____ 10 ____ 11 ns

tOH Output Hold from Address Change 3 ____ 3____ 3____ ns

tLZ Output Low-Z Time (1,2) 0____ 0____ 0____ ns

tHZ Output Hig h-Z Time (1,2) ____ 8____ 9____ 10 ns

tPU Ch ip Enab le to Po we r Up Time (2,5) 0____ 0____ 0____ ns

tPD Chip Dis ab le to P owe r Down Time (2,5) ____ 15 ____ 20 ____ 25 ns

tMOP Mailbox Flag Update Pulse (OE or MBSEL)10

____ 10 ____ 10 ____ ns

tMAA Mailbox Address Access Time ____ 15 ____ 20 ____ 25 ns

3592 tbl 12

Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)

*Including scope and jig.

6.42

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:

1. Bank 0 refers to the first 16Kx16 memory spaces, Bank 1 to the second 16Kx16

memory spaces, Bank 2 to the third 16Kx16 memory spaces, and Bank 3

to the fourth 16Kx16 memory spaces. 'LEFT' indicates the bank is assigned

to the left port; 'RIGHT' indicates the bank is assigned to the right port. 0-4 banks

may be assigned to either port.

2 . The bank select pin inputs must be set at either VIH or VIL - these inputs are not

tri-statable. When changing the bank assignments, accesses of the affected

banks must be suspended. Accesses may continue uninterrupted in banks that

are not beign reallocated.

3. 'H' = VIH, 'L' = VIL, 'X' = Don't Care.

Assigning the Banks via the

External Bank Selects

There are four bank select pins available on the IDT707288, and each

of these pins is associated with a specific bank within the memory array.

The pins are user-controlled inputs: access to a specific bank is assigned

to a particular port by setting the input to the appropriate level. The process

of assigning the banks is detailed in Truth Table IV. Once a bank is assigned

to a port, the owning port has full access to read and write within that bank.

The opposite port is unable to access that bank until the user reassigns the

port. Access by a port to a bank which it does not control will have no effect

Truth Table IV  Memory Bank

Assignment (CE = VIH)(2,3)

Mailbox Interrupts and Interrupt

Control Registers

If the user chooses the mailbox interrupt function, four mailbox locations

are assigned to each port. These mailbox locations are external to the

memory array. The mailboxes are accessed by setting MBSEL = VIL

while holding CE = VIH.

The mailboxes are 16 bits wide and controllable by byte: the message

is user-defined since these are addressable SRAM locations. An interrupt

is generated to the opposite port upon writing to the upper byte of any

mailbox location. A port can read the message it has just written in order

to verify it: this read will not alter the status of the interrupt sent to the opposite

port. The interrupted port can clear the interrupt by reading the upper byte

of the applicable mailbox. This read will not alter the contents of the mailbox.

The use of mailboxes to generate interrupts to the opposite port and the

reading of mailboxes to clear interrupts is detailed in Truth Table V.

If desired, any of the mailbox interrupts can be independently masked

via software. Masking of the interrupt sources is done in the Mask Register.

The masks are individual and independent: a port can mask any

combination of interrupt sources with no effect on the other sources. Each

port can modify only its own Mask Register. The use of this register is

detailed in Truth Table V.

Two registers are provided to permit interpretation of interrupts: these

are the Interrupt Cause Register and the Interrupt Status Register. The

Interrupt Cause Register gives the user a snapshot of what has caused

the interrupt to be generated - the specific mailbox written to by the opposite

port. The information in this register provides post-mask signals: interrupt

sources that have been masked will not be updated. The Interrupt Status

interrupt regardless of whether they have been masked. The use of the

Interrupt Cause Register and the Interrupt Status Register is detailed in

Truth Table V.

if written, and if read unknown values on D0-D15 will be returned. Each

port can be assigned as many banks within the array as needed, up to

and including all four banks.

The bank select pin inputs must be set at either VIH or VIL - these inputs

are not tri-statable. When changing the bankassignments, accesses of the

affected banks must be suspended. Accesses may continue uninterrupted

in banks that are not being reallocated.

BKSEL0 BKSEL1 BKSEL2 BKSEL3 BANK AND

DIRECTION(1)

HX X XBANK 0 LEFT

XHXXBANK 1 LEFT

XXHXBANK 2 LEFT

XXXHBANK 3 LEFT

L X X X BANK 0 RIGHT

X L X X BANK 1 RIGHT

X X L X BANK 2 RIGHT

X X X L BANK 3 RIGHT

3592 tbl 13

6.42

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth Table V  Mailbox Interrupts (CE = VIH)(8,9)

NOTES:

1. There are four independent mailbox locations available to each side, external to the standard memory array. The mailboxes can be written to in either 8-bit or

16-bit widths. The upper byte of each mailbox has an associated interrupt to the opposite port. The mailbox interrupts can be individually masked if desired,

and the status of the interrupt determined by polling the Interrupt Status Register (see Note 6 for this table). A port can read its own mailboxes to verify the data

written, without affecting the interrupt which is sent to the opposite port.

2. These registers allow a port to read the data written to a specific mailbox location by the opposite port. Reading the upper byte of the data in a particular

mailbox clears the interrupt associated with that mailbox without modifying the data written. Once the address and R/W are stable, the actual clearing of the

interrupt is triggered by the transition of MBSEL from VIH to VIL.

3. This register contains the Mask Register (bits D0-D3), the Interrupt Cause Register (bits D4-D7), and the Interrupt Status Register (bits D8-D11). The controls for

R/W, UB, and LB are manipulated in accordance with the appropriate function. See Notes 4, 5, and 6 for this table. Bits D12-D15 are "Don't Care".

4. This register, the Mask Register, allows the user to independently mask the various interrupt sources. Writing VIH to the appropriate bit (D0 = Mailbox 0, D1 =

Mailbox 1, D2 = Mailbox 2, and D3 = Mailbox 3) disables the interrupt, while writing VIL enables the interrupt. All four bits in this register must be written at the

same time. This register can be read at any time to verify the mask settings. The masks are individual and independent: any single interrupt source can be

masked with no effect on the other sources. Each port can modify only its own mask settings.

5. This register, the Interrupt Cause Register, gives the user a snapshot of what has caused the interrupt to be generated. Reading VOL for a specific bit (D4 =

Mailbox 0, D5 = Mailbox 1, D6 = Mailbox 2, and D7 = Mailbox 3) indicates that the associated interrupt source has generated an interrupt. Acknowledging the

interrupt clears the bit in this register (see Note 2 for this table). This register provides post-mask information: if the interrupt source has been masked, the

associated bit in this register will not update.

6. This register, the Interrupt Status Register, gives the user the status of all interrupt sources that could potentially cause an interrupt regardless of whether they

have been masked. Reading VOL for a specific bit (D8 = Mailbox 0, D9 = Mailbox 1, D10 = Mailbox 2, and D11 = Mailbox 3) indicates that the associated

interrupt source has generated an interrupt. Acknowledging the interrupt clears the associated bit in this register (see Note 2 for this table). This register provides

pre-mask information: regardless of whether an interrupt source has been masked, the associated bit in this register will update.

7. Access to registers defined as "RESERVED" will have no effect, if written, and if read unknown values on D0-D15 will be returned.

8. These registers are not guaranteed to initialize in any known state. At power-up, the initialization sequence should include the set-up of these registers.

9. 'L' = VIL or VOL, 'H' = VIH or VOH, 'X' = Don't Care.

SEL R/WUB LB A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DES CRIP TI ON

L X X X L L L L L L RESERVED (7) RESERVED (7)

LXXX

•

• •

•

• •

•

• •

•

• •

•

• •

•

• RESERVED (7) RESERVED (7)

L(1)(1)(1)HLLLLLXXXXXXXXXXXXXXXX MAILBOX 0 - SET INTERRUP T ON OP POS ITE P ORT

L(1)(1)(1)HLLLLHXXXXXXXXXXXX XXXX MAILBOX 1 - SET INTERRUP T ON OP P OS ITE PORT

L(1)(1)(1)HLLLHLXXXXXXXXXXXX XXXX MAILBOX 2 - SET INTERRUP T ON OP POS ITE P ORT

L(1)(1)(1)HLLLHHXXXXXXXXXXXX XXXX MAILBOX 3 - SET INTERRUP T ON OP POS ITE P ORT

↑H(2)(2)HLLHLLXXXXXXXXXXXXXXXX MAILBOX 0 - CLEAR OPPOSITE PORT INTERRUPT

↑H(2)(2)HLLHLHXXXXXXXXXXXX XXXX MAILBOX 1 - CLEAR OPPOSITE PORT INTERRUPT

↑H(2)(2)HLLHHLXXXXXXXXXXXX XXXX MAILBOX 2 - CLEAR OPPOSITE PORT INTERRUPT

↑H(2)(2)HLLHHHXXXXXXXXXXXX XXXX MAILBOX 3 - CLEAR OPPOSITE PORT INTERRUPT

L(3)(3)(3)HLHLLL(4)(4)(4)(4)(5)(5)(5)(5)(6)(6)(6)(6)XXXX MAILBOX INTERRUP T CONTROL S

LXXX

•

• •

•

• •

•

• •

•

• •

•

• •

•

• RESERVED (7) RESERVED (7)

L X X X H H H H H H RESERVED (7) RESERVED (7)

3592 tbl 14

6.42

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

tRC

R/W

ADDR

tAA

UB,LB

3592 drw 06

(3)

tACE (3)

tAOE(3)

tABE (3)

(1)

tLZ tOH

(2)

tHZ

DATAOUT VALID DATA(3)

(5)

Waveform of Read Cycles(4)

Timing of Power-Up Power-Down

NOTES:

1. Timing depends on which signal is asserted last, CE, OE, LB, or UB.

2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.

3. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tABE or tAA.

4. MBSEL = VIH.

5. Refer to Truth Table I.

3592 drw 07

tPU

ICC

ISB

tPD

50% 50%

(5)

6.42

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = VIL and MBSEL = VIH. To access mailbox, CE = VIH and MBSEL = VIL. Either condition must be valid for the entire tEW time.

Refer to Truth Tables I and III.

4 . The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and t OW values will vary over voltage

and temperature, the actual tDH will always be smaller than the actual tOW.

5. 'X' in part numbers indicates power rating (S or L).

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage(5)

Symbol Parameter

707288X15

Com'l Only 707288X20

Com' l & I nd 707288X25

Com' l & I nd

UnitMin. Max. Min. Max. Min. Max.

WRI TE CYCLE

tWC Write Cycle Time 15 ____ 20 ____ 25 ____ ns

tEW Chip Enable to End-of-Write(3) 12 ____ 15 ____ 20 ____ ns

tAW Address Valid to End-of-Write 12 ____ 15 ____ 20 ____ ns

tAS Address Set-up Time(3) 0____ 0____ 0____ ns

tBS B ank Se t-up Time 0 ____ 0____ 0____ ns

tWP Write Pulse Width 12 ____ 15 ____ 20 ____ ns

tWR Write Re c o ve ry Tim e 0 ____ 0____ 0____ ns

tDW Data Valid to End-of-Write 15 ____ 15 ____ 20 ____ ns

tHZ Output Hig h-Z Time (1,2) ____ 8____ 9____ 10 ns

tDH Data Ho ld Time (4) 0____ 0____ 0____ ns

tWZ Write Enab le to Outp ut in Hi gh-Z(1,2) ____ 8____ 9____ 10 ns

tOW Outp ut A cti ve fro m En d -o f-Write(1,2,4) 3____ 3____ 3____ ns

tMWRD Mailbox Write to Read Time 5 ____ 5____ 5____ ns

3592 tbl 15

6.42

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)

NOTES:

1. R/W or CE or UB and LB = VIH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or MBSEL or R/W) going to VIH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or MBSEL = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7 . This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure

2).

8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed

on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified

tWP.

9. To access RAM, CE = VIL and MBSEL = VIH. To access mailboxes, CE = VIH and MBSEL = VIL. tEW must be met for either condition.

10. Refer to Truth Table I.

Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)

R/W

tWC

tHZ

tAW

tWR

tAS tWP

DATAOUT

(2)

tWZ

tDW tDH

tOW

ADDRESS

DATAIN

(6)

(4)

(7)

UB or LB

3592 drw 08

(9)

CE or

MBSEL

(9,10)

(7)

(3)

tLZ

VALID(4)

3592 drw 09

tWC

tAS tWR

tDW tDH

ADDRESS

DATAIN

R/W

tAW

tEW

UB or LB

(3)

(2)

(6)

CE or MBSEL(9,10)

(9)

6.42

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Mailbox Read after Write Timing, Either Side(1,2)

NOTES:

1. CE = VIH for the duration of the above timing (both write and read cycle), refer to Truth Table I.

2. UB and LB are controlled as necessary to enable the desired byte accesses.

Timing Waveform of Left Port Write to right Port Read of Same Data(1,2,3)

NOTES:

1. UB and LB are controlled as necessary to enable the desired byte accesses.

2 . Timing for Right Port Write to Left Port Read is identical.

3 . Refer to Truth Table I and IV.

BKSEL0-3

3592 drw 10

tWC

I/O0L-15L

ADDRESSES MATCH

R/WL

DATAIN

VALID

DATAOUT

VALID

Read Cycle

Write Cycle

CEL

A0L-13L

and A0R-13R

CER

I/O0R-15R

R/WR

OER

tAS tWP

tAWtEW

tDW tDH

tWR

tBS

tLZ

tACE

tHZ

tOH

MBSEL

3592 drw 11

tAW tEW

tMOP

I/O0-15

VALID ADDRESS

tMAA

R/W

tWR

tOH

tACE

VALID ADDRESS

DATAIN

VALID DATAOUT

VALID

tDW

tWP tDH

tAS

tMWRD tAOE

Read CycleWrite Cycle

A0-A5

6.42

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing(1,5)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. See Interrupt Truth Table V.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

5. Refer to Truth Table I.

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(1)

707288X15

Com'l Only 707288X20

Com'l & Ind 707288X25

Com'l & Ind

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

INTE RRUPT TIMI NG

tAS Address Set-up Time 0 ____ 0____ 0____ ns

tWR Write Recovery Time 0 ____ 0____ 0____ ns

tINS Inte rrup t S e t Tim e ____ 15 ____ 20 ____ 25 ns

tINR Inte rrup t Re s e t Tim e ____ 15 ____ 20 ____ 25 ns

3 592 t bl 16

3592 drw 12

ADDR"A" MAILBOX SET ADDRESS

MBSEL"A"

R/W"A"

tAS

tWC

tWR

(3) (4)

tINS(3)

INT"B"

(2)

3592 drw 13

ADDR"B" MAILBOX CLEAR ADDRESS

MBSEL"B"

OE"B"

tAS

tRC

(3)

tINR(3)

INT"B"

(2)

6.42

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

3592 drw 14

IDT707288

Bank-Switchable

SRAM

CE0

CE1

CE0

CE1

A14(1)

CE1

CE0

VCC VCC

IDT707288

Bank-Switchable

SRAM

IDT707288

Bank-Switchable

SRAM

IDT707288

Bank-Switchable

SRAM

Control Inputs

Control Inputs BKSEL0-3

R/W

LB,UB

Depth and Width Expansion

The IDT707288 features dual chip enables (refer to Truth Table I) in

order to facilitate rapid and simple depth expansion with no requirements

for external logic. Figure 4 illustrates how to control the various chip

enables in order to expand two devices in depth.

The IDT707288 can also be used in applications requiring expanded

Figure 4. Depth and Width Expansion with IDT707288

width, as indicated in Figure 4. Since the banks are allocated at the

discretion of the user, the external controller can be set up to drive the input

signals for the various devices as required to allow for 32-bit or wider

applications.

NOTE:

1. This signal is provided by external logic. It is not a bit present on the address bus.

6.42

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

Power

999

Speed

Package

Process/

Temperature

Range

Blank

ICommercial (0°Cto+70°C)

Industrial (-40°Cto+85°C)

PF 100-pin TQFP (PN100-1)

LStandard Power

Low Power

XXXXX

Device

Type

1Mbit (4 x 16K x 16)

Bank-Switchable Dual-Ported SRAM

with External Bank Selects

707288

IDT

3592 drw 15

Commercial Only

Commercial & Industrial

Commercial & Industrial Speed in nanoseconds

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Datasheet Document History

1/18/99: Initiated datasheet document history

Converted to new format

Cosmetic and typographical corrections

Page 2 Added additional notes to pin configurations

3/11/99: Removed preliminary note

Cosmetic and typographical corrections

6/4/99: Changed drawing format

Page 1 Corrected DSC number

3/10/00: Added Industrial Temperature Ranges and removed corresponding notes

Replaced IDT logo

Page 1 Made overbar correction on drawing

Changed ±200mV to 0mV in notes

5/23/00: Page 5 Increased storage temperature parameter

Clarified TA parameter

Page 6 DC Electrical parameters–changed wording from "open" to "disabled"

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Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com