Features
•Supply Voltage: 5 V
•Low Power Consumption: 15 mA/5 V
•Output Level and Spurious Products Adjustable (Optional)
•Excellent Sideband Suppression by Means of Duty Cycle Regeneration
of the LO Input Signal
•Phase-control Loop for Precise 90° Phase Shifting
•Power-down Mode
•Low LO Input Level: -15 dBm
•50-Ω Single-ended LO and RF Port
•LO Frequency Range of 30 MHz to 300 MHz
Benefits
•Low Current Consumption
•Few External Components Result in Cost and Board Space Saving
•Adjustment Free Hence Saves Time
Electrostatic sensitive device.
Observe precautions for handling.
Description
The IC U2793B is a 300-MHz quadrature modulator that uses Atmel‘s advanced UHF
process. It features low current consumption, single-ended RF ports and adjustment-
free application, which makes the device suitable for all digital radio systems, e.g.,
GSM, PCN, JDC and WLAN. As an option, output level and spurious products are
adjustable at pins 19 and 20. In conjunction with Atmel’s U2795B mixer, an up-con-
verter up to 2 GHz can be realized.
Figure 0-1. Block Diagram
Frequency
doubler
Duty cycle
regenerator
0°
90°
90° control
loop Σ
Power
up
1
8
6,7
13
V
S
V
Ref
4
2
5
3,16,17,18
GND
10
14
15
19
20
11
12
9
BB
Ai
BB
Ai
LO
i
BB
Bi
BB
Bi
S
PD
PU
RF
o
AC
GND
LP1
LP2
LO
i
AC
GND
300-MHz
Quadrature
Modulator
U2793B
Rev. 4651D–CELL–03/05
2
4651D–CELL–03/05
U2793B
1. Pin Configuration
Figure 1-1. Pinning SSO20
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
GND
PU
17
18
19
20
GND
SPU
BBBI
VREF
GND
GND
LP1
LP2
VS
RFO
U2793B
ACGND
LOI
LOI
ACGND
VS
BBAI
BBBI
BBAI
3
4651D–CELL–03/05
U2793B
Table 1-1. Pin Description
Pin Symbol Function
1 PU Power-up input
2 ACGND AC ground
3 GND Ground
4 RFO RF output
5 ACGND AC ground
6 VS Supply voltage
7 VS Supply voltage
8 SPU Settling time power-up
9 BBAI Baseband input A
10 BBAI Baseband input A inverse
11 BBBI Baseband input B
12 BBBI Baseband input B inverse
13 VREF Reference voltage (2.5 V)
14 LOI Input LO
15 LOI Input LO inverse, typically grounded
16 GND Ground
17 GND Ground
18 GND Ground
19 LP2 Output low pass and power control
20 LP1 Output low pass and power control
4
4651D–CELL–03/05
U2793B
2. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters Symbol Value Unit
Supply voltage VS6V
Input voltage Vi0 to VSV
Junction temperature Tj125 °C
Storage temperature range TStg -40 to +125 °C
3. Thermal Resistance
Parameters Symbol Value Unit
Junction ambient SSO20 RthJA 140 K/W
4. Operating Range
Parameters Symbol Value Unit
Supply voltage VS4.5 to 5.5 V
Ambient temperature range Tamb -40 to +85 °C
5. Electrical Characteristics
Test conditions (unless otherwise specified); VS = 5 V, Tamb = 25°C, referred to test circuit.
System impedance Zo = 50 Ω, fLO =150 MHz, PLO = -15 dBm, VBBi = 1.0 Vpp, differential
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1.1 Supply voltage range 6, 7 VS4.5 5 5.5 V A
1.2 Supply current 6, 7 IS15 mA A
2 Baseband Inputs, Pin 9-10, 11-12
2.1 Input-voltage range (differential) VBBi 1000 1500 mVpp D
2.2 Input impedance ZBBi 30 kΩD
2.3 Input-frequency range fBBi 050MHzD
2.4 Input voltage, common mode 2.5 V
3 LO Input, Pins 14 and 15
3.1 Frequency range fLOi 30 300 MHz D
3.2 Input level(1) PLOi -15 -5 dBm D
3.3 Input impedance ZiLO (2) ΩD
3.4 Voltage standing wave ratio VSWRLO 3.5 D
3.5 Duty-cycle range DCRLO 0.4 0.6 D
Notes: 1. Required LO level is a function of the LO frequency.
2. The LO input impedance is consisting of a 50 Ω resistor in series with a 15 pF capacitor.
3. With the pins 19 and 20 spurious performance especially for low frequency application can be improved by adding a chip
capacitor between LP1 and LP2. In conjunction with a parallel resistor the output level can be adjusted to the following
mixer stage without degration of LO suppression and noise performance which would decrease if the I/Q input level is
reduced.
4. For Tamb = -40°C to +85°C and VS = 4.5 V to 5.5 V
5
4651D–CELL–03/05
U2793B
4 RF Output, Pin 4
4.1 Output level
fLO = 150 MHz,
VBBi = 1 Vpp, differential
fLO = 50 MHz,
VBBi = 0.3 Vpp, differential
PRFo
- 3 -1
0
+2
dBm A/B
4.2 LO suppression PLO = -20 dBM LORFO 32 45 dB A
4.3 Voltage standing wave ratio VSWRRF 1.4 2 D
4.4 Sideband suppression(3) SBSRFo 35 45 dB A
4.5 Phase error(4) Pe < 1 deg D
4.6 Amplitude error Ae < ±0.25 dB D
4.7 Noise floor VBBi = 2 V, VBBi = 3 V
VBBi = VBBi = 2.5 V NFL -137
-143 dBm/Hz D
5 Power-up Mode
5.1 Supply current VPU ≤ 0.5 V, pins 6, 7
VPU = 1 V IPU 10 1µAD
5.2 Settling time Pins 1 to 4, CSPU = 100 pF
CLO = 100 pF, CRFo = 1 nF tSPU 10 µs D
6 Switching Voltage, Pin 1
6.1 Power on VPUON 4VD
7 Reference Voltage, Pin 13
7.1 Voltage range VRef 2.375 2.5 2.625 V A
7.2 Output impedance ZoRef 30 ΩD
5. Electrical Characteristics (Continued)
Test conditions (unless otherwise specified); VS = 5 V, Tamb = 25°C, referred to test circuit.
System impedance Zo = 50 Ω, fLO =150 MHz, PLO = -15 dBm, VBBi = 1.0 Vpp, differential (Continued)
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
Notes: 1. Required LO level is a function of the LO frequency.
2. The LO input impedance is consisting of a 50 Ω resistor in series with a 15 pF capacitor.
3. With the pins 19 and 20 spurious performance especially for low frequency application can be improved by adding a chip
capacitor between LP1 and LP2. In conjunction with a parallel resistor the output level can be adjusted to the following
mixer stage without degration of LO suppression and noise performance which would decrease if the I/Q input level is
reduced.
4. For Tamb = -40°C to +85°C and VS = 4.5 V to 5.5 V
6
4651D–CELL–03/05
U2793B
6. Diagrams
Figure 6-1. Reference Voltage versus Tamb
Figure 6-2. OIP3 versus Tamb, LO = 150 MHz, Level -10 dBm
Figure 6-3. Supply Current versus Tamb
-40 0 40 80
2.5
2.52
2.55
2.54
2.56
2.57
V
Ref
(V)
Temperature (°C)
120
2.53
2.51
-40 0 40 80
0
2
4
6
8
IP3 (dBm)
Temperature (°C)
120
0
4
8
12
16
20
Supply Current (mA)
Temperature (°C)
-40 0 40 80 120
7
4651D–CELL–03/05
U2793B
Figure 6-4. Recommended LO Power Range versus LO Frequency at Tamb = 25°C
Figure 6-5. Output Power versus Tamb
Figure 6-6. Typical Output Power versus LO Frequency at Tamb = 25°C,
VBBi = 250 mV (Differential)
0 50 100 200 250
-40
-30
-20
-10
0
P
LO
(dBm)
f
LO
(MHz)
300
150
-2
-1.6
-1.2
-0.8
-0.4
0
Output Power (dBm)
Temperature (°C)
-40 0 40 80 120
-35
-30
-25
-20
-15
-10
-5
0
5
0 50 100 150 200 250 300
F
LO
(MHz)
P
out
(dBm)
400 mVpp
600 mVpp
800 mVpp
1.0 Vpp
1.2 Vpp
100 mVpp
200 mVpp
8
4651D–CELL–03/05
U2793B
Figure 6-7. Typical Required VBBi Input Signal (Differential) versus LO Frequency
for PO = 1 dBm and PO = -3 dBm
0
200
400
600
800
1000
1200
1400
1600
1800
2000
0 50 100 150 200 250 300
FLO (MHz)
Pout (dBm)
-1 dBm -3 dBm
-5 dBm
9
4651D–CELL–03/05
U2793B
7. Evaluation Board Drawings
Figure 7-1. Evaluation Board Circuitry
Part List
C1, C2, C3, C4, C6=1 nF
C7, C8=100 pF
C5=100 nF
C9, R1= 1 pF to 10 pF
=50-Ω Microstrip
= optional
The above listed components result in a PD settling time of <20 µs. The use of other component
values will require consideration for time requirements in burst-mode applications.
1
3
4
2
5
7
8
6
9
10 11
12
13
14
15
16
17
18
19
20
L
1
PU
OUT
LO
V
S
GND
U2793B
C
9
R
1
B
inv
B
AA
inv
V
Ref
C
7
C
8
C
6
C
5
C
4
C
3
C
2
C
1
L
2
10
4651D–CELL–03/05
U2793B
Figure 7-2. PCB Layout Evaluation Board
11
4651D–CELL–03/05
U2793B
8. Application Circuits
Bias network for AC-coupled baseband inputs (VBA, VBB).
R1 = 2.5 kΩ, R2 ≤ 10 kΩ for ≥ 35 dB LO suppression which is in reference to < 2 mV input offset.
Figure 8-1. Application Circuit with AC-coupled Baseband Inputs
Figure 8-2. Application Circuit with DC-coupled Baseband Inputs
Duty cycle
regenerator
Frequency
doubler
90° control
loop
Σ
Power
up
1
8
6,7
13 V
S
4
2
5
3,16,17,18
GND
10
14
15
19
20
11
12
9
LO
i
BB
Bi
R
1
V
Ref
PU
S
PU
RF
o
AC
GND
R
2
0°90°
LP2
LP1
AC
GND
BB
Bi
LO
i
BB
Ai
BB
Ai
Power down
1n
100n
Duty cycle
regenerator Frequency
doubler
90° control
loop
Σ
Power
up
1
8
6,7
13 V
S
4
2
5
3,16,17,18
GND
10
14
15
19
20
11
12
9
BB
Ai
LO
i
BB
BI
V
Ref
PU
S
PU
RF
o
AC
GND
0°
90°
LP2
LP1
Baseband
processing
LO
100n
10k
100n
10k
10k
10k
100p
OUT
Power down
1n
1n
1n
1n
1n
100n
AC
GND
BB
BI
LO
i
BB
Ai
12
4651D–CELL–03/05
U2793B
10. Package Information
9. Ordering Information
Extended Type Number Package Remarks
U2793B-NFSH SSO20 Tube, lead free
U2793B-NFSG3H SSO20 Taped and reeled, lead free
Printed on recycled paper.
4651D–CELL–03/05
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